Merge "project: msm8610: Enable the feature of power on vibrator"
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index ce740a7..9dff1a3 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,7 +54,7 @@
/* Panel resolution */
/*---------------------------------------------------------------------------*/
static struct panel_resolution nt35590_720p_video_panel_res = {
- 720, 1280, 140, 164, 8, 0, 6, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 720, 1280, 140, 164, 8, 0, 6, 11, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
@@ -2387,475 +2387,488 @@
0x29, 0x00, 0xFF, 0xFF, };
+static char nt35590_720p_video_on_cmd464[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xFF, 0x00, 0xFF, 0xFF, };
+
+
+static char nt35590_720p_video_on_cmd465[] = {
+0x06, 0x00, 0x29, 0xC0,
+0x3B, 0x03, 0x06, 0x03,
+0x02, 0x02, 0xFF, 0xFF, };
+
+
static struct mipi_dsi_cmd nt35590_720p_video_on_command[] = {
-{ 0x8 , nt35590_720p_video_on_cmd0},
-{ 0x8 , nt35590_720p_video_on_cmd1},
-{ 0x8 , nt35590_720p_video_on_cmd2},
-{ 0x8 , nt35590_720p_video_on_cmd3},
-{ 0x8 , nt35590_720p_video_on_cmd4},
-{ 0x8 , nt35590_720p_video_on_cmd5},
-{ 0x8 , nt35590_720p_video_on_cmd6},
-{ 0x8 , nt35590_720p_video_on_cmd7},
-{ 0x8 , nt35590_720p_video_on_cmd8},
-{ 0x8 , nt35590_720p_video_on_cmd9},
-{ 0x8 , nt35590_720p_video_on_cmd10},
-{ 0x8 , nt35590_720p_video_on_cmd11},
-{ 0x8 , nt35590_720p_video_on_cmd12},
-{ 0x8 , nt35590_720p_video_on_cmd13},
-{ 0x8 , nt35590_720p_video_on_cmd14},
-{ 0x8 , nt35590_720p_video_on_cmd15},
-{ 0x8 , nt35590_720p_video_on_cmd16},
-{ 0x8 , nt35590_720p_video_on_cmd17},
-{ 0x8 , nt35590_720p_video_on_cmd18},
-{ 0x8 , nt35590_720p_video_on_cmd19},
-{ 0x8 , nt35590_720p_video_on_cmd20},
-{ 0x8 , nt35590_720p_video_on_cmd21},
-{ 0x8 , nt35590_720p_video_on_cmd22},
-{ 0x8 , nt35590_720p_video_on_cmd23},
-{ 0x8 , nt35590_720p_video_on_cmd24},
-{ 0x8 , nt35590_720p_video_on_cmd25},
-{ 0x8 , nt35590_720p_video_on_cmd26},
-{ 0x8 , nt35590_720p_video_on_cmd27},
-{ 0x8 , nt35590_720p_video_on_cmd28},
-{ 0x8 , nt35590_720p_video_on_cmd29},
-{ 0x8 , nt35590_720p_video_on_cmd30},
-{ 0x8 , nt35590_720p_video_on_cmd31},
-{ 0x8 , nt35590_720p_video_on_cmd32},
-{ 0x8 , nt35590_720p_video_on_cmd33},
-{ 0x8 , nt35590_720p_video_on_cmd34},
-{ 0x8 , nt35590_720p_video_on_cmd35},
-{ 0x8 , nt35590_720p_video_on_cmd36},
-{ 0x8 , nt35590_720p_video_on_cmd37},
-{ 0x8 , nt35590_720p_video_on_cmd38},
-{ 0x8 , nt35590_720p_video_on_cmd39},
-{ 0x8 , nt35590_720p_video_on_cmd40},
-{ 0x8 , nt35590_720p_video_on_cmd41},
-{ 0x8 , nt35590_720p_video_on_cmd42},
-{ 0x8 , nt35590_720p_video_on_cmd43},
-{ 0x8 , nt35590_720p_video_on_cmd44},
-{ 0x8 , nt35590_720p_video_on_cmd45},
-{ 0x8 , nt35590_720p_video_on_cmd46},
-{ 0x8 , nt35590_720p_video_on_cmd47},
-{ 0x8 , nt35590_720p_video_on_cmd48},
-{ 0x8 , nt35590_720p_video_on_cmd49},
-{ 0x8 , nt35590_720p_video_on_cmd50},
-{ 0x8 , nt35590_720p_video_on_cmd51},
-{ 0x8 , nt35590_720p_video_on_cmd52},
-{ 0x8 , nt35590_720p_video_on_cmd53},
-{ 0x8 , nt35590_720p_video_on_cmd54},
-{ 0x8 , nt35590_720p_video_on_cmd55},
-{ 0x8 , nt35590_720p_video_on_cmd56},
-{ 0x8 , nt35590_720p_video_on_cmd57},
-{ 0x8 , nt35590_720p_video_on_cmd58},
-{ 0x8 , nt35590_720p_video_on_cmd59},
-{ 0x8 , nt35590_720p_video_on_cmd60},
-{ 0x8 , nt35590_720p_video_on_cmd61},
-{ 0x8 , nt35590_720p_video_on_cmd62},
-{ 0x8 , nt35590_720p_video_on_cmd63},
-{ 0x8 , nt35590_720p_video_on_cmd64},
-{ 0x8 , nt35590_720p_video_on_cmd65},
-{ 0x8 , nt35590_720p_video_on_cmd66},
-{ 0x8 , nt35590_720p_video_on_cmd67},
-{ 0x8 , nt35590_720p_video_on_cmd68},
-{ 0x8 , nt35590_720p_video_on_cmd69},
-{ 0x8 , nt35590_720p_video_on_cmd70},
-{ 0x8 , nt35590_720p_video_on_cmd71},
-{ 0x8 , nt35590_720p_video_on_cmd72},
-{ 0x8 , nt35590_720p_video_on_cmd73},
-{ 0x8 , nt35590_720p_video_on_cmd74},
-{ 0x8 , nt35590_720p_video_on_cmd75},
-{ 0x8 , nt35590_720p_video_on_cmd76},
-{ 0x8 , nt35590_720p_video_on_cmd77},
-{ 0x8 , nt35590_720p_video_on_cmd78},
-{ 0x8 , nt35590_720p_video_on_cmd79},
-{ 0x8 , nt35590_720p_video_on_cmd80},
-{ 0x8 , nt35590_720p_video_on_cmd81},
-{ 0x8 , nt35590_720p_video_on_cmd82},
-{ 0x8 , nt35590_720p_video_on_cmd83},
-{ 0x8 , nt35590_720p_video_on_cmd84},
-{ 0x8 , nt35590_720p_video_on_cmd85},
-{ 0x8 , nt35590_720p_video_on_cmd86},
-{ 0x8 , nt35590_720p_video_on_cmd87},
-{ 0x8 , nt35590_720p_video_on_cmd88},
-{ 0x8 , nt35590_720p_video_on_cmd89},
-{ 0x8 , nt35590_720p_video_on_cmd90},
-{ 0x8 , nt35590_720p_video_on_cmd91},
-{ 0x8 , nt35590_720p_video_on_cmd92},
-{ 0x8 , nt35590_720p_video_on_cmd93},
-{ 0x8 , nt35590_720p_video_on_cmd94},
-{ 0x8 , nt35590_720p_video_on_cmd95},
-{ 0x8 , nt35590_720p_video_on_cmd96},
-{ 0x8 , nt35590_720p_video_on_cmd97},
-{ 0x8 , nt35590_720p_video_on_cmd98},
-{ 0x8 , nt35590_720p_video_on_cmd99},
-{ 0x8 , nt35590_720p_video_on_cmd100},
-{ 0x8 , nt35590_720p_video_on_cmd101},
-{ 0x8 , nt35590_720p_video_on_cmd102},
-{ 0x8 , nt35590_720p_video_on_cmd103},
-{ 0x8 , nt35590_720p_video_on_cmd104},
-{ 0x8 , nt35590_720p_video_on_cmd105},
-{ 0x8 , nt35590_720p_video_on_cmd106},
-{ 0x8 , nt35590_720p_video_on_cmd107},
-{ 0x8 , nt35590_720p_video_on_cmd108},
-{ 0x8 , nt35590_720p_video_on_cmd109},
-{ 0x8 , nt35590_720p_video_on_cmd110},
-{ 0x8 , nt35590_720p_video_on_cmd111},
-{ 0x8 , nt35590_720p_video_on_cmd112},
-{ 0x8 , nt35590_720p_video_on_cmd113},
-{ 0x8 , nt35590_720p_video_on_cmd114},
-{ 0x8 , nt35590_720p_video_on_cmd115},
-{ 0x8 , nt35590_720p_video_on_cmd116},
-{ 0x8 , nt35590_720p_video_on_cmd117},
-{ 0x8 , nt35590_720p_video_on_cmd118},
-{ 0x8 , nt35590_720p_video_on_cmd119},
-{ 0x8 , nt35590_720p_video_on_cmd120},
-{ 0x8 , nt35590_720p_video_on_cmd121},
-{ 0x8 , nt35590_720p_video_on_cmd122},
-{ 0x8 , nt35590_720p_video_on_cmd123},
-{ 0x8 , nt35590_720p_video_on_cmd124},
-{ 0x8 , nt35590_720p_video_on_cmd125},
-{ 0x8 , nt35590_720p_video_on_cmd126},
-{ 0x8 , nt35590_720p_video_on_cmd127},
-{ 0x8 , nt35590_720p_video_on_cmd128},
-{ 0x8 , nt35590_720p_video_on_cmd129},
-{ 0x8 , nt35590_720p_video_on_cmd130},
-{ 0x8 , nt35590_720p_video_on_cmd131},
-{ 0x8 , nt35590_720p_video_on_cmd132},
-{ 0x8 , nt35590_720p_video_on_cmd133},
-{ 0x8 , nt35590_720p_video_on_cmd134},
-{ 0x8 , nt35590_720p_video_on_cmd135},
-{ 0x8 , nt35590_720p_video_on_cmd136},
-{ 0x8 , nt35590_720p_video_on_cmd137},
-{ 0x8 , nt35590_720p_video_on_cmd138},
-{ 0x8 , nt35590_720p_video_on_cmd139},
-{ 0x8 , nt35590_720p_video_on_cmd140},
-{ 0x8 , nt35590_720p_video_on_cmd141},
-{ 0x8 , nt35590_720p_video_on_cmd142},
-{ 0x8 , nt35590_720p_video_on_cmd143},
-{ 0x8 , nt35590_720p_video_on_cmd144},
-{ 0x8 , nt35590_720p_video_on_cmd145},
-{ 0x8 , nt35590_720p_video_on_cmd146},
-{ 0x8 , nt35590_720p_video_on_cmd147},
-{ 0x8 , nt35590_720p_video_on_cmd148},
-{ 0x8 , nt35590_720p_video_on_cmd149},
-{ 0x8 , nt35590_720p_video_on_cmd150},
-{ 0x8 , nt35590_720p_video_on_cmd151},
-{ 0x8 , nt35590_720p_video_on_cmd152},
-{ 0x8 , nt35590_720p_video_on_cmd153},
-{ 0x8 , nt35590_720p_video_on_cmd154},
-{ 0x8 , nt35590_720p_video_on_cmd155},
-{ 0x8 , nt35590_720p_video_on_cmd156},
-{ 0x8 , nt35590_720p_video_on_cmd157},
-{ 0x8 , nt35590_720p_video_on_cmd158},
-{ 0x8 , nt35590_720p_video_on_cmd159},
-{ 0x8 , nt35590_720p_video_on_cmd160},
-{ 0x8 , nt35590_720p_video_on_cmd161},
-{ 0x8 , nt35590_720p_video_on_cmd162},
-{ 0x8 , nt35590_720p_video_on_cmd163},
-{ 0x8 , nt35590_720p_video_on_cmd164},
-{ 0x8 , nt35590_720p_video_on_cmd165},
-{ 0x8 , nt35590_720p_video_on_cmd166},
-{ 0x8 , nt35590_720p_video_on_cmd167},
-{ 0x8 , nt35590_720p_video_on_cmd168},
-{ 0x8 , nt35590_720p_video_on_cmd169},
-{ 0x8 , nt35590_720p_video_on_cmd170},
-{ 0x8 , nt35590_720p_video_on_cmd171},
-{ 0x8 , nt35590_720p_video_on_cmd172},
-{ 0x8 , nt35590_720p_video_on_cmd173},
-{ 0x8 , nt35590_720p_video_on_cmd174},
-{ 0x8 , nt35590_720p_video_on_cmd175},
-{ 0x8 , nt35590_720p_video_on_cmd176},
-{ 0x8 , nt35590_720p_video_on_cmd177},
-{ 0x8 , nt35590_720p_video_on_cmd178},
-{ 0x8 , nt35590_720p_video_on_cmd179},
-{ 0x8 , nt35590_720p_video_on_cmd180},
-{ 0x8 , nt35590_720p_video_on_cmd181},
-{ 0x8 , nt35590_720p_video_on_cmd182},
-{ 0x8 , nt35590_720p_video_on_cmd183},
-{ 0x8 , nt35590_720p_video_on_cmd184},
-{ 0x8 , nt35590_720p_video_on_cmd185},
-{ 0x8 , nt35590_720p_video_on_cmd186},
-{ 0x8 , nt35590_720p_video_on_cmd187},
-{ 0x8 , nt35590_720p_video_on_cmd188},
-{ 0x8 , nt35590_720p_video_on_cmd189},
-{ 0x8 , nt35590_720p_video_on_cmd190},
-{ 0x8 , nt35590_720p_video_on_cmd191},
-{ 0x8 , nt35590_720p_video_on_cmd192},
-{ 0x8 , nt35590_720p_video_on_cmd193},
-{ 0x8 , nt35590_720p_video_on_cmd194},
-{ 0x8 , nt35590_720p_video_on_cmd195},
-{ 0x8 , nt35590_720p_video_on_cmd196},
-{ 0x8 , nt35590_720p_video_on_cmd197},
-{ 0x8 , nt35590_720p_video_on_cmd198},
-{ 0x8 , nt35590_720p_video_on_cmd199},
-{ 0x8 , nt35590_720p_video_on_cmd200},
-{ 0x8 , nt35590_720p_video_on_cmd201},
-{ 0x8 , nt35590_720p_video_on_cmd202},
-{ 0x8 , nt35590_720p_video_on_cmd203},
-{ 0x8 , nt35590_720p_video_on_cmd204},
-{ 0x8 , nt35590_720p_video_on_cmd205},
-{ 0x8 , nt35590_720p_video_on_cmd206},
-{ 0x8 , nt35590_720p_video_on_cmd207},
-{ 0x8 , nt35590_720p_video_on_cmd208},
-{ 0x8 , nt35590_720p_video_on_cmd209},
-{ 0x8 , nt35590_720p_video_on_cmd210},
-{ 0x8 , nt35590_720p_video_on_cmd211},
-{ 0x8 , nt35590_720p_video_on_cmd212},
-{ 0x8 , nt35590_720p_video_on_cmd213},
-{ 0x8 , nt35590_720p_video_on_cmd214},
-{ 0x8 , nt35590_720p_video_on_cmd215},
-{ 0x8 , nt35590_720p_video_on_cmd216},
-{ 0x8 , nt35590_720p_video_on_cmd217},
-{ 0x8 , nt35590_720p_video_on_cmd218},
-{ 0x8 , nt35590_720p_video_on_cmd219},
-{ 0x8 , nt35590_720p_video_on_cmd220},
-{ 0x8 , nt35590_720p_video_on_cmd221},
-{ 0x8 , nt35590_720p_video_on_cmd222},
-{ 0x8 , nt35590_720p_video_on_cmd223},
-{ 0x8 , nt35590_720p_video_on_cmd224},
-{ 0x8 , nt35590_720p_video_on_cmd225},
-{ 0x8 , nt35590_720p_video_on_cmd226},
-{ 0x8 , nt35590_720p_video_on_cmd227},
-{ 0x8 , nt35590_720p_video_on_cmd228},
-{ 0x8 , nt35590_720p_video_on_cmd229},
-{ 0x8 , nt35590_720p_video_on_cmd230},
-{ 0x8 , nt35590_720p_video_on_cmd231},
-{ 0x8 , nt35590_720p_video_on_cmd232},
-{ 0x8 , nt35590_720p_video_on_cmd233},
-{ 0x8 , nt35590_720p_video_on_cmd234},
-{ 0x8 , nt35590_720p_video_on_cmd235},
-{ 0x8 , nt35590_720p_video_on_cmd236},
-{ 0x8 , nt35590_720p_video_on_cmd237},
-{ 0x8 , nt35590_720p_video_on_cmd238},
-{ 0x8 , nt35590_720p_video_on_cmd239},
-{ 0x8 , nt35590_720p_video_on_cmd240},
-{ 0x8 , nt35590_720p_video_on_cmd241},
-{ 0x8 , nt35590_720p_video_on_cmd242},
-{ 0x8 , nt35590_720p_video_on_cmd243},
-{ 0x8 , nt35590_720p_video_on_cmd244},
-{ 0x8 , nt35590_720p_video_on_cmd245},
-{ 0x8 , nt35590_720p_video_on_cmd246},
-{ 0x8 , nt35590_720p_video_on_cmd247},
-{ 0x8 , nt35590_720p_video_on_cmd248},
-{ 0x8 , nt35590_720p_video_on_cmd249},
-{ 0x8 , nt35590_720p_video_on_cmd250},
-{ 0x8 , nt35590_720p_video_on_cmd251},
-{ 0x8 , nt35590_720p_video_on_cmd252},
-{ 0x8 , nt35590_720p_video_on_cmd253},
-{ 0x8 , nt35590_720p_video_on_cmd254},
-{ 0x8 , nt35590_720p_video_on_cmd255},
-{ 0x8 , nt35590_720p_video_on_cmd256},
-{ 0x8 , nt35590_720p_video_on_cmd257},
-{ 0x8 , nt35590_720p_video_on_cmd258},
-{ 0x8 , nt35590_720p_video_on_cmd259},
-{ 0x8 , nt35590_720p_video_on_cmd260},
-{ 0x8 , nt35590_720p_video_on_cmd261},
-{ 0x8 , nt35590_720p_video_on_cmd262},
-{ 0x8 , nt35590_720p_video_on_cmd263},
-{ 0x8 , nt35590_720p_video_on_cmd264},
-{ 0x8 , nt35590_720p_video_on_cmd265},
-{ 0x8 , nt35590_720p_video_on_cmd266},
-{ 0x8 , nt35590_720p_video_on_cmd267},
-{ 0x8 , nt35590_720p_video_on_cmd268},
-{ 0x8 , nt35590_720p_video_on_cmd269},
-{ 0x8 , nt35590_720p_video_on_cmd270},
-{ 0x8 , nt35590_720p_video_on_cmd271},
-{ 0x8 , nt35590_720p_video_on_cmd272},
-{ 0x8 , nt35590_720p_video_on_cmd273},
-{ 0x8 , nt35590_720p_video_on_cmd274},
-{ 0x8 , nt35590_720p_video_on_cmd275},
-{ 0x8 , nt35590_720p_video_on_cmd276},
-{ 0x8 , nt35590_720p_video_on_cmd277},
-{ 0x8 , nt35590_720p_video_on_cmd278},
-{ 0x8 , nt35590_720p_video_on_cmd279},
-{ 0x8 , nt35590_720p_video_on_cmd280},
-{ 0x8 , nt35590_720p_video_on_cmd281},
-{ 0x8 , nt35590_720p_video_on_cmd282},
-{ 0x8 , nt35590_720p_video_on_cmd283},
-{ 0x8 , nt35590_720p_video_on_cmd284},
-{ 0x8 , nt35590_720p_video_on_cmd285},
-{ 0x8 , nt35590_720p_video_on_cmd286},
-{ 0x8 , nt35590_720p_video_on_cmd287},
-{ 0x8 , nt35590_720p_video_on_cmd288},
-{ 0x8 , nt35590_720p_video_on_cmd289},
-{ 0x8 , nt35590_720p_video_on_cmd290},
-{ 0x8 , nt35590_720p_video_on_cmd291},
-{ 0x8 , nt35590_720p_video_on_cmd292},
-{ 0x8 , nt35590_720p_video_on_cmd293},
-{ 0x8 , nt35590_720p_video_on_cmd294},
-{ 0x8 , nt35590_720p_video_on_cmd295},
-{ 0x8 , nt35590_720p_video_on_cmd296},
-{ 0x8 , nt35590_720p_video_on_cmd297},
-{ 0x8 , nt35590_720p_video_on_cmd298},
-{ 0x8 , nt35590_720p_video_on_cmd299},
-{ 0x8 , nt35590_720p_video_on_cmd300},
-{ 0x8 , nt35590_720p_video_on_cmd301},
-{ 0x8 , nt35590_720p_video_on_cmd302},
-{ 0x8 , nt35590_720p_video_on_cmd303},
-{ 0x8 , nt35590_720p_video_on_cmd304},
-{ 0x8 , nt35590_720p_video_on_cmd305},
-{ 0x8 , nt35590_720p_video_on_cmd306},
-{ 0x8 , nt35590_720p_video_on_cmd307},
-{ 0x8 , nt35590_720p_video_on_cmd308},
-{ 0x8 , nt35590_720p_video_on_cmd309},
-{ 0x8 , nt35590_720p_video_on_cmd310},
-{ 0x8 , nt35590_720p_video_on_cmd311},
-{ 0x8 , nt35590_720p_video_on_cmd312},
-{ 0x8 , nt35590_720p_video_on_cmd313},
-{ 0x8 , nt35590_720p_video_on_cmd314},
-{ 0x8 , nt35590_720p_video_on_cmd315},
-{ 0x8 , nt35590_720p_video_on_cmd316},
-{ 0x8 , nt35590_720p_video_on_cmd317},
-{ 0x8 , nt35590_720p_video_on_cmd318},
-{ 0x8 , nt35590_720p_video_on_cmd319},
-{ 0x8 , nt35590_720p_video_on_cmd320},
-{ 0x8 , nt35590_720p_video_on_cmd321},
-{ 0x8 , nt35590_720p_video_on_cmd322},
-{ 0x8 , nt35590_720p_video_on_cmd323},
-{ 0x8 , nt35590_720p_video_on_cmd324},
-{ 0x8 , nt35590_720p_video_on_cmd325},
-{ 0x8 , nt35590_720p_video_on_cmd326},
-{ 0x8 , nt35590_720p_video_on_cmd327},
-{ 0x8 , nt35590_720p_video_on_cmd328},
-{ 0x8 , nt35590_720p_video_on_cmd329},
-{ 0x8 , nt35590_720p_video_on_cmd330},
-{ 0x8 , nt35590_720p_video_on_cmd331},
-{ 0x8 , nt35590_720p_video_on_cmd332},
-{ 0x8 , nt35590_720p_video_on_cmd333},
-{ 0x8 , nt35590_720p_video_on_cmd334},
-{ 0x8 , nt35590_720p_video_on_cmd335},
-{ 0x8 , nt35590_720p_video_on_cmd336},
-{ 0x8 , nt35590_720p_video_on_cmd337},
-{ 0x8 , nt35590_720p_video_on_cmd338},
-{ 0x8 , nt35590_720p_video_on_cmd339},
-{ 0x8 , nt35590_720p_video_on_cmd340},
-{ 0x8 , nt35590_720p_video_on_cmd341},
-{ 0x8 , nt35590_720p_video_on_cmd342},
-{ 0x8 , nt35590_720p_video_on_cmd343},
-{ 0x8 , nt35590_720p_video_on_cmd344},
-{ 0x8 , nt35590_720p_video_on_cmd345},
-{ 0x8 , nt35590_720p_video_on_cmd346},
-{ 0x8 , nt35590_720p_video_on_cmd347},
-{ 0x8 , nt35590_720p_video_on_cmd348},
-{ 0x8 , nt35590_720p_video_on_cmd349},
-{ 0x8 , nt35590_720p_video_on_cmd350},
-{ 0x8 , nt35590_720p_video_on_cmd351},
-{ 0x8 , nt35590_720p_video_on_cmd352},
-{ 0x8 , nt35590_720p_video_on_cmd353},
-{ 0x8 , nt35590_720p_video_on_cmd354},
-{ 0x8 , nt35590_720p_video_on_cmd355},
-{ 0x8 , nt35590_720p_video_on_cmd356},
-{ 0x8 , nt35590_720p_video_on_cmd357},
-{ 0x8 , nt35590_720p_video_on_cmd358},
-{ 0x8 , nt35590_720p_video_on_cmd359},
-{ 0x8 , nt35590_720p_video_on_cmd360},
-{ 0x8 , nt35590_720p_video_on_cmd361},
-{ 0x8 , nt35590_720p_video_on_cmd362},
-{ 0x8 , nt35590_720p_video_on_cmd363},
-{ 0x8 , nt35590_720p_video_on_cmd364},
-{ 0x8 , nt35590_720p_video_on_cmd365},
-{ 0x8 , nt35590_720p_video_on_cmd366},
-{ 0x8 , nt35590_720p_video_on_cmd367},
-{ 0x8 , nt35590_720p_video_on_cmd368},
-{ 0x8 , nt35590_720p_video_on_cmd369},
-{ 0x8 , nt35590_720p_video_on_cmd370},
-{ 0x8 , nt35590_720p_video_on_cmd371},
-{ 0x8 , nt35590_720p_video_on_cmd372},
-{ 0x8 , nt35590_720p_video_on_cmd373},
-{ 0x8 , nt35590_720p_video_on_cmd374},
-{ 0x8 , nt35590_720p_video_on_cmd375},
-{ 0x8 , nt35590_720p_video_on_cmd376},
-{ 0x8 , nt35590_720p_video_on_cmd377},
-{ 0x8 , nt35590_720p_video_on_cmd378},
-{ 0x8 , nt35590_720p_video_on_cmd379},
-{ 0x8 , nt35590_720p_video_on_cmd380},
-{ 0x8 , nt35590_720p_video_on_cmd381},
-{ 0x8 , nt35590_720p_video_on_cmd382},
-{ 0x8 , nt35590_720p_video_on_cmd383},
-{ 0x8 , nt35590_720p_video_on_cmd384},
-{ 0x8 , nt35590_720p_video_on_cmd385},
-{ 0x8 , nt35590_720p_video_on_cmd386},
-{ 0x8 , nt35590_720p_video_on_cmd387},
-{ 0x8 , nt35590_720p_video_on_cmd388},
-{ 0x8 , nt35590_720p_video_on_cmd389},
-{ 0x8 , nt35590_720p_video_on_cmd390},
-{ 0x8 , nt35590_720p_video_on_cmd391},
-{ 0x8 , nt35590_720p_video_on_cmd392},
-{ 0x8 , nt35590_720p_video_on_cmd393},
-{ 0x8 , nt35590_720p_video_on_cmd394},
-{ 0x8 , nt35590_720p_video_on_cmd395},
-{ 0x8 , nt35590_720p_video_on_cmd396},
-{ 0x8 , nt35590_720p_video_on_cmd397},
-{ 0x8 , nt35590_720p_video_on_cmd398},
-{ 0x8 , nt35590_720p_video_on_cmd399},
-{ 0x8 , nt35590_720p_video_on_cmd400},
-{ 0x8 , nt35590_720p_video_on_cmd401},
-{ 0x8 , nt35590_720p_video_on_cmd402},
-{ 0x8 , nt35590_720p_video_on_cmd403},
-{ 0x8 , nt35590_720p_video_on_cmd404},
-{ 0x8 , nt35590_720p_video_on_cmd405},
-{ 0x8 , nt35590_720p_video_on_cmd406},
-{ 0x8 , nt35590_720p_video_on_cmd407},
-{ 0x8 , nt35590_720p_video_on_cmd408},
-{ 0x8 , nt35590_720p_video_on_cmd409},
-{ 0x8 , nt35590_720p_video_on_cmd410},
-{ 0x8 , nt35590_720p_video_on_cmd411},
-{ 0x8 , nt35590_720p_video_on_cmd412},
-{ 0x8 , nt35590_720p_video_on_cmd413},
-{ 0x8 , nt35590_720p_video_on_cmd414},
-{ 0x8 , nt35590_720p_video_on_cmd415},
-{ 0x8 , nt35590_720p_video_on_cmd416},
-{ 0x8 , nt35590_720p_video_on_cmd417},
-{ 0x8 , nt35590_720p_video_on_cmd418},
-{ 0x8 , nt35590_720p_video_on_cmd419},
-{ 0x8 , nt35590_720p_video_on_cmd420},
-{ 0x8 , nt35590_720p_video_on_cmd421},
-{ 0x8 , nt35590_720p_video_on_cmd422},
-{ 0x8 , nt35590_720p_video_on_cmd423},
-{ 0x8 , nt35590_720p_video_on_cmd424},
-{ 0x8 , nt35590_720p_video_on_cmd425},
-{ 0x8 , nt35590_720p_video_on_cmd426},
-{ 0x8 , nt35590_720p_video_on_cmd427},
-{ 0x8 , nt35590_720p_video_on_cmd428},
-{ 0x8 , nt35590_720p_video_on_cmd429},
-{ 0x8 , nt35590_720p_video_on_cmd430},
-{ 0x8 , nt35590_720p_video_on_cmd431},
-{ 0x8 , nt35590_720p_video_on_cmd432},
-{ 0x8 , nt35590_720p_video_on_cmd433},
-{ 0x8 , nt35590_720p_video_on_cmd434},
-{ 0x8 , nt35590_720p_video_on_cmd435},
-{ 0x8 , nt35590_720p_video_on_cmd436},
-{ 0x8 , nt35590_720p_video_on_cmd437},
-{ 0x8 , nt35590_720p_video_on_cmd438},
-{ 0x8 , nt35590_720p_video_on_cmd439},
-{ 0x8 , nt35590_720p_video_on_cmd440},
-{ 0x8 , nt35590_720p_video_on_cmd441},
-{ 0x8 , nt35590_720p_video_on_cmd442},
-{ 0x8 , nt35590_720p_video_on_cmd443},
-{ 0x8 , nt35590_720p_video_on_cmd444},
-{ 0x8 , nt35590_720p_video_on_cmd445},
-{ 0x8 , nt35590_720p_video_on_cmd446},
-{ 0x8 , nt35590_720p_video_on_cmd447},
-{ 0x8 , nt35590_720p_video_on_cmd448},
-{ 0x8 , nt35590_720p_video_on_cmd449},
-{ 0x8 , nt35590_720p_video_on_cmd450},
-{ 0x8 , nt35590_720p_video_on_cmd451},
-{ 0x8 , nt35590_720p_video_on_cmd452},
-{ 0x8 , nt35590_720p_video_on_cmd453},
-{ 0x8 , nt35590_720p_video_on_cmd454},
-{ 0x8 , nt35590_720p_video_on_cmd455},
-{ 0x8 , nt35590_720p_video_on_cmd456},
-{ 0x8 , nt35590_720p_video_on_cmd457},
-{ 0x8 , nt35590_720p_video_on_cmd458},
-{ 0x8 , nt35590_720p_video_on_cmd459},
-{ 0x8 , nt35590_720p_video_on_cmd460},
-{ 0x8 , nt35590_720p_video_on_cmd461},
-{ 0x8 , nt35590_720p_video_on_cmd462},
-{ 0x8 , nt35590_720p_video_on_cmd463}
+{ 0x8 , nt35590_720p_video_on_cmd0, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd1, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd2, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd3, 0x10},
+{ 0x8 , nt35590_720p_video_on_cmd4, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd5, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd6, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd7, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd8, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd9, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd10, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd11, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd12, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd13, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd14, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd15, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd16, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd17, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd18, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd19, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd20, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd21, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd22, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd23, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd24, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd25, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd26, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd27, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd28, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd29, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd30, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd31, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd32, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd33, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd34, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd35, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd36, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd37, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd38, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd39, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd40, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd41, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd42, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd43, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd44, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd45, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd46, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd47, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd48, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd49, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd50, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd51, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd52, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd53, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd54, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd55, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd56, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd57, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd58, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd59, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd60, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd61, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd62, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd63, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd64, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd65, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd66, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd67, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd68, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd69, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd70, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd71, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd72, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd73, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd74, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd75, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd76, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd77, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd78, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd79, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd80, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd81, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd82, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd83, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd84, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd85, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd86, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd87, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd88, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd89, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd90, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd91, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd92, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd93, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd94, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd95, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd96, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd97, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd98, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd99, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd100, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd101, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd102, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd103, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd104, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd105, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd106, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd107, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd108, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd109, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd110, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd111, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd112, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd113, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd114, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd115, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd116, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd117, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd118, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd119, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd120, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd121, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd122, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd123, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd124, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd125, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd126, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd127, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd128, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd129, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd130, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd131, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd132, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd133, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd134, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd135, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd136, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd137, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd138, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd139, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd140, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd141, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd142, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd143, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd144, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd145, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd146, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd147, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd148, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd149, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd150, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd151, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd152, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd153, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd154, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd155, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd156, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd157, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd158, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd159, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd160, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd161, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd162, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd163, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd164, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd165, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd166, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd167, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd168, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd169, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd170, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd171, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd172, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd173, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd174, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd175, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd176, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd177, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd178, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd179, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd180, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd181, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd182, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd183, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd184, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd185, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd186, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd187, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd188, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd189, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd190, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd191, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd192, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd193, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd194, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd195, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd196, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd197, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd198, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd199, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd200, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd201, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd202, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd203, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd204, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd205, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd206, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd207, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd208, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd209, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd210, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd211, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd212, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd213, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd214, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd215, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd216, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd217, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd218, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd219, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd220, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd221, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd222, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd223, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd224, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd225, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd226, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd227, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd228, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd229, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd230, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd231, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd232, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd233, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd234, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd235, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd236, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd237, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd238, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd239, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd240, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd241, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd242, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd243, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd244, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd245, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd246, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd247, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd248, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd249, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd250, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd251, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd252, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd253, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd254, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd255, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd256, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd257, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd258, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd259, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd260, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd261, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd262, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd263, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd264, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd265, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd266, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd267, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd268, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd269, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd270, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd271, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd272, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd273, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd274, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd275, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd276, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd277, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd278, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd279, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd280, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd281, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd282, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd283, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd284, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd285, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd286, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd287, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd288, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd289, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd290, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd291, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd292, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd293, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd294, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd295, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd296, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd297, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd298, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd299, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd300, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd301, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd302, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd303, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd304, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd305, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd306, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd307, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd308, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd309, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd310, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd311, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd312, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd313, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd314, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd315, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd316, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd317, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd318, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd319, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd320, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd321, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd322, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd323, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd324, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd325, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd326, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd327, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd328, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd329, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd330, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd331, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd332, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd333, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd334, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd335, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd336, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd337, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd338, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd339, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd340, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd341, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd342, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd343, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd344, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd345, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd346, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd347, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd348, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd349, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd350, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd351, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd352, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd353, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd354, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd355, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd356, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd357, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd358, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd359, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd360, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd361, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd362, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd363, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd364, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd365, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd366, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd367, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd368, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd369, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd370, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd371, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd372, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd373, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd374, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd375, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd376, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd377, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd378, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd379, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd380, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd381, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd382, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd383, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd384, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd385, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd386, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd387, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd388, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd389, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd390, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd391, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd392, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd393, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd394, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd395, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd396, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd397, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd398, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd399, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd400, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd401, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd402, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd403, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd404, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd405, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd406, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd407, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd408, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd409, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd410, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd411, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd412, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd413, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd414, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd415, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd416, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd417, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd418, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd419, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd420, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd421, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd422, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd423, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd424, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd425, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd426, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd427, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd428, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd429, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd430, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd431, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd432, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd433, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd434, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd435, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd436, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd437, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd438, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd439, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd440, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd441, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd442, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd443, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd444, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd445, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd446, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd447, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd448, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd449, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd450, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd451, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd452, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd453, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd454, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd455, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd456, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd457, 0x64},
+{ 0x8 , nt35590_720p_video_on_cmd458, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd459, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd460, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd461, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd462, 0x00},
+{ 0x8 , nt35590_720p_video_on_cmd463, 0x78},
+{ 0x8 , nt35590_720p_video_on_cmd464, 0x00},
+{ 0xc , nt35590_720p_video_on_cmd465, 0x00}
};
-#define NT35590_720P_VIDEO_ON_COMMAND 464
+#define NT35590_720P_VIDEO_ON_COMMAND 466
static char nt35590_720p_videooff_cmd0[] = {
@@ -2869,8 +2882,8 @@
static struct mipi_dsi_cmd nt35590_720p_video_off_command[] = {
-{ 0x4 , nt35590_720p_videooff_cmd0},
-{ 0x4 , nt35590_720p_videooff_cmd1}
+{ 0x4 , nt35590_720p_videooff_cmd0, 0x32},
+{ 0x4 , nt35590_720p_videooff_cmd1, 0x78}
};
#define NT35590_720P_VIDEO_OFF_COMMAND 2
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index 5deaecf..f9593a4 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -271,9 +271,13 @@
return;
}
+ /* bits 0:15 of BAM_P_EVNT_REGn denotes the offset. We read the offset,
+ * and update the offset to notify BAM HW that new descriptors have been written
+ */
+ val = readl(BAM_P_EVNT_REGn(bam->pipe[pipe_num].pipe_num, bam->base));
+
/* Update the fifo peer offset */
- val = (num_desc - 1) * BAM_DESC_SIZE;
- val += bam->pipe[pipe_num].fifo.offset;
+ val += (num_desc) * BAM_DESC_SIZE;
val &= (bam->pipe[pipe_num].fifo.size * BAM_DESC_SIZE - 1);
writel(val, BAM_P_EVNT_REGn(bam->pipe[pipe_num].pipe_num, bam->base));
@@ -282,9 +286,11 @@
/* Function to read the updates for FIFO offsets.
* bam : BAM that uses the FIFO.
* pipe : BAM pipe that uses the FIFO.
- * return : FIFO offset where the next descriptor should be written.
- * Note : S/W maintains the circular properties of the FIFO and updates
- * the offsets accordingly.
+ * return : void.
+ * Note : As per IPCAT This register denotes the pointer Offset of the first un-Acknowledged Descriptor.
+ * This register is only used by the Software. After receiving an interrupt, software reads this register
+ * in order to know what descriptors has been processed. Although being Writable, Software
+ * should never write to this register.
*/
void bam_read_offset_update(struct bam_instance *bam, unsigned int pipe_num)
{
@@ -294,12 +300,6 @@
offset &= 0xFFFF;
dprintf(SPEW, "Offset value is %d \n", offset);
-
- /* Save the next offset to be written to. */
- bam->pipe[pipe_num].fifo.current = (struct bam_desc*)
- ((uint32_t)bam->pipe[pipe_num].fifo.head + offset);
-
- bam->pipe[pipe_num].fifo.offset = offset + BAM_DESC_SIZE ;
}
/* Function to get the next desc address.
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 161a2ea..48baa8f 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -88,7 +88,7 @@
board.pmic_info[0].pmic_type = board_info_v7.pmic_type;
board.pmic_info[0].pmic_version = board_info_v7.pmic_version;
}
- else if (format == 8)
+ else if (format == 8 || format == 9)
{
board_info_len = sizeof(board_info_v8);
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index 0c86597..f638e37 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -1352,6 +1352,10 @@
uint32_t status;
uint32_t i;
int nand_ret = NANDC_RESULT_SUCCESS;
+ uint8_t flags = 0;
+ uint32_t *cmd_list_temp = NULL;
+
+ uint32_t temp_status = 0;
/* UD bytes in last CW is 512 - cws_per_page *4.
* Since each of the CW read earlier reads 4 spare bytes.
*/
@@ -1384,6 +1388,8 @@
/* Reset and Configure erased CW/page detection controller */
qpic_nand_erased_status_reset(ce_array, BAM_DESC_LOCK_FLAG);
+ /* Queue up the command and data descriptors for all the codewords in a page
+ * and do a single bam transfer at the end.*/
for (i = 0; i < flash.cws_per_page; i++)
{
num_cmd_desc = 0;
@@ -1436,7 +1442,7 @@
DATA_PRODUCER_PIPE_INDEX,
(unsigned char *)PA((addr_t)buffer),
DATA_BYTES_IN_IMG_PER_CW,
- BAM_DESC_INT_FLAG);
+ 0);
num_data_desc++;
bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc);
}
@@ -1454,39 +1460,57 @@
CE_WRITE_TYPE);
cmd_list_ptr++;
- /* Enqueue the desc for the above commands */
- bam_add_one_desc(&bam,
+ /* Enqueue the desc for the above commands */
+ bam_add_one_desc(&bam,
CMD_PIPE_INDEX,
(unsigned char*)cmd_list_ptr_start,
PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
- BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG);
- num_cmd_desc++;
+ BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG);
+ num_cmd_desc++;
- qpic_nand_wait_for_cmd_exec(num_cmd_desc);
+ bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE);
+
+ cmd_list_temp = cmd_list_ptr;
+
+ cmd_list_ptr++;
+
+ bam_add_cmd_element(cmd_list_ptr, NAND_BUFFER_STATUS, (uint32_t)PA((addr_t)&(buffer_sts[i])), CE_READ_TYPE);
+ cmd_list_ptr++;
+
+ if (i == flash.cws_per_page - 1)
+ {
+ flags = BAM_DESC_CMD_FLAG | BAM_DESC_UNLOCK_FLAG;
+ }
+ else
+ flags = BAM_DESC_CMD_FLAG;
+
+ /* Enqueue the desc for the above command */
+ bam_add_one_desc(&bam,
+ CMD_PIPE_INDEX,
+ (unsigned char*)PA((addr_t)cmd_list_temp),
+ PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_temp),
+ flags);
+ num_cmd_desc++;
+
+ buffer += DATA_BYTES_IN_IMG_PER_CW;
+
+ /* Notify BAM HW about the newly added descriptors */
+ bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_cmd_desc);
+ }
qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX);
- /* Save the status registers. */
- flash_sts[i] = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++);
- buffer_sts[i] = qpic_nand_read_reg(NAND_BUFFER_STATUS, 0, cmd_list_ptr++);
-
- flash_sts[i] = qpic_nand_check_status(flash_sts[i]);
-
- buffer += DATA_BYTES_IN_IMG_PER_CW;
- }
-
- /* Read the buffer status again so that we can unlock the bam with this desc. */
- buffer_sts[--i] = qpic_nand_read_reg(NAND_BUFFER_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr++);
-
/* Check status */
for (i = 0; i < flash.cws_per_page ; i ++)
+ {
+ flash_sts[i] = qpic_nand_check_status(flash_sts[i]);
if (flash_sts[i])
{
nand_ret = NANDC_RESULT_BAD_PAGE;
- dprintf(CRITICAL, "NAND page read failed. page: %x\n", page);
+ dprintf(CRITICAL, "NAND page read failed. page: %x status %x\n", page, flash_sts[i]);
goto qpic_nand_read_page_error;
}
-
+ }
qpic_nand_read_page_error:
return nand_ret;
}
@@ -1558,8 +1582,11 @@
return NANDC_RESULT_SUCCESS;
}
- result = qpic_nand_read_page(page, rdwr_buf, (unsigned char *)spare);
-
+#if CONTIGUOUS_MEMORY
+ result = qpic_nand_read_page(page, image, (unsigned char *) spare);
+#else
+ result = qpic_nand_read_page(page, rdwr_buf, (unsigned char *) spare);
+#endif
if (result == NANDC_RESULT_BAD_PAGE)
{
/* bad page, go to next page. */
@@ -1575,14 +1602,19 @@
continue;
}
+#ifndef CONTIGUOUS_MEMORY
/* Copy the read page into correct location. */
memcpy(image, rdwr_buf, flash.page_size);
-
+#endif
page++;
image += flash.page_size;
/* Copy spare bytes to image */
- memcpy(image, spare, extra_per_page);
- image += extra_per_page;
+ if(extra_per_page)
+ {
+ memcpy(image, spare, extra_per_page);
+ image += extra_per_page;
+ }
+
count -= 1;
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 1b10150..096336b 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -343,6 +343,30 @@
$(LOCAL_DIR)/dload_util.o
endif
+ifeq ($(PLATFORM),msmplutonium)
+ OBJS += $(LOCAL_DIR)/qgic.o \
+ $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/ufs.o \
+ $(LOCAL_DIR)/utp.o \
+ $(LOCAL_DIR)/uic.o \
+ $(LOCAL_DIR)/ucs.o \
+ $(LOCAL_DIR)/ufs_hci.o \
+ $(LOCAL_DIR)/dme.o
+endif
+
ifeq ($(ENABLE_USB30_SUPPORT),1)
OBJS += \
$(LOCAL_DIR)/usb30_dwc.o \
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index c62bf1e..1e533f9 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -328,6 +328,7 @@
MSM8926 = 200,
MSM8326 = 205,
MSM8916 = 206,
+ MSMPLUTONIUM = 207,
APQ8074AA = 208,
APQ8074AB = 209,
APQ8074AC = 210,
diff --git a/platform/msmplutonium/acpuclock.c b/platform/msmplutonium/acpuclock.c
new file mode 100644
index 0000000..c90718e
--- /dev/null
+++ b/platform/msmplutonium/acpuclock.c
@@ -0,0 +1,207 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <reg.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+void hsusb_clock_init(void)
+{
+ int ret;
+ struct clk *iclk, *cclk;
+
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for the clocks to be stable since we are disabling soon after. */
+ mdelay(1);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ /* Wait for the clock disable to complete. */
+ mdelay(1);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ /* Wait for reset to complete. */
+ mdelay(1);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ /* Wait for the block to be brought out of reset. */
+ mdelay(1);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ int ret;
+ uint32_t reg;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+}
+
+/* Function to asynchronously reset CE (Crypto Engine).
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
diff --git a/platform/msmplutonium/gpio.c b/platform/msmplutonium/gpio.c
new file mode 100644
index 0000000..28aa739
--- /dev/null
+++ b/platform/msmplutonium/gpio.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+/* Remove the file after the gpio patch to move this to msm_shared gets merged. */
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+ return;
+}
+
+/* Configure gpio for blsp uart */
+void gpio_config_uart_dm(uint8_t id)
+{
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/msmplutonium/include/platform/clock.h b/platform/msmplutonium/include/platform/clock.h
new file mode 100644
index 0000000..df24dc9
--- /dev/null
+++ b/platform/msmplutonium/include/platform/clock.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSMPLUTONIUM_CLOCK_H
+#define __MSMPLUTONIUM_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void mdp_clock_init(void);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+
+#endif
diff --git a/platform/msmplutonium/include/platform/gpio.h b/platform/msmplutonium/include/platform/gpio.h
new file mode 100644
index 0000000..01929ec
--- /dev/null
+++ b/platform/msmplutonium/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSMPLUTONIUM_GPIO_H
+#define __PLATFORM_MSMPLUTONIUM_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/msmplutonium/include/platform/iomap.h b/platform/msmplutonium/include/platform/iomap.h
new file mode 100644
index 0000000..df7a769
--- /dev/null
+++ b/platform/msmplutonium/include/platform/iomap.h
@@ -0,0 +1,171 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSMPLUTONIUM_IOMAP_H_
+#define _PLATFORM_MSMPLUTONIUM_IOMAP_H_
+
+#define MSM_SHARED_BASE 0x0FA00000
+
+
+#define MSM_IOMAP_BASE 0xF9000000
+#define MSM_IOMAP_END 0xFEFFFFFF
+
+#define SYSTEM_IMEM_BASE 0xFE800000
+#define MSM_SHARED_IMEM_BASE 0xFE87F000
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+
+#define KPSS_BASE 0xF9000000
+
+#define MSM_GIC_DIST_BASE KPSS_BASE
+#define MSM_GIC_CPU_BASE (KPSS_BASE + 0x00002000)
+#define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000)
+#define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000)
+#define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000)
+#define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000)
+#define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000)
+#define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000)
+#define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE 0xF9800000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
+#define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000)
+#define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
+#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+
+#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+
+/* Clocks */
+#define CLK_CTL_BASE 0xFC400000
+
+/* GPLL */
+#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
+#define GPLL4_MODE (CLK_CTL_BASE + 0x1DC0)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+
+/* UART */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
+
+/* USB */
+#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
+
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+
+/* SDCC */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* SDCC3 */
+#define SDCC3_BCR (CLK_CTL_BASE + 0x540) /* block reset */
+#define SDCC3_APPS_CBCR (CLK_CTL_BASE + 0x544) /* branch control */
+#define SDCC3_AHB_CBCR (CLK_CTL_BASE + 0x548)
+#define SDCC3_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x54C)
+#define SDCC3_CMD_RCGR (CLK_CTL_BASE + 0x550) /* cmd */
+#define SDCC3_CFG_RCGR (CLK_CTL_BASE + 0x554) /* cfg */
+#define SDCC3_M (CLK_CTL_BASE + 0x558) /* m */
+#define SDCC3_N (CLK_CTL_BASE + 0x55C) /* n */
+#define SDCC3_D (CLK_CTL_BASE + 0x560) /* d */
+
+
+#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
+
+#define UFS_BASE (0xFC590000 + 0x00004000)
+
+#define SPMI_BASE 0xFC4C0000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
+
+#define MSM_CE2_BAM_BASE 0xFD444000
+#define MSM_CE2_BASE 0xFD45A000
+
+#define TLMM_BASE_ADDR 0xFD510000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE 0xFC4A1000
+#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* Boot config */
+#define SEC_CTRL_CORE_BASE 0xFC4B8000
+#define BOOT_CONFIG_OFFSET 0x00006034
+#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
+
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
+
+#endif
diff --git a/platform/msmplutonium/include/platform/irqs.h b/platform/msmplutonium/include/platform/irqs.h
new file mode 100644
index 0000000..a3064d7
--- /dev/null
+++ b/platform/msmplutonium/include/platform/irqs.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_MSMPLUTONIUM_H
+#define __IRQS_MSMPLUTONIUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
+
+#define USB1_HS_IRQ (GIC_SPI_START + 134)
+
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#define SDCC3_PWRCTL_IRQ (GIC_SPI_START + 224)
+#define SDCC4_PWRCTL_IRQ (GIC_SPI_START + 227)
+
+#define UFS_IRQ (GIC_SPI_START + 265)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#endif /* __IRQS_MSMPLUTONIUM_H */
diff --git a/platform/msmplutonium/msmplutonium-clock.c b/platform/msmplutonium/msmplutonium-clock.c
new file mode 100644
index 0000000..06a6a8b
--- /dev/null
+++ b/platform/msmplutonium/msmplutonium-clock.c
@@ -0,0 +1,346 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define gpll4_source_val 5
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(4),
+ .status_reg = (void *) GPLL4_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1600000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp2_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(15),
+
+ .c = {
+ .dbg_name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F( 96000000, gpll4, 16, 0, 0),
+ F(192000000, gpll4, 8, 0, 0),
+ F(384000000, gpll4, 4, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_plutonium[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_plutonium, ARRAY_SIZE(msm_clocks_plutonium));
+}
diff --git a/platform/msmplutonium/platform.c b/platform/msmplutonium/platform.c
new file mode 100644
index 0000000..229ee9c
--- /dev/null
+++ b/platform/msmplutonium/platform.c
@@ -0,0 +1,168 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+#if DISPLAY_SPLASH_SCREEN
+ display_shutdown();
+#endif
+
+ qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ ram_partition ptn_entry;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
diff --git a/platform/msmplutonium/rules.mk b/platform/msmplutonium/rules.mk
new file mode 100644
index 0000000..d86f57d
--- /dev/null
+++ b/platform/msmplutonium/rules.mk
@@ -0,0 +1,28 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msmplutonium-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/project/mdm9635.mk b/project/mdm9635.mk
index eec4abe..7a246d2 100644
--- a/project/mdm9635.mk
+++ b/project/mdm9635.mk
@@ -12,7 +12,7 @@
DEFINES += WITH_DEBUG_UART=1
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
-
+DEFINES += CONTIGUOUS_MEMORY=1
#disable Thumb mode for the codesourcery/arm-2011.03 toolchain
ENABLE_THUMB := false
diff --git a/project/plutonium.mk b/project/plutonium.mk
new file mode 100644
index 0000000..b343a5d
--- /dev/null
+++ b/project/plutonium.mk
@@ -0,0 +1,37 @@
+# top level project rules for the msmplutonium project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msmplutonium
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_UFS_SUPPORT := 1
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00080000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_UFS_SUPPORT),1)
+DEFINES += UFS_SUPPORT=1
+endif
diff --git a/target/msmplutonium/init.c b/target/msmplutonium/init.c
new file mode 100644
index 0000000..a057df7
--- /dev/null
+++ b/target/msmplutonium/init.c
@@ -0,0 +1,361 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <pm8x41.h>
+#include <crypto5_wrapper.h>
+#include <hsusb.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <platform/timer.h>
+#include <stdlib.h>
+#include <ufs.h>
+
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+
+#define FASTBOOT_MODE 0x77665500
+
+#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1)
+
+static void set_sdc_power_ctrl(void);
+static uint32_t mmc_pwrctl_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+struct mmc_device *dev;
+struct ufs_dev ufs_device;
+
+extern void ulpi_write(unsigned val, unsigned reg);
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(2, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+ struct pm8x41_gpio gpio;
+
+ /* Configure the GPIO */
+ gpio.direction = PM_GPIO_DIR_IN;
+ gpio.function = 0;
+ gpio.pull = PM_GPIO_PULL_UP_30;
+ gpio.vin_sel = 2;
+
+ pm8x41_gpio_config(3, &gpio);
+
+ /* Wait for the pmic gpio config to take effect */
+ thread_sleep(1);
+
+ /* Get status of P_GPIO_5 */
+ pm8x41_gpio_get(3, &status);
+
+ return !status; /* active low */
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ return pm8x41_resin_status();
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+void target_uninit(void)
+{
+ if (target_is_emmc_boot())
+ mmc_put_card_to_sleep(dev);
+}
+
+/* Do target specific usb initialization */
+void target_usb_init(void)
+{
+ uint32_t val;
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+}
+
+void target_usb_stop(void)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+void target_sdc_init()
+{
+ struct mmc_config_data config;
+
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
+
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_192MHZ;
+
+ /* Try slot 1*/
+ config.slot = 1;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
+ {
+ /* Try slot 2 */
+ config.slot = 2;
+ config.max_clk_rate = MMC_CLK_200MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
+ {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+}
+
+static uint32_t boot_device;
+static uint32_t target_read_boot_config()
+{
+ uint32_t val;
+
+ val = readl(BOOT_CONFIG_REG);
+
+ val = BOOT_DEVICE_MASK(val);
+
+ return val;
+}
+
+uint32_t target_get_boot_device()
+{
+ return boot_device;
+}
+
+/*
+ * Return 1 if boot from emmc else 0
+ */
+uint32_t target_boot_device_emmc()
+{
+ uint32_t boot_dev_type;
+
+ boot_dev_type = target_get_boot_device();
+
+ if (boot_dev_type == BOOT_EMMC || boot_dev_type == BOOT_DEFAULT)
+ boot_dev_type = 1;
+ else
+ boot_dev_type = 0;
+
+ return boot_dev_type;
+}
+
+void *target_mmc_device()
+{
+ if (target_boot_device_emmc())
+ return (void *) dev;
+ else
+ return (void *) &ufs_device;
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ boot_device = target_read_boot_config();
+
+ if (target_boot_device_emmc())
+ {
+ target_sdc_init();
+ }
+ else
+ {
+ ufs_device.base = UFS_BASE;
+ ufs_init(&ufs_device);
+ }
+
+ /* Storage initialization is complete, read the partition table info */
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+}
+
+unsigned board_machtype(void)
+{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ /* This is filled from board.c */
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+
+ switch(platform) {
+ case MSMPLUTONIUM:
+ board->baseband = BASEBAND_MSM;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ };
+}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+ unsigned int serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned check_reboot_mode(void)
+{
+ uint32_t restart_reason = 0;
+ uint32_t restart_reason_addr;
+
+ restart_reason_addr = RESTART_REASON_ADDR;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(restart_reason_addr);
+ writel(0x00, restart_reason_addr);
+
+ return restart_reason;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ uint8_t reset_type = 0;
+
+ /* Write the reboot reason */
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ if(reboot_reason == FASTBOOT_MODE)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
diff --git a/target/msmplutonium/meminfo.c b/target/msmplutonium/meminfo.c
new file mode 100644
index 0000000..cb8c726
--- /dev/null
+++ b/target/msmplutonium/meminfo.c
@@ -0,0 +1,88 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ ram_partition ptn_entry;
+ unsigned int index;
+ int ret = 0;
+ uint32_t len = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Calculating the size of the mem_info_ptr */
+ for (index = 0 ; index < len; index++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ptn_entry.start,
+ ptn_entry.size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n"
+);
+ goto target_dev_tree_mem_err;
+ }
+
+ }
+ }
+
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
diff --git a/target/msmplutonium/rules.mk b/target/msmplutonium/rules.mk
new file mode 100644
index 0000000..23604ae
--- /dev/null
+++ b/target/msmplutonium/rules.mk
@@ -0,0 +1,36 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := msmplutonium
+
+MEMBASE := 0x0F900000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x0000000
+
+SCRATCH_ADDR := 0x10000000
+
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
+MODULES += \
+ dev/keys \
+ dev/pmic/pm8x41 \
+ lib/ptable \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ TAGS_ADDR=$(TAGS_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o \
diff --git a/target/msmplutonium/tools/makefile b/target/msmplutonium/tools/makefile
new file mode 100644
index 0000000..8297318
--- /dev/null
+++ b/target/msmplutonium/tools/makefile
@@ -0,0 +1,13 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTOUT_DIR := $(BUILDDIR)
+else
+APPSBOOTOUT_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+ABOOTMBN := emmc_appsboot.mbn
+APPSBOOTHEADER: $(ABOOTMBN)
+
+$(ABOOTMBN): $(OUTELF_STRIP)
+ $(hide) cp -f $(OUTELF_STRIP) $(APPSBOOTOUT_DIR)/$(ABOOTMBN)