Merge "platform: msm_shared: Add Ping Pong register offsets for MDP"
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index f3629e7..d0c4f42 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -114,4 +114,85 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+
+/* MDSS */
+#define MIPI_DSI_BASE (0x1AC8000)
+#define MIPI_DSI0_BASE MIPI_DSI_BASE
+#define MIPI_DSI1_BASE MIPI_DSI_BASE
+#define DSI0_PHY_BASE (0x1AC8500)
+#define DSI1_PHY_BASE DSI0_PHY_BASE
+#define DSI0_PLL_BASE (0x1AC8300)
+#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+
+
+/* MDP */
+#define MDP_BASE 0x1A00000
+#define REG_MDP(off) (MDP_BASE + (off))
+
+#define MDP_DMA_P_CONFIG REG_MDP(0x90000)
+#define MDP_DMA_P_OUT_XY REG_MDP(0x90010)
+#define MDP_DMA_P_SIZE REG_MDP(0x90004)
+#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
+#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
+
+#define MDP_DSI_VIDEO_EN REG_MDP(0xF0000)
+#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xF0004)
+#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xF0008)
+#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH REG_MDP(0xF000C)
+#define MDP_DSI_VIDEO_DISPLAY_HCTL REG_MDP(0xF0010)
+#define MDP_DSI_VIDEO_DISPLAY_V_START REG_MDP(0xF0014)
+#define MDP_DSI_VIDEO_DISPLAY_V_END REG_MDP(0xF0018)
+#define MDP_DSI_VIDEO_BORDER_CLR REG_MDP(0xF0028)
+#define MDP_DSI_VIDEO_HSYNC_SKEW REG_MDP(0xF0030)
+#define MDP_DSI_VIDEO_CTL_POLARITY REG_MDP(0xF0038)
+#define MDP_DSI_VIDEO_TEST_CTL REG_MDP(0xF0034)
+
+#define MDP_DMA_P_START REG_MDP(0x00044)
+#define MDP_DMA_S_START REG_MDP(0x00048)
+#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
+#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
+#define MDP_INTR_ENABLE REG_MDP(0x00020)
+#define MDP_INTR_CLEAR REG_MDP(0x00028)
+#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0xF1000)
+#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0XF1004)
+
+#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
+#define MDP_INTR_STATUS REG_MDP(0x00054)
+
+#define SOFT_RESET 0x118
+#define CLK_CTRL 0x11C
+#define TRIG_CTRL 0x084
+#define CTRL 0x004
+#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
+#define ERR_INT_MASK0 0x10C
+
+#define LANE_SWAP_CTL 0x0B0
+#define TIMING_CTL 0x0C4
+
+#define VIDEO_MODE_ACTIVE_H 0x024
+#define VIDEO_MODE_ACTIVE_V 0x028
+#define VIDEO_MODE_TOTAL 0x02C
+#define VIDEO_MODE_HSYNC 0x030
+#define VIDEO_MODE_VSYNC 0x034
+#define VIDEO_MODE_VSYNC_VPOS 0x038
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
+
#endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 9596622..c815bd0 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -43,9 +43,14 @@
#define SDRAM_START_ADDR 0x80000000
#define MSM_SHARED_BASE 0x86300000
-
#define APPS_SS_BASE 0x0B000000
+#define DDR_START get_ddr_start()
+#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
+#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
+#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
+#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
+
#define MSM_GIC_DIST_BASE APPS_SS_BASE
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index 4deaa1b..7e583c6 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -52,7 +52,7 @@
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* IMEM memory - cacheable, write through */
-#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
static mmu_section_t mmu_section_table[] = {
@@ -60,7 +60,10 @@
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
{ MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
{ A53_SS_BASE, A53_SS_BASE, A53_SS_SIZE, IOMAP_MEMORY},
- { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
+ { BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
};
static struct smem_ram_ptable ram_ptable;
@@ -114,39 +117,6 @@
uint32_t i;
uint32_t sections;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- ram_partition ptn_entry;
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
@@ -216,3 +186,30 @@
else
return MSM_SHARED_BASE;
}
+uint32_t get_ddr_start()
+{
+ uint32_t i;
+ ram_partition ptn_entry;
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Determine the Start addr of the DDR RAM */
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+ return ptn_entry.start;
+ }
+ }
+ }
+ ASSERT("DDR Start Mem Not found\n");
+}
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 932331b..341c0a6 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -296,8 +296,8 @@
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
-#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x13d8)
-#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x13dc)
+#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
+#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index f9593a4..00abeda 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -90,14 +90,6 @@
/* Flush out the right most global interrupt bit */
} while (!((val & 0x7FFF) & (1 << bam->pipe[pipe_num].pipe_num)));
- /* Check the reason for this BAM interrupt */
- bamsts = readl(BAM_IRQ_STTS(bam->base));
- if (bamsts)
- {
- dprintf(CRITICAL,"ERROR:BAM_IRQ_STTS %u \n", bamsts);
- goto bam_wait_int_error;
- }
-
/* Check the interrupt type */
/* Read interrupt status register */
val = readl(BAM_P_IRQ_STTSn(bam->pipe[pipe_num].pipe_num, bam->base));
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index fdc8553..fbbe62b 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -150,11 +150,11 @@
}
/* HLOS subtype
- * bit no |31 16 | 15 8 | 7 0|
- * board.platform_hlos_subtype = |reserved | DDR detection | subtype|
- * | bits | bits | |
+ * bit no |31 20 | 19 16| 15 8 | 7 0|
+ * board.platform_hlos_subtype = |reserved | Boot device | DDR detection | subtype|
+ * | bits | | bits |
*/
- board.platform_hlos_subtype = board_get_ddr_subtype() << 8;
+ board.platform_hlos_subtype = (board_get_ddr_subtype() << 8) | (platform_get_boot_dev() << 16);
}
else
{
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index 849b294..9681de0 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -78,7 +78,8 @@
dprintf(INFO, "Config MIPI_VIDEO_PANEL.\n");
mdp_rev = mdp_get_revision();
- if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
+ if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304 ||
+ mdp_rev == MDP_REV_305)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
@@ -96,7 +97,8 @@
case MIPI_CMD_PANEL:
dprintf(INFO, "Config MIPI_CMD_PANEL.\n");
mdp_rev = mdp_get_revision();
- if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
+ if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304 ||
+ mdp_rev == MDP_REV_305)
ret = mdss_dsi_config(panel);
else
ret = mipi_config(panel);
@@ -180,7 +182,8 @@
if (ret)
goto msm_display_on_out;
mdp_rev = mdp_get_revision();
- if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304) {
+ if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304 &&
+ mdp_rev != MDP_REV_305) {
ret = mipi_cmd_trigger();
if (ret)
goto msm_display_on_out;
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 670d344..2571763 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -151,6 +151,51 @@
return ret;
}
+int dme_set_fpoweronwpen(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ uint32_t try_again = DME_FPOWERONWPEN_RETRIES;
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+
+
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+
+ if (*result == 1)
+ goto utp_set_fpoweronwpen_done;
+
+ do
+ {
+ try_again--;
+ dprintf(CRITICAL, "Power on Write Protect request failed. Retrying again.\n");
+
+ if (dme_send_query_upiu(dev, &set_query))
+ return -UFS_FAILURE;
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ if (*result == 1)
+ break;
+ } while (try_again);
+
+utp_set_fpoweronwpen_done:
+ dprintf(INFO,"Power on Write Protect status: %u\n", *result);
+ return UFS_SUCCESS;
+}
+
int dme_set_fdeviceinit(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 31be6c5..c9ac677 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,7 @@
/* Retry value for commands. */
#define DME_NOP_NUM_RETRIES 20
#define DME_FDEVICEINIT_RETRIES 20
+#define DME_FPOWERONWPEN_RETRIES 20
/* Timeout value for commands. */
#define DME_NOP_QUERY_TIMEOUT 10
@@ -221,6 +222,7 @@
struct upiu_req_build_type *upiu_data);
int dme_send_nop_query(struct ufs_dev *dev);
int dme_set_fdeviceinit(struct ufs_dev *dev);
+int dme_set_fpoweronwpen(struct ufs_dev *dev);
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 254e767..8e17def 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -81,6 +81,7 @@
#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
+#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDSS_MAX_LINE_BUF_WIDTH 2048
@@ -123,6 +124,7 @@
#define MDP_INTF_2_BASE REG_MDP(0x12900)
#define MDP_INTF_3_BASE REG_MDP(0x12B00)
+#define MDP_INTF_CONFIG 0x04
#define MDP_HSYNC_CTL 0x08
#define MDP_VSYNC_PERIOD_F0 0x0C
#define MDP_VSYNC_PERIOD_F1 0x10
@@ -140,6 +142,7 @@
#define MDP_ACTIVE_V_END_F1 0x38
#define MDP_UNDERFFLOW_COLOR 0x48
#define MDP_PANEL_FORMAT 0x90
+#define MDP_PROG_FETCH_START 0x170
#define MDP_CLK_CTRL0 REG_MDP(0x03AC)
#define MDP_CLK_CTRL1 REG_MDP(0x03B4)
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 6befefd..c3497a8 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -63,6 +63,7 @@
MDP_REV_30,
MDP_REV_303,
MDP_REV_304,
+ MDP_REV_305,
MDP_REV_31,
MDP_REV_40,
MDP_REV_41,
diff --git a/platform/msm_shared/include/ufs.h b/platform/msm_shared/include/ufs.h
index bbe9a40..b5c76fc 100644
--- a/platform/msm_shared/include/ufs.h
+++ b/platform/msm_shared/include/ufs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -120,5 +120,6 @@
uint32_t ufs_get_serial_num(struct ufs_dev* dev);
uint8_t ufs_get_num_of_luns(struct ufs_dev* dev);
uint32_t ufs_get_erase_blk_size(struct ufs_dev* dev);
+void ufs_dump_is_register(struct ufs_dev* dev);
void ufs_dump_hc_registers(struct ufs_dev* dev);
#endif
diff --git a/platform/msm_shared/include/utp.h b/platform/msm_shared/include/utp.h
index 042c002..e7a6df9 100644
--- a/platform/msm_shared/include/utp.h
+++ b/platform/msm_shared/include/utp.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -145,5 +145,5 @@
int utp_enqueue_upiu(struct ufs_dev *dev, struct upiu_req_build_type *upiu_data);
void utp_process_req_completion(struct ufs_req_irq_type *irq);
-
+int utp_poll_utrd_complete(struct ufs_dev *dev);
#endif
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index b53b3d8..f466d26 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -60,7 +60,7 @@
lcdc->h_back_porch + 1;
vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
lcdc->v_back_porch + 1;
- if (mdp_rev == MDP_REV_304) {
+ if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
hsync_period += lcdc->h_pulse_width - 1;
vsync_period_intmd += lcdc->v_pulse_width - 1;
}
@@ -78,7 +78,7 @@
writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
writel(lcdc->v_pulse_width * hsync_period, \
MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- if (mdp_rev == MDP_REV_304) {
+ if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
writel((pinfo->xres + lcdc->h_back_porch + \
lcdc->h_pulse_width - 1) << 16 | \
lcdc->h_back_porch + lcdc->h_pulse_width, \
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 1c0f1aa..dd32038 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -40,6 +40,9 @@
#include <clock.h>
#include <scm.h>
+#define MDP_MIN_FETCH 9
+#define MDSS_MDP_MAX_FETCH 12
+
int restore_secure_cfg(uint32_t id);
static int mdp_rev;
@@ -121,11 +124,15 @@
*ctl1_reg_val = 0x24082;
break;
}
- /* For 8916/8939, MDP INTF registers are double buffered */
+ /* For targets from MDP v1.5, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108)) {
*ctl0_reg_val |= BIT(30);
- *ctl1_reg_val |= BIT(30);
+ *ctl1_reg_val |= BIT(31);
+ } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) {
+ *ctl0_reg_val |= BIT(30);
+ *ctl1_reg_val |= BIT(29);
}
}
@@ -442,6 +449,63 @@
writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
}
+void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
+ uint32_t intf_base)
+{
+ uint32_t mdp_hw_rev = readl(MDP_HW_REV);
+ uint32_t mdss_mdp_intf_off;
+ uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
+ uint32_t adjust_xres = 0;
+
+ struct lcdc_panel_info *lcdc = NULL;
+
+ if (pinfo == NULL)
+ return;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return;
+
+ /*
+ * MDP programmable fetch is for MDP with rev >= 1.05.
+ * Programmable fetch is not needed if vertical back porch
+ * is >= 9.
+ */
+ if (mdp_hw_rev < MDSS_MDP_HW_REV_105 ||
+ lcdc->v_back_porch >= MDP_MIN_FETCH)
+ return;
+
+ mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
+
+ adjust_xres = pinfo->xres;
+ if (pinfo->lcdc.split_display)
+ adjust_xres /= 2;
+
+ /*
+ * Fetch should always be outside the active lines. If the fetching
+ * is programmed within active region, hardware behavior is unknown.
+ */
+ v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres +
+ lcdc->v_front_porch;
+ h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres +
+ lcdc->h_front_porch;
+ vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres;
+
+ fetch_lines = v_total - vfp_start;
+
+ /*
+ * In some cases, vertical front porch is too high. In such cases limit
+ * the mdp fetch lines as the last 12 lines of vertical front porch.
+ */
+ if (fetch_lines > MDSS_MDP_MAX_FETCH)
+ fetch_lines = MDSS_MDP_MAX_FETCH;
+
+ fetch_start = (v_total - fetch_lines) * h_total + 1;
+
+ writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off);
+ writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off);
+}
+
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
*pinfo)
{
@@ -522,12 +586,15 @@
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_108) ||
- MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_105))
+ MDSS_MDP_HW_REV_108))
map = 0xE4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_103))
+ MDSS_MDP_HW_REV_105) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_109))
+ map = 0xA4;
+ else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_103))
map = 0xFA;
else
return;
@@ -551,11 +618,12 @@
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
- } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105)) {
- vbif_qos[0] = 2;
+ } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) {
+ vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
- vbif_qos[3] = 1;
+ vbif_qos[3] = 2;
} else {
return;
}
@@ -601,9 +669,12 @@
uint32_t reg;
mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
+ mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);
- if (pinfo->mipi.dual_dsi)
+ if (pinfo->mipi.dual_dsi) {
mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
+ mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
+ }
mdp_clk_gating_ctrl();
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 3878be3..2a29a7f 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -607,7 +607,8 @@
ctl_base + VIDEO_MODE_ACTIVE_V);
if (mdp_get_revision() >= MDP_REV_41 ||
- mdp_get_revision() == MDP_REV_304) {
+ mdp_get_revision() == MDP_REV_304 ||
+ mdp_get_revision() == MDP_REV_305) {
writel(((disp_height + vsync_porch0_fp
+ vsync_porch0_bp - 1) << 16)
| (disp_width + hsync_porch0_fp
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 276840b..c660a5f 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -357,6 +357,15 @@
blk_addr += unaligned_blks;
blk_count -= unaligned_blks;
+
+ head_unit = blk_addr / erase_unit_sz;
+ tail_unit = (blk_addr + blk_count - 1) / erase_unit_sz;
+
+ if (tail_unit - head_unit <= 1)
+ {
+ dprintf(INFO, "SDHCI unit erase not required\n");
+ return mmc_zero_out(dev, blk_addr, blk_count);
+ }
}
unaligned_blks = blk_count % erase_unit_sz;
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index f21e032..ecb5bbb 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -68,6 +68,7 @@
{0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
{0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
{0x9590DC2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590aa98, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 6675d67..fce33f2 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -31,6 +31,11 @@
#include <bits.h>
#include <debug.h>
+__WEAK int platform_is_msm8994()
+{
+ return 0;
+}
+
void qusb2_phy_reset(void)
{
uint32_t val;
@@ -61,7 +66,8 @@
/* Disable the PHY */
writel(0x23, QUSB2PHY_PORT_POWERDOWN);
/* Enable ULPI mode */
- writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
+ if (platform_is_msm8994())
+ writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
/* Enable PHY */
/* set CLAMP_N_EN and USB PHY is enabled*/
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index dd9d160..81e3f70 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -472,6 +472,11 @@
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
$(LOCAL_DIR)/i2c_qup.o
+ $(LOCAL_DIR)/mdp3.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
index 8244576..1897735 100644
--- a/platform/msm_shared/ufs.c
+++ b/platform/msm_shared/ufs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -81,7 +81,7 @@
writel(1, UFS_UTRLRSR(dev->base));
/* Enable the required irqs. */
- val = UFS_IE_UTRCE | UFS_IE_UEE | UFS_IE_UTMRCE | UFS_IE_UCCE ;
+ val = UFS_IE_UEE | UFS_IE_UCCE ;
ufs_irq_enable(dev, val);
}
@@ -266,6 +266,12 @@
return ret;
}
+void ufs_dump_is_register(struct ufs_dev *dev)
+{
+ uint32_t base = dev->base;
+ dprintf(CRITICAL,"UFS_IS 0x%x\n",readl(UFS_IS(base)));
+}
+
void ufs_dump_hc_registers(struct ufs_dev *dev)
{
uint32_t base = dev->base;
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index ccaa3b5..d8858b9 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -456,6 +456,7 @@
for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
{
dwc_ep_t *ep = &dev->ep[ep_index];
+ ASSERT(ep != NULL);
DBG("\n RESET on EP = %d while state = %s", ep_index,
ep_state_lookup[ep->state]);
@@ -489,7 +490,7 @@
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -573,7 +574,11 @@
uint8_t status = 0;
uint8_t trb_updated = 0;
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
+
dwc_trb_t *trb = ep->trb;
uint32_t num_of_trb = ep->trb_queued;
uint32_t bytes_remaining = 0;
@@ -641,7 +646,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -756,7 +761,7 @@
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -930,6 +935,8 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1011,7 +1018,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1085,7 +1092,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1164,7 +1171,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1239,7 +1246,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1289,7 +1296,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1373,7 +1380,7 @@
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
#endif
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1433,6 +1440,7 @@
*/
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index)
{
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
uint8_t ep_phy_num = dev->ep[index].phy_num;
dwc_ep_cmd_set_config(dev, index, SET_CONFIG_ACTION_INIT);
@@ -1455,6 +1463,7 @@
/* Control OUT */
index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dev->ep[index].number = 0;
dev->ep[index].dir = DWC_EP_DIRECTION_OUT;
@@ -1525,7 +1534,9 @@
/* entry function into inactive state for data transfer fsm */
static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
/* queue request to receive the first setup pkt from host */
ep->req.data = NULL;
@@ -1605,7 +1616,9 @@
{
uint8_t index = DWC_EP_INDEX(new_ep->number, new_ep->dir);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
memset(ep, 0, sizeof(ep));
@@ -1691,7 +1704,9 @@
uint8_t ep_phy_num,
dwc_request_t *req)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
dwc_trb_t *trb = ep->trb;
uint8_t *data_ptr = req->data;
diff --git a/platform/msm_shared/utp.c b/platform/msm_shared/utp.c
index c7d30ff..0c0e14b 100644
--- a/platform/msm_shared/utp.c
+++ b/platform/msm_shared/utp.c
Binary files differ
diff --git a/platform/msmzirc/gpio.c b/platform/msmzirc/gpio.c
index 98ff2e4..b285906 100644
--- a/platform/msmzirc/gpio.c
+++ b/platform/msmzirc/gpio.c
@@ -64,13 +64,13 @@
void gpio_config_uart_dm(uint8_t id)
{
- if (id == 2)
+ if (id == 3)
{
/* configure rx gpio. */
- gpio_tlmm_config(9, 1, GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(9, 3, GPIO_INPUT, GPIO_NO_PULL, GPIO_6MA, GPIO_DISABLE);
/* configure tx gpio. */
- gpio_tlmm_config(8, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(8, 3, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_6MA, GPIO_DISABLE);
}
else
{
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/msmzirc/include/platform/iomap.h
index be34590..5aefde8 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/msmzirc/include/platform/iomap.h
@@ -36,8 +36,8 @@
#define APPS_SS_BASE 0x0B000000
-#define MSM_IOMAP_BASE 0x0078000
-#define MSM_IOMAP_END 0x0BFFFFFF
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x80000000
#define SYSTEM_IMEM_BASE 0x08600000
#define MSM_SHARED_IMEM_BASE 0x08600000
@@ -68,6 +68,7 @@
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x000B1000)
#define MSM_USB30_BASE 0x08A00000
#define MSM_USB30_QSCRATCH_BASE 0x08AF8800
@@ -127,8 +128,8 @@
#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x403C)
#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x4044)
-#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x4848)
-#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x484C)
+#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x4048)
+#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x404C)
#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x4050)
#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x4054)
@@ -156,6 +157,7 @@
#define USB3_PIPE_CFG_RCGR (CLK_CTL_BASE + 0x5E04C)
#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x5E080)
#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x5E040)
+#define USB3_PIPE_BCR (CLK_CTL_BASE + 0x5E03C)
#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5E05C)
#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x5E060)
diff --git a/platform/msmzirc/msmzirc-clock.c b/platform/msmzirc/msmzirc-clock.c
index ca97cb0..497ed35 100644
--- a/platform/msmzirc/msmzirc-clock.c
+++ b/platform/msmzirc/msmzirc-clock.c
@@ -55,6 +55,7 @@
.enable = clock_lib2_branch_clk_enable,
.disable = clock_lib2_branch_clk_disable,
.set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
};
static struct clk_ops clk_ops_rcg_mnd =
@@ -188,31 +189,31 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp1_uart3_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart2_apps_clk",
+ .dbg_name = "blsp1_uart3_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+ .parent = &blsp1_uart3_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -307,6 +308,7 @@
static struct branch_clk gcc_usb30_pipe_clk = {
.cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
+ .bcr_reg = (uint32_t *) USB3_PIPE_BCR,
.parent = &usb30_pipe_clk_src.c,
.has_sibling = 0,
@@ -371,8 +373,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
diff --git a/platform/msmzirc/platform.c b/platform/msmzirc/platform.c
index bed6f22..96b5dc5 100644
--- a/platform/msmzirc/platform.c
+++ b/platform/msmzirc/platform.c
@@ -50,17 +50,12 @@
#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE)
/* Scratch memory - Strongly ordered, non-executable */
-#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL | \
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* Peripherals - shared device */
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
-#define SCRATCH_REGION1_VIRT_START SCRATCH_REGION1
-#define SCRATCH_REGION2_VIRT_START SCRATCH_REGION2
-
-#define SDRAM_BANK0_LAST_FIXED_ADDR (SCRATCH_REGION2 + SCRATCH_REGION2_SIZE)
-
/* Map all the accesssible memory according to the following rules:
* 1. Map 1MB from MSM_SHARED_BASE with 1 -1 mapping.
* 2. Map MEMBASE - MEMSIZE with 1 -1 mapping.
@@ -74,8 +69,9 @@
{MSM_SHARED_BASE, MSM_SHARED_BASE, 1, SCRATCH_MEMORY},
{MEMBASE, MEMBASE, MEMSIZE / MB, LK_MEMORY},
{MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
- {SCRATCH_REGION1, SCRATCH_REGION1_VIRT_START, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
- {SCRATCH_REGION2, SCRATCH_REGION2_VIRT_START, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
+ {SCRATCH_REGION1, SCRATCH_REGION1, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
+ {SCRATCH_REGION2, SCRATCH_REGION2, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
+ {KERNEL_REGION, KERNEL_REGION, KERNEL_REGION_SIZE / MB, SCRATCH_MEMORY},
};
void platform_early_init(void)
@@ -126,41 +122,7 @@
{
uint32_t i;
uint32_t sections;
- ram_partition ptn_entry;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH |
- MMU_MEMORY_AP_READ_WRITE |
- MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
@@ -181,50 +143,12 @@
addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
{
- uint32_t paddr;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t limit;
-
- for (uint32_t i = 0; i < table_size; i++)
- {
- limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
-
- if (virt_addr >= mmu_section_table[i].vaddress &&
- virt_addr <= (mmu_section_table[i].vaddress + limit))
- {
- paddr = mmu_section_table[i].paddress + (virt_addr - mmu_section_table[i].vaddress);
- return paddr;
- }
- }
- /* No special mapping found.
- * Assume 1-1 mapping.
- */
- paddr = virt_addr;
- return paddr;
+ /* Fixed 1-1 mapping */
+ return virt_addr;
}
addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
{
- uint32_t vaddr;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- uint32_t limit;
-
- for (uint32_t i = 0; i < table_size; i++)
- {
- limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
-
- if (phys_addr >= mmu_section_table[i].paddress &&
- phys_addr <= (mmu_section_table[i].paddress + limit))
- {
- vaddr = mmu_section_table[i].vaddress + (phys_addr - mmu_section_table[i].paddress);
- return vaddr;
- }
- }
-
- /* No special mapping found.
- * Assume 1-1 mapping.
- */
- vaddr = phys_addr;
-
- return vaddr;
+ /* Fixed 1-1 mapping */
+ return phys_addr;
}
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 1984ab2..5f51f80 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -25,11 +25,6 @@
DEFINES += BAM_V170=1
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
-DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
-DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
-DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
-
#Enable the feature of long press power on
DEFINES += LONG_PRESS_POWER_ON=1
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index aec33ec..81ee581 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -450,6 +450,9 @@
if (target_is_ssd_enabled())
clock_ce_disable(SSD_CE_INSTANCE);
+
+ /* Disable HC mode before jumping to kernel */
+ sdhci_mode_disable(&dev->host);
}
void target_usb_init(void)
diff --git a/target/msm8909/include/target/display.h b/target/msm8909/include/target/display.h
new file mode 100644
index 0000000..74613c0
--- /dev/null
+++ b/target/msm8909/include/target/display.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM8909_DISPLAY_H
+#define _TARGET_MSM8909_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 25, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = {
+ "msmgpio", 98, 3, 1, 0, 1
+};
+
+static struct gpio_pin enp_gpio = {
+ "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin enn_gpio = {
+ "msmgpio", 32, 3, 1, 0, 1
+};
+
+static struct gpio_pin te_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin pwm_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR 0x83200000
+
+#define MIPI_HSYNC_PULSE_WIDTH 12
+#define MIPI_HSYNC_BACK_PORCH_DCLK 32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 144
+
+#define MIPI_VSYNC_PULSE_WIDTH 4
+#define MIPI_VSYNC_BACK_PORCH_LINES 3
+#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+
+#endif
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 604e0ba..8382017 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -202,4 +202,36 @@
ASSERT(0);
};
}
+uint8_t target_panel_auto_detect_enabled()
+{
+ uint8_t ret = 0;
+
+ switch(board_hardware_id()) {
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+static uint8_t splash_override;
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ uint8_t splash_screen = 0;
+ if (!splash_override) {
+ switch (board_hardware_id()) {
+ default:
+ splash_screen = 0;
+ break;
+ }
+ dprintf(SPEW, "Target_cont_splash=%d\n", splash_screen);
+ }
+ return splash_screen;
+}
+
+void target_force_cont_splash_disable(uint8_t override)
+{
+ splash_override = override;
+}
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
new file mode 100644
index 0000000..b18c74a
--- /dev/null
+++ b/target/msm8909/oem_panel.c
@@ -0,0 +1,168 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+#include <target/display.h>
+#include "include/panel.h"
+#include "panel_display.h"
+
+#include "include/panel_hx8394d_720p_video.h"
+
+#define DISPLAY_MAX_PANEL_DETECTION 0
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+static uint32_t auto_pan_loop = 0;
+
+enum {
+ HX8394D_720P_VIDEO_PANEL,
+ UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL}
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+ /*
+ * OEM can keep there panel specific on instructions in this
+ * function
+ */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /*
+ * OEM can keep their panel specific off instructions
+ * in this function
+ */
+ return NO_ERROR;
+}
+
+static int init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ int pan_type = PANEL_TYPE_DSI;
+
+ switch (panel_id) {
+ case HX8394D_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394d_720p_video_panel_data;
+ panelstruct->panelres = &hx8394d_720p_video_panel_res;
+ panelstruct->color = &hx8394d_720p_video_color;
+ panelstruct->videopanel = &hx8394d_720p_video_video_panel;
+ panelstruct->commandpanel = &hx8394d_720p_video_command_panel;
+ panelstruct->state = &hx8394d_720p_video_state;
+ panelstruct->laneconfig = &hx8394d_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394d_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394d_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &hx8394d_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8394d_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8394D_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394d_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
+ break;
+ case UNKNOWN_PANEL:
+ default:
+ memset(panelstruct, 0, sizeof(struct panel_struct));
+ memset(pinfo->mipi.panel_cmds, 0, sizeof(struct mipi_dsi_cmd));
+ pinfo->mipi.num_of_panel_cmds = 0;
+ memset(phy_db->timing, 0, TIMING_SIZE);
+ pan_type = PANEL_TYPE_UNKNOWN;
+ break;
+ }
+ return pan_type;
+}
+
+uint32_t oem_panel_max_auto_detect_panels()
+{
+ return target_panel_auto_detect_enabled() ?
+ DISPLAY_MAX_PANEL_DETECTION : 0;
+}
+
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ int32_t panel_override_id;
+
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
+ switch (hw_id) {
+ case HW_PLATFORM_SURF:
+ panel_id = HX8394D_720P_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n",
+ hw_id);
+ return PANEL_TYPE_UNKNOWN;
+ }
+
+panel_init:
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8909/rules.mk b/target/msm8909/rules.mk
index 9b6f73b..58d841a 100644
--- a/target/msm8909/rules.mk
+++ b/target/msm8909/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8909
@@ -10,10 +11,15 @@
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x90000000
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
MODULES += \
dev/keys \
dev/vib \
lib/ptable \
+ dev/gcdb/display \
dev/pmic/pm8x41 \
lib/libfdt
@@ -26,4 +32,6 @@
OBJS += \
$(LOCAL_DIR)/init.o \
- $(LOCAL_DIR)/meminfo.o
+ $(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
new file mode 100755
index 0000000..338c5da
--- /dev/null
+++ b/target/msm8909/target_display.c
@@ -0,0 +1,249 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <board.h>
+#include <mdp3.h>
+#include <scm.h>
+#include <platform/gpio.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define VCO_DELAY_USEC 1000
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+
+static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
+{
+ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
+ mdelay(1);
+ writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+ mdelay(1);
+}
+
+static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
+ udelay(1);
+ writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
+ udelay(1);
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+
+ writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(1);
+ writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(512);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ struct pm8x41_mpp mpp;
+ int rc;
+
+ if (bl->bl_interface_type == BL_DCS)
+ return 0;
+
+ mpp.base = PM8x41_MMP4_BASE;
+ mpp.vin = MPP_VIN0;
+ if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0)
+ mpp.mode = MPP_HIGH;
+ else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm_pwm_enable(false);
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+ mdelay(20);
+ return 0;
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ int32_t ret = 0;
+ struct mdss_dsi_pll_config *pll_data;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
+ pll_data->vco_delay = VCO_DELAY_USEC;
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mdss_bus_clocks_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+ mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ if (!dsi_pll_enable_seq_8909(DSI0_PLL_BASE))
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ gcc_dsi_clocks_enable(pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+ } else if(!target_cont_splash_screen()) {
+ gcc_dsi_clocks_disable();
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return 0;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ uint32_t hw_id = board_hardware_id();
+ uint32_t hw_subtype = board_hardware_subtype();
+
+ if (enable) {
+ if (pinfo->mipi.use_enable_gpio) {
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength,
+ enable_gpio.pin_state);
+
+ gpio_set_dir(enable_gpio.pin_id, 2);
+ }
+
+ if (hw_id == HW_PLATFORM_SURF) {
+ /* configure backlight gpio for CDP */
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ bkl_gpio.pin_direction, bkl_gpio.pin_pull,
+ bkl_gpio.pin_strength, bkl_gpio.pin_state);
+ gpio_set_dir(bkl_gpio.pin_id, 2);
+ }
+
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+
+ gpio_set_dir(reset_gpio.pin_id, 2);
+
+ /* reset */
+ for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+ if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW);
+ else
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH);
+ mdelay(resetseq->sleep[i]);
+ }
+ } else if(!target_cont_splash_screen()) {
+ gpio_set_dir(reset_gpio.pin_id, 0);
+ if (pinfo->mipi.use_enable_gpio)
+ gpio_set_dir(enable_gpio.pin_id, 0);
+ }
+
+ return ret;
+}
+
+int target_ldo_ctrl(uint8_t enable)
+{
+ /*
+ * The PMIC regulators needed for display are enabled in SBL.
+ * There is no access to the regulators is LK.
+ */
+ return NO_ERROR;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+ return gcdb_display_cmdline_arg(pbuf, buf_size);
+}
+
+void target_display_init(const char *panel_name)
+{
+ uint32_t panel_loop = 0;
+ uint32_t ret = 0;
+
+ if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
+ dprintf(INFO, "Skip panel configuration\n");
+ return;
+ }
+
+ do {
+ target_force_cont_splash_disable(false);
+ ret = gcdb_display_init(panel_name, MDP_REV_305, MIPI_FB_ADDR);
+ if (!ret || ret == ERR_NOT_SUPPORTED) {
+ break;
+ } else {
+ target_force_cont_splash_disable(true);
+ msm_display_off();
+ }
+ } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+}
+
+void target_display_shutdown(void)
+{
+ gcdb_display_shutdown();
+}
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 25344d0..33a11f2 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -448,10 +448,10 @@
break;
case HW_PLATFORM_SUBTYPE_SKUI:
/* qrd SKUIC */
- if ((plat_hw_ver_major >> 4) == 0x1)
- panel_id = HX8379A_FWVGA_VIDEO_PANEL;
- else
+ if ((plat_hw_ver_major >> 4) == 0)
panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
+ else
+ panel_id = HX8379A_FWVGA_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 0780268..961b5a4 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -182,6 +182,26 @@
{
}
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index edf1ceb..2463515 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -351,8 +351,6 @@
int target_display_pre_on()
{
- writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
- writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
writel(0xC0000CCC, MDP_CLK_CTRL0);
writel(0xC0000CCC, MDP_CLK_CTRL1);
writel(0x00CCCCCC, MDP_CLK_CTRL2);
diff --git a/target/msmzirc/init.c b/target/msmzirc/init.c
index a94ef0d..bd2a158 100644
--- a/target/msmzirc/init.c
+++ b/target/msmzirc/init.c
@@ -75,6 +75,9 @@
#define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF
+#define EXT4_CMDLINE " rootfstype=ext4 root=/dev/mmcblk0p"
+#define UBI_CMDLINE " rootfstype=ubifs rootflags=bulk_read ubi.fm_autoconvert=1"
+
struct qpic_nand_init_config config;
void update_ptable_names(void)
@@ -111,7 +114,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(3, 0, BLSP1_UART2_BASE);
#endif
}
@@ -217,39 +220,45 @@
struct ptable *ptable;
int system_ptn_index = -1;
- if (!target_is_emmc_boot()) {
- if (!cmdline || !part || !buf || buflen < 0) {
- dprintf(CRITICAL, "WARN: Invalid input param\n");
- return -1;
- }
-
- ptable = flash_get_ptable();
- if (!ptable) {
- dprintf(CRITICAL,
- "WARN: Cannot get flash partition table\n");
- return -1;
- }
-
- system_ptn_index = ptable_get_index(ptable, part);
- if (system_ptn_index < 0) {
- dprintf(CRITICAL,
- "WARN: Cannot get partition index for %s\n", part);
- return -1;
- }
-
- /*
- * check if cmdline contains "root=" at the beginning of buffer or
- * " root=" in the middle of buffer.
- */
- if (((!strncmp(cmdline, "root=", strlen("root="))) ||
- (strstr(cmdline, " root="))))
- dprintf(DEBUG, "DEBUG: cmdline has root=\n");
- else
- snprintf(buf, buflen, " root=/dev/mtdblock%d",
- system_ptn_index);
+ if (!cmdline || !part || !buf || buflen < 0) {
+ dprintf(CRITICAL, "WARN: Invalid input param\n");
+ return -1;
}
- return 0;
+ if (!strstr(cmdline, "root=/dev/ram")) /* This check is to handle kdev boot */
+ {
+ if (!target_is_emmc_boot()) {
+ /* Below is for NAND boot */
+ ptable = flash_get_ptable();
+ if (!ptable) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get flash partition table\n");
+ return -1;
+ }
+
+ system_ptn_index = ptable_get_index(ptable, part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+ /* Adding command line parameters according to target boot type */
+ snprintf(buf, buflen, UBI_CMDLINE);
+ snprintf(buf+strlen(buf), buflen, " root=ubi0:rootfs ubi.mtd=%d", system_ptn_index);
+ }
+ else {
+ /* Below is for emmc boot */
+ system_ptn_index = partition_get_index(part);
+ if (system_ptn_index < 0) {
+ dprintf(CRITICAL,
+ "WARN: Cannot get partition index for %s\n", part);
+ return -1;
+ }
+ snprintf(buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
+ }
+
+ return 0;
+ }
}
const char * target_usb_controller()
@@ -319,8 +328,8 @@
void target_usb_phy_reset(void)
{
- qusb2_phy_reset();
usb30_qmp_phy_reset();
+ qusb2_phy_reset();
}
target_usb_iface_t* target_usb30_init()
@@ -338,3 +347,8 @@
return t_usb_iface;
}
+
+uint32_t target_override_pll()
+{
+ return 1;
+}
diff --git a/target/msmzirc/keypad.c b/target/msmzirc/keypad.c
index 569ea66..11ba6e8 100644
--- a/target/msmzirc/keypad.c
+++ b/target/msmzirc/keypad.c
@@ -33,7 +33,7 @@
/* GPIO that controls the button
* for FASTBOOT.
*/
-#define FASTBOOT_KEY_GPIO_ID 17
+#define FASTBOOT_KEY_GPIO_ID 92
/*
* Returns fastboot button state.
diff --git a/target/msmzirc/meminfo.c b/target/msmzirc/meminfo.c
index 7516b42..d71630c 100644
--- a/target/msmzirc/meminfo.c
+++ b/target/msmzirc/meminfo.c
@@ -77,10 +77,10 @@
void *target_get_scratch_address(void)
{
- return ((void *) VA((addr_t)SCRATCH_REGION2));
+ return ((void *) VA((addr_t)SCRATCH_REGION1));
}
unsigned target_get_max_flash_size(void)
{
- return (SCRATCH_REGION2_SIZE);
+ return (SCRATCH_REGION1_SIZE);
}
diff --git a/target/msmzirc/rules.mk b/target/msmzirc/rules.mk
index c0831cc..7a19970 100644
--- a/target/msmzirc/rules.mk
+++ b/target/msmzirc/rules.mk
@@ -4,14 +4,17 @@
PLATFORM := msmzirc
-MEMBASE := 0x87C00000
+MEMBASE := 0x81200000
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x80000000
-SCRATCH_REGION1 := 0x80000000
-SCRATCH_REGION1_SIZE := 0x07C00000 # 124MB
+SCRATCH_REGION1 := 0x81300000
+SCRATCH_REGION1_SIZE := 0x06900000 # 105MB
SCRATCH_REGION2 := 0x88000000
SCRATCH_REGION2_SIZE := 0x08000000 # 128MB
+KERNEL_REGION := 0x80000000
+KERNEL_REGION_SIZE := 0x01200000 # 18MB
+
DEFINES += NO_KEYPAD_DRIVER=1
DEFINES += PERIPH_BLK_BLSP=1
@@ -31,6 +34,9 @@
MEMSIZE=$(MEMSIZE) \
SCRATCH_REGION1_SIZE=$(SCRATCH_REGION1_SIZE) \
SCRATCH_REGION2_SIZE=$(SCRATCH_REGION2_SIZE) \
+ KERNEL_REGION=$(KERNEL_REGION) \
+ KERNEL_REGION_SIZE=$(KERNEL_REGION_SIZE) \
+
OBJS += \
$(LOCAL_DIR)/init.o \