Merge "target: Add weak API to get HLOS subtype"
diff --git a/dev/gcdb/display/include/panel_innolux_720p_video.h b/dev/gcdb/display/include/panel_innolux_720p_video.h
index 2509048..8bd4680 100644
--- a/dev/gcdb/display/include/panel_innolux_720p_video.h
+++ b/dev/gcdb/display/include/panel_innolux_720p_video.h
@@ -973,7 +973,7 @@
/* Backlight setting */
/*---------------------------------------------------------------------------*/
static struct backlight innolux_720p_video_backlight = {
- 0, 1, 255, 0, 2, 0
+ 2, 1, 255, 0, 2, 0
};
#endif /*_PANEL_INNOLUX_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
index a931aae..eecc775 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
@@ -1616,7 +1616,7 @@
static char nt35596_1080p_skuk_video_on_cmd310[] = {
0x02, 0x00, 0x29, 0xC0,
- 0x53, 0x05, 0xFF, 0xFF,
+ 0x53, 0x2C, 0xFF, 0xFF,
};
static char nt35596_1080p_skuk_video_on_cmd311[] = {
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index f8d59a2..c30af8a 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -251,8 +251,12 @@
#define VIDEO_MODE_VSYNC 0x034
#define VIDEO_MODE_VSYNC_VPOS 0x038
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x2200)
#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2600)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x3200)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x3600)
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index c6a2d24..681072a 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -149,7 +149,9 @@
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 0a90531..4c77c7d 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -32,6 +32,8 @@
#include <msm_panel.h>
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x1E00)
#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2200)
#define MDP_VP_0_DMA_0_BASE REG_MDP(0x2A00)
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index d8824cc..8bf3a8f 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -51,6 +51,12 @@
#define LVDS_PANEL 11 /* LVDS */
#define EDP_PANEL 12 /* EDP */
+enum mdss_mdp_pipe_type {
+ MDSS_MDP_PIPE_TYPE_VIG,
+ MDSS_MDP_PIPE_TYPE_RGB,
+ MDSS_MDP_PIPE_TYPE_DMA,
+};
+
enum msm_mdp_hw_revision {
MDP_REV_20 = 1,
MDP_REV_22,
@@ -189,8 +195,8 @@
uint32_t wait_cycle;
uint32_t clk_rate;
uint32_t rotation;
- /* Enable if DMA pipe used for handoff */
- uint32_t use_dma_pipe;
+ /* Select pipe type for handoff */
+ uint32_t pipe_type;
char lowpowerstop;
struct lcd_panel_info lcd;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index d60e5cf..c8e9227 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -96,10 +96,12 @@
pipe_swap = (pinfo->lcdc.pipe_swap == TRUE) ? 1 : 0;
if (pipe_swap && ((pipe_base == MDP_VP_0_RGB_0_BASE) ||
- (pipe_base == MDP_VP_0_DMA_0_BASE)))
+ (pipe_base == MDP_VP_0_DMA_0_BASE) ||
+ (pipe_base == MDP_VP_0_VIG_0_BASE)))
fb_off = (pinfo->xres / 2);
else if (!pipe_swap && ((pipe_base == MDP_VP_0_RGB_1_BASE) ||
- (pipe_base == MDP_VP_0_DMA_1_BASE)))
+ (pipe_base == MDP_VP_0_DMA_1_BASE) ||
+ (pipe_base == MDP_VP_0_VIG_1_BASE)))
fb_off = (pinfo->xres / 2);
}
@@ -195,20 +197,54 @@
} else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
(mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
smp_size = 8192;
- fixed_smp_cnt = 2;
free_smp_offset = 0xC;
+ if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB)
+ fixed_smp_cnt = 2;
+ else
+ fixed_smp_cnt = 0;
}
- if (pinfo->use_dma_pipe)
- right_sspp_client_id = 0xD; /* 13 */
- else
- right_sspp_client_id = 0x11; /* 17 */
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ right_sspp_client_id = 0x11; /* 17 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ right_sspp_client_id = 0xD; /* 13 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ right_sspp_client_id = 0x4; /* 4 */
+ break;
+ }
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
- MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106))
- left_sspp_client_id = (pinfo->use_dma_pipe) ? 0x4 : 0x07; /* 4 or 7 */
- else
- left_sspp_client_id = (pinfo->use_dma_pipe) ? 0xA : 0x10; /* 10 or 16 */
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106)) {
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ left_sspp_client_id = 0x7; /* 7 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ left_sspp_client_id = 0x4; /* 4 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ left_sspp_client_id = 0x1; /* 1 */
+ break;
+ }
+ } else {
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ left_sspp_client_id = 0x10; /* 16 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ left_sspp_client_id = 0xA; /* 10 */
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ left_sspp_client_id = 0x1; /* 1 */
+ break;
+ }
+ }
/* Each pipe driving half the screen */
if (pinfo->lcdc.dual_pipe)
@@ -329,7 +365,8 @@
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
*pinfo)
{
- uint32_t mdp_rgb_size, height, width, val;
+ uint32_t mdp_rgb_size, height, width;
+ uint32_t reg_val;
height = fb->height;
width = fb->width;
@@ -352,10 +389,20 @@
writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA);
/* Baselayer for layer mixer 0 */
- if (pinfo->use_dma_pipe)
- writel(0x0040000, MDP_CTL_0_BASE + CTL_LAYER_0);
- else
- writel(0x0000200, MDP_CTL_0_BASE + CTL_LAYER_0);
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ reg_val = 0x0000200;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ reg_val = 0x0040000;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ reg_val = 0x1;
+ break;
+ }
+
+ writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_0);
if (pinfo->lcdc.dual_pipe) {
writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
@@ -370,11 +417,23 @@
writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA);
/* Baselayer for layer mixer 1 */
- val = pinfo->use_dma_pipe ? 0x200000 : 0x1000;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ reg_val = 0x1000;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ reg_val = 0x200000;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ reg_val = 0x8;
+ break;
+ }
+
if (pinfo->lcdc.split_display)
- writel(val, MDP_CTL_1_BASE + CTL_LAYER_1);
+ writel(reg_val, MDP_CTL_1_BASE + CTL_LAYER_1);
else
- writel(val, MDP_CTL_0_BASE + CTL_LAYER_1);
+ writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_1);
}
}
@@ -417,12 +476,20 @@
mdp_clk_gating_ctrl();
- if (pinfo->use_dma_pipe) {
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- } else {
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ left_pipe = MDP_VP_0_RGB_0_BASE;
+ right_pipe = MDP_VP_0_RGB_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ left_pipe = MDP_VP_0_DMA_0_BASE;
+ right_pipe = MDP_VP_0_DMA_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ left_pipe = MDP_VP_0_VIG_0_BASE;
+ right_pipe = MDP_VP_0_VIG_1_BASE;
+ break;
}
mdss_vbif_setup();
@@ -461,12 +528,20 @@
mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
- if (pinfo->use_dma_pipe) {
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- } else {
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ left_pipe = MDP_VP_0_RGB_0_BASE;
+ right_pipe = MDP_VP_0_RGB_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ left_pipe = MDP_VP_0_DMA_0_BASE;
+ right_pipe = MDP_VP_0_DMA_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ left_pipe = MDP_VP_0_VIG_0_BASE;
+ right_pipe = MDP_VP_0_VIG_1_BASE;
+ break;
}
mdp_clk_gating_ctrl();
@@ -527,12 +602,20 @@
writel(intf_sel, MDP_DISP_INTF_SEL);
- if (pinfo->use_dma_pipe) {
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- } else {
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ left_pipe = MDP_VP_0_RGB_0_BASE;
+ right_pipe = MDP_VP_0_RGB_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ left_pipe = MDP_VP_0_DMA_0_BASE;
+ right_pipe = MDP_VP_0_DMA_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ left_pipe = MDP_VP_0_VIG_0_BASE;
+ right_pipe = MDP_VP_0_VIG_1_BASE;
+ break;
}
mdss_vbif_setup();
@@ -559,13 +642,25 @@
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
- if (pinfo->use_dma_pipe) {
- writel(0x22840, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x25080, MDP_CTL_1_BASE + CTL_FLUSH);
- } else {
- writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
+ uint32_t ctl0_reg_val, ctl1_reg_val;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ ctl0_reg_val = 0x22048;
+ ctl1_reg_val = 0x24090;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ ctl0_reg_val = 0x22840;
+ ctl1_reg_val = 0x25080;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ ctl0_reg_val = 0x22041;
+ ctl1_reg_val = 0x24082;
+ break;
}
+
+ writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
@@ -603,13 +698,25 @@
int mdp_dma_on(struct msm_panel_info *pinfo)
{
- if (pinfo->use_dma_pipe) {
- writel(0x22840, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x25080, MDP_CTL_1_BASE + CTL_FLUSH);
- } else {
- writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(0x24090, MDP_CTL_1_BASE + CTL_FLUSH);
+ uint32_t ctl0_reg_val, ctl1_reg_val;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ ctl0_reg_val = 0x22048;
+ ctl1_reg_val = 0x24090;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ ctl0_reg_val = 0x22840;
+ ctl1_reg_val = 0x25080;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ ctl0_reg_val = 0x22041;
+ ctl1_reg_val = 0x24082;
+ break;
}
+
+ writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
@@ -621,10 +728,21 @@
int mdp_edp_on(struct msm_panel_info *pinfo)
{
- if (pinfo->use_dma_pipe)
- writel(0x22840, MDP_CTL_0_BASE + CTL_FLUSH);
- else
- writel(0x22048, MDP_CTL_0_BASE + CTL_FLUSH);
+ uint32_t ctl0_reg_val;
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ ctl0_reg_val = 0x22048;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ ctl0_reg_val = 0x22840;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ ctl0_reg_val = 0x22041;
+ break;
+ }
+
+ writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
diff --git a/target/mdm9635/init.c b/target/mdm9635/init.c
index 8de21ed..5b2e00c 100644
--- a/target/mdm9635/init.c
+++ b/target/mdm9635/init.c
@@ -43,6 +43,7 @@
#include <hsusb.h>
#include <bits.h>
#include <qmp_phy.h>
+#include <scm.h>
extern void smem_ptable_init(void);
extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -180,9 +181,27 @@
return t_usb_iface;
}
+
+static int scm_clear_boot_partition_select()
+{
+ int ret = 0;
+
+ ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
+ if (ret)
+ dprintf(CRITICAL, "Failed to disable the wdog debug \n");
+
+ return ret;
+}
+
/* reboot */
void reboot_device(unsigned reboot_reason)
{
+ uint8_t reset_type = 0;
+
+ /* Clear the boot partition select cookie to indicate
+ * its a normal reset and avoid going to download mode */
+ scm_clear_boot_partition_select();
+
/* Write the reboot reason */
writel(reboot_reason, RESTART_REASON_ADDR);
@@ -191,7 +210,12 @@
* This call should be based on the pmic version
* when PM8019 v2 is available.
*/
- pm8x41_v2_reset_configure(PON_PSHOLD_WARM_RESET);
+ if(reboot_reason)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_v2_reset_configure(reset_type);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 8587b39..9b6edbd 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -129,12 +129,6 @@
return NO_ERROR;
}
-static void mdss_source_pipe_select(struct msm_panel_info *pinfo)
-{
- /* Use DMA pipe for splash logo on 8x26 */
- pinfo->use_dma_pipe = 1;
-}
-
static void init_panel_data(struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
@@ -420,7 +414,6 @@
panel_init:
init_panel_data(panelstruct, pinfo, phy_db);
- mdss_source_pipe_select(pinfo);
return ret;
}
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index bbea4bc..4e3db96 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -98,6 +98,9 @@
struct pm8x41_mpp mpp;
int rc;
+ if (bl->bl_interface_type == BL_DCS)
+ return 0;
+
mpp.base = PM8x41_MMP4_BASE;
mpp.vin = MPP_VIN0;
if (enable) {