msm: uart/gsbi driver update
AP8064 does not share the same gsbi address mappings
as well as offsets with MSM8960. As such, addresses have to be
passed at run time instead of compile time for single binary image.
Change-Id: I204efaffcd7e5502bbd980865a77568f5063beac
diff --git a/include/platform.h b/include/platform.h
index cff84c3..309bfef 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -40,6 +40,7 @@
void display_image_on_screen(void);
unsigned board_machtype(void);
+unsigned board_platform_id(void);
unsigned check_reboot_mode(void);
void platform_uninit_timer(void);
void reboot_device(unsigned);
diff --git a/platform/mdm9x15/platform.c b/platform/mdm9x15/platform.c
index 99e1ad4..eea6f81 100644
--- a/platform/mdm9x15/platform.c
+++ b/platform/mdm9x15/platform.c
@@ -49,8 +49,10 @@
{
uint8_t cfg_bid = 0x1;
uint8_t cfg_pid = 0x1;
+ uint8_t gsbi_id = target_uart_gsbi();
- uart_init(target_uart_gsbi());
+ uart_dm_init(gsbi_id, GSBI_BASE(gsbi_id), GSBI_UART_DM_BASE(gsbi_id));
+
/* Timers - QGIC Config */
writel((cfg_bid << 7 | cfg_pid << 10), APCS_GLB_QGIC_CFG);
qgic_init();
diff --git a/platform/msm8960/gpio.c b/platform/msm8960/gpio.c
index 6a25fb5..9403be0 100644
--- a/platform/msm8960/gpio.c
+++ b/platform/msm8960/gpio.c
@@ -33,6 +33,7 @@
#include <gsbi.h>
#include <dev/pm8921.h>
#include <sys/types.h>
+#include <smem.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
@@ -55,31 +56,65 @@
return;
}
+/* TODO: this and other code below in this file should ideally by in target dir.
+ * keeping it here for this brigup.
+ */
+
/* Configure gpio for uart - based on gsbi id */
void gpio_config_uart_dm(uint8_t id)
{
- switch (id) {
+ if(board_platform_id() == APQ8064)
+ {
+ switch (id) {
- case GSBI_ID_3:
- /* configure rx gpio */
- gpio_tlmm_config(15, 1, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
- /* configure tx gpio */
- gpio_tlmm_config(14, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
- break;
+ case GSBI_ID_1:
+ /* configure rx gpio */
+ gpio_tlmm_config(19, 1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(18, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
- case GSBI_ID_5:
- /* configure rx gpio */
- gpio_tlmm_config(23, 1, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
- /* configure tx gpio */
- gpio_tlmm_config(22, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
- break;
- default:
- ASSERT(0);
+ case GSBI_ID_7:
+ /* configure rx gpio */
+ gpio_tlmm_config(83, 1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(82, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+
+ default:
+ ASSERT(0);
+ }
+ }
+ else
+ {
+ switch (id) {
+
+ case GSBI_ID_3:
+ /* configure rx gpio */
+ gpio_tlmm_config(15, 1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(14, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+
+ case GSBI_ID_5:
+ /* configure rx gpio */
+ gpio_tlmm_config(23, 1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(22, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+
+ default:
+ ASSERT(0);
+ }
}
}
diff --git a/platform/msm8960/include/platform/iomap.h b/platform/msm8960/include/platform/iomap.h
index f653437..08f8a4b 100644
--- a/platform/msm8960/include/platform/iomap.h
+++ b/platform/msm8960/include/platform/iomap.h
@@ -83,11 +83,6 @@
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
-#define GSBI_BASE(id) ((id) <= 7 ? (0x16000000 + (((id)-1) << 20)) : \
- (0x1A000000 + (((id)-8) << 20)))
-#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
-#define QUP_BASE(id) (GSBI_BASE(id) + 0x80000)
-
#define EBI2_CHIP_SELECT_CFG0 0x1A100000
#define EBI2_XMEM_CS3_CFG1 0x1A110034
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
index e2369f7..478aec9 100755
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -108,7 +108,8 @@
void platform_early_init(void)
{
- uart_init(target_uart_gsbi());
+ uint8_t gsbi_id = target_uart_gsbi();
+ uart_dm_init(gsbi_id, GSBI_BASE(gsbi_id), GSBI_UART_DM_BASE(gsbi_id));
qgic_init();
platform_init_timer();
}
diff --git a/platform/msm_shared/include/gsbi.h b/platform/msm_shared/include/gsbi.h
index 8d504a7..2b1ad75 100644
--- a/platform/msm_shared/include/gsbi.h
+++ b/platform/msm_shared/include/gsbi.h
@@ -31,7 +31,7 @@
#include <platform/iomap.h>
/* GSBI Registers */
-#define GSBI_CTRL_REG(id) (GSBI_BASE(id) + 0x0)
+#define GSBI_CTRL_REG(base) ((base) + 0x0)
#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4
#define GSBI_PROTOCOL_CODE_I2C 0x2
diff --git a/platform/msm_shared/include/uart_dm.h b/platform/msm_shared/include/uart_dm.h
index c3c5718..484e7b5 100644
--- a/platform/msm_shared/include/uart_dm.h
+++ b/platform/msm_shared/include/uart_dm.h
@@ -67,19 +67,19 @@
/* UART_DM Registers */
/* UART Operational Mode Register */
-#define MSM_BOOT_UART_DM_MR1(id) (GSBI_UART_DM_BASE(id) + 0x00)
-#define MSM_BOOT_UART_DM_MR2(id) (GSBI_UART_DM_BASE(id) + 0x04)
+#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
/* UART Clock Selection Register */
-#define MSM_BOOT_UART_DM_CSR(id) (GSBI_UART_DM_BASE(id) + 0x08)
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
/* UART DM TX FIFO Registers - 4 */
-#define MSM_BOOT_UART_DM_TF(id, x) (GSBI_UART_DM_BASE(id) + 0x70+(4*(x)))
+#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
/* UART Command Register */
-#define MSM_BOOT_UART_DM_CR(id) (GSBI_UART_DM_BASE(id) + 0x10)
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
@@ -121,7 +121,7 @@
#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
/* UART Interrupt Mask Register */
-#define MSM_BOOT_UART_DM_IMR(id) (GSBI_UART_DM_BASE(id) + 0x14)
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
@@ -142,42 +142,42 @@
MSM_BOOT_UART_DM_RXSTALE)
/* UART Interrupt Programming Register */
-#define MSM_BOOT_UART_DM_IPR(id) (GSBI_UART_DM_BASE(id) + 0x18)
+#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
/* UART Transmit/Receive FIFO Watermark Register */
-#define MSM_BOOT_UART_DM_TFWR(id) (GSBI_UART_DM_BASE(id) + 0x1C)
+#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
/* Interrupt is generated when FIFO level is less than or equal to this value */
#define MSM_BOOT_UART_DM_TFW_VALUE 0
-#define MSM_BOOT_UART_DM_RFWR(id) (GSBI_UART_DM_BASE(id) + 0x20)
+#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
/*Interrupt generated when no of words in RX FIFO is greater than this value */
#define MSM_BOOT_UART_DM_RFW_VALUE 0
/* UART Hunt Character Register */
-#define MSM_BOOT_UART_DM_HCR(id) (GSBI_UART_DM_BASE(id) + 0x24)
+#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
/* Used for RX transfer initialization */
-#define MSM_BOOT_UART_DM_DMRX(id) (GSBI_UART_DM_BASE(id) + 0x34)
+#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
/* Default DMRX value - any value bigger than FIFO size would be fine */
#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
/* Register to enable IRDA function */
-#define MSM_BOOT_UART_DM_IRDA(id) (GSBI_UART_DM_BASE(id) + 0x38)
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
/* UART Data Mover Enable Register */
-#define MSM_BOOT_UART_DM_DMEN(id) (GSBI_UART_DM_BASE(id) + 0x3C)
+#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
/* Number of characters for Transmission */
-#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id) (GSBI_UART_DM_BASE(id) + 0x040)
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
/* UART RX FIFO Base Address */
-#define MSM_BOOT_UART_DM_BADR(id) (GSBI_UART_DM_BASE(id) + 0x44)
+#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
/* UART Status Register */
-#define MSM_BOOT_UART_DM_SR(id) (GSBI_UART_DM_BASE(id) + 0x008)
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
@@ -189,26 +189,26 @@
#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
/* UART Receive FIFO Registers - 4 in numbers */
-#define MSM_BOOT_UART_DM_RF(id, x) (GSBI_UART_DM_BASE(id) + 0x70 + (4*(x)))
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
/* UART Masked Interrupt Status Register */
-#define MSM_BOOT_UART_DM_MISR(id) (GSBI_UART_DM_BASE(id) + 0x10)
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
/* UART Interrupt Status Register */
-#define MSM_BOOT_UART_DM_ISR(id) (GSBI_UART_DM_BASE(id) + 0x14)
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
/* Number of characters received since the end of last RX transfer */
-#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id) (GSBI_UART_DM_BASE(id) + 0x38)
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
/* UART TX FIFO Status Register */
-#define MSM_BOOT_UART_DM_TXFS(id) (GSBI_UART_DM_BASE(id) + 0x4C)
+#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
/* UART RX FIFO Status Register */
-#define MSM_BOOT_UART_DM_RXFS(id) (GSBI_UART_DM_BASE(id) + 0x50)
+#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
@@ -222,5 +222,7 @@
#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
-void uart_init(uint8_t gsbi_id);
+void uart_dm_init(uint8_t id,
+ uint32_t gsbi_base,
+ uint32_t uart_dm_base);
#endif /* __UART_DM_H__ */
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 614bd56..d3f2a05 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -70,22 +70,21 @@
}
/* Static Function Prototype Declarations */
-static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id);
static unsigned int msm_boot_uart_replace_lr_with_cr(char *data_in,
int num_of_chars,
char *data_out,
int *num_of_chars_out);
-static unsigned int msm_boot_uart_dm_init(uint8_t id);
-static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int *data,
- int wait);
-static unsigned int msm_boot_uart_dm_write(uint8_t id, char *data,
- unsigned int num_of_chars);
-static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id);
-static unsigned int msm_boot_uart_dm_reset(uint8_t id);
+static unsigned int msm_boot_uart_dm_init(uint32_t base);
+static unsigned int msm_boot_uart_dm_read(uint32_t base, unsigned int *data,
+ int wait);
+static unsigned int msm_boot_uart_dm_write(uint32_t base, char *data,
+ unsigned int num_of_chars);
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint32_t base);
+static unsigned int msm_boot_uart_dm_reset(uint32_t base);
/* Keep track of gsbi vs port mapping.
*/
-static uint8_t gsbi_lookup[4];
+static uint32_t gsbi_lookup[4];
/* Extern functions */
void udelay(unsigned usecs);
@@ -120,47 +119,15 @@
}
/*
- * Initialize and configure GSBI for operation
- */
-static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id)
-{
- /* Configure the uart clock */
- clock_config_uart_dm(id);
- dsb();
-
- /* Configure GPIO to provide connectivity between GSBI
- product ports and chip pads */
- gpio_config_uart_dm(id);
- dsb();
-
- /* Configure Data Mover for GSBI operation.
- * Currently not supported. */
-
- /* Configure GSBI for UART_DM protocol.
- * I2C on 2 ports, UART (without HS flow control) on the other 2. */
- writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,
- GSBI_CTRL_REG(id));
- dsb();
-
- /* Configure clock selection register for tx and rx rates.
- * Selecting 115.2k for both RX and TX.
- */
- writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));
- dsb();
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/*
* Reset the UART
*/
-static unsigned int msm_boot_uart_dm_reset(uint8_t id)
+static unsigned int msm_boot_uart_dm_reset(uint32_t base)
{
- writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -168,42 +135,39 @@
/*
* Initialize UART_DM - configure clock and required registers.
*/
-static unsigned int msm_boot_uart_dm_init(uint8_t id)
+static unsigned int msm_boot_uart_dm_init(uint32_t uart_dm_base)
{
- /* Configure GSBI for uart dm */
- msm_boot_uart_dm_gsbi_init(id);
-
/* Configure UART mode registers MR1 and MR2 */
/* Hardware flow control isn't supported */
- writel(0x0, MSM_BOOT_UART_DM_MR1(id));
+ writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
- writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(id));
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base));
/* Configure Interrupt Mask register IMR */
- writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(id));
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base));
/* Configure Tx and Rx watermarks configuration registers */
/* TX watermark value is set to 0 - interrupt is generated when
* FIFO level is less than or equal to 0 */
- writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(id));
+ writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base));
/* RX watermark value */
- writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(id));
+ writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base));
/* Configure Interrupt Programming Register */
/* Set initial Stale timeout value */
- writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(id));
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(uart_dm_base));
/* Configure IRDA if required */
/* Disabling IRDA mode */
- writel(0x0, MSM_BOOT_UART_DM_IRDA(id));
+ writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
/* Configure and enable sim interface if required */
/* Configure hunt character value in HCR register */
/* Keep it in reset state */
- writel(0x0, MSM_BOOT_UART_DM_HCR(id));
+ writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
/* Configure Rx FIFO base address */
/* Both TX/RX shares same SRAM and default is half-n-half.
@@ -212,18 +176,18 @@
* We have found RAM_ADDR_WIDTH = 0x7f */
/* Issue soft reset command */
- msm_boot_uart_dm_reset(id);
+ msm_boot_uart_dm_reset(uart_dm_base);
/* Enable/Disable Rx/Tx DM interfaces */
/* Data Mover not currently utilized. */
- writel(0x0, MSM_BOOT_UART_DM_DMEN(id));
+ writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
/* Enable transmitter and receiver */
- writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(uart_dm_base));
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(uart_dm_base));
/* Initialize Receive Path */
- msm_boot_uart_dm_init_rx_transfer(id);
+ msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -231,12 +195,12 @@
/*
* Initialize Receive Path
*/
-static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id)
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint32_t uart_dm_base)
{
- writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(id));
- writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR(uart_dm_base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(uart_dm_base));
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(uart_dm_base));
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(uart_dm_base));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -246,7 +210,7 @@
* Reads a word from the RX FIFO.
*/
static unsigned int
-msm_boot_uart_dm_read(uint8_t id, unsigned int *data, int wait)
+msm_boot_uart_dm_read(uint32_t base, unsigned int *data, int wait)
{
static int rx_last_snap_count = 0;
static int rx_chars_read_since_last_xfer = 0;
@@ -256,7 +220,7 @@
}
/* We will be polling RXRDY status bit */
- while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_RXRDY)) {
+ while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_RXRDY)) {
/* if this is not a blocking call, we'll just return */
if (!wait) {
return MSM_BOOT_UART_DM_E_RX_NOT_READY;
@@ -264,13 +228,13 @@
}
/* Check for Overrun error. We'll just reset Error Status */
- if (readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
+ if (readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
- MSM_BOOT_UART_DM_CR(id));
+ MSM_BOOT_UART_DM_CR(base));
}
/* RX FIFO is ready; read a word. */
- *data = readl(MSM_BOOT_UART_DM_RF(id, 0));
+ *data = readl(MSM_BOOT_UART_DM_RF(base, 0));
/* increment the total count of chars we've read so far */
rx_chars_read_since_last_xfer += 4;
@@ -284,15 +248,15 @@
/* If RX transfer has not ended yet */
if (rx_last_snap_count == 0) {
/* Check if we've received stale event */
- if (readl(MSM_BOOT_UART_DM_MISR(id)) & MSM_BOOT_UART_DM_RXSTALE) {
+ if (readl(MSM_BOOT_UART_DM_MISR(base)) & MSM_BOOT_UART_DM_RXSTALE) {
/* Send command to reset stale interrupt */
writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
- MSM_BOOT_UART_DM_CR(id));
+ MSM_BOOT_UART_DM_CR(base));
}
/* Check if we haven't read more than DMRX value */
else if ((unsigned int)rx_chars_read_since_last_xfer <
- readl(MSM_BOOT_UART_DM_DMRX(id))) {
+ readl(MSM_BOOT_UART_DM_DMRX(base))) {
/* We can still continue reading before initializing RX transfer */
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -301,7 +265,7 @@
/* Read UART_DM_RX_TOTAL_SNAP register to know how many valid chars
* we've read so far since last transfer */
- rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id));
+ rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
}
@@ -311,7 +275,7 @@
return MSM_BOOT_UART_DM_E_SUCCESS;
}
- msm_boot_uart_dm_init_rx_transfer(id);
+ msm_boot_uart_dm_init_rx_transfer(base);
rx_last_snap_count = 0;
rx_chars_read_since_last_xfer = 0;
@@ -322,7 +286,7 @@
* UART transmit operation
*/
static unsigned int
-msm_boot_uart_dm_write(uint8_t id, char *data, unsigned int num_of_chars)
+msm_boot_uart_dm_write(uint32_t base, char *data, unsigned int num_of_chars)
{
unsigned int tx_word_count = 0;
unsigned int tx_char_left = 0, tx_char = 0;
@@ -349,9 +313,9 @@
/* Check if transmit FIFO is empty.
* If not we'll wait for TX_READY interrupt. */
- if (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXEMT)) {
+ if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) {
while (!
- (readl(MSM_BOOT_UART_DM_ISR(id)) &
+ (readl(MSM_BOOT_UART_DM_ISR(base)) &
MSM_BOOT_UART_DM_TX_READY)) {
udelay(1);
/* Kick watchdog? */
@@ -360,10 +324,10 @@
/* We are here. FIFO is ready to be written. */
/* Write number of characters to be written */
- writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id));
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
/* Clear TX_READY interrupt */
- writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base));
/* We use four-character word FIFO. So we need to divide data into
* four characters and write in UART_DM_TF register */
@@ -377,13 +341,13 @@
/* Wait till TX FIFO has space */
while (!
- (readl(MSM_BOOT_UART_DM_SR(id)) &
+ (readl(MSM_BOOT_UART_DM_SR(base)) &
MSM_BOOT_UART_DM_SR_TXRDY)) {
udelay(1);
}
/* TX FIFO has space. Write the chars */
- writel(tx_word, MSM_BOOT_UART_DM_TF(id, 0));
+ writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0));
tx_char_left = num_of_chars - (i + 1) * 4;
tx_data = tx_data + 4;
}
@@ -395,16 +359,39 @@
* existing uart implemention. These functions are being called to initialize
* UART and print debug messages in bootloader.
*/
-void uart_init(uint8_t gsbi_id)
+void uart_dm_init(uint8_t id, uint32_t gsbi_base, uint32_t uart_dm_base)
{
static uint8_t port = 0;
char *data = "Android Bootloader - UART_DM Initialized!!!\n";
- msm_boot_uart_dm_init(gsbi_id);
- msm_boot_uart_dm_write(gsbi_id, data, 44);
+ /* Configure the uart clock */
+ clock_config_uart_dm(id);
+ dsb();
+
+ /* Configure GPIO to provide connectivity between GSBI
+ product ports and chip pads */
+ gpio_config_uart_dm(id);
+ dsb();
+
+ /* Configure GSBI for UART_DM protocol.
+ * I2C on 2 ports, UART (without HS flow control) on the other 2. */
+ writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,
+ GSBI_CTRL_REG(gsbi_base));
+ dsb();
+
+ /* Configure clock selection register for tx and rx rates.
+ * Selecting 115.2k for both RX and TX.
+ */
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(uart_dm_base));
+ dsb();
+
+ /* Intialize UART_DM */
+ msm_boot_uart_dm_init(uart_dm_base);
+
+ msm_boot_uart_dm_write(uart_dm_base, data, 44);
ASSERT(port < ARRAY_SIZE(gsbi_lookup));
- gsbi_lookup[port++] = gsbi_id;
+ gsbi_lookup[port++] = uart_dm_base;
/* Set UART init flag */
uart_init_flag = 1;
@@ -417,13 +404,13 @@
*/
int uart_putc(int port, char c)
{
- uint8_t gsbi_id = gsbi_lookup[port];
+ uint32_t gsbi_base = gsbi_lookup[port];
/* Don't do anything if UART is not initialized */
if (!uart_init_flag)
- return;
+ return -1;
- msm_boot_uart_dm_write(gsbi_id, &c, 1);
+ msm_boot_uart_dm_write(gsbi_base, &c, 1);
return 0;
}
@@ -436,16 +423,16 @@
{
int byte;
static unsigned int word = 0;
- uint8_t gsbi_id = gsbi_lookup[port];
+ uint32_t gsbi_base = gsbi_lookup[port];
/* Don't do anything if UART is not initialized */
if (!uart_init_flag)
- return;
+ return -1;
if (!word) {
/* Read from FIFO only if it's a first read or all the four
* characters out of a word have been read */
- if (msm_boot_uart_dm_read(gsbi_id, &word, wait) !=
+ if (msm_boot_uart_dm_read(gsbi_base, &word, wait) !=
MSM_BOOT_UART_DM_E_SUCCESS) {
return -1;
}
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index 5a619f8..0673dea 100644
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -44,6 +44,7 @@
#include <target.h>
#include <platform.h>
#include <baseband.h>
+#include <uart_dm.h>
/* 8960 */
#define LINUX_MACHTYPE_8960_SIM 3230
@@ -84,14 +85,14 @@
static pm8921_dev_t pmic;
static void target_detect(void);
-static uint8_t get_uart_gsbi(void);
+static void target_uart_init(void);
void target_early_init(void)
{
target_detect();
#if WITH_DEBUG_UART
- uart_init(get_uart_gsbi());
+ target_uart_init();
#endif
}
@@ -169,6 +170,11 @@
return target_id;
}
+unsigned board_platform_id(void)
+{
+ return platform_id;
+}
+
void target_detect(void)
{
struct smem_board_info_v6 board_info_v6;
@@ -375,7 +381,7 @@
pm8921_boot_done();
}
-uint8_t get_uart_gsbi(void)
+void target_uart_init(void)
{
switch (target_id) {
case LINUX_MACHTYPE_8960_SIM:
@@ -386,23 +392,32 @@
case LINUX_MACHTYPE_8960_APQ:
case LINUX_MACHTYPE_8960_LIQUID:
- return GSBI_ID_5;
+ uart_dm_init(5, 0x16400000, 0x16440000);
+ break;
case LINUX_MACHTYPE_8930_CDP:
case LINUX_MACHTYPE_8930_MTP:
case LINUX_MACHTYPE_8930_FLUID:
- return GSBI_ID_5;
+ uart_dm_init(5, 0x16400000, 0x16440000);
+ break;
case LINUX_MACHTYPE_8064_SIM:
case LINUX_MACHTYPE_8064_RUMI3:
+ uart_dm_init(3, 0x16200000, 0x16240000);
+ break;
- return GSBI_ID_3;
+ case LINUX_MACHTYPE_8064_CDP:
+ case LINUX_MACHTYPE_8064_MTP:
+ case LINUX_MACHTYPE_8064_LIQUID:
+ uart_dm_init(7, 0x16600000, 0x16640000);
+ break;
case LINUX_MACHTYPE_8627_CDP:
case LINUX_MACHTYPE_8627_MTP:
- return GSBI_ID_5;
+ uart_dm_init(5, 0x16400000, 0x16440000);
+ break;
default:
dprintf(CRITICAL, "uart gsbi not defined for target: %d\n",