Merge change Ic5ec30e2
* changes:
[target/msm7630]: Change MACH IDs for 8x55_surf and 8x55_ffa targets.
diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index fd7bf28..52c5f61 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -289,6 +289,13 @@
//;WCP15_L2VR3F1 r0
MCR p15, 0x3, r0, c15, c15, 0x1 //;write r0 to L2VR3F1
+ LDR r0, =0x20 //;additional delay for amp setting
+ LDR r1, =0x0
+loop:
+ SUBS r0, r0, #0x1
+ CMP r0, r1
+ BNE loop
+
LDR r0, =0 //;make sure the registers we touched
LDR r1, =0 //;are cleared when we return
LDR r2, =0
diff --git a/platform/msm_shared/timer.c b/platform/msm_shared/timer.c
index b249b23..9bdb166 100644
--- a/platform/msm_shared/timer.c
+++ b/platform/msm_shared/timer.c
@@ -82,6 +82,14 @@
#define SPSS_TIMER_STATUS GPT_REG(0x0034)
#endif
+#if defined PLATFORM_QSD8K
+#define DGT_HZ 4800000 /* Uses TCXO/4 (19.2 MHz / 4) */
+#elif defined PLATFORM_MSM7X30
+#define DGT_HZ 6144000 /* Uses LPXO/4 (24.576 MHz / 4) */
+#else
+#define DGT_HZ 19200000 /* Uses TCXO (19.2 MHz) */
+#endif
+
static platform_timer_callback timer_callback;
static void *timer_arg;
@@ -113,7 +121,7 @@
timer_arg = arg;
timer_interval = interval;
- writel(timer_interval * 19200, DGT_MATCH_VAL);
+ writel(timer_interval * (DGT_HZ / 1000), DGT_MATCH_VAL);
writel(0, DGT_CLEAR);
writel(DGT_ENABLE_EN | DGT_ENABLE_CLR_ON_MATCH_EN, DGT_ENABLE);
diff --git a/target/qsd8250_ffa/atags.c b/target/qsd8250_ffa/atags.c
index ec80183..77a1fb8 100644
--- a/target/qsd8250_ffa/atags.c
+++ b/target/qsd8250_ffa/atags.c
@@ -63,7 +63,7 @@
/* 2nd segment */
#ifdef USE_512M_RAM
- size = EBT1_SIZE2_512M;
+ size = EBI1_SIZE2_512M;
#else
size = 0;
#endif
diff --git a/target/qsd8250_surf/atags.c b/target/qsd8250_surf/atags.c
index ec80183..77a1fb8 100644
--- a/target/qsd8250_surf/atags.c
+++ b/target/qsd8250_surf/atags.c
@@ -63,7 +63,7 @@
/* 2nd segment */
#ifdef USE_512M_RAM
- size = EBT1_SIZE2_512M;
+ size = EBI1_SIZE2_512M;
#else
size = 0;
#endif