Merge "appsbl: qseecom_lk: Add stub for cmnlib64 loading"
diff --git a/include/platform.h b/include/platform.h
index 9c8e698..745389d 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -70,6 +70,5 @@
uint32_t platform_detect_panel();
uint32_t platform_get_max_periph();
int platform_is_msm8996();
-uint64_t platform_get_ddr_start();
bool platform_use_qmp_misc_settings();
#endif
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index b1d223f..de4616b 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -544,9 +544,4 @@
#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
-#define DDR_START platform_get_ddr_start()
-#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
-#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2200000
-#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x2000000
-#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
#endif
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index 6bad8f6..79bf7c9 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -68,19 +68,12 @@
/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
{ 0x00000000, 0x00000000, MMU_L2_NS_SECTION_MAPPING, 512, IOMAP_MEMORY},
{ MEMBASE, MEMBASE, MMU_L2_NS_SECTION_MAPPING, (MEMSIZE / MB), LK_MEMORY},
+ { KERNEL_ADDR, KERNEL_ADDR, MMU_L2_NS_SECTION_MAPPING, KERNEL_SIZE, SCRATCH_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, MMU_L2_NS_SECTION_MAPPING, SCRATCH_SIZE, SCRATCH_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, MMU_L2_NS_SECTION_MAPPING, MSM_SHARED_SIZE, COMMON_MEMORY},
{ RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, MMU_L2_NS_SECTION_MAPPING, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
-static mmu_section_t default_mmu_section_table_3gb[] =
-{
-/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
- { 0x40000000, 0x40000000, MMU_L1_NS_SECTION_MAPPING, 1024 , COMMON_MEMORY},
- { 0x80000000, 0x80000000, MMU_L2_NS_SECTION_MAPPING, 88 , COMMON_MEMORY},
-};
-
-
/* Map the ddr for download mode, this region belongs to non-hlos images and pil */
static mmu_section_t dload_mmu_section_table[] =
{
@@ -122,52 +115,11 @@
{
int i;
int table_sz = ARRAY_SIZE(default_mmu_section_table);
- mmu_section_t kernel_mmu_section_table;
- uint64_t ddr_size = smem_get_ddr_size();
- uint32_t kernel_size = 0;
-
- if (ddr_size == MEM_4GB)
- {
- ddr_start = 0x80000000;
- /* As per the memory map when DDR is 4GB first 88 MB is hlos memory
- * use this for loading the kernel
- */
- kernel_size = 88;
- }
- else if (ddr_size == MEM_3GB)
- {
- ddr_start = 0x20000000;
- /* As per memory map wheh DDR is 3GB the first 512 MB is assigned to hlos
- * use this region for loading kernel
- */
- kernel_size = 512;
- }
- else
- {
- dprintf(CRITICAL, "Unsupported memory map\n");
- ASSERT(0);
- }
-
- kernel_mmu_section_table.paddress = ddr_start;
- kernel_mmu_section_table.vaddress = ddr_start;
- kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
- kernel_mmu_section_table.size = kernel_size;
- kernel_mmu_section_table.flags = SCRATCH_MEMORY;
-
- /* Map kernel entry */
- arm_mmu_map_entry(&kernel_mmu_section_table);
/* Map default memory needed for lk , scratch, rpmb & iomap */
for (i = 0 ; i < table_sz; i++)
arm_mmu_map_entry(&default_mmu_section_table[i]);
- /* Map the rest of the DDR for 3GB needed for ramdump */
- if (ddr_size == MEM_3GB)
- {
- for (i = 0 ; i < (int)ARRAY_SIZE(default_mmu_section_table_3gb); i++)
- arm_mmu_map_entry(&default_mmu_section_table_3gb[i]);
- }
-
if (scm_device_enter_dload())
{
/* TZ & Hyp memory can be mapped only while entering the download mode */
diff --git a/platform/msm_shared/include/qusb2_phy.h b/platform/msm_shared/include/qusb2_phy.h
index fc971c8..d3ed338 100644
--- a/platform/msm_shared/include/qusb2_phy.h
+++ b/platform/msm_shared/include/qusb2_phy.h
@@ -32,6 +32,8 @@
void qusb2_phy_reset(void);
+#define QUSB2PHY_PLL_LOCK 0x20
+
#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
#define QUSB2PHY_PLL_TEST (QUSB2_PHY_BASE + 0x00000004)
@@ -45,6 +47,7 @@
#define QUSB2PHY_PORT_TEST2 (QUSB2_PHY_BASE + 0x0000009C)
#define QUSB2PHY_PLL_PWR_CTL (QUSB2_PHY_BASE + 0x00000018)
#define QUSB2PHY_PLL_AUTOPGM_CTL1 (QUSB2_PHY_BASE + 0x0000001C)
+#define QUSB2PHY_PLL_STATUS (QUSB2_PHY_BASE + 0x00000038)
#endif
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 0474f37..d336f8b 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -837,7 +837,7 @@
}
writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL);
- if (pinfo->mipi.broadcast)
+ if (pinfo->mipi.dual_dsi)
writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL);
return NO_ERROR;
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 8981df7..edc0ecc 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -49,6 +49,11 @@
/* Default tune value */
uint8_t tune2 = 0xB3;
+ /* Disable the ref clock before phy reset */
+#if GCC_RX2_USB2_CLKREF_EN
+ writel((readl(GCC_RX2_USB2_CLKREF_EN) & ~0x1), GCC_RX2_USB2_CLKREF_EN);
+ dmb();
+#endif
/* Block Reset */
val = readl(GCC_QUSB2_PHY_BCR) | BIT(0);
writel(val, GCC_QUSB2_PHY_BCR);
@@ -113,4 +118,16 @@
/* Enable PHY */
/* set CLAMP_N_EN and USB PHY is enabled*/
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
+ udelay(150);
+
+ /* Check PLL status */
+ if (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK))
+ {
+ dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS));
+ }
+
+#if GCC_RX2_USB2_CLKREF_EN
+ writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN);
+ dmb();
+#endif
}
diff --git a/platform/msm_shared/reboot.c b/platform/msm_shared/reboot.c
index 8f53633..6d97b0c 100644
--- a/platform/msm_shared/reboot.c
+++ b/platform/msm_shared/reboot.c
@@ -71,12 +71,13 @@
uint8_t hard_restart_reason = 0;
/* Read reboot reason and scrub it
- * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason
+ * Bit-2 to bit-7 of SOFT_RB_SPARE for hard reset reason
*/
hard_restart_reason = REG_READ(PON_SOFT_RB_SPARE);
- REG_WRITE(PON_SOFT_RB_SPARE, hard_restart_reason & 0x1f);
+ REG_WRITE(PON_SOFT_RB_SPARE, hard_restart_reason & 0x03);
- return hard_restart_reason;
+ /* Extract the bits 5 to 7 and return */
+ return hard_restart_reason & 0xFC;
}
/* Return true if it is triggered by alarm. */
diff --git a/project/msm8996.mk b/project/msm8996.mk
index 7033b92..586922a 100644
--- a/project/msm8996.mk
+++ b/project/msm8996.mk
@@ -36,6 +36,11 @@
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80080000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82200000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x82000000
+DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
+
DEFINES += USB_RESET_FROM_CLK=1
DEFINES += USE_BOOTDEV_CMDLINE=1
DEFINES += USE_RPMB_FOR_DEVINFO=1
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index 49bacca..cf294bf 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -15,6 +15,9 @@
SCRATCH_ADDR := 0x91C00000
SCRATCH_SIZE := 740
+KERNEL_ADDR := 0x80000000
+KERNEL_SIZE := 88
+
# LPAE supports only 32 virtual address, L1 pt size is 4
L1_PT_SZ := 4
L2_PT_SZ := 3
@@ -39,6 +42,8 @@
BASE_ADDR=$(BASE_ADDR) \
TAGS_ADDR=$(TAGS_ADDR) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ KERNEL_SIZE=$(KERNEL_SIZE) \
SCRATCH_ADDR=$(SCRATCH_ADDR) \
SCRATCH_SIZE=$(SCRATCH_SIZE) \
L1_PT_SZ=$(L1_PT_SZ) \