Merge "target: mdm9635: Do not fill board target info"
diff --git a/platform/mdm9x35/include/platform/iomap.h b/platform/mdm9x35/include/platform/iomap.h
index cf84ee7..81fd263 100755
--- a/platform/mdm9x35/include/platform/iomap.h
+++ b/platform/mdm9x35/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -55,6 +55,9 @@
#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
#define SPMI_BASE 0xFC4C0000
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
diff --git a/platform/mdm9x35/platform.c b/platform/mdm9x35/platform.c
index cab35c5..3604205 100755
--- a/platform/mdm9x35/platform.c
+++ b/platform/mdm9x35/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -110,6 +110,16 @@
return 0;
}
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
+
void platform_init_mmu_mappings(void)
{
struct smem_ram_ptable *ram_ptable;
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 00c6bdf..94fd16d 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -29,12 +29,12 @@
#ifndef _PLATFORM_MSM8916_IOMAP_H_
#define _PLATFORM_MSM8916_IOMAP_H_
-#define MSM_IOMAP_BASE 0xF9000000
-#define MSM_IOMAP_END 0xFEFFFFFF
+#define MSM_IOMAP_BASE 0x0B000000
+#define MSM_IOMAP_END 0xBEFFFFF
#define SDRAM_START_ADDR 0x80000000
-#define MSM_SHARED_BASE 0xFA000000
+#define MSM_SHARED_BASE 0x8E380000
#define APPS_SS_BASE 0x0B000000
@@ -64,15 +64,15 @@
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
-#define MSM_CE1_BAM_BASE 0xFD404000
-#define MSM_CE1_BASE 0xFD41A000
+#define MSM_CE1_BAM_BASE 0x00704000
+#define MSM_CE1_BASE 0x0073A000
-#define TLMM_BASE_ADDR 0xFD510000
+#define TLMM_BASE_ADDR 0x1000000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
-#define MPM2_MPM_CTRL_BASE 0xFC4A1000
-#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_CTRL_BASE 0x004A1000
+#define MPM2_MPM_PS_HOLD 0x004AB0000
/* CE 2 */
#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index e9ea428..0f592f9 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -364,9 +364,6 @@
uint32_t iv_len = 0;
uint32_t *auth_iv = sha1_ctx->auth_iv;
uint32_t seg_cfg_val;
- uint32_t total_bytes_to_write = sha256_ctx->bytes_to_write;
- uint32_t bytes_to_write = total_bytes_to_write;
- uint32_t burst_mask;
if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
{
@@ -388,6 +385,8 @@
/* Initialize CE pointers. */
REG_WRITE_QUEUE_INIT(dev);
+ /* For authentication operation set the encryption cfg reg to 0 as per HPG */
+ REG_WRITE_QUEUE(dev, CRYPTO_ENCR_SEG_CFG(dev->base), 0);
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_CFG(dev->base), seg_cfg_val);
for (i = 0; i < iv_len; i++)
@@ -398,31 +397,77 @@
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), (*(auth_iv + i)));
}
- /* Check if the transfer length is a 8 beat burst multiple. */
- burst_mask = CRYPTO_BURST_LEN - 1;
- if (bytes_to_write & burst_mask)
- {
- /* Add trailer to make it a burst multiple. */
- total_bytes_to_write = (bytes_to_write + burst_mask) & (~burst_mask);
- }
-
- sha256_ctx->bytes_to_write = total_bytes_to_write;
-
/* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt
* in both crypto_SHA1_ctx and crypto_SHA256_ctx are same.
*/
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 0), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0]);
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 1), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1]);
+}
- /* Assume no header, always. */
- REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_START(dev->base), 0);
+/* Function: crypto5_set_auth_cfg
+ * Arg : dev, ptr to data buffer, buffer_size, burst_mask for alignment
+ * Return : aligned buffer incase of unaligned data_ptr and total no. of bytes
+ * passed to crypto HW(includes header and trailer size).
+ * Flow : If data buffer is aligned, we just configure the crypto auth
+ * registers for start, size of data etc. If buffer is unaligned
+ * we align it to burst(64-byte) boundary and also make the no. of
+ * bytes a multiple of 64 for bam and then configure the registers
+ * for header/trailer settings.
+ */
+static void crypto5_set_auth_cfg(struct crypto_dev *dev, uint8_t **buffer,
+ uint8_t *data_ptr,
+ uint32_t burst_mask,
+ uint32_t bytes_to_write,
+ uint32_t *total_bytes_to_write)
+{
+ uint32_t minor_ver = 0;
+ uint32_t auth_seg_start = 0;
+
+ /* Bits 23:16 - minor version */
+ minor_ver = (readl(CRYPTO_VERSION(dev->base)) & 0x00FF0000) >> 16;
+
+ /* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must
+ * be burst aligned. Here we use the header/trailer crypto register settings.
+ * buffer : The previous 64 byte aligned address for data_ptr.
+ * CRYPTO_AUTH_SEG_START : Number of bytes to skip to reach the address data_ptr.
+ * CRYPTO_AUTH_SEG_SIZE : Number of bytes to be sent to crypto HW.
+ * CRYPTO_SEG_SIZE : CRYPTO_AUTH_SEG_START + CRYPTO_AUTH_SEG_SIZE.
+ * Function: We pick a previous 64 byte aligned address buffer, and tell crypto to
+ * skip (data_ptr - buffer) number of bytes.
+ * This bug is fixed in 5.1.0 onwards.*/
+
+ if(minor_ver == 0)
+ {
+ if ((uint32_t) data_ptr & (CRYPTO_BURST_LEN - 1))
+ {
+ dprintf(CRITICAL, "Data start not aligned at burst length.\n");
+
+ *buffer = (uint8_t *)ROUNDDOWN((uint32_t)data_ptr, CRYPTO_BURST_LEN);
+
+ /* Header & Trailer */
+ *total_bytes_to_write = ((bytes_to_write +(data_ptr - *buffer) + burst_mask) & (~burst_mask));
+
+ auth_seg_start = (data_ptr - *buffer);
+ }
+ else
+ {
+ /* No header */
+ /* Add trailer to make it a burst multiple as 5.0.x HW mandates data to be a multiple of 64. */
+ *total_bytes_to_write = (bytes_to_write + burst_mask) & (~burst_mask);
+ }
+ }
+ else
+ {
+ /* No header. 5.1 crypto HW doesnt require alignment as partial reads and writes are possible*/
+ *total_bytes_to_write = bytes_to_write;
+ }
+
+ REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_START(dev->base), auth_seg_start);
REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_SIZE(dev->base), bytes_to_write);
- REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), total_bytes_to_write);
+ REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), *total_bytes_to_write);
REG_WRITE_QUEUE(dev, CRYPTO_GOPROC(dev->base), GOPROC_GO);
-
REG_WRITE_QUEUE_DONE(dev, BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG);
-
REG_WRITE_EXEC(&dev->bam, 1, CRYPTO_WRITE_PIPE_INDEX);
}
@@ -434,44 +479,22 @@
crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
uint32_t wr_flags = BAM_DESC_NWD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_EOT_FLAG;
uint32_t ret_status;
- uint32_t minor_ver = 0;
uint8_t *buffer = NULL;
+ uint32_t total_bytes_to_write = 0;
- /* Bits 23:16 - minor version */
- minor_ver = (readl(CRYPTO_VERSION(dev->base)) & 0x00FF0000) >> 16;
-
- /* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must be burst aligned.
- * This bug is fixed in 5.1.0 onwards.*/
-
- if(minor_ver == 0)
- {
- if ((uint32_t) data_ptr & (CRYPTO_BURST_LEN - 1))
- {
- dprintf(CRITICAL, "Data start not aligned at burst length.\n");
-
- buffer = (uint8_t *)memalign(CRYPTO_BURST_LEN, sha256_ctx->bytes_to_write);
- if(!buffer)
- {
- dprintf(CRITICAL, "ERROR: Failed to allocate burst aligned crypto buffer\n");
- ret_status = CRYPTO_ERR_FAIL;
- goto CRYPTO_SEND_DATA_ERR;
- }
-
- memset(buffer, 0, sha256_ctx->bytes_to_write);
- memcpy(buffer, data_ptr, sha256_ctx->bytes_to_write);
- }
- }
+ crypto5_set_auth_cfg(dev, &buffer, data_ptr, CRYPTO_BURST_LEN - 1, sha256_ctx->bytes_to_write,
+ &total_bytes_to_write);
if(buffer)
{
- arch_clean_invalidate_cache_range((addr_t) buffer, sha256_ctx->bytes_to_write);
+ arch_clean_invalidate_cache_range((addr_t) buffer, total_bytes_to_write);
- bam_status = ADD_WRITE_DESC(&dev->bam, buffer, sha256_ctx->bytes_to_write, wr_flags);
+ bam_status = ADD_WRITE_DESC(&dev->bam, buffer, total_bytes_to_write, wr_flags);
}
else
{
- arch_clean_invalidate_cache_range((addr_t) data_ptr, sha256_ctx->bytes_to_write);
- bam_status = ADD_WRITE_DESC(&dev->bam, data_ptr, sha256_ctx->bytes_to_write, wr_flags);
+ arch_clean_invalidate_cache_range((addr_t) data_ptr, total_bytes_to_write);
+ bam_status = ADD_WRITE_DESC(&dev->bam, data_ptr, total_bytes_to_write, wr_flags);
}
if (bam_status)
@@ -505,9 +528,6 @@
CRYPTO_SEND_DATA_ERR:
- if(buffer)
- free(buffer);
-
return ret_status;
}
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index ec6a88b..fd77583 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -2479,9 +2479,24 @@
mmc_read(unsigned long long data_addr, unsigned int *out, unsigned int data_len)
{
int val = 0;
- val =
- mmc_boot_read_from_card(&mmc_host, &mmc_card, data_addr, data_len,
- out);
+ unsigned int data_limit = mmc_card.rd_block_len * 0xffff;
+ unsigned int this_len;
+
+ do {
+ this_len = (data_len > data_limit) ? data_limit : data_len;
+
+ val =
+ mmc_boot_read_from_card(&mmc_host, &mmc_card, data_addr,
+ this_len, out);
+
+ if (val != MMC_BOOT_E_SUCCESS)
+ return val;
+
+ data_len -= this_len;
+ data_addr += this_len;
+ out += (this_len / sizeof(*out));
+ } while (data_len > 0);
+
return val;
}
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 5592f20..db09374 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -69,6 +69,7 @@
cmd = memalign(CACHE_LINE, ROUNDUP(len, CACHE_LINE));
if (cmd) {
+ memset(cmd, 0, len);
cmd->len = len;
cmd->buf_offset = offsetof(struct scm_command, buf);
cmd->resp_hdr_offset = cmd->buf_offset + cmd_size;
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index 9aa36cc..35b5c6c 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -867,6 +867,12 @@
switch (event_id)
{
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ break;
case DWC_EVENT_EP_XFER_NOT_READY:
{
if (event_ctrl_stage == CONTROL_DATA_REQUEST)
@@ -923,6 +929,12 @@
switch (event_id)
{
+ case DWC_EVENT_EP_CMD_COMPLETE:
+ {
+ dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
+ DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ }
+ break;
case DWC_EVENT_EP_XFER_NOT_READY:
{
if (event_ctrl_stage == CONTROL_DATA_REQUEST)/* data request */
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index e61a6e7..4a8c577 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -122,6 +122,7 @@
struct ufs_dev ufs_device;
extern void ulpi_write(unsigned val, unsigned reg);
+extern int _emmc_recovery_init(void);
void target_early_init(void)
{
@@ -568,6 +569,11 @@
}
}
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
unsigned check_reboot_mode(void)
{
uint32_t restart_reason = 0;
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index a72f592..f5f1add 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -416,15 +416,19 @@
uint8_t target_panel_auto_detect_enabled()
{
uint8_t ret = 0;
+ uint32_t hw_subtype = board_hardware_subtype();
switch(board_hardware_id())
{
case HW_PLATFORM_QRD:
- /* Enable auto detect for DVT boards only */
- if (((board_target_id() >> 16) & 0xFF) == 0x2)
- ret = 1;
- else
- ret = 0;
+ if (hw_subtype != HW_PLATFORM_SUBTYPE_SKUF
+ && hw_subtype != HW_PLATFORM_SUBTYPE_SKUG) {
+ /* Enable autodetect for 8x26 DVT boards only */
+ if (((board_target_id() >> 16) & 0xFF) == 0x2)
+ ret = 1;
+ else
+ ret = 0;
+ }
break;
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP: