target: display: add supports of edp panel
Add edp support functions, such as clock, backlight and
edp panel type.
CRs-Fixed: 661151
Change-Id: I4acc69c90dc0fee2930ea2d55b167ef317c58f87
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 8d0637a..7f903fb 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -555,3 +555,59 @@
writel(0x0, DSI_PIXEL1_CBCR);
}
}
+
+void edp_clk_enable(void)
+{
+ int ret;
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_pixel_clk", 138500000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_pixel_clk ret = %d\n",
+ ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_link_clk", 270000000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_link_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_aux_clk", 19200000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_aux_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void edp_clk_disable(void)
+{
+
+ writel(0x0, MDSS_EDPPIXEL_CBCR);
+ writel(0x0, MDSS_EDPLINK_CBCR);
+ clk_disable(clk_get("edp_pixel_clk"));
+ clk_disable(clk_get("edp_link_clk"));
+ clk_disable(clk_get("edp_aux_clk"));
+}
+
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 1b5504c..08d6d2a 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -45,6 +45,8 @@
#define mmpll1_mm_source_val 2
#define mmpll3_mm_source_val 3
#define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -688,6 +690,87 @@
},
};
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+ .cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edpaux_clk,
+
+ .c = {
+ .dbg_name = "edpaux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+ .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .parent = &edpaux_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_edpaux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+ F_MDSS(162000000, edppll_270, 2, 0, 0),
+ F_MDSS(270000000, edppll_270, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+ .cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edplink_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edplink_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+ F_MDSS(138500000, edppll_350, 2, 0, 0),
+ F_MDSS(350000000, edppll_350, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+ .cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_mdss_edppixel_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edppixel_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk mdss_edplink_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+ .has_sibling = 0,
+ .parent = &edplink_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edplink_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+ .has_sibling = 0,
+ .parent = &edppixel_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edppixel_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct branch_clk gcc_sdcc1_cdccal_ff_clk = {
.cbcr_reg = SDCC1_CDCCAL_FF_CBCR,
.has_sibling = 1,
@@ -751,6 +834,10 @@
CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
+
+ CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
+ CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
+ CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index 943b9e5..7f4ebfd 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -87,6 +87,19 @@
#define DSI_PIXEL1_N REG_MM(0x202C)
#define DSI_PIXEL1_D REG_MM(0x2030)
+#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR REG_MM(0x2334)
+#define EDPPIXEL_M REG_MM(0x20A8)
+#define EDPPIXEL_N REG_MM(0x20AC)
+#define EDPPIXEL_D REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 08d3e3b..241285f 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -213,6 +213,8 @@
#define BOOT_CONFIG_OFFSET 0x00006034
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
+#define EDP_BASE (0xFD923400)
+
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
#define TRIG_CTRL 0x084
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 4bd6e6f..9b03643 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -233,7 +233,11 @@
$(LOCAL_DIR)/image_verify.o \
$(LOCAL_DIR)/crypto_hash.o \
$(LOCAL_DIR)/crypto5_eng.o \
- $(LOCAL_DIR)/crypto5_wrapper.o
+ $(LOCAL_DIR)/crypto5_wrapper.o \
+ $(LOCAL_DIR)/edp.o \
+ $(LOCAL_DIR)/edp_util.o \
+ $(LOCAL_DIR)/edp_aux.o \
+ $(LOCAL_DIR)/edp_phy.o
endif
diff --git a/target/apq8084/include/target/display.h b/target/apq8084/include/target/display.h
index 79fa6be..8d6eb87 100644
--- a/target/apq8084/include/target/display.h
+++ b/target/apq8084/include/target/display.h
@@ -52,6 +52,15 @@
static struct gpio_pin pwm_gpio = {
"pm8084", 7, 3, 1, 0, 1
};
+
+static struct gpio_pin edp_lvl_en_gpio = {
+ "msmgpio", 91, 3, 1, 0, 1
+};
+
+static struct gpio_pin edp_hpd_gpio = { /* input */
+ "msmgpio", 103, 3, 0, 0, 1
+};
+
/*---------------------------------------------------------------------------*/
/* LDO configuration */
/*---------------------------------------------------------------------------*/
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 706ee58..ae3b071 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -51,6 +51,10 @@
#define GPIO_STATE_HIGH 2
#define RESET_GPIO_SEQ_LEN 3
+static struct backlight edp_bklt = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
static uint32_t dsi_pll_lock_status(uint32_t pll_base)
{
uint32_t counter, status;
@@ -137,7 +141,7 @@
if (enable) {
pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
- /* lpg channel 2 */
+ /* lpg channel 3 */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
@@ -285,6 +289,79 @@
return NO_ERROR;
}
+void target_edp_panel_init(struct msm_panel_info *pinfo)
+{
+ edp_panel_init(pinfo);
+}
+
+int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ uint32_t ret;
+
+ dprintf(SPEW, "%s: target_panel_clock\n", __func__);
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+
+ edp_clk_enable();
+ } else if(!target_cont_splash_screen()) {
+ /* Disable clocks if continuous splash off */
+ edp_clk_disable();
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return NO_ERROR;
+}
+
+int target_edp_panel_enable(void)
+{
+ gpio_tlmm_config(enable_gpio.pin_id, 0, /* gpio 137 */
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength, enable_gpio.pin_state);
+
+
+ gpio_tlmm_config(edp_hpd_gpio.pin_id, 0, /* hpd 103 */
+ edp_hpd_gpio.pin_direction, edp_hpd_gpio.pin_pull,
+ edp_hpd_gpio.pin_strength, edp_hpd_gpio.pin_state);
+
+
+ gpio_tlmm_config(edp_lvl_en_gpio.pin_id, 0, /* lvl_en 91 */
+ edp_lvl_en_gpio.pin_direction, edp_lvl_en_gpio.pin_pull,
+ edp_lvl_en_gpio.pin_strength, edp_lvl_en_gpio.pin_state);
+
+ gpio_set(enable_gpio.pin_id, 2);
+ gpio_set(edp_lvl_en_gpio.pin_id, 2);
+
+ return NO_ERROR;
+}
+
+int target_edp_panel_disable(void)
+{
+ gpio_set(edp_lvl_en_gpio.pin_id, 0);
+ gpio_set(enable_gpio.pin_id, 0);
+
+ return NO_ERROR;
+}
+
+int target_edp_bl_ctrl(int enable)
+{
+ return target_backlight_ctrl(&edp_bklt, enable);
+}
+
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);