lk: msm: Fix files to have uniform coding style
No functional changes, just style code formatting style changes here.
Change-Id: Id3f1995ef97765b393c5c26259011c9ce1321106
diff --git a/platform/msm_shared/adm.c b/platform/msm_shared/adm.c
old mode 100755
new mode 100644
index c5bf140..a06e77a
--- a/platform/msm_shared/adm.c
+++ b/platform/msm_shared/adm.c
@@ -27,7 +27,6 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
#include <stdlib.h>
#include <reg.h>
@@ -39,7 +38,6 @@
* by other peripherals such as usb/uart/nand/display etc.
*/
-
/* TODO:
* adm module shouldn't have to include mmc.h.
* clean this up when generic adm interface is implemented.
@@ -59,24 +57,22 @@
* Must be aligned on 8 byte boundary.
*/
static uint32_t adm_cmd_ptr_list[8] __attribute__ ((aligned(8)));
-static uint32_t box_mode_entry[8] __attribute__ ((aligned(8)));
+static uint32_t box_mode_entry[8] __attribute__ ((aligned(8)));
-adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t *cmd_ptr_list);
-
+adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t * cmd_ptr_list);
/* CRCI - mmc slot mapping. */
extern uint8_t sdc_crci_map[5];
-
/* TODO:
* This interface is very specific to MMC.
* We need a generic ADM interface that can be easily
* used by other modules such as usb/uart/nand.
*/
-adm_result_t adm_transfer_mmc_data(unsigned char slot,
- unsigned char* data_ptr,
- unsigned int data_len,
- unsigned char direction)
+adm_result_t
+adm_transfer_mmc_data(unsigned char slot,
+ unsigned char *data_ptr,
+ unsigned int data_len, unsigned char direction)
{
uint32_t num_rows;
uint16_t row_len;
@@ -85,33 +81,26 @@
uint32_t adm_crci_num;
adm_result_t result = ADM_RESULT_SUCCESS;
-
/* Make sure slot value is in the range 1..4 */
- ASSERT( (slot >= 1) && (slot <= 4));
+ ASSERT((slot >= 1) && (slot <= 4));
- adm_crci_num = sdc_crci_map[slot];
- row_len = MMC_BOOT_MCI_FIFO_SIZE;
- num_rows = data_len/MMC_BOOT_MCI_FIFO_SIZE;
-
+ adm_crci_num = sdc_crci_map[slot];
+ row_len = MMC_BOOT_MCI_FIFO_SIZE;
+ num_rows = data_len / MMC_BOOT_MCI_FIFO_SIZE;
/* While there is data to be transferred */
- while(data_len)
- {
- if(data_len <= MAX_ROW_LEN)
- {
- row_len = data_len;
+ while (data_len) {
+ if (data_len <= MAX_ROW_LEN) {
+ row_len = data_len;
row_offset = 0;
- row_num = 1;
- }
- else
- {
- row_len = MAX_ROW_LEN;
+ row_num = 1;
+ } else {
+ row_len = MAX_ROW_LEN;
row_offset = MAX_ROW_LEN;
- row_num = data_len/MAX_ROW_LEN;
+ row_num = data_len / MAX_ROW_LEN;
/* Limit the number of row to the max value allowed */
- if(row_num > MAX_ROW_NUM)
- {
+ if (row_num > MAX_ROW_NUM) {
row_num = MAX_ROW_NUM;
}
}
@@ -119,52 +108,47 @@
/* Program ADM registers and initiate data transfer */
/* Initialize the Box Mode command entry (single entry) */
- box_mode_entry[0] = ( ADM_CMD_LIST_LC |
- (adm_crci_num << 3) |
- ADM_ADDR_MODE_BOX);
+ box_mode_entry[0] = (ADM_CMD_LIST_LC |
+ (adm_crci_num << 3) | ADM_ADDR_MODE_BOX);
- if(direction == ADM_MMC_READ)
- {
- box_mode_entry[1] = MMC_BOOT_MCI_FIFO; /* SRC addr */
- box_mode_entry[2] = (uint32_t) data_ptr; /* DST addr */
- box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
- (row_len << 0)); /* DST row len */
- box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
- (row_num << 0)); /* DST row # */
- box_mode_entry[5] = ((0 << 16) | /* SRC offset */
- (row_offset << 0)); /* DST offset */
- }
- else
- {
- box_mode_entry[1] = (uint32_t) data_ptr; /* SRC addr */
- box_mode_entry[2] = MMC_BOOT_MCI_FIFO; /* DST addr */
- box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
- (row_len << 0)); /* DST row len */
- box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
- (row_num << 0)); /* DST row # */
- box_mode_entry[5] = ((row_offset << 16)| /* SRC offset */
- (0 << 0)); /* DST offset */
+ if (direction == ADM_MMC_READ) {
+ box_mode_entry[1] = MMC_BOOT_MCI_FIFO; /* SRC addr */
+ box_mode_entry[2] = (uint32_t) data_ptr; /* DST addr */
+ box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
+ (row_len << 0)); /* DST row len */
+ box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
+ (row_num << 0)); /* DST row # */
+ box_mode_entry[5] = ((0 << 16) | /* SRC offset */
+ (row_offset << 0)); /* DST offset */
+ } else {
+ box_mode_entry[1] = (uint32_t) data_ptr; /* SRC addr */
+ box_mode_entry[2] = MMC_BOOT_MCI_FIFO; /* DST addr */
+ box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
+ (row_len << 0)); /* DST row len */
+ box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
+ (row_num << 0)); /* DST row # */
+ box_mode_entry[5] = ((row_offset << 16) | /* SRC offset */
+ (0 << 0)); /* DST offset */
}
/* Initialize the ADM Command Pointer List (single entry) */
adm_cmd_ptr_list[0] = (ADM_CMD_PTR_LP |
ADM_CMD_PTR_CMD_LIST |
- (((uint32_t)(&box_mode_entry[0])) >> 3));
-
+ (((uint32_t) (&box_mode_entry[0])) >>
+ 3));
/* Start ADM transfer, this is a blocking call. */
result = adm_transfer_start(ADM_CHN, adm_cmd_ptr_list);
- if(result != ADM_RESULT_SUCCESS)
- {
+ if (result != ADM_RESULT_SUCCESS) {
break;
}
/* Update the data ptr and data len by the amount
* we just transferred.
*/
- data_ptr += (row_len*row_num);
- data_len -= (row_len*row_num);
+ data_ptr += (row_len * row_num);
+ data_len -= (row_len * row_num);
}
return result;
@@ -174,32 +158,29 @@
* Start the ADM data transfer and return the result of the transfer.
* Blocks until transfer is completed.
*/
-adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t *cmd_ptr_list)
+adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t * cmd_ptr_list)
{
uint32_t reg_value;
- uint32_t timeout = 1;
+ uint32_t timeout = 1;
uint32_t delay_count = 100;
-
/* Memory barrier to ensure that all ADM command list structure
* writes have completed before starting the ADM transfer.
*/
dmb();
/* Start the ADM transfer by writing the command ptr */
- writel( ((uint32_t)cmd_ptr_list) >> 3,
- ADM_REG_CMD_PTR(adm_chn, ADM_SD));
+ writel(((uint32_t) cmd_ptr_list) >> 3,
+ ADM_REG_CMD_PTR(adm_chn, ADM_SD));
/* Poll the status register to check for transfer complete.
* Bail out if transfer is not finished within 1 sec.
* Note: This time depends on the amount of data being transferred.
* Increase the delay_count if this is not sufficient.
*/
- do
- {
+ do {
reg_value = readl(ADM_REG_STATUS(adm_chn, ADM_SD));
- if((reg_value & ADM_REG_STATUS__RSLT_VLD___M) != 0)
- {
+ if ((reg_value & ADM_REG_STATUS__RSLT_VLD___M) != 0) {
timeout = 0;
break;
}
@@ -207,7 +188,8 @@
/* 10ms wait */
mdelay(10);
- } while(delay_count--);
+ }
+ while (delay_count--);
/* Read out the IRQ register to clear the interrupt.
* Even though we are not using interrupts,
@@ -216,20 +198,16 @@
*/
reg_value = readl(ADM_REG_IRQ(ADM_SD));
- if(timeout)
- {
+ if (timeout) {
return ADM_RESULT_TIMEOUT;
- }
- else
- {
+ } else {
/* Get the result from the RSLT FIFO */
reg_value = readl(ADM_REG_RSLT(adm_chn, ADM_SD));
/* Check for any error */
- if(((reg_value & ADM_REG_RSLT__ERR___M) != 0) ||
- ((reg_value & ADM_REG_RSLT__TPD___M) == 0) ||
- ((reg_value & ADM_REG_RSLT__V___M) == 0))
- {
+ if (((reg_value & ADM_REG_RSLT__ERR___M) != 0) ||
+ ((reg_value & ADM_REG_RSLT__TPD___M) == 0) ||
+ ((reg_value & ADM_REG_RSLT__V___M) == 0)) {
return ADM_RESULT_FAILURE;
}
}