lk: msm: Fix files to have uniform coding style
No functional changes, just style code formatting style changes here.
Change-Id: Id3f1995ef97765b393c5c26259011c9ce1321106
diff --git a/platform/msm7x27a/acpuclock.c b/platform/msm7x27a/acpuclock.c
index 4d923e6..33375ad 100644
--- a/platform/msm7x27a/acpuclock.c
+++ b/platform/msm7x27a/acpuclock.c
@@ -49,11 +49,11 @@
#define PLL_BYPASSNL BIT(1)
#define PLL_OUTCTRL BIT(0)
-#define SRC_SEL_TCX0 0 /* TCXO */
-#define SRC_SEL_PLL1 1 /* PLL1: modem_pll */
-#define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */
-#define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */
-#define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */
+#define SRC_SEL_TCX0 0 /* TCXO */
+#define SRC_SEL_PLL1 1 /* PLL1: modem_pll */
+#define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */
+#define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */
+#define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */
#define DIV_1 0
#define DIV_2 1
@@ -77,7 +77,7 @@
#define MIN_AXI_HZ 120000000
#define ACPU_800MHZ 41
-#define A11S_CLK_SEL_MASK 0x7 /* bits 2:0 */
+#define A11S_CLK_SEL_MASK 0x7 /* bits 2:0 */
/* The stepping frequencies have been choosen to make sure the step
* is <= 256 MHz for both 7x27a and 7x25a targets. The
@@ -91,21 +91,21 @@
*/
uint32_t const clk_cntl_reg_val_7627A[] = {
- (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8),
- (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
/* TODO: Fix it for 800MHz */
#if 0
- (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1,
#endif
};
uint32_t const clk_cntl_reg_val_7625A[] = {
- (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8),
- (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
};
@@ -113,34 +113,33 @@
* mode. Able to use DIV_1 for all steps because it's the largest AND
* the final value. */
uint32_t const clk_sel_reg_val[] = {
- DIV_1 << 1 | 1, /* Switch to src1 */
- DIV_1 << 1 | 0, /* Switch to src0 */
+ DIV_1 << 1 | 1, /* Switch to src1 */
+ DIV_1 << 1 | 0, /* Switch to src0 */
};
/*
* Mask to make sure current selected src frequency doesn't change.
*/
uint32_t const clk_cntl_mask[] = {
- 0x0000FF00, /* Mask to read src0 */
- 0x000000FF /* Mask to read src1 */
+ 0x0000FF00, /* Mask to read src0 */
+ 0x000000FF /* Mask to read src1 */
};
/* enum for SDC CLK IDs */
-enum
-{
- SDC1_CLK = 19,
+enum {
+ SDC1_CLK = 19,
SDC1_PCLK = 20,
- SDC2_CLK = 21,
+ SDC2_CLK = 21,
SDC2_PCLK = 22,
- SDC3_CLK = 23,
+ SDC3_CLK = 23,
SDC3_PCLK = 24,
- SDC4_CLK = 25,
+ SDC4_CLK = 25,
SDC4_PCLK = 26
};
/* Zero'th entry is dummy */
-static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
-static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+static uint8_t sdc_clk[] = { 0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK };
+static uint8_t sdc_pclk[] = { 0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK };
void mdelay(unsigned msecs);
unsigned board_msm_id(void);
@@ -151,8 +150,8 @@
uint32_t nVal;
/* Check status */
- nVal = readl(pll_mode_addr);
- if(nVal & PLL_OUTCTRL)
+ nVal = readl(pll_mode_addr);
+ if (nVal & PLL_OUTCTRL)
return;
/* Put the PLL in reset mode */
@@ -180,25 +179,25 @@
void pll_request(unsigned pll, unsigned enable)
{
int val = 0;
- if(!enable) {
+ if (!enable) {
/* Disable not supported */
return;
}
- switch(pll) {
- case 2:
- pll_enable(PLL2_MODE_ADDR);
- return;
- case 4:
- pll_enable(PLL4_MODE_ADDR);
- return;
- default:
- return;
+ switch (pll) {
+ case 2:
+ pll_enable(PLL2_MODE_ADDR);
+ return;
+ case 4:
+ pll_enable(PLL4_MODE_ADDR);
+ return;
+ default:
+ return;
};
}
void acpu_clock_init(void)
{
- uint32_t i,clk;
+ uint32_t i, clk;
uint32_t val;
uint32_t *clk_cntl_reg_val, size;
unsigned msm_id;
@@ -213,27 +212,27 @@
#endif
msm_id = board_msm_id();
- switch(msm_id) {
- case MSM7227A:
- case MSM7627A:
- case ESM7227A:
- clk_cntl_reg_val = clk_cntl_reg_val_7627A;
- size = ARRAY_SIZE(clk_cntl_reg_val_7627A);
- pll_request(2, 1);
+ switch (msm_id) {
+ case MSM7227A:
+ case MSM7627A:
+ case ESM7227A:
+ clk_cntl_reg_val = clk_cntl_reg_val_7627A;
+ size = ARRAY_SIZE(clk_cntl_reg_val_7627A);
+ pll_request(2, 1);
/* TODO: Enable this PLL while switching to 800MHz */
- #if 0
- pll_request(4, 1);
- #endif
- break;
+#if 0
+ pll_request(4, 1);
+#endif
+ break;
- case MSM7225A:
- case MSM7625A:
- default:
- clk_cntl_reg_val = clk_cntl_reg_val_7625A;
- size = ARRAY_SIZE(clk_cntl_reg_val_7625A);
- pll_request(2, 1);
- break;
+ case MSM7225A:
+ case MSM7625A:
+ default:
+ clk_cntl_reg_val = clk_cntl_reg_val_7625A;
+ size = ARRAY_SIZE(clk_cntl_reg_val_7625A);
+ pll_request(2, 1);
+ break;
};
/* Read clock source select bit. */
@@ -241,12 +240,12 @@
i = val & 1;
/* Jump into table and set every entry. */
- for(; i < size; i++) {
+ for (; i < size; i++) {
val = readl(A11S_CLK_CNTL_ADDR);
/* Make sure not to disturb already used src */
- val &= clk_cntl_mask[i%2];
+ val &= clk_cntl_mask[i % 2];
val += clk_cntl_reg_val[i];
writel(val, A11S_CLK_CNTL_ADDR);
@@ -255,7 +254,7 @@
*/
val = readl(A11S_CLK_SEL_ADDR);
val &= ~(A11S_CLK_SEL_MASK);
- val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i%2]);
+ val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i % 2]);
writel(val, A11S_CLK_SEL_ADDR);
#if (!ENABLE_NANDWRITE)
@@ -277,16 +276,14 @@
{
uint32_t reg = 0;
- if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
- {
+ if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0) {
dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
- "clk_rate: %d\n!", freq);
+ "clk_rate: %d\n!", freq);
ASSERT(0);
}
/* enable clock */
- if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
- {
+ if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0) {
dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
ASSERT(0);
}
@@ -294,16 +291,14 @@
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel( reg, MMC_BOOT_MCI_CLK );
+ writel(reg, MMC_BOOT_MCI_CLK);
}
/* Intialize MMC clock */
void clock_init_mmc(uint32_t interface)
{
- if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
- {
+ if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0) {
dprintf(CRITICAL, "Failure enabling PCLK!\n");
ASSERT(0);
}
}
-
diff --git a/platform/msm7x27a/gpio.c b/platform/msm7x27a/gpio.c
index 9615d33..9487ca4 100644
--- a/platform/msm7x27a/gpio.c
+++ b/platform/msm7x27a/gpio.c
@@ -35,12 +35,12 @@
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
/* output value */
-#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
-#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
-#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
-#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
-#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
-#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 132-107 */
+#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
+#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
+#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
+#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
+#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
+#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 132-107 */
/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x10)
@@ -100,8 +100,7 @@
typedef struct gpioregs gpioregs;
-struct gpioregs
-{
+struct gpioregs {
unsigned out;
unsigned in;
unsigned int_status;
@@ -114,88 +113,88 @@
static gpioregs GPIO_REGS[] = {
{
- .out = GPIO_OUT_0,
- .in = GPIO_IN_0,
- .int_status = GPIO_INT_STATUS_0,
- .int_clear = GPIO_INT_CLEAR_0,
- .int_en = GPIO_INT_EN_0,
- .int_edge = GPIO_INT_EDGE_0,
- .int_pos = GPIO_INT_POS_0,
- .oe = GPIO_OE_0,
- },
+ .out = GPIO_OUT_0,
+ .in = GPIO_IN_0,
+ .int_status = GPIO_INT_STATUS_0,
+ .int_clear = GPIO_INT_CLEAR_0,
+ .int_en = GPIO_INT_EN_0,
+ .int_edge = GPIO_INT_EDGE_0,
+ .int_pos = GPIO_INT_POS_0,
+ .oe = GPIO_OE_0,
+ },
{
- .out = GPIO_OUT_1,
- .in = GPIO_IN_1,
- .int_status = GPIO_INT_STATUS_1,
- .int_clear = GPIO_INT_CLEAR_1,
- .int_en = GPIO_INT_EN_1,
- .int_edge = GPIO_INT_EDGE_1,
- .int_pos = GPIO_INT_POS_1,
- .oe = GPIO_OE_1,
- },
+ .out = GPIO_OUT_1,
+ .in = GPIO_IN_1,
+ .int_status = GPIO_INT_STATUS_1,
+ .int_clear = GPIO_INT_CLEAR_1,
+ .int_en = GPIO_INT_EN_1,
+ .int_edge = GPIO_INT_EDGE_1,
+ .int_pos = GPIO_INT_POS_1,
+ .oe = GPIO_OE_1,
+ },
{
- .out = GPIO_OUT_2,
- .in = GPIO_IN_2,
- .int_status = GPIO_INT_STATUS_2,
- .int_clear = GPIO_INT_CLEAR_2,
- .int_en = GPIO_INT_EN_2,
- .int_edge = GPIO_INT_EDGE_2,
- .int_pos = GPIO_INT_POS_2,
- .oe = GPIO_OE_2,
- },
+ .out = GPIO_OUT_2,
+ .in = GPIO_IN_2,
+ .int_status = GPIO_INT_STATUS_2,
+ .int_clear = GPIO_INT_CLEAR_2,
+ .int_en = GPIO_INT_EN_2,
+ .int_edge = GPIO_INT_EDGE_2,
+ .int_pos = GPIO_INT_POS_2,
+ .oe = GPIO_OE_2,
+ },
{
- .out = GPIO_OUT_3,
- .in = GPIO_IN_3,
- .int_status = GPIO_INT_STATUS_3,
- .int_clear = GPIO_INT_CLEAR_3,
- .int_en = GPIO_INT_EN_3,
- .int_edge = GPIO_INT_EDGE_3,
- .int_pos = GPIO_INT_POS_3,
- .oe = GPIO_OE_3,
- },
+ .out = GPIO_OUT_3,
+ .in = GPIO_IN_3,
+ .int_status = GPIO_INT_STATUS_3,
+ .int_clear = GPIO_INT_CLEAR_3,
+ .int_en = GPIO_INT_EN_3,
+ .int_edge = GPIO_INT_EDGE_3,
+ .int_pos = GPIO_INT_POS_3,
+ .oe = GPIO_OE_3,
+ },
{
- .out = GPIO_OUT_4,
- .in = GPIO_IN_4,
- .int_status = GPIO_INT_STATUS_4,
- .int_clear = GPIO_INT_CLEAR_4,
- .int_en = GPIO_INT_EN_4,
- .int_edge = GPIO_INT_EDGE_4,
- .int_pos = GPIO_INT_POS_4,
- .oe = GPIO_OE_4,
- },
+ .out = GPIO_OUT_4,
+ .in = GPIO_IN_4,
+ .int_status = GPIO_INT_STATUS_4,
+ .int_clear = GPIO_INT_CLEAR_4,
+ .int_en = GPIO_INT_EN_4,
+ .int_edge = GPIO_INT_EDGE_4,
+ .int_pos = GPIO_INT_POS_4,
+ .oe = GPIO_OE_4,
+ },
{
- .out = GPIO_OUT_5,
- .in = GPIO_IN_5,
- .int_status = GPIO_INT_STATUS_5,
- .int_clear = GPIO_INT_CLEAR_5,
- .int_en = GPIO_INT_EN_5,
- .int_edge = GPIO_INT_EDGE_5,
- .int_pos = GPIO_INT_POS_5,
- .oe = GPIO_OE_5,
- },
+ .out = GPIO_OUT_5,
+ .in = GPIO_IN_5,
+ .int_status = GPIO_INT_STATUS_5,
+ .int_clear = GPIO_INT_CLEAR_5,
+ .int_en = GPIO_INT_EN_5,
+ .int_edge = GPIO_INT_EDGE_5,
+ .int_pos = GPIO_INT_POS_5,
+ .oe = GPIO_OE_5,
+ },
};
static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
- if(n > 132)
+ if (n > 132)
return 0;
- if(n > 106) {
+ if (n > 106) {
*bit = 1 << (n - 107);
return GPIO_REGS + 5;
}
- if(n > 94) {
+ if (n > 94) {
*bit = 1 << (n - 95);
return GPIO_REGS + 4;
}
- if(n > 67) {
+ if (n > 67) {
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
- if(n > 42) {
+ if (n > 42) {
*bit = 1 << (n - 43);
return GPIO_REGS + 2;
}
- if(n > 15) {
+ if (n > 15) {
*bit = 1 << (n - 16);
return GPIO_REGS + 1;
}
@@ -227,11 +226,11 @@
unsigned b;
unsigned v;
- if((r = find_gpio(n, &b)) == 0)
+ if ((r = find_gpio(n, &b)) == 0)
return;
v = readl(r->out);
- if(on) {
+ if (on) {
writel(v | b, r->out);
} else {
writel(v & (~b), r->out);
@@ -243,8 +242,8 @@
gpioregs *r;
unsigned b;
- if((r = find_gpio(n, &b)) == 0) return 0;
+ if ((r = find_gpio(n, &b)) == 0)
+ return 0;
return (readl(r->in) & b) ? 1 : 0;
}
-
diff --git a/platform/msm7x27a/interrupts.c b/platform/msm7x27a/interrupts.c
index aca4cdc..b94cf78 100644
--- a/platform/msm7x27a/interrupts.c
+++ b/platform/msm7x27a/interrupts.c
@@ -40,22 +40,22 @@
#define VIC_REG(off) (MSM_VIC_BASE + (off))
-#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
-#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
-#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
-#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
-#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
-#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
-#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
+#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
@@ -66,8 +66,8 @@
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
-#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
-#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
@@ -137,4 +137,3 @@
handler[vector].arg = arg;
exit_critical_section();
}
-
diff --git a/platform/msm7x27a/panel.c b/platform/msm7x27a/panel.c
index 8afcd19..759ae49 100644
--- a/platform/msm7x27a/panel.c
+++ b/platform/msm7x27a/panel.c
@@ -14,7 +14,6 @@
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
-
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
@@ -38,7 +37,6 @@
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
-
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
@@ -82,7 +80,6 @@
#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
-
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
@@ -93,11 +90,9 @@
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
-
#define I2CSETUP (I2C_BLOCK_BASE|0x00)
#define I2CCTRL (I2C_BLOCK_BASE|0x04)
-
#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
@@ -120,7 +115,6 @@
#define PWMID (PWM_BLOCK_BASE|0x6C)
#define PWMMON (PWM_BLOCK_BASE|0x70)
-
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
@@ -135,7 +129,6 @@
#define GPIOID (GPIO_BLOCK_BASE|0x30)
-
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
@@ -148,280 +141,279 @@
};
static struct init_table toshiba_480x640_init_table[] = {
- { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
- { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
- { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
- { 0, 14 }, // wait_ms(14);
- { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
- { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
- { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
- { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
- { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
- { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
- { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
- { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
- { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
- { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
- { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
- { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
- { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
- { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
- { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
- { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
- //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
+ {DPSET0, 0x4BEC0066}, // # MDC.DPSET0 # Setup DPLL parameters
+ {DPSET1, 0x00000113}, // # MDC.DPSET1
+ {DPSUS, 0x00000000}, // # MDC.DPSUS # Set DPLL oscillation enable
+ {DPRUN, 0x00000001}, // # MDC.DPRUN # Release reset signal for DPLL
+ {0, 14}, // wait_ms(14);
+ {SYSCKENA, 0x00000001}, // # MDC.SYSCKENA # Enable system clock output
+ {CLKENB, 0x000000EF}, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
+ {GPIO_BLOCK_BASE, 0x03FF0000}, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
+ {GPIODIR, 0x0000024D}, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
+ {SYSTEM_BLOCK2_BASE, 0x00000173}, // # SYS.GPIOSEL # GPIO port multiplexing control
+ {GPIOPC, 0x03C300C0}, // # GPI .GPIOPC # GPIO2,3 PD cut
+ {SYSTEM_BLOCK1_BASE, 0x00000000}, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
+ {GPIOIS, 0x00000000}, // # GPI .GPIOIS # Set interrupt sense of GPIO
+ {GPIOIEV, 0x00000001}, // # GPI .GPIOIEV # Set interrupt event of GPIO
+ {GPIOIC, 0x000003FF}, // # GPI .GPIOIC # GPIO interrupt clear
+ {GPIO_BLOCK_BASE, 0x00060006}, // # GPI .GPIODATA # Release LCDD reset
+ {GPIO_BLOCK_BASE, 0x00080008}, // # GPI .GPIODATA # eDRAM VD supply
+ {GPIO_BLOCK_BASE, 0x02000200}, // # GPI .GPIODATA # TEST LED ON
+ {DRAMPWR, 0x00000001}, // # SYS.DRAMPWR # eDRAM power up
+ {TIMER0CONTROL, 0x00000060}, // # PWM.Timer0Control # PWM0 output stop
+ {PWM_BLOCK_BASE, 0x00001388}, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
+ //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
#if 0
- { PWM0OFF, 0x00001387 }, // SURF 100% backlight
- { PWM0OFF, 0x00000000 }, // FFA 100% backlight
+ {PWM0OFF, 0x00001387}, // SURF 100% backlight
+ {PWM0OFF, 0x00000000}, // FFA 100% backlight
#endif
- { PWM0OFF, 0x000009C3 }, // 50% BL
- { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
- { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
- //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
- { PWM1OFF, 0x00001387 },
- { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
- { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
- { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
- { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
- { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
- { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
+ {PWM0OFF, 0x000009C3}, // 50% BL
+ {TIMER1CONTROL, 0x00000060}, // # PWM.Timer1Control # PWM1 output stop
+ {TIMER1LOAD, 0x00001388}, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
+ //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
+ {PWM1OFF, 0x00001387},
+ {TIMER0CONTROL, 0x000000E0}, // # PWM.Timer0Control # PWM0 output start
+ {TIMER1CONTROL, 0x000000E0}, // # PWM.Timer1Control # PWM1 output start
+ {PWMCR, 0x00000003}, // # PWM.PWMCR # PWM output enable
+ {0, 1}, // wait_ms(1);
+ {SPI_BLOCK_BASE, 0x00000799}, // # SPI .SSICTL # SPI operation mode setting
+ {SSITIME, 0x00000100}, // # SPI .SSITIME # SPI serial interface timing setting
+ {SPI_BLOCK_BASE, 0x0000079b}, // # SPI .SSICTL # Set SPI active mode
- { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
- { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
- { SSITX, 0x00080036 }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Memory access control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BB }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Display mode setup(2)
- { SSITX, 0x0008003A }, // # Command setting of SPI block
- { SSITX, 0x00000160 }, // # RGB Interface data format
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BF }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Drivnig method
- { SSITX, 0x000800B1 }, // # Command setting of SPI block
- { SSITX, 0x0000015D }, // # Booster operation setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B2 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Booster mode setup
- { SSITX, 0x000800B3 }, // # Command setting of SPI block
- { SSITX, 0x00000122 }, // # Booster frequencies setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B4 }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
- { SSITX, 0x000800B5 }, // # Command setting of SPI block
- { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B6 }, // # Command setting of SPI block
- { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
- { SSITX, 0x000800B7 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # Configure an external display signal
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B9 }, // # Command setting of SPI block
- { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
- { SSITX, 0x000800BD }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # ASW signal control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BE }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { SSITX, 0x000800C0 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C1 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
- { SSITX, 0x000800C2 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C3 }, // # Command setting of SPI block
- { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C4 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C5 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C6 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C7 }, // # Command setting of SPI block
- { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000143 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C8 }, // # Command setting of SPI block
- { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
- { SSITX, 0x000800C9 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CA }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EC }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D0 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D1 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D2 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D3 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D4 }, // # Command setting of SPI block
- { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000016E }, //
- { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
- { SSITX, 0x000800D5 }, // # Command setting of SPI block
- { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800ED }, // # Command setting of SPI block
- { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D6 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D7 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D8 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D9 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DE }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DF }, // # Command setting of SPI block
- { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000013F }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E0 }, // # Command setting of SPI block
- { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x000800E2 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E3 }, // # Command setting of SPI block
- { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E4 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
- { SSITX, 0x00000103 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E5 }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E6 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E7 }, // # Command setting of SPI block
- { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E8 }, // # Command setting of SPI block
- { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
+ {SSITX, 0x00000000}, // # SPI.SSITX # Release from Deep Stanby mode
+ {0, 1}, // wait_ms(1);
+ {SSITX, 0x00000000}, // # SPI.SSITX
+ {0, 1}, // wait_ms(1);
+ {SSITX, 0x00000000}, // # SPI.SSITX
+ {0, 1}, // wait_ms(1);
+ {SSITX, 0x000800BA}, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
+ {SSITX, 0x00000111}, // # Display mode setup(1) : Normaly Black
+ {SSITX, 0x00080036}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Memory access control
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BB}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Display mode setup(2)
+ {SSITX, 0x0008003A}, // # Command setting of SPI block
+ {SSITX, 0x00000160}, // # RGB Interface data format
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BF}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Drivnig method
+ {SSITX, 0x000800B1}, // # Command setting of SPI block
+ {SSITX, 0x0000015D}, // # Booster operation setup
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B2}, // # Command setting of SPI block
+ {SSITX, 0x00000133}, // # Booster mode setup
+ {SSITX, 0x000800B3}, // # Command setting of SPI block
+ {SSITX, 0x00000122}, // # Booster frequencies setup
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B4}, // # Command setting of SPI block
+ {SSITX, 0x00000102}, // # OP-amp capability/System clock freq. division setup
+ {SSITX, 0x000800B5}, // # Command setting of SPI block
+ {SSITX, 0x0000011F}, // # VCS Voltage adjustment (1C->1F for Rev 2)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B6}, // # Command setting of SPI block
+ {SSITX, 0x00000128}, // # VCOM Voltage adjustment
+ {SSITX, 0x000800B7}, // # Command setting of SPI block
+ {SSITX, 0x00000103}, // # Configure an external display signal
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B9}, // # Command setting of SPI block
+ {SSITX, 0x00000120}, // # DCCK/DCEV timing setup
+ {SSITX, 0x000800BD}, // # Command setting of SPI block
+ {SSITX, 0x00000102}, // # ASW signal control
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BE}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Dummy display (white/black) count setup for QUAD Data operation
+ {SSITX, 0x000800C0}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (A)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C1}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (B)
+ {SSITX, 0x000800C2}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (C)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C3}, // # Command setting of SPI block
+ {SSITX, 0x0008010A}, // # wait_ms(-in line clock count setup (D)
+ {SSITX, 0x0000010A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C4}, // # Command setting of SPI block
+ {SSITX, 0x00080160}, // # Seep-in line clock count setup (E)
+ {SSITX, 0x00000160}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C5}, // # Command setting of SPI block
+ {SSITX, 0x00080160}, // # wait_ms(-in line clock count setup (F)
+ {SSITX, 0x00000160}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C6}, // # Command setting of SPI block
+ {SSITX, 0x00080160}, // # wait_ms(-in line clock setup (G)
+ {SSITX, 0x00000160}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C7}, // # Command setting of SPI block
+ {SSITX, 0x00080133}, // # Gamma 1 fine tuning (1)
+ {SSITX, 0x00000143}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C8}, // # Command setting of SPI block
+ {SSITX, 0x00000144}, // # Gamma 1 fine tuning (2)
+ {SSITX, 0x000800C9}, // # Command setting of SPI block
+ {SSITX, 0x00000133}, // # Gamma 1 inclination adjustment
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800CA}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Gamma 1 blue offset adjustment
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800EC}, // # Command setting of SPI block
+ {SSITX, 0x00080102}, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
+ {SSITX, 0x00000118}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800CF}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D0}, // # Command setting of SPI block
+ {SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x00000104}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D1}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D2}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x0000013A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D3}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x0000013A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D4}, // # Command setting of SPI block
+ {SSITX, 0x00080124}, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x0000016E}, //
+ {0, 1}, // wait_ms(1); // # Wait SPI fifo empty
+ {SSITX, 0x000800D5}, // # Command setting of SPI block
+ {SSITX, 0x00000124}, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800ED}, // # Command setting of SPI block
+ {SSITX, 0x00080101}, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
+ {SSITX, 0x0000010A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D6}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D7}, // # Command setting of SPI block
+ {SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
+ {SSITX, 0x0000010A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D8}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D9}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
+ {SSITX, 0x00000114}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800DE}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table2 for QVGA]
+ {SSITX, 0x00000114}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800DF}, // # Command setting of SPI block
+ {SSITX, 0x00080112}, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
+ {SSITX, 0x0000013F}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E0}, // # Command setting of SPI block
+ {SSITX, 0x0000010B}, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
+ {SSITX, 0x000800E2}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E3}, // # Command setting of SPI block
+ {SSITX, 0x00000136}, // # Built-in oscillator clock count setup
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E4}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # CKV timing control for using build-in osc
+ {SSITX, 0x00000103}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E5}, // # Command setting of SPI block
+ {SSITX, 0x00080102}, // # OEV timing control for using build-in osc
+ {SSITX, 0x00000104}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E6}, // # Command setting of SPI block
+ {SSITX, 0x00000103}, // # DCEV timing control for using build-in osc
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E7}, // # Command setting of SPI block
+ {SSITX, 0x00080104}, // # ASW timing setup for using build-in osc(1)
+ {SSITX, 0x0000010A}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800E8}, // # Command setting of SPI block
+ {SSITX, 0x00000104}, // # ASW timing setup for using build-in osc(2)
+ {CLKENB, 0x000001EF}, // # SYS.CLKENB # DCLK enable
+ {START, 0x00000000}, // # LCD.START # LCDC wait_ms( mode
+ {WRSTB, 0x0000003F}, // # LCD.WRSTB # write_client_reg( strobe
+ {RDSTB, 0x00000432}, // # LCD.RDSTB # Read strobe
+ {PORT_ENB, 0x00000002}, // # LCD.PORT_ENB # Asynchronous port enable
+ {VSYNIF, 0x00000000}, // # LCD.VSYNCIF # VSYNC I/F mode set
+ {ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ {ASY_DATB, 0x00000001}, // # Oscillator start
+ {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
+ {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
+ {0, 10}, // wait_ms(10);
+ {ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
+ {ASY_DATB, 0x80000000}, //
+ {ASY_DATC, 0x80000000}, //
+ {ASY_DATD, 0x80000000}, //
+ {ASY_CMDSET, 0x00000009}, // # LCD.ASY_CMDSET
+ {ASY_CMDSET, 0x00000008}, // # LCD.ASY_CMDSET
+ {ASY_DATA, 0x80000007}, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ {ASY_DATB, 0x00004005}, // # LCD driver control
+ {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
+ {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
+ {0, 20}, // wait_ms(20);
+ {ASY_DATA, 0x80000059}, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ {ASY_DATB, 0x00000000}, // # LTPS I/F control
+ {ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
+ {ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
- { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
- { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
- { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
- { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
- { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
- { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000001 }, // # Oscillator start
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 10 }, // wait_ms(10);
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
- { ASY_DATB, 0x80000000 }, //
- { ASY_DATC, 0x80000000 }, //
- { ASY_DATD, 0x80000000 }, //
- { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
- { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
- { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00004005 }, // # LCD driver control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 20 }, // wait_ms(20);
- { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000000 }, // # LTPS I/F control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
-
- { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
+ {VSYNIF, 0x00000001}, // # LCD.VSYNCIF # VSYNC I/F mode OFF
+ {PORT_ENB, 0x00000001}, // # LCD.PORT_ENB # SYNC I/F output select
/******************************/
- { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
+ {VSYNIF, 0x00000001}, // VSYNC I/F mode OFF
+ {PORT_ENB, 0x00000001}, // SYNC I/F mode ON
- { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
- { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
- { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
- { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
- { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
- { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
- { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
- { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
- { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
- { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
- { HSW, 0x00000003 }, // LCD.HSW
- { HDE_START, 0x00000007 }, // LCD.HDE_START
- { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
- { VCYCLE, 0x00000285 }, // LCD.VCYCLE
- { VSW, 0x00000001 }, // LCD.VSW
- { VDE_START, 0x00000003 }, // LCD.VDE_START
- { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
+ {BITMAP1, 0x01E000F0}, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
+ {BITMAP2, 0x01E000F0}, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
+ {BITMAP3, 0x01E000F0}, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
+ {BITMAP4, 0x00DC00B0}, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
+ {CLKENB, 0x000001EF}, // SYS.CLKENB ); // DCLK supply
+ {PORT_ENB, 0x00000001}, // LCD.PORT_ENB ); // Synchronous port enable
+ {PORT, 0x00000004}, // LCD.PORT ); // Polarity of DE is set to high active
+ {PXL, 0x00000002}, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
+ {MPLFBUF, 0x00000000}, // LCD.MPLFBUF ); // Select the reading buffer
+ {HCYCLE, 0x0000010b}, // LCD.HCYCLE ); // Setup to VGA size
+ {HSW, 0x00000003}, // LCD.HSW
+ {HDE_START, 0x00000007}, // LCD.HDE_START
+ {HDE_SIZE, 0x000000EF}, // LCD.HDE_SIZE
+ {VCYCLE, 0x00000285}, // LCD.VCYCLE
+ {VSW, 0x00000001}, // LCD.VSW
+ {VDE_START, 0x00000003}, // LCD.VDE_START
+ {VDE_SIZE, 0x0000027F}, // LCD.VDE_SIZE
- { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
+ {START, 0x00000001}, // LCD.START ); // LCDC - Pixel data transfer start
- { 0, 10 }, // wait_ms( 10 );
- { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
- { SSITX, 0x00000180 }, // Display data setup
- { SSITX, 0x0008003B }, // Command setting of SPI block
- { SSITX, 0x00000100 }, // Quad Data configuration - VGA
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B0 }, // Command setting of SPI block
- { SSITX, 0x00000116 }, // Power supply ON/OFF control
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B8 }, // Command setting of SPI block
- { SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
- { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
- { SSITX, 0x00000029 }, // Display on (Command only)
+ {0, 10}, // wait_ms( 10 );
+ {SSITX, 0x000800BC}, // SPI.SSITX ); // Command setting of SPI block
+ {SSITX, 0x00000180}, // Display data setup
+ {SSITX, 0x0008003B}, // Command setting of SPI block
+ {SSITX, 0x00000100}, // Quad Data configuration - VGA
+ {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
+ {SSITX, 0x000800B0}, // Command setting of SPI block
+ {SSITX, 0x00000116}, // Power supply ON/OFF control
+ {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
+ {SSITX, 0x000800B8}, // Command setting of SPI block
+ {SSITX, 0x000801FF}, // Output control
+ {SSITX, 0x000001F5},
+ {0, 1}, // wait_ms( 1); // Wait SPI fifo empty
+ {SSITX, 0x00000011}, // wait_ms(-out (Command only)
+ {SSITX, 0x00000029}, // Display on (Command only)
- { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
+ {SYSTEM_BLOCK1_BASE, 0x00000002}, // # wakeREQ -> GPIO
- { 0, 0 }
+ {0, 0}
};
static void _panel_init(struct init_table *init_table)
@@ -444,12 +436,12 @@
void panel_init(struct mddi_client_caps *client_caps)
{
- switch(client_caps->manufacturer_name) {
- case 0xd263: // Toshiba
+ switch (client_caps->manufacturer_name) {
+ case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
_panel_init(toshiba_480x640_init_table);
break;
- case 0x4474: //??
+ case 0x4474: //??
if (client_caps->product_code == 0xc065)
dprintf(INFO, "Found WVGA panel\n");
break;
@@ -468,4 +460,5 @@
}
void panel_backlight(int on)
-{}
+{
+}
diff --git a/platform/msm7x27a/platform.c b/platform/msm7x27a/platform.c
index 18e4c41..288f77c 100644
--- a/platform/msm7x27a/platform.c
+++ b/platform/msm7x27a/platform.c
@@ -102,7 +102,7 @@
dprintf(SPEW, "display_shutdown()\n");
mipi_dsi_shutdown();
/* Power down DSI bridge chip */
- gpio_set(128,0x1);
+ gpio_set(128, 0x1);
#endif
}
@@ -121,7 +121,7 @@
/* disable timer */
writel(0, DGT_ENABLE);
- ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
+ ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
}
/* Returns timer ticks per sec */
@@ -129,6 +129,7 @@
{
return ticks_per_sec;
}
+
bool machine_is_7x25a(void)
{
if ((board_msm_id() == MSM7225A) || (board_msm_id() == MSM7625A))
@@ -142,12 +143,12 @@
*/
void panel_dsi_init(void)
{
- gpio_set(128,0x1);
+ gpio_set(128, 0x1);
mdelay(5);
- gpio_set(128,0x0);
- gpio_set(129,0x1);
+ gpio_set(128, 0x0);
+ gpio_set(129, 0x1);
gpio_config(129, GPIO_OUTPUT);
- gpio_set(129,0x0);
- gpio_set(129,0x1);
+ gpio_set(129, 0x0);
+ gpio_set(129, 0x1);
mdelay(10);
}
diff --git a/platform/msm7x30/acpuclock.c b/platform/msm7x30/acpuclock.c
index af16c88..7d6687b 100644
--- a/platform/msm7x30/acpuclock.c
+++ b/platform/msm7x30/acpuclock.c
@@ -43,106 +43,104 @@
#define ACPU_SRC_DIV 0
#define BIT(n) (1 << (n))
-#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */
+#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */
#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5))
-#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
-#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
+#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
+#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
#define MV(mv) ((mv) / (!((mv) % V_STEP)))
/* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */
#define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA)
-
/* enum for SDC CLK IDs */
-enum
-{
- SDC1_CLK = 19,
+enum {
+ SDC1_CLK = 19,
SDC1_PCLK = 20,
- SDC2_CLK = 21,
+ SDC2_CLK = 21,
SDC2_PCLK = 22,
- SDC3_CLK = 23,
+ SDC3_CLK = 23,
SDC3_PCLK = 24,
- SDC4_CLK = 25,
+ SDC4_CLK = 25,
SDC4_PCLK = 26
};
/* Zero'th entry is dummy */
-static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
-static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+static uint8_t sdc_clk[] = { 0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK };
+static uint8_t sdc_pclk[] = { 0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK };
void spm_init(void)
{
- writel(0x05, MSM_SAW_BASE + 0x10); /* MSM_SPM_REG_SAW_CFG */
- writel(0x18, MSM_SAW_BASE + 0x14); /* MSM_SPM_REG_SAW_SPM_CTL */
- writel(0x00006666, MSM_SAW_BASE + 0x18); /* MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY */
- writel(0xFF000666, MSM_SAW_BASE + 0x1C); /* MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY */
+ writel(0x05, MSM_SAW_BASE + 0x10); /* MSM_SPM_REG_SAW_CFG */
+ writel(0x18, MSM_SAW_BASE + 0x14); /* MSM_SPM_REG_SAW_SPM_CTL */
+ writel(0x00006666, MSM_SAW_BASE + 0x18); /* MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY */
+ writel(0xFF000666, MSM_SAW_BASE + 0x1C); /* MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY */
- writel(0x01, MSM_SAW_BASE + 0x24); /* MSM_SPM_REG_SAW_SLP_CLK_EN */
- writel(0x03, MSM_SAW_BASE + 0x28); /* MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN */
- writel(0x00, MSM_SAW_BASE + 0x2C); /* MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN */
+ writel(0x01, MSM_SAW_BASE + 0x24); /* MSM_SPM_REG_SAW_SLP_CLK_EN */
+ writel(0x03, MSM_SAW_BASE + 0x28); /* MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN */
+ writel(0x00, MSM_SAW_BASE + 0x2C); /* MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN */
- writel(0x01, MSM_SAW_BASE + 0x30); /* MSM_SPM_REG_SAW_SLP_CLMP_EN */
- writel(0x00, MSM_SAW_BASE + 0x34); /* MSM_SPM_REG_SAW_SLP_RST_EN */
- writel(0x00, MSM_SAW_BASE + 0x38); /* MSM_SPM_REG_SAW_SPM_MPM_CFG */
+ writel(0x01, MSM_SAW_BASE + 0x30); /* MSM_SPM_REG_SAW_SLP_CLMP_EN */
+ writel(0x00, MSM_SAW_BASE + 0x34); /* MSM_SPM_REG_SAW_SLP_RST_EN */
+ writel(0x00, MSM_SAW_BASE + 0x38); /* MSM_SPM_REG_SAW_SPM_MPM_CFG */
}
/* Configures msmc2 voltage. vlevel is in mV */
void msmc2_config(unsigned vlevel)
{
- unsigned val;
- val = readl(MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
- val &= ~0xFF;
- val |= VDD_RAW(vlevel);
- writel(val, MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
+ unsigned val;
+ val = readl(MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
+ val &= ~0xFF;
+ val |= VDD_RAW(vlevel);
+ writel(val, MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
- /* Wait for PMIC state to return to idle and for VDD to stabilize */
- while(((readl(MSM_SAW_BASE + 0x0C) >> 0x20) & 0x3) != 0);
- udelay(160);
+ /* Wait for PMIC state to return to idle and for VDD to stabilize */
+ while (((readl(MSM_SAW_BASE + 0x0C) >> 0x20) & 0x3) != 0) ;
+ udelay(160);
}
void enable_pll(unsigned num)
{
- unsigned reg_val;
- reg_val = readl(PLL_ENA_REG);
- reg_val |= (1 << num);
- writel(reg_val, PLL_ENA_REG);
- /* Wait until PLL is enabled */
- while ((readl(PLL2_STATUS_BASE_REG) & (1 << 16)) == 0);
+ unsigned reg_val;
+ reg_val = readl(PLL_ENA_REG);
+ reg_val |= (1 << num);
+ writel(reg_val, PLL_ENA_REG);
+ /* Wait until PLL is enabled */
+ while ((readl(PLL2_STATUS_BASE_REG) & (1 << 16)) == 0) ;
}
void acpu_clock_init(void)
{
- unsigned clk, reg_clksel, reg_clkctl, src_sel;
- /* Fixing msmc2 voltage */
- spm_init();
+ unsigned clk, reg_clksel, reg_clkctl, src_sel;
+ /* Fixing msmc2 voltage */
+ spm_init();
- clk = readl(PLL2_L_VAL_ADDR) & 0xFF;
- if (clk == ACPU_806MHZ)
- msmc2_config(1100);
- else if (clk == ACPU_1024MHZ || clk == ACPU_1200MHZ)
- msmc2_config(1200);
- else if (clk == ACPU_1400MHZ)
- msmc2_config(1250);
+ clk = readl(PLL2_L_VAL_ADDR) & 0xFF;
+ if (clk == ACPU_806MHZ)
+ msmc2_config(1100);
+ else if (clk == ACPU_1024MHZ || clk == ACPU_1200MHZ)
+ msmc2_config(1200);
+ else if (clk == ACPU_1400MHZ)
+ msmc2_config(1250);
- /* Enable pll 2 */
- enable_pll(2);
+ /* Enable pll 2 */
+ enable_pll(2);
- reg_clksel = readl(SCSS_CLK_SEL);
+ reg_clksel = readl(SCSS_CLK_SEL);
- /* CLK_SEL_SRC1NO */
- src_sel = reg_clksel & 1;
+ /* CLK_SEL_SRC1NO */
+ src_sel = reg_clksel & 1;
- /* Program clock source and divider. */
- reg_clkctl = readl(SCSS_CLK_CTL);
- reg_clkctl &= ~(0xFF << (8 * src_sel));
- reg_clkctl |= ACPU_SRC_SEL<< (4 + 8 * src_sel);
- reg_clkctl |= ACPU_SRC_DIV<< (0 + 8 * src_sel);
- writel(reg_clkctl, SCSS_CLK_CTL);
+ /* Program clock source and divider. */
+ reg_clkctl = readl(SCSS_CLK_CTL);
+ reg_clkctl &= ~(0xFF << (8 * src_sel));
+ reg_clkctl |= ACPU_SRC_SEL << (4 + 8 * src_sel);
+ reg_clkctl |= ACPU_SRC_DIV << (0 + 8 * src_sel);
+ writel(reg_clkctl, SCSS_CLK_CTL);
- /* Toggle clock source. */
- reg_clksel ^= 1;
+ /* Toggle clock source. */
+ reg_clksel ^= 1;
- /* Program clock source selection. */
- writel(reg_clksel, SCSS_CLK_SEL);
+ /* Program clock source selection. */
+ writel(reg_clksel, SCSS_CLK_SEL);
}
void hsusb_clock_init(void)
@@ -152,37 +150,34 @@
unsigned sh2_own_row2_hsusb_mask = (1 << 11);
sh2_own_row2 = readl(SH2_OWN_ROW2_BASE_REG);
- if(sh2_own_row2 & sh2_own_row2_hsusb_mask)
- {
+ if (sh2_own_row2 & sh2_own_row2_hsusb_mask) {
/* USB local clock control enabled */
- /* Set value in MD register */
- val = 0x5DF;
- writel(val, SH2_USBH_MD_REG);
+ /* Set value in MD register */
+ val = 0x5DF;
+ writel(val, SH2_USBH_MD_REG);
- /* Set value in NS register */
- val = 1 << 8;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
+ /* Set value in NS register */
+ val = 1 << 8;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
- val = 1 << 11;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
+ val = 1 << 11;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
- val = 1 << 9;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
+ val = 1 << 9;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
- val = 1 << 13;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
+ val = 1 << 13;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
- /* Enable USBH_P_CLK */
- val = 1 << 25;
- val = val | readl(SH2_GLBL_CLK_ENA_SC);
- writel(val, SH2_GLBL_CLK_ENA_SC);
- }
- else
- {
+ /* Enable USBH_P_CLK */
+ val = 1 << 25;
+ val = val | readl(SH2_GLBL_CLK_ENA_SC);
+ writel(val, SH2_GLBL_CLK_ENA_SC);
+ } else {
/* USB local clock control not enabled; use proc comm */
usb_clock_init();
}
@@ -190,7 +185,7 @@
void adm_enable_clock(void)
{
- unsigned int val=0;
+ unsigned int val = 0;
/* Enable ADM_CLK */
val = 1 << 5;
@@ -205,8 +200,7 @@
unsigned sh2_own_apps2_lcdc_mask = (1 << 3);
sh2_own_apps2 = readl(SH2_OWN_APPS2_BASE_REG);
- if(sh2_own_apps2 & sh2_own_apps2_lcdc_mask)
- {
+ if (sh2_own_apps2 & sh2_own_apps2_lcdc_mask) {
/* MDP local clock control enabled */
/* Select clock source and divider */
val = 0x29;
@@ -277,9 +271,7 @@
val = 1 << 12;
val = val | readl(SH2_MDP_LCDC_NS_REG);
writel(val, SH2_MDP_LCDC_NS_REG);
- }
- else
- {
+ } else {
/* MDP local clock control not enabled; use proc comm */
mdp_clock_init(122880000);
@@ -295,8 +287,7 @@
unsigned sh2_own_row1_pmdh_mask = (1 << 19);
sh2_own_row1 = readl(SH2_OWN_ROW1_BASE_REG);
- if(sh2_own_row1 & sh2_own_row1_pmdh_mask)
- {
+ if (sh2_own_row1 & sh2_own_row1_pmdh_mask) {
/* Select clock source and divider */
val = 1;
val |= (1 << 3);
@@ -312,9 +303,7 @@
val = 1 << 4;
val = val | readl(SH2_GLBL_CLK_ENA_2_SC);
writel(val, SH2_GLBL_CLK_ENA_2_SC);
- }
- else
- {
+ } else {
/* MDDI local clock control not enabled; use proc comm */
mddi_clock_init(0, 480000000);
}
@@ -322,7 +311,7 @@
void ce_clock_init(void)
{
- unsigned int val=0;
+ unsigned int val = 0;
/* Enable CE_CLK */
val = 1 << 6;
@@ -335,16 +324,14 @@
{
uint32_t reg = 0;
- if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
- {
+ if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0) {
dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
- "clk_rate: %d\n!", freq);
+ "clk_rate: %d\n!", freq);
ASSERT(0);
}
/* enable clock */
- if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
- {
+ if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0) {
dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
ASSERT(0);
}
@@ -352,16 +339,14 @@
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel( reg, MMC_BOOT_MCI_CLK );
+ writel(reg, MMC_BOOT_MCI_CLK);
}
/* Intialize MMC clock */
void clock_init_mmc(uint32_t interface)
{
- if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
- {
- dprintf(CRITICAL, "Failure enabling PCLK!\n");
+ if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0) {
+ dprintf(CRITICAL, "Failure enabling PCLK!\n");
ASSERT(0);
}
}
-
diff --git a/platform/msm7x30/gpio.c b/platform/msm7x30/gpio.c
index 1204944..2370794 100644
--- a/platform/msm7x30/gpio.c
+++ b/platform/msm7x30/gpio.c
@@ -37,8 +37,7 @@
typedef struct gpioregs gpioregs;
-struct gpioregs
-{
+struct gpioregs {
unsigned out;
unsigned in;
unsigned int_status;
@@ -51,114 +50,114 @@
static gpioregs GPIO_REGS[] = {
{
- .out = GPIO_OUT_0,
- .in = GPIO_IN_0,
- .int_status = GPIO_INT_STATUS_0,
- .int_clear = GPIO_INT_CLEAR_0,
- .int_en = GPIO_INT_EN_0,
- .int_edge = GPIO_INT_EDGE_0,
- .int_pos = GPIO_INT_POS_0,
- .oe = GPIO_OE_0,
- },
+ .out = GPIO_OUT_0,
+ .in = GPIO_IN_0,
+ .int_status = GPIO_INT_STATUS_0,
+ .int_clear = GPIO_INT_CLEAR_0,
+ .int_en = GPIO_INT_EN_0,
+ .int_edge = GPIO_INT_EDGE_0,
+ .int_pos = GPIO_INT_POS_0,
+ .oe = GPIO_OE_0,
+ },
{
- .out = GPIO_OUT_1,
- .in = GPIO_IN_1,
- .int_status = GPIO_INT_STATUS_1,
- .int_clear = GPIO_INT_CLEAR_1,
- .int_en = GPIO_INT_EN_1,
- .int_edge = GPIO_INT_EDGE_1,
- .int_pos = GPIO_INT_POS_1,
- .oe = GPIO_OE_1,
- },
+ .out = GPIO_OUT_1,
+ .in = GPIO_IN_1,
+ .int_status = GPIO_INT_STATUS_1,
+ .int_clear = GPIO_INT_CLEAR_1,
+ .int_en = GPIO_INT_EN_1,
+ .int_edge = GPIO_INT_EDGE_1,
+ .int_pos = GPIO_INT_POS_1,
+ .oe = GPIO_OE_1,
+ },
{
- .out = GPIO_OUT_2,
- .in = GPIO_IN_2,
- .int_status = GPIO_INT_STATUS_2,
- .int_clear = GPIO_INT_CLEAR_2,
- .int_en = GPIO_INT_EN_2,
- .int_edge = GPIO_INT_EDGE_2,
- .int_pos = GPIO_INT_POS_2,
- .oe = GPIO_OE_2,
- },
+ .out = GPIO_OUT_2,
+ .in = GPIO_IN_2,
+ .int_status = GPIO_INT_STATUS_2,
+ .int_clear = GPIO_INT_CLEAR_2,
+ .int_en = GPIO_INT_EN_2,
+ .int_edge = GPIO_INT_EDGE_2,
+ .int_pos = GPIO_INT_POS_2,
+ .oe = GPIO_OE_2,
+ },
{
- .out = GPIO_OUT_3,
- .in = GPIO_IN_3,
- .int_status = GPIO_INT_STATUS_3,
- .int_clear = GPIO_INT_CLEAR_3,
- .int_en = GPIO_INT_EN_3,
- .int_edge = GPIO_INT_EDGE_3,
- .int_pos = GPIO_INT_POS_3,
- .oe = GPIO_OE_3,
- },
+ .out = GPIO_OUT_3,
+ .in = GPIO_IN_3,
+ .int_status = GPIO_INT_STATUS_3,
+ .int_clear = GPIO_INT_CLEAR_3,
+ .int_en = GPIO_INT_EN_3,
+ .int_edge = GPIO_INT_EDGE_3,
+ .int_pos = GPIO_INT_POS_3,
+ .oe = GPIO_OE_3,
+ },
{
- .out = GPIO_OUT_4,
- .in = GPIO_IN_4,
- .int_status = GPIO_INT_STATUS_4,
- .int_clear = GPIO_INT_CLEAR_4,
- .int_en = GPIO_INT_EN_4,
- .int_edge = GPIO_INT_EDGE_4,
- .int_pos = GPIO_INT_POS_4,
- .oe = GPIO_OE_4,
- },
+ .out = GPIO_OUT_4,
+ .in = GPIO_IN_4,
+ .int_status = GPIO_INT_STATUS_4,
+ .int_clear = GPIO_INT_CLEAR_4,
+ .int_en = GPIO_INT_EN_4,
+ .int_edge = GPIO_INT_EDGE_4,
+ .int_pos = GPIO_INT_POS_4,
+ .oe = GPIO_OE_4,
+ },
{
- .out = GPIO_OUT_5,
- .in = GPIO_IN_5,
- .int_status = GPIO_INT_STATUS_5,
- .int_clear = GPIO_INT_CLEAR_5,
- .int_en = GPIO_INT_EN_5,
- .int_edge = GPIO_INT_EDGE_5,
- .int_pos = GPIO_INT_POS_5,
- .oe = GPIO_OE_5,
- },
+ .out = GPIO_OUT_5,
+ .in = GPIO_IN_5,
+ .int_status = GPIO_INT_STATUS_5,
+ .int_clear = GPIO_INT_CLEAR_5,
+ .int_en = GPIO_INT_EN_5,
+ .int_edge = GPIO_INT_EDGE_5,
+ .int_pos = GPIO_INT_POS_5,
+ .oe = GPIO_OE_5,
+ },
{
- .out = GPIO_OUT_6,
- .in = GPIO_IN_6,
- .int_status = GPIO_INT_STATUS_6,
- .int_clear = GPIO_INT_CLEAR_6,
- .int_en = GPIO_INT_EN_6,
- .int_edge = GPIO_INT_EDGE_6,
- .int_pos = GPIO_INT_POS_6,
- .oe = GPIO_OE_6,
- },
+ .out = GPIO_OUT_6,
+ .in = GPIO_IN_6,
+ .int_status = GPIO_INT_STATUS_6,
+ .int_clear = GPIO_INT_CLEAR_6,
+ .int_en = GPIO_INT_EN_6,
+ .int_edge = GPIO_INT_EDGE_6,
+ .int_pos = GPIO_INT_POS_6,
+ .oe = GPIO_OE_6,
+ },
{
- .out = GPIO_OUT_7,
- .in = GPIO_IN_7,
- .int_status = GPIO_INT_STATUS_7,
- .int_clear = GPIO_INT_CLEAR_7,
- .int_en = GPIO_INT_EN_7,
- .int_edge = GPIO_INT_EDGE_7,
- .int_pos = GPIO_INT_POS_7,
- .oe = GPIO_OE_7,
- },
+ .out = GPIO_OUT_7,
+ .in = GPIO_IN_7,
+ .int_status = GPIO_INT_STATUS_7,
+ .int_clear = GPIO_INT_CLEAR_7,
+ .int_en = GPIO_INT_EN_7,
+ .int_edge = GPIO_INT_EDGE_7,
+ .int_pos = GPIO_INT_POS_7,
+ .oe = GPIO_OE_7,
+ },
};
static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
- if(n > 150) {
+ if (n > 150) {
*bit = 1 << (n - 151);
return GPIO_REGS + 7;
}
- if(n > 133) {
+ if (n > 133) {
*bit = 1 << (n - 134);
return GPIO_REGS + 6;
}
- if(n > 106) {
+ if (n > 106) {
*bit = 1 << (n - 107);
return GPIO_REGS + 5;
}
- if(n > 94) {
+ if (n > 94) {
*bit = 1 << (n - 95);
return GPIO_REGS + 4;
}
- if(n > 67) {
+ if (n > 67) {
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
- if(n > 43) {
+ if (n > 43) {
*bit = 1 << (n - 44);
return GPIO_REGS + 2;
}
- if(n > 15) {
+ if (n > 15) {
*bit = 1 << (n - 16);
return GPIO_REGS + 1;
}
@@ -189,11 +188,12 @@
gpioregs *r;
unsigned b;
unsigned v;
-
- if((r = find_gpio(n, &b)) == 0) return;
+
+ if ((r = find_gpio(n, &b)) == 0)
+ return;
v = readl(r->out);
- if(on) {
+ if (on) {
writel(v | b, r->out);
} else {
writel(v & (~b), r->out);
@@ -205,19 +205,20 @@
gpioregs *r;
unsigned b;
- if((r = find_gpio(n, &b)) == 0) return 0;
+ if ((r = find_gpio(n, &b)) == 0)
+ return 0;
return (readl(r->in) & b) ? 1 : 0;
}
void platform_config_interleaved_mode_gpios(void)
{
- /* configure EB2_CS1 through GPIO86 */
- writel (GPIO_ALT_FUNC_PAGE_REG, 0x56);
- writel (GPIO_ALT_FUNC_CFG_REG, 0x04);
+ /* configure EB2_CS1 through GPIO86 */
+ writel(GPIO_ALT_FUNC_PAGE_REG, 0x56);
+ writel(GPIO_ALT_FUNC_CFG_REG, 0x04);
/* configure the EBI2_BUSY1_N through GPIO115 */
- writel (GPIO_ALT_FUNC_PAGE_REG, 0x73);
- writel (GPIO_ALT_FUNC_CFG_REG, 0x08);
+ writel(GPIO_ALT_FUNC_PAGE_REG, 0x73);
+ writel(GPIO_ALT_FUNC_CFG_REG, 0x08);
}
/* Enables all gpios passed in table*/
@@ -228,14 +229,13 @@
const struct msm_gpio *g;
for (i = 0; i < size; i++) {
g = table + i;
- /* Enable gpio */
+ /* Enable gpio */
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
if (rc) {
goto err;
}
}
return 0;
-err:
+ err:
return rc;
}
-
diff --git a/platform/msm7x30/gpio_hw.h b/platform/msm7x30/gpio_hw.h
index 7d7e722..650ea7a 100644
--- a/platform/msm7x30/gpio_hw.h
+++ b/platform/msm7x30/gpio_hw.h
@@ -38,14 +38,14 @@
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
/* output value */
-#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
-#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */
-#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */
-#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
-#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
-#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */
-#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */
-#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */
+#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
+#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */
+#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */
+#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
+#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
+#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */
+#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */
+#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */
/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x10)
@@ -117,7 +117,6 @@
#define GPIO_INT_STATUS_6 GPIO1_REG(0xE0)
#define GPIO_INT_STATUS_7 GPIO1_REG(0x234)
-
#define GPIO_OUT_VAL_REG_BASE 0xABC00000
#define GPIO_ALT_FUNC_PAGE_REG (GPIO_OUT_VAL_REG_BASE + 0x20)
#define GPIO_ALT_FUNC_CFG_REG (GPIO_OUT_VAL_REG_BASE + 0x24)
@@ -165,8 +164,8 @@
* and facilitete group operations provided by msm_gpios_xxx()
*/
struct msm_gpio {
- unsigned gpio_cfg;
- const char *label;
+ unsigned gpio_cfg;
+ const char *label;
};
/**
diff --git a/platform/msm7x30/include/platform/irqs.h b/platform/msm7x30/include/platform/irqs.h
index ad58b59..2df1f28 100644
--- a/platform/msm7x30/include/platform/irqs.h
+++ b/platform/msm7x30/include/platform/irqs.h
@@ -167,4 +167,4 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
+#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/platform/msm7x30/interrupts.c b/platform/msm7x30/interrupts.c
index 9071677..e7a7d48 100644
--- a/platform/msm7x30/interrupts.c
+++ b/platform/msm7x30/interrupts.c
@@ -40,21 +40,21 @@
#define VIC_REG(off) (MSM_VIC_BASE + (off))
-#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
-#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
-#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
-#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
-#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
-#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */
+#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
+#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */
#define VIC_SECURITY0 VIC_REG(0x0070)
#define VIC_SECURITY1 VIC_REG(0x0074)
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
@@ -67,11 +67,11 @@
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
-#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
-#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
-#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */
-#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */
+#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */
+#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */
#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
@@ -81,13 +81,13 @@
#define SIRC_REG(off) (MSM_SIRC_BASE + (off))
-#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */
+#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */
#define SIRC_INT_ENABLE SIRC_REG(0x0004)
#define SIRC_INT_ENCLEAR SIRC_REG(0x0008)
#define SIRC_INT_ENSET SIRC_REG(0x000C)
-#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */
-#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */
-#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */
+#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */
+#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */
+#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */
#define SIRC_IRQ0_STATUS SIRC_REG(0x001C)
#define SIRC_IRQ1_STATUS SIRC_REG(0x0020)
#define SIRC_RAW_STATUS SIRC_REG(0x0024)
@@ -156,4 +156,3 @@
handler[vector].arg = arg;
exit_critical_section();
}
-
diff --git a/platform/msm7x30/panel.c b/platform/msm7x30/panel.c
index 465ccb6..510b2fc 100644
--- a/platform/msm7x30/panel.c
+++ b/platform/msm7x30/panel.c
@@ -54,7 +54,6 @@
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
-
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
@@ -78,7 +77,6 @@
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
-
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
@@ -122,7 +120,6 @@
#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
-
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
@@ -133,11 +130,9 @@
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
-
#define I2CSETUP (I2C_BLOCK_BASE|0x00)
#define I2CCTRL (I2C_BLOCK_BASE|0x04)
-
#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
@@ -160,7 +155,6 @@
#define PWMID (PWM_BLOCK_BASE|0x6C)
#define PWMMON (PWM_BLOCK_BASE|0x70)
-
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
@@ -175,7 +169,6 @@
#define GPIOID (GPIO_BLOCK_BASE|0x30)
-
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
@@ -184,200 +177,200 @@
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
struct init_table {
- unsigned int reg;
- unsigned int val;
+ unsigned int reg;
+ unsigned int val;
};
static struct init_table toshiba_480x800_init_table[] = {
- { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
- { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
- { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
- { 0, 15 }, // wait_ms(15);
- { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
- { CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
+ {DPSET0, 0x4BEC0066}, // # MDC.DPSET0 # Setup DPLL parameters
+ {DPSET1, 0x00000113}, // # MDC.DPSET1
+ {DPSUS, 0x00000000}, // # MDC.DPSUS # Set DPLL oscillation enable
+ {DPRUN, 0x00000001}, // # MDC.DPRUN # Release reset signal for DPLL
+ {0, 15}, // wait_ms(15);
+ {SYSCKENA, 0x00000001}, // # MDC.SYSCKENA # Enable system clock output
+ {CLKENB, 0x000000E9}, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
- { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
- { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
- { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
- { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
- { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
- { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
- { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
- { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
- { GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
+ {GPIO_BLOCK_BASE, 0x03FF0000}, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
+ {GPIODIR, 0x0000024D}, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
+ {SYSTEM_BLOCK2_BASE, 0x00000173}, // # SYS.GPIOSEL # GPIO port multiplexing control
+ {GPIOPC, 0x03C300C0}, // # GPI .GPIOPC # GPIO2,3 PD cut
+ {SYSTEM_BLOCK1_BASE, 0x00000000}, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
+ {GPIOIS, 0x00000000}, // # GPI .GPIOIS # Set interrupt sense of GPIO
+ {GPIOIEV, 0x00000001}, // # GPI .GPIOIEV # Set interrupt event of GPIO
+ {GPIOIC, 0x000003FF}, // # GPI .GPIOIC # GPIO interrupt clear
+ {GPIO_BLOCK_BASE, 0x00040004}, // # GPI .GPIODATA # Release LCDD reset
- { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
- { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
- { CLKENB, 0x000000EB }, // # enable eDRAM clock
+ {GPIO_BLOCK_BASE, 0x00080008}, // # GPI .GPIODATA # eDRAM VD supply
+ {DRAMPWR, 0x00000001}, // # SYS.DRAMPWR # eDRAM power up
+ {CLKENB, 0x000000EB}, // # enable eDRAM clock
- { PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
- { SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
- { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
- { CNT_DIS, 0x00000002 }, // # SPI .SSITIME # SPI serial interface timing setting
- { SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
+ {PWMCR, 0x00000000}, // # PWM.PWMCR # PWM output enable
+ {0, 1}, // wait_ms(1);
+ {SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
+ {SSITIME, 0x00000100}, // # SPI .SSITIME # SPI serial interface timing setting
+ {CNT_DIS, 0x00000002}, // # SPI .SSITIME # SPI serial interface timing setting
+ {SPI_BLOCK_BASE, 0x0006039B}, // # SPI .SSICTL # Set SPI active mode
- { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
- { 0, 7 }, // wait_ms(2);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 7 }, // wait_ms(2);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 7 }, // wait_ms(2);
+ {SSITX, 0x00000000}, // # SPI.SSITX # Release from Deep Stanby mode
+ {0, 7}, // wait_ms(2);
+ {SSITX, 0x00000000}, // # SPI.SSITX
+ {0, 7}, // wait_ms(2);
+ {SSITX, 0x00000000}, // # SPI.SSITX
+ {0, 7}, // wait_ms(2);
- { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
- { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
- { SSITX, 0x00080036 }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Memory access control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x0008003A }, // # Command setting of SPI block
- { SSITX, 0x00000160 }, // # Display mode setup(2)
- { SSITX, 0x000800B1 }, // # Command setting of SPI block
- { SSITX, 0x0000015D }, // # RGB Interface data format
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B2 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Drivnig method
- { SSITX, 0x000800B3 }, // # Command setting of SPI block
- { SSITX, 0x00000122 }, // # Booster operation setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B4 }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
- { SSITX, 0x000800B5 }, // # Command setting of SPI block
- { SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B6 }, // # Command setting of SPI block
- { SSITX, 0x00000127 }, // # VCOM Voltage adjustment
- { SSITX, 0x000800B7 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # Configure an external display signal
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B9 }, // # Command setting of SPI block
- { SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
- { SSITX, 0x000800BD }, // # Command setting of SPI block
- { SSITX, 0x000001A1 }, // # ASW signal control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BB }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { SSITX, 0x000800BF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BE }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
- { SSITX, 0x000800C0 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C1 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
- { SSITX, 0x000800C2 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C3 }, // # Command setting of SPI block
- { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x00000132 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C4 }, // # Command setting of SPI block
- { SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000132 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C5 }, // # Command setting of SPI block
- { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000132 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C6 }, // # Command setting of SPI block
- { SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000132 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C7 }, // # Command setting of SPI block
- { SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000145 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C8 }, // # Command setting of SPI block
- { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
- { SSITX, 0x000800C9 }, // # Command setting of SPI block
- { SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CA }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EC }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D0 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D1 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D2 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000128 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D3 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000128 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D4 }, // # Command setting of SPI block
- { SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x000001A4 }, //
- { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
- { SSITX, 0x000800D5 }, // # Command setting of SPI block
- { SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EF }, // # Command setting of SPI block
- { SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x00000100 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BA}, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
+ {SSITX, 0x00000111}, // # Display mode setup(1) : Normaly Black
+ {SSITX, 0x00080036}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Memory access control
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x0008003A}, // # Command setting of SPI block
+ {SSITX, 0x00000160}, // # Display mode setup(2)
+ {SSITX, 0x000800B1}, // # Command setting of SPI block
+ {SSITX, 0x0000015D}, // # RGB Interface data format
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B2}, // # Command setting of SPI block
+ {SSITX, 0x00000133}, // # Drivnig method
+ {SSITX, 0x000800B3}, // # Command setting of SPI block
+ {SSITX, 0x00000122}, // # Booster operation setup
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B4}, // # Command setting of SPI block
+ {SSITX, 0x00000102}, // # OP-amp capability/System clock freq. division setup
+ {SSITX, 0x000800B5}, // # Command setting of SPI block
+ {SSITX, 0x0000011E}, // # VCS Voltage adjustment (1C->1F for Rev 2)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B6}, // # Command setting of SPI block
+ {SSITX, 0x00000127}, // # VCOM Voltage adjustment
+ {SSITX, 0x000800B7}, // # Command setting of SPI block
+ {SSITX, 0x00000103}, // # Configure an external display signal
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800B9}, // # Command setting of SPI block
+ {SSITX, 0x00000124}, // # DCCK/DCEV timing setup
+ {SSITX, 0x000800BD}, // # Command setting of SPI block
+ {SSITX, 0x000001A1}, // # ASW signal control
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BB}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Dummy display (white/black) count setup for QUAD Data operation
+ {SSITX, 0x000800BF}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # Dummy display (white/black) count setup for QUAD Data operation
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800BE}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # wait_ms(-out FR count setup (A)
+ {SSITX, 0x000800C0}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (A)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C1}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (B)
+ {SSITX, 0x000800C2}, // # Command setting of SPI block
+ {SSITX, 0x00000111}, // # wait_ms(-out FR count setup (C)
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C3}, // # Command setting of SPI block
+ {SSITX, 0x00080132}, // # wait_ms(-in line clock count setup (D)
+ {SSITX, 0x00000132}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C4}, // # Command setting of SPI block
+ {SSITX, 0x00080132}, // # Seep-in line clock count setup (E)
+ {SSITX, 0x00000132}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C5}, // # Command setting of SPI block
+ {SSITX, 0x00080132}, // # wait_ms(-in line clock count setup (F)
+ {SSITX, 0x00000132}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C6}, // # Command setting of SPI block
+ {SSITX, 0x00080132}, // # wait_ms(-in line clock setup (G)
+ {SSITX, 0x00000132}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C7}, // # Command setting of SPI block
+ {SSITX, 0x00080164}, // # Gamma 1 fine tuning (1)
+ {SSITX, 0x00000145}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800C8}, // # Command setting of SPI block
+ {SSITX, 0x00000144}, // # Gamma 1 fine tuning (2)
+ {SSITX, 0x000800C9}, // # Command setting of SPI block
+ {SSITX, 0x00000152}, // # Gamma 1 inclination adjustment
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800CA}, // # Command setting of SPI block
+ {SSITX, 0x00000100}, // # Gamma 1 blue offset adjustment
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800EC}, // # Command setting of SPI block
+ {SSITX, 0x00080102}, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
+ {SSITX, 0x00000118}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800CF}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D0}, // # Command setting of SPI block
+ {SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x00000104}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D1}, // # Command setting of SPI block
+ {SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D2}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x00000128}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D3}, // # Command setting of SPI block
+ {SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x00000128}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800D4}, // # Command setting of SPI block
+ {SSITX, 0x00080126}, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
+ {SSITX, 0x000001A4}, //
+ {0, 1}, // wait_ms(1); // # Wait SPI fifo empty
+ {SSITX, 0x000800D5}, // # Command setting of SPI block
+ {SSITX, 0x00000120}, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
+ {SSITX, 0x000800EF}, // # Command setting of SPI block
+ {SSITX, 0x00080132}, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
+ {SSITX, 0x00000100}, //
+ {0, 2}, // wait_ms(2); // # Wait SPI fifo empty
- { BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
- { BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
- { BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
- { BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
- { BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
- { CLKENB, 0x000001EB }, // SYS.CLKENB ); // DCLK supply
- { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
- { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
- { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
- { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
- { HCYCLE, 0x0000010B }, // LCD.HCYCLE ); // Setup to VGA size
- { HSW, 0x00000003 }, // LCD.HSW
- { HDE_START, 0x00000007 }, // LCD.HDE_START
- { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
- { VCYCLE, 0x00000325 }, // LCD.VCYCLE
- { VSW, 0x00000001 }, // LCD.VSW
- { VDE_START, 0x00000003 }, // LCD.VDE_START
- { VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
+ {BITMAP0, 0x032001E0}, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
+ {BITMAP1, 0x032001E0}, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
+ {BITMAP2, 0x014000F0}, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
+ {BITMAP3, 0x014000F0}, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
+ {BITMAP4, 0x014000F0}, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
+ {CLKENB, 0x000001EB}, // SYS.CLKENB ); // DCLK supply
+ {PORT_ENB, 0x00000001}, // LCD.PORT_ENB ); // Synchronous port enable
+ {PORT, 0x00000004}, // LCD.PORT ); // Polarity of DE is set to high active
+ {PXL, 0x00000002}, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
+ {MPLFBUF, 0x00000000}, // LCD.MPLFBUF ); // Select the reading buffer
+ {HCYCLE, 0x0000010B}, // LCD.HCYCLE ); // Setup to VGA size
+ {HSW, 0x00000003}, // LCD.HSW
+ {HDE_START, 0x00000007}, // LCD.HDE_START
+ {HDE_SIZE, 0x000000EF}, // LCD.HDE_SIZE
+ {VCYCLE, 0x00000325}, // LCD.VCYCLE
+ {VSW, 0x00000001}, // LCD.VSW
+ {VDE_START, 0x00000003}, // LCD.VDE_START
+ {VDE_SIZE, 0x0000031F}, // LCD.VDE_SIZE
- { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
+ {START, 0x00000001}, // LCD.START ); // LCDC - Pixel data transfer start
- { 0, 10 }, // wait_ms( 10 );
- { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
- { SSITX, 0x00000180 }, // Display data setup
- { SSITX, 0x0008003B }, // Command setting of SPI block
- { SSITX, 0x00000100 }, // Quad Data configuration - VGA
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B0 }, // Command setting of SPI block
- { SSITX, 0x00000116 }, // Power supply ON/OFF control
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B8 }, // Command setting of SPI block
- { SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
- { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
- { 0, 5 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000029 }, // Display on (Command only)
+ {0, 10}, // wait_ms( 10 );
+ {SSITX, 0x000800BC}, // SPI.SSITX ); // Command setting of SPI block
+ {SSITX, 0x00000180}, // Display data setup
+ {SSITX, 0x0008003B}, // Command setting of SPI block
+ {SSITX, 0x00000100}, // Quad Data configuration - VGA
+ {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
+ {SSITX, 0x000800B0}, // Command setting of SPI block
+ {SSITX, 0x00000116}, // Power supply ON/OFF control
+ {0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
+ {SSITX, 0x000800B8}, // Command setting of SPI block
+ {SSITX, 0x000801FF}, // Output control
+ {SSITX, 0x000001F5},
+ {0, 1}, // wait_ms( 1); // Wait SPI fifo empty
+ {SSITX, 0x00000011}, // wait_ms(-out (Command only)
+ {0, 5}, // wait_ms( 1); // Wait SPI fifo empty
+ {SSITX, 0x00000029}, // Display on (Command only)
- //{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
+ //{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
- { 0, 0 }
+ {0, 0}
};
void mddi_panel_poweron(void)
{
- display_common_power(1);
+ display_common_power(1);
}
static void _panel_init(struct init_table *init_table)
@@ -400,28 +393,25 @@
void panel_init(struct mddi_client_caps *client_caps)
{
- switch(client_caps->manufacturer_name) {
- case 0xd263: // Toshiba
+ switch (client_caps->manufacturer_name) {
+ case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
_panel_init(toshiba_480x800_init_table);
break;
- case 0x4474: //??
+ case 0x4474: //??
if (client_caps->product_code == 0xc065)
dprintf(INFO, "Found WVGA panel\n");
break;
}
}
-#endif //mddi
+#endif //mddi
void panel_poweron(void)
{
#if DISPLAY_TYPE_LCDC
- if (board_machtype() == LINUX_MACHTYPE_7x30_FLUID)
- {
+ if (board_machtype() == LINUX_MACHTYPE_7x30_FLUID) {
sharp_lcdc_on();
- }
- else
- {
+ } else {
panel_backlight(1);
lcdc_on();
}
@@ -430,11 +420,11 @@
void panel_backlight(int on)
{
- unsigned char reg_data = 0xA0;
- if(on)
- pmic_write(0x132, reg_data);
- else
- pmic_write(0x132, 0);
+ unsigned char reg_data = 0xA0;
+ if (on)
+ pmic_write(0x132, reg_data);
+ else
+ pmic_write(0x132, 0);
}
static unsigned wega_reset_gpio =
@@ -442,240 +432,234 @@
static int display_common_power(int on)
{
- int rc = 0, flag_on = !!on;
- static int display_common_power_save_on;
- unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8;
- if (display_common_power_save_on == flag_on)
- return 0;
+ int rc = 0, flag_on = !!on;
+ static int display_common_power_save_on;
+ unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8;
+ if (display_common_power_save_on == flag_on)
+ return 0;
- display_common_power_save_on = flag_on;
+ display_common_power_save_on = flag_on;
- if (on) {
- /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
- rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE);
- if (rc) {
- return rc;
- }
+ if (on) {
+ /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
+ rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE);
+ if (rc) {
+ return rc;
+ }
- gpio_set(180, 0); /* bring reset line low to hold reset*/
- }
+ gpio_set(180, 0); /* bring reset line low to hold reset */
+ }
+ // Set power for WEGA chip.
+ // Set LD020 to 1.5V
+ pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK);
+ mdelay(5);
- // Set power for WEGA chip.
- // Set LD020 to 1.5V
- pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK);
- mdelay(5);
+ // Set LD012 to 1.8V
+ pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK);
+ mdelay(5);
- // Set LD012 to 1.8V
- pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK);
- mdelay(5);
+ // Set LD016 to 2.6V
+ pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK);
+ mdelay(5);
- // Set LD016 to 2.6V
- pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK);
- mdelay(5);
+ // Set LD015 to 3.0V
+ pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK);
+ mdelay(5);
- // Set LD015 to 3.0V
- pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK);
- mdelay(5);
+ gpio_set(180, 1); /* bring reset line high */
+ mdelay(10); /* 10 msec before IO can be accessed */
+ if (rc) {
+ return rc;
+ }
- gpio_set(180, 1); /* bring reset line high */
- mdelay(10); /* 10 msec before IO can be accessed */
- if (rc) {
- return rc;
- }
-
- return rc;
+ return rc;
}
#if DISPLAY_TYPE_LCDC
static struct msm_gpio lcd_panel_gpios[] = {
- { GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" },
- { GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" },
- { GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" },
- { GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" }
+ {GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk"},
+ {GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0"},
+ {GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi"},
+ {GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso"}
};
int lcdc_toshiba_panel_power(int on)
{
- int rc, i;
- struct msm_gpio *gp;
+ int rc, i;
+ struct msm_gpio *gp;
- rc = display_common_power(on);
- if (rc < 0) {
- return rc;
- }
+ rc = display_common_power(on);
+ if (rc < 0) {
+ return rc;
+ }
- if (on) {
- rc = platform_gpios_enable(lcd_panel_gpios,
- ARRAY_SIZE(lcd_panel_gpios));
- if(rc)
- {
- return rc;
- }
- } else { /* off */
- gp = lcd_panel_gpios;
- for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
- /* ouput low */
- gpio_set(GPIO_PIN(gp->gpio_cfg), 0);
- gp++;
- }
- }
+ if (on) {
+ rc = platform_gpios_enable(lcd_panel_gpios,
+ ARRAY_SIZE(lcd_panel_gpios));
+ if (rc) {
+ return rc;
+ }
+ } else { /* off */
+ gp = lcd_panel_gpios;
+ for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
+ /* ouput low */
+ gpio_set(GPIO_PIN(gp->gpio_cfg), 0);
+ gp++;
+ }
+ }
- return rc;
+ return rc;
}
static void toshiba_spi_write_byte(char dc, unsigned char data)
{
- unsigned bit;
- int bnum;
+ unsigned bit;
+ int bnum;
- gpio_set(SPI_SCLK, 0); /* clk low */
- /* dc: 0 for command, 1 for parameter */
- gpio_set(SPI_MOSI, dc);
- mdelay(1); /* at least 20 ns */
- gpio_set(SPI_SCLK, 1); /* clk high */
- mdelay(1); /* at least 20 ns */
- bnum = 8; /* 8 data bits */
- bit = 0x80;
- while (bnum) {
- gpio_set(SPI_SCLK, 0); /* clk low */
- if (data & bit)
- gpio_set(SPI_MOSI, 1);
- else
- gpio_set(SPI_MOSI, 0);
- mdelay(1);
- gpio_set(SPI_SCLK, 1); /* clk high */
- mdelay(1);
- bit >>= 1;
- bnum--;
- }
+ gpio_set(SPI_SCLK, 0); /* clk low */
+ /* dc: 0 for command, 1 for parameter */
+ gpio_set(SPI_MOSI, dc);
+ mdelay(1); /* at least 20 ns */
+ gpio_set(SPI_SCLK, 1); /* clk high */
+ mdelay(1); /* at least 20 ns */
+ bnum = 8; /* 8 data bits */
+ bit = 0x80;
+ while (bnum) {
+ gpio_set(SPI_SCLK, 0); /* clk low */
+ if (data & bit)
+ gpio_set(SPI_MOSI, 1);
+ else
+ gpio_set(SPI_MOSI, 0);
+ mdelay(1);
+ gpio_set(SPI_SCLK, 1); /* clk high */
+ mdelay(1);
+ bit >>= 1;
+ bnum--;
+ }
}
-static int toshiba_spi_write (char cmd, unsigned data, int num)
+static int toshiba_spi_write(char cmd, unsigned data, int num)
{
- char *bp;
- gpio_set(SPI_CS, 1); /* cs high */
+ char *bp;
+ gpio_set(SPI_CS, 1); /* cs high */
- /* command byte first */
- toshiba_spi_write_byte(0, cmd);
+ /* command byte first */
+ toshiba_spi_write_byte(0, cmd);
- /* followed by parameter bytes */
- if (num) {
- bp = (char *)&data;;
- bp += (num - 1);
- while (num) {
- toshiba_spi_write_byte(1, *bp);
- num--;
- bp--;
- }
- }
- gpio_set(SPI_CS, 0); /* cs low */
- mdelay(1);
- return 0;
+ /* followed by parameter bytes */
+ if (num) {
+ bp = (char *)&data;;
+ bp += (num - 1);
+ while (num) {
+ toshiba_spi_write_byte(1, *bp);
+ num--;
+ bp--;
+ }
+ }
+ gpio_set(SPI_CS, 0); /* cs low */
+ mdelay(1);
+ return 0;
}
-
-void lcdc_disp_on (void)
+void lcdc_disp_on(void)
{
- gpio_set(SPI_CS, 0); /* low */
- gpio_set(SPI_SCLK, 1); /* high */
- gpio_set(SPI_MOSI, 0);
- gpio_set(SPI_MISO, 0);
+ gpio_set(SPI_CS, 0); /* low */
+ gpio_set(SPI_SCLK, 1); /* high */
+ gpio_set(SPI_MOSI, 0);
+ gpio_set(SPI_MISO, 0);
- if (1) {
- toshiba_spi_write(0, 0, 0);
- mdelay(7);
- toshiba_spi_write(0, 0, 0);
- mdelay(7);
- toshiba_spi_write(0, 0, 0);
- mdelay(7);
- toshiba_spi_write(0xba, 0x11, 1);
- toshiba_spi_write(0x36, 0x00, 1);
- mdelay(1);
- toshiba_spi_write(0x3a, 0x60, 1);
- toshiba_spi_write(0xb1, 0x5d, 1);
- mdelay(1);
- toshiba_spi_write(0xb2, 0x33, 1);
- toshiba_spi_write(0xb3, 0x22, 1);
- mdelay(1);
- toshiba_spi_write(0xb4, 0x02, 1);
- toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
- mdelay(1);
- toshiba_spi_write(0xb6, 0x27, 1);
- toshiba_spi_write(0xb7, 0x03, 1);
- mdelay(1);
- toshiba_spi_write(0xb9, 0x24, 1);
- toshiba_spi_write(0xbd, 0xa1, 1);
- mdelay(1);
- toshiba_spi_write(0xbb, 0x00, 1);
- toshiba_spi_write(0xbf, 0x01, 1);
- mdelay(1);
- toshiba_spi_write(0xbe, 0x00, 1);
- toshiba_spi_write(0xc0, 0x11, 1);
- mdelay(1);
- toshiba_spi_write(0xc1, 0x11, 1);
- toshiba_spi_write(0xc2, 0x11, 1);
- mdelay(1);
- toshiba_spi_write(0xc3, 0x3232, 2);
- mdelay(1);
- toshiba_spi_write(0xc4, 0x3232, 2);
- mdelay(1);
- toshiba_spi_write(0xc5, 0x3232, 2);
- mdelay(1);
- toshiba_spi_write(0xc6, 0x3232, 2);
- mdelay(1);
- toshiba_spi_write(0xc7, 0x6445, 2);
- mdelay(1);
- toshiba_spi_write(0xc8, 0x44, 1);
- toshiba_spi_write(0xc9, 0x52, 1);
- mdelay(1);
- toshiba_spi_write(0xca, 0x00, 1);
- mdelay(1);
- toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */
- mdelay(1);
- toshiba_spi_write(0xcf, 0x01, 1);
- mdelay(1);
- toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */
- mdelay(1);
- toshiba_spi_write(0xd1, 0x01, 1);
- mdelay(1);
- toshiba_spi_write(0xd2, 0x0028, 2);
- mdelay(1);
- toshiba_spi_write(0xd3, 0x0028, 2);
- mdelay(1);
- toshiba_spi_write(0xd4, 0x26a4, 2);
- mdelay(1);
- toshiba_spi_write(0xd5, 0x20, 1);
- mdelay(1);
- toshiba_spi_write(0xef, 0x3200, 2);
- mdelay(32);
- toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */
- toshiba_spi_write(0x3b, 0x00, 1);
- mdelay(1);
- toshiba_spi_write(0xb0, 0x16, 1);
- mdelay(1);
- toshiba_spi_write(0xb8, 0xfff5, 2);
- mdelay(1);
- toshiba_spi_write(0x11, 0, 0);
- mdelay(5);
- toshiba_spi_write(0x29, 0, 0);
- mdelay(5);
- }
+ if (1) {
+ toshiba_spi_write(0, 0, 0);
+ mdelay(7);
+ toshiba_spi_write(0, 0, 0);
+ mdelay(7);
+ toshiba_spi_write(0, 0, 0);
+ mdelay(7);
+ toshiba_spi_write(0xba, 0x11, 1);
+ toshiba_spi_write(0x36, 0x00, 1);
+ mdelay(1);
+ toshiba_spi_write(0x3a, 0x60, 1);
+ toshiba_spi_write(0xb1, 0x5d, 1);
+ mdelay(1);
+ toshiba_spi_write(0xb2, 0x33, 1);
+ toshiba_spi_write(0xb3, 0x22, 1);
+ mdelay(1);
+ toshiba_spi_write(0xb4, 0x02, 1);
+ toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
+ mdelay(1);
+ toshiba_spi_write(0xb6, 0x27, 1);
+ toshiba_spi_write(0xb7, 0x03, 1);
+ mdelay(1);
+ toshiba_spi_write(0xb9, 0x24, 1);
+ toshiba_spi_write(0xbd, 0xa1, 1);
+ mdelay(1);
+ toshiba_spi_write(0xbb, 0x00, 1);
+ toshiba_spi_write(0xbf, 0x01, 1);
+ mdelay(1);
+ toshiba_spi_write(0xbe, 0x00, 1);
+ toshiba_spi_write(0xc0, 0x11, 1);
+ mdelay(1);
+ toshiba_spi_write(0xc1, 0x11, 1);
+ toshiba_spi_write(0xc2, 0x11, 1);
+ mdelay(1);
+ toshiba_spi_write(0xc3, 0x3232, 2);
+ mdelay(1);
+ toshiba_spi_write(0xc4, 0x3232, 2);
+ mdelay(1);
+ toshiba_spi_write(0xc5, 0x3232, 2);
+ mdelay(1);
+ toshiba_spi_write(0xc6, 0x3232, 2);
+ mdelay(1);
+ toshiba_spi_write(0xc7, 0x6445, 2);
+ mdelay(1);
+ toshiba_spi_write(0xc8, 0x44, 1);
+ toshiba_spi_write(0xc9, 0x52, 1);
+ mdelay(1);
+ toshiba_spi_write(0xca, 0x00, 1);
+ mdelay(1);
+ toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */
+ mdelay(1);
+ toshiba_spi_write(0xcf, 0x01, 1);
+ mdelay(1);
+ toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */
+ mdelay(1);
+ toshiba_spi_write(0xd1, 0x01, 1);
+ mdelay(1);
+ toshiba_spi_write(0xd2, 0x0028, 2);
+ mdelay(1);
+ toshiba_spi_write(0xd3, 0x0028, 2);
+ mdelay(1);
+ toshiba_spi_write(0xd4, 0x26a4, 2);
+ mdelay(1);
+ toshiba_spi_write(0xd5, 0x20, 1);
+ mdelay(1);
+ toshiba_spi_write(0xef, 0x3200, 2);
+ mdelay(32);
+ toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */
+ toshiba_spi_write(0x3b, 0x00, 1);
+ mdelay(1);
+ toshiba_spi_write(0xb0, 0x16, 1);
+ mdelay(1);
+ toshiba_spi_write(0xb8, 0xfff5, 2);
+ mdelay(1);
+ toshiba_spi_write(0x11, 0, 0);
+ mdelay(5);
+ toshiba_spi_write(0x29, 0, 0);
+ mdelay(5);
+ }
}
void lcdc_on(void)
{
- lcdc_toshiba_panel_power(1);
- lcdc_disp_on();
+ lcdc_toshiba_panel_power(1);
+ lcdc_disp_on();
}
struct lcdc_timing_parameters *get_lcd_timing(void)
{
- if (board_machtype() == LINUX_MACHTYPE_7x30_FLUID)
- {
+ if (board_machtype() == LINUX_MACHTYPE_7x30_FLUID) {
return sharp_timing_param();
- }
- else
- {
+ } else {
return DEFAULT_LCD_TIMING;
}
}
diff --git a/platform/msm7x30/panel.h b/platform/msm7x30/panel.h
index 0154686..cb85901 100644
--- a/platform/msm7x30/panel.h
+++ b/platform/msm7x30/panel.h
@@ -34,7 +34,7 @@
#define LDO12_CNTRL 0x015
#define LDO15_CNTRL 0x089
#define LDO16_CNTRL 0x08A
-#define LDO20_CNTRL 0x11F /* PM8058 only */
+#define LDO20_CNTRL 0x11F /* PM8058 only */
#define LDO_LOCAL_EN_BMSK 0x80
#define SPI_SCLK 45
@@ -42,5 +42,4 @@
#define SPI_MOSI 47
#define SPI_MISO 48
-
#endif
diff --git a/platform/msm7x30/panel_sharp_wvga.c b/platform/msm7x30/panel_sharp_wvga.c
index d4c05f0..a70185b 100644
--- a/platform/msm7x30/panel_sharp_wvga.c
+++ b/platform/msm7x30/panel_sharp_wvga.c
@@ -36,11 +36,10 @@
#include "panel.h"
#include <dev/lcdc.h>
-
#define VEE_RESET 20
#define LCD_RESET 180
-#define GPIO26_GPIO_CNTRL 0x169 /* backlight */
+#define GPIO26_GPIO_CNTRL 0x169 /* backlight */
struct sharp_spi_data {
unsigned addr;
@@ -48,72 +47,72 @@
};
static struct sharp_spi_data init_sequence[] = {
- { 15, 0x01 },
- { 5, 0x01 },
- { 7, 0x10 },
- { 9, 0x1E },
- { 10, 0x04 },
- { 17, 0xFF },
- { 21, 0x8A },
- { 22, 0x00 },
- { 23, 0x82 },
- { 24, 0x24 },
- { 25, 0x22 },
- { 26, 0x6D },
- { 27, 0xEB },
- { 28, 0xB9 },
- { 29, 0x3A },
- { 49, 0x1A },
- { 50, 0x16 },
- { 51, 0x05 },
- { 55, 0x7F },
- { 56, 0x15 },
- { 57, 0x7B },
- { 60, 0x05 },
- { 61, 0x0C },
- { 62, 0x80 },
- { 63, 0x00 },
- { 92, 0x90 },
- { 97, 0x01 },
- { 98, 0xFF },
- { 113, 0x11 },
- { 114, 0x02 },
- { 115, 0x08 },
- { 123, 0xAB },
- { 124, 0x04 },
- { 6, 0x02 },
- { 133, 0x00 },
- { 134, 0xFE },
- { 135, 0x22 },
- { 136, 0x0B },
- { 137, 0xFF },
- { 138, 0x0F },
- { 139, 0x00 },
- { 140, 0xFE },
- { 141, 0x22 },
- { 142, 0x0B },
- { 143, 0xFF },
- { 144, 0x0F },
- { 145, 0x00 },
- { 146, 0xFE },
- { 147, 0x22 },
- { 148, 0x0B },
- { 149, 0xFF },
- { 150, 0x0F },
- { 202, 0x30 },
- { 30, 0x01 },
- { 4, 0x01 },
- { 31, 0x41 }
+ {15, 0x01},
+ {5, 0x01},
+ {7, 0x10},
+ {9, 0x1E},
+ {10, 0x04},
+ {17, 0xFF},
+ {21, 0x8A},
+ {22, 0x00},
+ {23, 0x82},
+ {24, 0x24},
+ {25, 0x22},
+ {26, 0x6D},
+ {27, 0xEB},
+ {28, 0xB9},
+ {29, 0x3A},
+ {49, 0x1A},
+ {50, 0x16},
+ {51, 0x05},
+ {55, 0x7F},
+ {56, 0x15},
+ {57, 0x7B},
+ {60, 0x05},
+ {61, 0x0C},
+ {62, 0x80},
+ {63, 0x00},
+ {92, 0x90},
+ {97, 0x01},
+ {98, 0xFF},
+ {113, 0x11},
+ {114, 0x02},
+ {115, 0x08},
+ {123, 0xAB},
+ {124, 0x04},
+ {6, 0x02},
+ {133, 0x00},
+ {134, 0xFE},
+ {135, 0x22},
+ {136, 0x0B},
+ {137, 0xFF},
+ {138, 0x0F},
+ {139, 0x00},
+ {140, 0xFE},
+ {141, 0x22},
+ {142, 0x0B},
+ {143, 0xFF},
+ {144, 0x0F},
+ {145, 0x00},
+ {146, 0xFE},
+ {147, 0x22},
+ {148, 0x0B},
+ {149, 0xFF},
+ {150, 0x0F},
+ {202, 0x30},
+ {30, 0x01},
+ {4, 0x01},
+ {31, 0x41}
};
-static unsigned char bit_shift[8] = { (1 << 7), /* MSB */
+static unsigned char bit_shift[8] = { (1 << 7), /* MSB */
(1 << 6),
(1 << 5),
(1 << 4),
(1 << 3),
(1 << 2),
(1 << 1),
- (1 << 0) /* LSB */
+ (1 << 0) /* LSB */
};
static unsigned vee_reset_gpio =
@@ -122,7 +121,6 @@
static unsigned lcd_reset_gpio =
GPIO_CFG(LCD_RESET, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA);
-
static int sharp_display_common_power(int on)
{
int rc = 0, flag_on = !!on;
@@ -140,7 +138,7 @@
return rc;
}
- gpio_set(LCD_RESET, 0); /* bring reset line low to hold reset */
+ gpio_set(LCD_RESET, 0); /* bring reset line low to hold reset */
/* set VEE reset */
rc = gpio_tlmm_config(vee_reset_gpio, GPIO_ENABLE);
@@ -150,7 +148,7 @@
}
gpio_set(VEE_RESET, 1);
- gpio_set(VEE_RESET, 0); /* bring reset line low to hold reset */
+ gpio_set(VEE_RESET, 0); /* bring reset line low to hold reset */
mdelay(10);
}
@@ -166,41 +164,41 @@
/* wait for power to stabilize */
mdelay(10);
- gpio_config(VEE_RESET, 0); /*disable VEE_RESET, rely on pullups to bring it high */
+ gpio_config(VEE_RESET, 0); /*disable VEE_RESET, rely on pullups to bring it high */
mdelay(5);
- gpio_set(LCD_RESET, 1); /* bring reset line high */
- mdelay(10); /* 10 msec before IO can be accessed */
+ gpio_set(LCD_RESET, 1); /* bring reset line high */
+ mdelay(10); /* 10 msec before IO can be accessed */
return rc;
}
static struct msm_gpio sharp_lcd_panel_gpios[] = {
- { GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" },
- { GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" },
- { GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" },
- { GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" },
- { GPIO_CFG(22, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu2" },
- { GPIO_CFG(25, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red2" },
- { GPIO_CFG(90, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_pclk" },
- { GPIO_CFG(91, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_en" },
- { GPIO_CFG(92, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_vsync" },
- { GPIO_CFG(93, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_hsync" },
- { GPIO_CFG(94, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn2" },
- { GPIO_CFG(95, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn3" },
- { GPIO_CFG(96, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn4" },
- { GPIO_CFG(97, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn5" },
- { GPIO_CFG(98, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn6" },
- { GPIO_CFG(99, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn7" },
- { GPIO_CFG(100, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu3" },
- { GPIO_CFG(101, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu4" },
- { GPIO_CFG(102, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu5" },
- { GPIO_CFG(103, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu6" },
- { GPIO_CFG(104, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu7" },
- { GPIO_CFG(105, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red3" },
- { GPIO_CFG(106, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red4" },
- { GPIO_CFG(107, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red5" },
- { GPIO_CFG(108, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red6" },
+ {GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk"},
+ {GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0"},
+ {GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi"},
+ {GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso"},
+ {GPIO_CFG(22, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu2"},
+ {GPIO_CFG(25, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red2"},
+ {GPIO_CFG(90, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_pclk"},
+ {GPIO_CFG(91, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_en"},
+ {GPIO_CFG(92, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_vsync"},
+ {GPIO_CFG(93, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_hsync"},
+ {GPIO_CFG(94, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn2"},
+ {GPIO_CFG(95, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn3"},
+ {GPIO_CFG(96, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn4"},
+ {GPIO_CFG(97, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn5"},
+ {GPIO_CFG(98, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn6"},
+ {GPIO_CFG(99, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_grn7"},
+ {GPIO_CFG(100, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu3"},
+ {GPIO_CFG(101, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu4"},
+ {GPIO_CFG(102, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu5"},
+ {GPIO_CFG(103, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu6"},
+ {GPIO_CFG(104, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_blu7"},
+ {GPIO_CFG(105, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red3"},
+ {GPIO_CFG(106, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red4"},
+ {GPIO_CFG(107, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red5"},
+ {GPIO_CFG(108, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "lcdc_red6"},
};
int sharp_lcdc_panel_power(int on)
@@ -215,12 +213,11 @@
if (on) {
rc = platform_gpios_enable(sharp_lcd_panel_gpios,
- ARRAY_SIZE(sharp_lcd_panel_gpios));
- if(rc)
- {
+ ARRAY_SIZE(sharp_lcd_panel_gpios));
+ if (rc) {
return rc;
}
- } else { /* off */
+ } else { /* off */
gp = sharp_lcd_panel_gpios;
for (i = 0; i < ARRAY_SIZE(sharp_lcd_panel_gpios); i++) {
/* ouput low */
@@ -231,7 +228,6 @@
return rc;
}
-
static void sharp_spi_write_byte(unsigned val)
{
int i;
@@ -269,7 +265,7 @@
return 0;
}
-void sharp_lcdc_disp_on (void)
+void sharp_lcdc_disp_on(void)
{
unsigned i;
gpio_set(SPI_CS, 1);
@@ -293,26 +289,26 @@
sharp_lcdc_panel_power(1);
/*enable backlight, open up gpio, use default for LPG */
- pmic_write(GPIO26_GPIO_CNTRL,0x81); /* Write, Bank0, VIN0=VPH, Mode selection enabled */
- pmic_write(GPIO26_GPIO_CNTRL,0x99); /* Write, Bank1, OutOn/InOff, CMOS, Invert Output (GPIO High) */
- pmic_write(GPIO26_GPIO_CNTRL,0xAA); /* Write, Bank2, GPIO no pull */
- pmic_write(GPIO26_GPIO_CNTRL,0xB4); /* Write, Bank3, high drv strength */
- pmic_write(GPIO26_GPIO_CNTRL,0xC6); /* Write, Bank4, Src: Special Function 2 */
+ pmic_write(GPIO26_GPIO_CNTRL, 0x81); /* Write, Bank0, VIN0=VPH, Mode selection enabled */
+ pmic_write(GPIO26_GPIO_CNTRL, 0x99); /* Write, Bank1, OutOn/InOff, CMOS, Invert Output (GPIO High) */
+ pmic_write(GPIO26_GPIO_CNTRL, 0xAA); /* Write, Bank2, GPIO no pull */
+ pmic_write(GPIO26_GPIO_CNTRL, 0xB4); /* Write, Bank3, high drv strength */
+ pmic_write(GPIO26_GPIO_CNTRL, 0xC6); /* Write, Bank4, Src: Special Function 2 */
sharp_lcdc_disp_on();
}
static struct lcdc_timing_parameters param = {
- .lcdc_fb_width = 480,
- .lcdc_fb_height = 800,
- .lcdc_hsync_pulse_width_dclk = 10,
- .lcdc_hsync_back_porch_dclk = 20,
- .lcdc_hsync_front_porch_dclk = 10,
- .lcdc_hsync_skew_dclk = 0,
+ .lcdc_fb_width = 480,
+ .lcdc_fb_height = 800,
+ .lcdc_hsync_pulse_width_dclk = 10,
+ .lcdc_hsync_back_porch_dclk = 20,
+ .lcdc_hsync_front_porch_dclk = 10,
+ .lcdc_hsync_skew_dclk = 0,
- .lcdc_vsync_pulse_width_lines = 2,
- .lcdc_vsync_back_porch_lines = 2,
- .lcdc_vsync_front_porch_lines = 2,
+ .lcdc_vsync_pulse_width_lines = 2,
+ .lcdc_vsync_back_porch_lines = 2,
+ .lcdc_vsync_front_porch_lines = 2,
};
struct lcdc_timing_parameters *sharp_timing_param()
diff --git a/platform/msm7x30/platform.c b/platform/msm7x30/platform.c
index 5916866..83260f8 100644
--- a/platform/msm7x30/platform.c
+++ b/platform/msm7x30/platform.c
@@ -53,21 +53,21 @@
#define ARRAY_SIZE(a) (sizeof(a)/(sizeof((a)[0])))
static unsigned uart2_gpio_table[] = {
- GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
- GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
- GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
- GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
+ GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
+ GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
+ GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA),
+ GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
};
/* CRCI - mmc slot mapping.
* mmc slot numbering start from 1.
* entry at index 0 is just dummy.
*/
-uint8_t sdc_crci_map[5] = {0, 6, 7, 12, 13};
+uint8_t sdc_crci_map[5] = { 0, 6, 7, 12, 13 };
void uart2_mux_init(void)
{
- platform_gpios_enable(uart2_gpio_table, ARRAY_SIZE(uart2_gpio_table));
+ platform_gpios_enable(uart2_gpio_table, ARRAY_SIZE(uart2_gpio_table));
}
void platform_early_init(void)
@@ -92,61 +92,59 @@
void mdp4_display_intf_sel(int output, int intf)
{
- unsigned bits, mask;
- unsigned dma2_cfg_reg;
- bits = readl(MSM_MDP_BASE1 + 0x0038);
- mask = 0x03; /* 2 bits */
- intf &= 0x03; /* 2 bits */
+ unsigned bits, mask;
+ unsigned dma2_cfg_reg;
+ bits = readl(MSM_MDP_BASE1 + 0x0038);
+ mask = 0x03; /* 2 bits */
+ intf &= 0x03; /* 2 bits */
- switch (output) {
- case EXTERNAL_INTF_SEL:
- intf <<= 4;
- mask <<= 4;
- break;
- case SECONDARY_INTF_SEL:
- intf &= 0x02; /* only MDDI and EBI2 support */
- intf <<= 2;
- mask <<= 2;
- break;
- default:
- break;
- }
+ switch (output) {
+ case EXTERNAL_INTF_SEL:
+ intf <<= 4;
+ mask <<= 4;
+ break;
+ case SECONDARY_INTF_SEL:
+ intf &= 0x02; /* only MDDI and EBI2 support */
+ intf <<= 2;
+ mask <<= 2;
+ break;
+ default:
+ break;
+ }
- bits &= ~mask;
- bits |= intf;
- writel(bits, MSM_MDP_BASE1 + 0x0038); /* MDP_DISP_INTF_SEL */
+ bits &= ~mask;
+ bits |= intf;
+ writel(bits, MSM_MDP_BASE1 + 0x0038); /* MDP_DISP_INTF_SEL */
}
-
-
void display_init(void)
{
struct fbcon_config *fb_cfg;
#if DISPLAY_TYPE_MDDI
- mddi_pmdh_clock_init();
- mddi_panel_poweron();
- /* We need to config GPIO 38 for Sleep clock with Spl Fun 2 */
- toshiba_pmic_gpio_init(GPIO38_GPIO_CNTRL);
- fb_cfg = mddi_init();
- fbcon_setup(fb_cfg);
+ mddi_pmdh_clock_init();
+ mddi_panel_poweron();
+ /* We need to config GPIO 38 for Sleep clock with Spl Fun 2 */
+ toshiba_pmic_gpio_init(GPIO38_GPIO_CNTRL);
+ fb_cfg = mddi_init();
+ fbcon_setup(fb_cfg);
#endif
#if DISPLAY_TYPE_LCDC
- struct lcdc_timing_parameters *lcd_timing;
- mdp_lcdc_clock_init();
- lcd_timing = get_lcd_timing();
- fb_cfg = lcdc_init_set( lcd_timing );
- panel_poweron();
- fbcon_setup(fb_cfg);
+ struct lcdc_timing_parameters *lcd_timing;
+ mdp_lcdc_clock_init();
+ lcd_timing = get_lcd_timing();
+ fb_cfg = lcdc_init_set(lcd_timing);
+ panel_poweron();
+ fbcon_setup(fb_cfg);
#endif
}
void display_shutdown(void)
{
#if DISPLAY_TYPE_LCDC
- /* Turning off LCDC */
- lcdc_shutdown();
+ /* Turning off LCDC */
+ lcdc_shutdown();
#endif
}
@@ -169,13 +167,13 @@
/* Check for the hardware revision */
val = readl(HW_REVISION_NUMBER);
val = (val >> 28) & 0x0F;
- if(val >= 1)
+ if (val >= 1)
writel(1, DGT_CLK_CTL);
#if _EMMC_BOOT
- ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
+ ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
#else
- ticks_per_sec = 6144000; /* Uses LPXO/4 (24.576 MHz / 4) */
+ ticks_per_sec = 6144000; /* Uses LPXO/4 (24.576 MHz / 4) */
#endif
}
diff --git a/platform/msm8960/acpuclock.c b/platform/msm8960/acpuclock.c
index 1deed72..1b4a11e 100644
--- a/platform/msm8960/acpuclock.c
+++ b/platform/msm8960/acpuclock.c
@@ -75,12 +75,11 @@
}
/* Write the M,N,D values and enable the MMSS Clocks */
-void config_mmss_clk( uint32_t ns,
- uint32_t md,
- uint32_t cc,
- uint32_t ns_addr,
- uint32_t md_addr,
- uint32_t cc_addr){
+void config_mmss_clk(uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr)
+{
unsigned int val = 0;
clock_config(ns, md, ns_addr, md_addr);
@@ -116,7 +115,7 @@
writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
/* Proceed only after PLL is enabled */
- while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
+ while (!(readl(MSM_BOOT_PLL8_STATUS) & (1 << 16))) ;
}
void hsusb_clock_init(void)
@@ -126,9 +125,8 @@
/* Setup XCVR clock */
clock_config(USB_XCVR_CLK_NS,
- USB_XCVR_CLK_MD,
- USB_HS1_XCVR_FS_CLK_NS,
- USB_HS1_XCVR_FS_CLK_MD);
+ USB_XCVR_CLK_MD,
+ USB_HS1_XCVR_FS_CLK_NS, USB_HS1_XCVR_FS_CLK_MD);
}
/* Configure UART clock - based on the gsbi id */
@@ -136,10 +134,8 @@
{
/* Enable gsbi_uart_clk */
clock_config(UART_DM_CLK_NS_115200,
- UART_DM_CLK_MD_115200,
- GSBIn_UART_APPS_NS(id),
- GSBIn_UART_APPS_MD(id));
-
+ UART_DM_CLK_MD_115200,
+ GSBIn_UART_APPS_NS(id), GSBIn_UART_APPS_MD(id));
/* Enable gsbi_pclk */
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
@@ -151,8 +147,7 @@
uint32_t ns;
uint32_t md;
- switch (freq)
- {
+ switch (freq) {
case 24000000:
ns = I2C_CLK_NS_24MHz;
md = I2C_CLK_MD_24MHz;
@@ -167,27 +162,28 @@
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
-void pll1_enable(void){
+void pll1_enable(void)
+{
uint32_t val = 0;
/* Reset MND divider */
- val |= (1<<2);
+ val |= (1 << 2);
writel(val, MM_PLL1_MODE_REG);
/* Use PLL -- Disable Bypass */
- val |= (1<<1);
+ val |= (1 << 1);
writel(val, MM_PLL1_MODE_REG);
/* Activate PLL out control */
val |= 1;
writel(val, MM_PLL1_MODE_REG);
- while (!readl(MM_PLL1_STATUS_REG));
+ while (!readl(MM_PLL1_STATUS_REG)) ;
}
void config_mdp_lut_clk(void)
{
- /* Force on*/
+ /* Force on */
writel(MDP_LUT_VAL, MDP_LUT_CC_REG);
}
@@ -199,7 +195,7 @@
/* Turn on MDP clk */
config_mmss_clk(MDP_NS_VAL, MDP_MD_VAL,
- MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
+ MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
/* Seems to lose pixels without this from status 0x051E0048 */
config_mdp_lut_clk();
@@ -209,16 +205,20 @@
void mmss_clock_init(void)
{
/* Configure Pixel clock */
- config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, PIXEL_NS_REG, PIXEL_MD_REG, PIXEL_CC_REG);
+ config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, PIXEL_NS_REG,
+ PIXEL_MD_REG, PIXEL_CC_REG);
/* Configure DSI clock */
- config_mmss_clk(DSI_NS_VAL, DSI_MD_VAL, DSI_CC_VAL, DSI_NS_REG, DSI_MD_REG, DSI_CC_REG);
+ config_mmss_clk(DSI_NS_VAL, DSI_MD_VAL, DSI_CC_VAL, DSI_NS_REG,
+ DSI_MD_REG, DSI_CC_REG);
/* Configure Byte clock */
- config_mmss_clk(BYTE_NS_VAL, 0x0, BYTE_CC_VAL, BYTE_NS_REG, 0x0, BYTE_CC_REG);
+ config_mmss_clk(BYTE_NS_VAL, 0x0, BYTE_CC_VAL, BYTE_NS_REG, 0x0,
+ BYTE_CC_REG);
/* Configure ESC clock */
- config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, ESC_NS_REG, 0x0, ESC_CC_REG);
+ config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, ESC_NS_REG, 0x0,
+ ESC_CC_REG);
}
/* Intialize MMC clock */
@@ -232,20 +232,17 @@
{
uint32_t reg = 0;
- switch(freq)
- {
+ switch (freq) {
case MMC_CLK_400KHZ:
clock_config(SDC_CLK_NS_400KHZ,
- SDC_CLK_MD_400KHZ,
- SDC_NS(interface),
- SDC_MD(interface));
+ SDC_CLK_MD_400KHZ,
+ SDC_NS(interface), SDC_MD(interface));
break;
case MMC_CLK_48MHZ:
- case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
+ case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
clock_config(SDC_CLK_NS_48MHZ,
- SDC_CLK_MD_48MHZ,
- SDC_NS(interface),
- SDC_MD(interface));
+ SDC_CLK_MD_48MHZ,
+ SDC_NS(interface), SDC_MD(interface));
break;
default:
ASSERT(0);
@@ -255,15 +252,15 @@
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel( reg, MMC_BOOT_MCI_CLK );
+ writel(reg, MMC_BOOT_MCI_CLK);
}
/* Configure crypto engine clock */
void ce_clock_init(void)
{
/* Enable HCLK for CE1 */
- writel((1<<4), CE1_HCLK_CTL);
+ writel((1 << 4), CE1_HCLK_CTL);
/* Enable core clk for CE1 */
- writel((1<<4), CE1_CORE_CLK_CTL);
+ writel((1 << 4), CE1_CORE_CLK_CTL);
return;
}
diff --git a/platform/msm8960/gpio.c b/platform/msm8960/gpio.c
index f46da1f..638ad8c 100644
--- a/platform/msm8960/gpio.c
+++ b/platform/msm8960/gpio.c
@@ -33,52 +33,50 @@
#include <gsbi.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable)
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
{
- unsigned int val = 0;
- val |= pull;
- val |= func << 2;
- val |= drvstr << 6;
- val |= enable << 9;
- unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
- writel(val, addr);
- return;
+ unsigned int val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
+ writel(val, addr);
+ return;
}
void gpio_set(uint32_t gpio, uint32_t dir)
{
- unsigned int *addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio);
- writel(dir, addr);
- return;
+ unsigned int *addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio);
+ writel(dir, addr);
+ return;
}
/* Configure gpio for uart - based on gsbi id */
void gpio_config_uart_dm(uint8_t id)
{
- switch (id)
- {
+ switch (id) {
case GSBI_ID_3:
/* configure rx gpio */
gpio_tlmm_config(15, 1, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
gpio_tlmm_config(14, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
break;
case GSBI_ID_5:
/* configure rx gpio */
gpio_tlmm_config(23, 1, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
gpio_tlmm_config(22, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
break;
default:
ASSERT(0);
}
}
-
diff --git a/platform/msm8960/include/platform/clock.h b/platform/msm8960/include/platform/clock.h
index ae95601..c723294 100644
--- a/platform/msm8960/include/platform/clock.h
+++ b/platform/msm8960/include/platform/clock.h
@@ -41,10 +41,8 @@
#define UART_DM_CLK_NS_115200 0xFFE40040
#define UART_DM_CLK_MD_115200 0x0002FFE2
-
#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
-
/* NS/MD value for MMC */
#define SDC_CLK_NS_400KHZ 0x00440040
#define SDC_CLK_MD_400KHZ 0x00010043
@@ -100,12 +98,10 @@
#define MDP_LUT_VAL 0x00000001
-void config_mmss_clk( uint32_t ns,
- uint32_t md,
- uint32_t cc,
- uint32_t ns_addr,
- uint32_t md_addr,
- uint32_t cc_addr);
+void config_mmss_clk(uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr);
void pll1_enable(void);
void config_mdp_lut_clk(void);
void mdp_clock_init(void);
diff --git a/platform/msm8960/include/platform/iomap.h b/platform/msm8960/include/platform/iomap.h
index dadf70d..7494995 100644
--- a/platform/msm8960/include/platform/iomap.h
+++ b/platform/msm8960/include/platform/iomap.h
@@ -87,7 +87,6 @@
#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
#define QUP_BASE(id) (GSBI_BASE(id) + 0x80000)
-
#define EBI2_CHIP_SELECT_CFG0 0x1A100000
#define EBI2_XMEM_CS3_CFG1 0x1A110034
diff --git a/platform/msm8960/include/platform/irqs.h b/platform/msm8960/include/platform/irqs.h
index 033d790..c4ed400 100644
--- a/platform/msm8960/include/platform/irqs.h
+++ b/platform/msm8960/include/platform/irqs.h
@@ -49,7 +49,6 @@
#define GSBI_QUP_IRQ(id) ((id) <= 8 ? (GIC_SPI_START + 145 + 2*((id))) : \
(GIC_SPI_START + 187 + 2*((id)-8)))
-
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
@@ -59,4 +58,4 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#endif /* __IRQS_8960_H */
+#endif /* __IRQS_8960_H */
diff --git a/platform/msm8960/platform.c b/platform/msm8960/platform.c
index 9e41329..4735756 100644
--- a/platform/msm8960/platform.c
+++ b/platform/msm8960/platform.c
@@ -69,44 +69,44 @@
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_NON_SHARED | \
MMU_MEMORY_AP_READ_WRITE)
-
mmu_section_t mmu_section_table[] = {
/* Physical addr, Virtual addr, Size (in MB), Flags */
- {MEMBASE, MEMBASE, (MEMSIZE/MB), LK_MEMORY},
- {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
- {SCRATCH_ADDR, SCRATCH_ADDR, 128, SCRATCH_MEMORY},
- {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ {MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
+ {SCRATCH_ADDR, SCRATCH_ADDR, 128, SCRATCH_MEMORY},
+ {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
};
void platform_early_init(void)
{
- qgic_init();
- platform_init_timer();
+ qgic_init();
+ platform_init_timer();
}
void platform_init(void)
{
- dprintf(INFO, "platform_init()\n");
+ dprintf(INFO, "platform_init()\n");
}
-void display_init(void){
- struct fbcon_config *fb_cfg;
+void display_init(void)
+{
+ struct fbcon_config *fb_cfg;
- panel_backlight_on();
+ panel_backlight_on();
- mipi_dsi_panel_power_on();
- mipi_panel_reset();
+ mipi_dsi_panel_power_on();
+ mipi_panel_reset();
- mdp_clock_init();
- mmss_clock_init();
+ mdp_clock_init();
+ mmss_clock_init();
- fb_cfg = mipi_init();
- fbcon_setup(fb_cfg);
+ fb_cfg = mipi_init();
+ fbcon_setup(fb_cfg);
}
void display_shutdown(void)
{
- mipi_dsi_shutdown();
+ mipi_dsi_shutdown();
}
void platform_uninit(void)
@@ -120,21 +120,21 @@
/* Setup memory for this platform */
void platform_init_mmu_mappings(void)
{
- uint32_t i;
- uint32_t sections;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- for (i = 0; i < table_size; i++)
- {
- sections = mmu_section_table[i].num_of_sections;
+ for (i = 0; i < table_size; i++) {
+ sections = mmu_section_table[i].num_of_sections;
- while (sections--)
- {
- arm_mmu_map_section(mmu_section_table[i].paddress + sections*MB,
- mmu_section_table[i].vaddress + sections*MB,
- mmu_section_table[i].flags);
- }
- }
+ while (sections--) {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
}
/* Initialize DGT timer */
@@ -148,7 +148,7 @@
*/
writel(3, DGT_CLK_CTL);
- ticks_per_sec = 6750000; /* (27 MHz / 4) */
+ ticks_per_sec = 6750000; /* (27 MHz / 4) */
}
/* Returns timer ticks per sec */
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index 10116e0..47e6526 100644
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -40,203 +40,197 @@
/* Read, modify, then write-back a register. */
static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask)
{
- uint32_t regval = readl(reg);
- regval &= ~mask;
- regval |= val;
- writel(regval, reg);
+ uint32_t regval = readl(reg);
+ regval &= ~mask;
+ regval |= val;
+ writel(regval, reg);
}
/* Enable/disable for non-shared NT PLLs. */
int nt_pll_enable(uint8_t src, uint8_t enable)
{
- static const struct {
- uint32_t const mode_reg;
- uint32_t const status_reg;
- } pll_reg[] = {
- [PLL_1] = { MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG },
- [PLL_2] = { MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG },
- [PLL_3] = { MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG },
- };
- uint32_t pll_mode;
+ static const struct {
+ uint32_t const mode_reg;
+ uint32_t const status_reg;
+ } pll_reg[] = {
+ [PLL_1] = {
+ MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG},[PLL_2] = {
+ MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG},[PLL_3] = {
+ MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG},};
+ uint32_t pll_mode;
- pll_mode = secure_readl(pll_reg[src].mode_reg);
- if (enable) {
- /* Disable PLL bypass mode. */
- pll_mode |= (1<<1);
- secure_writel( pll_mode, pll_reg[src].mode_reg);
+ pll_mode = secure_readl(pll_reg[src].mode_reg);
+ if (enable) {
+ /* Disable PLL bypass mode. */
+ pll_mode |= (1 << 1);
+ secure_writel(pll_mode, pll_reg[src].mode_reg);
- /* H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe. */
- udelay(10);
+ /* H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe. */
+ udelay(10);
- /* De-assert active-low PLL reset. */
- pll_mode |= (1<<2);
- secure_writel( pll_mode, pll_reg[src].mode_reg);
+ /* De-assert active-low PLL reset. */
+ pll_mode |= (1 << 2);
+ secure_writel(pll_mode, pll_reg[src].mode_reg);
- /* Enable PLL output. */
- pll_mode |= (1<<0);
- secure_writel( pll_mode, pll_reg[src].mode_reg);
+ /* Enable PLL output. */
+ pll_mode |= (1 << 0);
+ secure_writel(pll_mode, pll_reg[src].mode_reg);
- /* Wait until PLL is enabled. */
- while (!secure_readl(pll_reg[src].status_reg));
- } else {
- /* Disable the PLL output, disable test mode, enable
- * the bypass mode, and assert the reset. */
- pll_mode &= 0xFFFFFFF0;
- secure_writel( pll_mode, pll_reg[src].mode_reg);
- }
+ /* Wait until PLL is enabled. */
+ while (!secure_readl(pll_reg[src].status_reg)) ;
+ } else {
+ /* Disable the PLL output, disable test mode, enable
+ * the bypass mode, and assert the reset. */
+ pll_mode &= 0xFFFFFFF0;
+ secure_writel(pll_mode, pll_reg[src].mode_reg);
+ }
- return 0;
+ return 0;
}
/* Write the M,N,D values and enable the MDP Core Clock */
-void config_mdp_clk( uint32_t ns,
- uint32_t md,
- uint32_t cc,
- uint32_t ns_addr,
- uint32_t md_addr,
- uint32_t cc_addr)
+void config_mdp_clk(uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr)
{
- unsigned int val = 0;
+ unsigned int val = 0;
- /* MN counter reset */
- val = 1 << 31;
- secure_writel(val, ns_addr);
+ /* MN counter reset */
+ val = 1 << 31;
+ secure_writel(val, ns_addr);
- /* Write the MD and CC register values */
- secure_writel(md, md_addr);
- secure_writel(cc, cc_addr);
+ /* Write the MD and CC register values */
+ secure_writel(md, md_addr);
+ secure_writel(cc, cc_addr);
- /* Reset the clk control, and Write ns val */
- val = 1 << 31;
- val |= ns;
- secure_writel(val, ns_addr);
+ /* Reset the clk control, and Write ns val */
+ val = 1 << 31;
+ val |= ns;
+ secure_writel(val, ns_addr);
- /* Clear MN counter reset */
- val = 1 << 31;
- val = ~val;
- val = val & secure_readl(ns_addr);
- secure_writel(val, ns_addr);
+ /* Clear MN counter reset */
+ val = 1 << 31;
+ val = ~val;
+ val = val & secure_readl(ns_addr);
+ secure_writel(val, ns_addr);
- /* Enable MND counter */
- val = 1 << 8;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable MND counter */
+ val = 1 << 8;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
- /* Enable the root of the clock tree */
- val = 1 << 2;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable the root of the clock tree */
+ val = 1 << 2;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
- /* Enable the MDP Clock */
- val = 1 << 0;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable the MDP Clock */
+ val = 1 << 0;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
}
/* Write the M,N,D values and enable the Pixel Core Clock */
-void config_pixel_clk( uint32_t ns,
- uint32_t md,
- uint32_t cc,
- uint32_t ns_addr,
- uint32_t md_addr,
- uint32_t cc_addr){
- unsigned int val = 0;
+void config_pixel_clk(uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr)
+{
+ unsigned int val = 0;
- /* Activate the reset for the M/N Counter */
- val = 1 << 7;
- secure_writel(val, ns_addr);
+ /* Activate the reset for the M/N Counter */
+ val = 1 << 7;
+ secure_writel(val, ns_addr);
- /* Write the MD and CC register values */
- secure_writel(md, md_addr);
- secure_writel(cc, cc_addr);
+ /* Write the MD and CC register values */
+ secure_writel(md, md_addr);
+ secure_writel(cc, cc_addr);
- /* Write the ns value, and active reset for M/N Counter, again */
- val = 1 << 7;
- val |= ns;
- secure_writel(val, ns_addr);
+ /* Write the ns value, and active reset for M/N Counter, again */
+ val = 1 << 7;
+ val |= ns;
+ secure_writel(val, ns_addr);
- /* De-activate the reset for M/N Counter */
- val = 1 << 7;
- val = ~val;
- val = val & secure_readl(ns_addr);
- secure_writel(val, ns_addr);
+ /* De-activate the reset for M/N Counter */
+ val = 1 << 7;
+ val = ~val;
+ val = val & secure_readl(ns_addr);
+ secure_writel(val, ns_addr);
- /* Enable MND counter */
- val = 1 << 5;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable MND counter */
+ val = 1 << 5;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
- /* Enable the root of the clock tree */
- val = 1 << 2;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable the root of the clock tree */
+ val = 1 << 2;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
- /* Enable the MDP Clock */
- val = 1 << 0;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable the MDP Clock */
+ val = 1 << 0;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
- /* Enable the LCDC Clock */
- val = 1 << 8;
- val = val | secure_readl(cc_addr);
- secure_writel(val, cc_addr);
+ /* Enable the LCDC Clock */
+ val = 1 << 8;
+ val = val | secure_readl(cc_addr);
+ secure_writel(val, cc_addr);
}
/* Set rate and enable the clock */
-void clock_config(uint32_t ns,
- uint32_t md,
- uint32_t ns_addr,
- uint32_t md_addr)
+void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
{
- unsigned int val = 0;
+ unsigned int val = 0;
- /* Activate the reset for the M/N Counter */
- val = 1 << 7;
- writel(val, ns_addr);
+ /* Activate the reset for the M/N Counter */
+ val = 1 << 7;
+ writel(val, ns_addr);
- /* Write the MD value into the MD register */
- writel(md, md_addr);
+ /* Write the MD value into the MD register */
+ writel(md, md_addr);
- /* Write the ns value, and active reset for M/N Counter, again */
- val = 1 << 7;
- val |= ns;
- writel(val, ns_addr);
+ /* Write the ns value, and active reset for M/N Counter, again */
+ val = 1 << 7;
+ val |= ns;
+ writel(val, ns_addr);
- /* De-activate the reset for M/N Counter */
- val = 1 << 7;
- val = ~val;
- val = val & readl(ns_addr);
- writel(val, ns_addr);
+ /* De-activate the reset for M/N Counter */
+ val = 1 << 7;
+ val = ~val;
+ val = val & readl(ns_addr);
+ writel(val, ns_addr);
- /* Enable the M/N Counter */
- val = 1 << 8;
- val = val | readl(ns_addr);
- writel(val, ns_addr);
+ /* Enable the M/N Counter */
+ val = 1 << 8;
+ val = val | readl(ns_addr);
+ writel(val, ns_addr);
- /* Enable the Clock Root */
- val = 1 << 11;
- val = val | readl(ns_addr);
- writel(val, ns_addr);
+ /* Enable the Clock Root */
+ val = 1 << 11;
+ val = val | readl(ns_addr);
+ writel(val, ns_addr);
- /* Enable the Clock Branch */
- val = 1 << 9;
- val = val | readl(ns_addr);
- writel(val, ns_addr);
+ /* Enable the Clock Branch */
+ val = 1 << 9;
+ val = val | readl(ns_addr);
+ writel(val, ns_addr);
}
void pll8_enable(void)
{
- /* Currently both UART and USB depend on this PLL8 clock initialization. */
- unsigned int curr_value = 0;
+ /* Currently both UART and USB depend on this PLL8 clock initialization. */
+ unsigned int curr_value = 0;
- /* Vote for PLL8 to be enabled */
- curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
- curr_value |= (1 << 8);
- writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
+ /* Vote for PLL8 to be enabled */
+ curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
+ curr_value |= (1 << 8);
+ writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
- /* Proceed only after PLL is enabled */
- while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
+ /* Proceed only after PLL is enabled */
+ while (!(readl(MSM_BOOT_PLL8_STATUS) & (1 << 16))) ;
}
void uart_clock_init(void)
@@ -289,7 +283,7 @@
void ce_clock_init(void)
{
/* Enable clock branch for CE2 */
- writel((1<<4), CE2_HCLK_CTL);
+ writel((1 << 4), CE2_HCLK_CTL);
return;
}
@@ -315,8 +309,7 @@
uint32_t ns;
uint32_t md;
- switch (freq)
- {
+ switch (freq) {
case 24000000:
ns = I2C_CLK_NS_24MHz;
md = I2C_CLK_MD_24MHz;
@@ -342,20 +335,17 @@
{
uint32_t reg = 0;
- switch(freq)
- {
+ switch (freq) {
case MMC_CLK_400KHZ:
clock_config(SDC_CLK_NS_400KHZ,
- SDC_CLK_MD_400KHZ,
- SDC_NS(interface),
- SDC_MD(interface));
+ SDC_CLK_MD_400KHZ,
+ SDC_NS(interface), SDC_MD(interface));
break;
case MMC_CLK_48MHZ:
- case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
+ case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
clock_config(SDC_CLK_NS_48MHZ,
- SDC_CLK_MD_48MHZ,
- SDC_NS(interface),
- SDC_MD(interface));
+ SDC_CLK_MD_48MHZ,
+ SDC_NS(interface), SDC_MD(interface));
break;
default:
ASSERT(0);
@@ -365,7 +355,7 @@
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
- writel( reg, MMC_BOOT_MCI_CLK );
+ writel(reg, MMC_BOOT_MCI_CLK);
}
void mdp_clock_init(void)
@@ -374,20 +364,19 @@
nt_pll_enable(PLL_2, 1);
config_mdp_clk(MDP_NS_VAL, MDP_MD_VAL,
- MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
+ MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
}
void mmss_pixel_clock_configure(uint32_t pclk_id)
{
if (pclk_id == PIXEL_CLK_INDEX_25M) {
config_pixel_clk(PIXEL_NS_VAL_25M, PIXEL_MD_VAL_25M,
- PIXEL_CC_VAL_25M, MMSS_PIXEL_NS_REG,
- MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG);
- }
- else {
+ PIXEL_CC_VAL_25M, MMSS_PIXEL_NS_REG,
+ MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG);
+ } else {
config_pixel_clk(PIXEL_NS_VAL, PIXEL_MD_VAL,
- PIXEL_CC_VAL, MMSS_PIXEL_NS_REG,
- MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG);
+ PIXEL_CC_VAL, MMSS_PIXEL_NS_REG,
+ MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG);
}
}
@@ -395,11 +384,11 @@
{
unsigned char mnd_mode, root_en, clk_en;
unsigned long src_sel = 0x3; // dsi_phy_pll0_src
- unsigned long pre_div_func = 0x00; // predivide by 1
+ unsigned long pre_div_func = 0x00; // predivide by 1
unsigned long pmxo_sel;
secure_writel(pre_div_func << 14 | src_sel, DSI_NS_REG);
- mnd_mode = 0; // Bypass MND
+ mnd_mode = 0; // Bypass MND
root_en = 1;
clk_en = 1;
pmxo_sel = 0;
@@ -411,23 +400,21 @@
void configure_dsicore_byteclk(void)
{
- secure_writel(0x00400401, MISC_CC2_REG); // select pxo
+ secure_writel(0x00400401, MISC_CC2_REG); // select pxo
}
void configure_dsicore_pclk(void)
{
unsigned char mnd_mode, root_en, clk_en;
unsigned long src_sel = 0x3; // dsi_phy_pll0_src
- unsigned long pre_div_func = 0x01; // predivide by 2
+ unsigned long pre_div_func = 0x01; // predivide by 2
secure_writel(pre_div_func << 12 | src_sel, PIXEL_NS_REG);
- mnd_mode = 0; // Bypass MND
+ mnd_mode = 0; // Bypass MND
root_en = 1;
clk_en = 1;
secure_writel(mnd_mode << 6, PIXEL_CC_REG);
- secure_writel(secure_readl(PIXEL_CC_REG) | root_en << 2,
- PIXEL_CC_REG);
- secure_writel(secure_readl(PIXEL_CC_REG) | clk_en,
- PIXEL_CC_REG);
+ secure_writel(secure_readl(PIXEL_CC_REG) | root_en << 2, PIXEL_CC_REG);
+ secure_writel(secure_readl(PIXEL_CC_REG) | clk_en, PIXEL_CC_REG);
}
diff --git a/platform/msm8x60/gpio.c b/platform/msm8x60/gpio.c
index d7bd786..fcd7fd4 100644
--- a/platform/msm8x60/gpio.c
+++ b/platform/msm8x60/gpio.c
@@ -33,38 +33,37 @@
#include <gsbi.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable)
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
{
- unsigned int val = 0;
- val |= pull;
- val |= func << 2;
- val |= drvstr << 6;
- val |= enable << 9;
- unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
- writel(val, addr);
- return;
+ unsigned int val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
+ writel(val, addr);
+ return;
}
void gpio_set(uint32_t gpio, uint32_t dir)
{
- unsigned int *addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio);
- writel(dir, addr);
- return;
+ unsigned int *addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio);
+ writel(dir, addr);
+ return;
}
/* Configure gpio for uart - based on gsbi id */
void gpio_config_uart_dm(uint8_t id)
{
- switch (id)
- {
+ switch (id) {
case GSBI_ID_12:
/* configure rx gpio */
gpio_tlmm_config(117, 2, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
gpio_tlmm_config(118, 2, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ GPIO_8MA, GPIO_DISABLE);
break;
default:
ASSERT(0);
@@ -74,13 +73,12 @@
/* Configure gpio for i2c - based on gsbi id */
void gpio_config_i2c(uint8_t id)
{
- switch (id)
- {
+ switch (id) {
case GSBI_ID_8:
gpio_tlmm_config(64, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_2MA, GPIO_DISABLE);
+ GPIO_2MA, GPIO_DISABLE);
gpio_tlmm_config(65, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_2MA, GPIO_DISABLE);
+ GPIO_2MA, GPIO_DISABLE);
break;
default:
ASSERT(0);
@@ -89,6 +87,6 @@
void gpio_config_pshold(void)
{
- gpio_tlmm_config(92, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_12MA, GPIO_DISABLE);
+ gpio_tlmm_config(92, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_12MA,
+ GPIO_DISABLE);
}
-
diff --git a/platform/msm8x60/hdmi_core.c b/platform/msm8x60/hdmi_core.c
index f96124c..1a804de 100644
--- a/platform/msm8x60/hdmi_core.c
+++ b/platform/msm8x60/hdmi_core.c
@@ -39,21 +39,21 @@
void hdmi_msm_init_phy()
{
- dprintf(SPEW,"PHY INIT\n");
+ dprintf(SPEW, "PHY INIT\n");
uint32_t offset = 0;
uint32_t len = 0;
- writel(0x0C,HDMI_PHY_REG_0);
- writel(0x54,HDMI_PHY_REG_1);
- writel(0x7F,HDMI_PHY_REG_2);
- writel(0x3F,HDMI_PHY_REG_2);
- writel(0x1F,HDMI_PHY_REG_2);
+ writel(0x0C, HDMI_PHY_REG_0);
+ writel(0x54, HDMI_PHY_REG_1);
+ writel(0x7F, HDMI_PHY_REG_2);
+ writel(0x3F, HDMI_PHY_REG_2);
+ writel(0x1F, HDMI_PHY_REG_2);
- writel(0x01,HDMI_PHY_REG_3);
- writel(0x00,HDMI_PHY_REG_9);
- writel(0x03,HDMI_PHY_REG_12);
- writel(0x01,HDMI_PHY_REG_2);
- writel(0x81,HDMI_PHY_REG_2);
+ writel(0x01, HDMI_PHY_REG_3);
+ writel(0x00, HDMI_PHY_REG_9);
+ writel(0x03, HDMI_PHY_REG_12);
+ writel(0x01, HDMI_PHY_REG_2);
+ writel(0x81, HDMI_PHY_REG_2);
offset = (HDMI_PHY_REG_4 - MSM_HDMI_BASE);
len = (HDMI_PHY_REG_11 - MSM_HDMI_BASE);
@@ -61,7 +61,7 @@
writel(0x0, MSM_HDMI_BASE + offset);
offset += 4;
}
- writel(0x13,HDMI_PHY_REG_12);
+ writel(0x13, HDMI_PHY_REG_12);
}
void hdmi_frame_ctrl_reg()
@@ -72,7 +72,7 @@
hdmi_frame_ctrl |= ((0 << 29) & 0x20000000);
hdmi_frame_ctrl |= ((0 << 28) & 0x10000000);
hdmi_frame_ctrl |= (1 << 12);
- writel(hdmi_frame_ctrl,HDMI_FRAME_CTRL);
+ writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL);
}
static void hdmi_gpio_config()
@@ -148,7 +148,7 @@
secure_writel(0xff, TV_MD_REG);
val = secure_readl(TV_CC_REG);
- val &= ~(BM(7,6));
+ val &= ~(BM(7, 6));
val |= CC(6, 0);
secure_writel(val, TV_CC_REG);
@@ -157,9 +157,9 @@
// confiure hdmi_ref clk to run @ 148.5 MHz
val = secure_readl(MISC_CC2_REG);
- val &= ~(BIT(28)|BM(21, 18));
+ val &= ~(BIT(28) | BM(21, 18));
ns_val = NS_MM(23, 16, 0, 0, 15, 14, 2, 2, 0, 3);
- val |= (BIT(28)| BVAL(21, 18, (ns_val >> 14) & 0x3));
+ val |= (BIT(28) | BVAL(21, 18, (ns_val >> 14) & 0x3));
secure_writel(val, MISC_CC2_REG);
pll_mode |= BIT(2);
diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
index 4bce765..62b31d4 100644
--- a/platform/msm8x60/include/platform/clock.h
+++ b/platform/msm8x60/include/platform/clock.h
@@ -93,8 +93,8 @@
#define PIXEL_CC_VAL_25M 0x00000080
/* PIXEL clock index */
-#define PIXEL_CLK_INDEX_54M 0 /* 53.99MHz */
-#define PIXEL_CLK_INDEX_25M 1 /* 25MHz */
+#define PIXEL_CLK_INDEX_54M 0 /* 53.99MHz */
+#define PIXEL_CLK_INDEX_25M 1 /* 25MHz */
#define MSM_CLK_CTL_BASE 0x00900000
#define BB_PLL8_L_VAL_REG (MSM_CLK_CTL_BASE + 0x3144)
@@ -107,7 +107,6 @@
#define UART_DM_CLK_NS_115200 0xFD940043
#define UART_DM_CLK_MD_115200 0x0006FD8E
-
#define UART_DM_CLK_RX_TX_BIT_RATE 0xEE
/* GSBI/I2C QUP APPS CLK definitions */
@@ -129,19 +128,19 @@
#define TV_MD_REG REG_MM(0x00F0)
enum clk_sources {
- PLL_0 = 0,
- PLL_1,
- PLL_2,
- PLL_3,
- PLL_4,
- PLL_5,
- PLL_6,
- PLL_7,
- PLL_8,
- MXO,
- PXO,
- CXO,
- NUM_SRC
+ PLL_0 = 0,
+ PLL_1,
+ PLL_2,
+ PLL_3,
+ PLL_4,
+ PLL_5,
+ PLL_6,
+ PLL_7,
+ PLL_8,
+ MXO,
+ PXO,
+ CXO,
+ NUM_SRC
};
void hsusb_clock_init(void);
diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index 6067bb7..9cb1a54 100644
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -121,7 +121,6 @@
#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
#define QUP_BASE(id) (GSBI_BASE(id) + 0x80000)
-
#define CLK_CTL_BASE 0x00900000
#define SDC_MD(n) (CLK_CTL_BASE + 0x2828 + (32 * ((n) - 1)))
#define SDC_NS(n) (CLK_CTL_BASE + 0x282C + (32 * ((n) - 1)))
@@ -149,7 +148,6 @@
#define EBI2_CHIP_SELECT_CFG0 0x1A100000
#define EBI2_XMEM_CS3_CFG1 0x1A110034
-
#define MSM_ADM_BASE 0x18400000
#define MSM_ADM_SD_OFFSET 0x00020800
diff --git a/platform/msm8x60/include/platform/irqs.h b/platform/msm8x60/include/platform/irqs.h
index feb3bd8..a795ed4 100644
--- a/platform/msm8x60/include/platform/irqs.h
+++ b/platform/msm8x60/include/platform/irqs.h
@@ -53,4 +53,4 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#endif /* __ASM_ARCH_MSM_IRQS_8x60_H */
+#endif /* __ASM_ARCH_MSM_IRQS_8x60_H */
diff --git a/platform/msm8x60/include/platform/machtype.h b/platform/msm8x60/include/platform/machtype.h
old mode 100755
new mode 100644
diff --git a/platform/msm8x60/include/platform/pmic.h b/platform/msm8x60/include/platform/pmic.h
old mode 100755
new mode 100644
index 258b368..51e6055
--- a/platform/msm8x60/include/platform/pmic.h
+++ b/platform/msm8x60/include/platform/pmic.h
@@ -138,59 +138,58 @@
#define PM8058_LDO_CTRL_L25 (0x124)
#define PM8058_LDO_TEST_L25 (0x12C)
-typedef enum
-{
- PM_KYPD_PWRON_IRQ_ID = 51,
+typedef enum {
+ PM_KYPD_PWRON_IRQ_ID = 51,
- /* Block 24 Interrupts */
- PM_GPIO01_CHGED_ST_IRQ_ID = 192,
- PM_GPIO02_CHGED_ST_IRQ_ID = 193,
- PM_GPIO03_CHGED_ST_IRQ_ID = 194,
- PM_GPIO04_CHGED_ST_IRQ_ID = 195,
- PM_GPIO05_CHGED_ST_IRQ_ID = 196,
- PM_GPIO06_CHGED_ST_IRQ_ID = 197,
- PM_GPIO07_CHGED_ST_IRQ_ID = 198,
- PM_GPIO08_CHGED_ST_IRQ_ID = 199,
+ /* Block 24 Interrupts */
+ PM_GPIO01_CHGED_ST_IRQ_ID = 192,
+ PM_GPIO02_CHGED_ST_IRQ_ID = 193,
+ PM_GPIO03_CHGED_ST_IRQ_ID = 194,
+ PM_GPIO04_CHGED_ST_IRQ_ID = 195,
+ PM_GPIO05_CHGED_ST_IRQ_ID = 196,
+ PM_GPIO06_CHGED_ST_IRQ_ID = 197,
+ PM_GPIO07_CHGED_ST_IRQ_ID = 198,
+ PM_GPIO08_CHGED_ST_IRQ_ID = 199,
- /* Block 25 Interrupts */
- PM_GPIO09_CHGED_ST_IRQ_ID = 200,
- PM_GPIO10_CHGED_ST_IRQ_ID = 201,
- PM_GPIO11_CHGED_ST_IRQ_ID = 202,
- PM_GPIO12_CHGED_ST_IRQ_ID = 203,
- PM_GPIO13_CHGED_ST_IRQ_ID = 204,
- PM_GPIO14_CHGED_ST_IRQ_ID = 205,
- PM_GPIO15_CHGED_ST_IRQ_ID = 206,
- PM_GPIO16_CHGED_ST_IRQ_ID = 207,
+ /* Block 25 Interrupts */
+ PM_GPIO09_CHGED_ST_IRQ_ID = 200,
+ PM_GPIO10_CHGED_ST_IRQ_ID = 201,
+ PM_GPIO11_CHGED_ST_IRQ_ID = 202,
+ PM_GPIO12_CHGED_ST_IRQ_ID = 203,
+ PM_GPIO13_CHGED_ST_IRQ_ID = 204,
+ PM_GPIO14_CHGED_ST_IRQ_ID = 205,
+ PM_GPIO15_CHGED_ST_IRQ_ID = 206,
+ PM_GPIO16_CHGED_ST_IRQ_ID = 207,
- /* Block 26 Interrupts */
- PM_GPIO17_CHGED_ST_IRQ_ID = 208,
- PM_GPIO18_CHGED_ST_IRQ_ID = 209,
- PM_GPIO19_CHGED_ST_IRQ_ID = 210,
- PM_GPIO20_CHGED_ST_IRQ_ID = 211,
- PM_GPIO21_CHGED_ST_IRQ_ID = 212,
- PM_GPIO22_CHGED_ST_IRQ_ID = 213,
- PM_GPIO23_CHGED_ST_IRQ_ID = 214,
- PM_GPIO24_CHGED_ST_IRQ_ID = 215,
+ /* Block 26 Interrupts */
+ PM_GPIO17_CHGED_ST_IRQ_ID = 208,
+ PM_GPIO18_CHGED_ST_IRQ_ID = 209,
+ PM_GPIO19_CHGED_ST_IRQ_ID = 210,
+ PM_GPIO20_CHGED_ST_IRQ_ID = 211,
+ PM_GPIO21_CHGED_ST_IRQ_ID = 212,
+ PM_GPIO22_CHGED_ST_IRQ_ID = 213,
+ PM_GPIO23_CHGED_ST_IRQ_ID = 214,
+ PM_GPIO24_CHGED_ST_IRQ_ID = 215,
- /* Block 27 Interrupts */
- PM_GPIO25_CHGED_ST_IRQ_ID = 216,
- PM_GPIO26_CHGED_ST_IRQ_ID = 217,
- PM_GPIO27_CHGED_ST_IRQ_ID = 218,
- PM_GPIO28_CHGED_ST_IRQ_ID = 219,
- PM_GPIO29_CHGED_ST_IRQ_ID = 220,
- PM_GPIO30_CHGED_ST_IRQ_ID = 221,
- PM_GPIO31_CHGED_ST_IRQ_ID = 222,
- PM_GPIO32_CHGED_ST_IRQ_ID = 223,
+ /* Block 27 Interrupts */
+ PM_GPIO25_CHGED_ST_IRQ_ID = 216,
+ PM_GPIO26_CHGED_ST_IRQ_ID = 217,
+ PM_GPIO27_CHGED_ST_IRQ_ID = 218,
+ PM_GPIO28_CHGED_ST_IRQ_ID = 219,
+ PM_GPIO29_CHGED_ST_IRQ_ID = 220,
+ PM_GPIO30_CHGED_ST_IRQ_ID = 221,
+ PM_GPIO31_CHGED_ST_IRQ_ID = 222,
+ PM_GPIO32_CHGED_ST_IRQ_ID = 223,
- /* Block 28 Interrupts */
- PM_GPIO33_CHGED_ST_IRQ_ID = 224,
- PM_GPIO34_CHGED_ST_IRQ_ID = 225,
- PM_GPIO35_CHGED_ST_IRQ_ID = 226,
- PM_GPIO36_CHGED_ST_IRQ_ID = 227,
- PM_GPIO37_CHGED_ST_IRQ_ID = 228,
- PM_GPIO38_CHGED_ST_IRQ_ID = 229,
- PM_GPIO39_CHGED_ST_IRQ_ID = 230,
- PM_GPIO40_CHGED_ST_IRQ_ID = 231,
-}pm_irq_id_type;
+ /* Block 28 Interrupts */
+ PM_GPIO33_CHGED_ST_IRQ_ID = 224,
+ PM_GPIO34_CHGED_ST_IRQ_ID = 225,
+ PM_GPIO35_CHGED_ST_IRQ_ID = 226,
+ PM_GPIO36_CHGED_ST_IRQ_ID = 227,
+ PM_GPIO37_CHGED_ST_IRQ_ID = 228,
+ PM_GPIO38_CHGED_ST_IRQ_ID = 229,
+ PM_GPIO39_CHGED_ST_IRQ_ID = 230,
+ PM_GPIO40_CHGED_ST_IRQ_ID = 231,
+} pm_irq_id_type;
#endif
diff --git a/platform/msm8x60/include/platform/pmic_batt_alarm.h b/platform/msm8x60/include/platform/pmic_batt_alarm.h
index 56f232a..e711fd7 100644
--- a/platform/msm8x60/include/platform/pmic_batt_alarm.h
+++ b/platform/msm8x60/include/platform/pmic_batt_alarm.h
@@ -119,13 +119,13 @@
HOLD_TIME_4_MS,
HOLD_TIME_8_MS,
HOLD_TIME_16_MS,
-}pm_batt_alarm_hold_time;
+} pm_batt_alarm_hold_time;
typedef enum {
ALARM_EN_NEVER = 0,
ALARM_EN_PWM,
ALARM_EN_ALWAYS,
-}pm_batt_alarm_pwm_ctrl;
+} pm_batt_alarm_pwm_ctrl;
struct pm_batt_alarm_device {
uint8_t reg_threshold;
@@ -135,8 +135,8 @@
};
extern int pm8058_mwrite(uint16_t addr, uint8_t val, uint8_t mask,
- uint8_t *reg_save);
-extern int pm8058_read(uint16_t addr, uint8_t *data, uint16_t length);
+ uint8_t * reg_save);
+extern int pm8058_read(uint16_t addr, uint8_t * data, uint16_t length);
extern void mdelay(uint32_t ms);
#endif
diff --git a/platform/msm8x60/include/platform/pmic_pwm.h b/platform/msm8x60/include/platform/pmic_pwm.h
index 810790b..04ac564 100644
--- a/platform/msm8x60/include/platform/pmic_pwm.h
+++ b/platform/msm8x60/include/platform/pmic_pwm.h
@@ -65,7 +65,7 @@
/* The MAX value is computation limit. Hardware limit is 393 seconds. */
#define PM_PWM_PERIOD_MAX (274 * USEC_PER_SEC)
/* The MIN value is hardware limit. */
-#define PM_PWM_PERIOD_MIN 7 /* micro seconds */
+#define PM_PWM_PERIOD_MIN 7 /* micro seconds */
#define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ)
#define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL)
@@ -137,10 +137,10 @@
#define PM_PWM_PAUSE_ENABLE_LOW 0x02
#define PM_PWM_RESERVED 0x01
-#define PM_PWM_PAUSE_COUNT_MAX 56 /* < 2^6 = 64*/
+#define PM_PWM_PAUSE_COUNT_MAX 56 /* < 2^6 = 64 */
struct pm_pwm_config {
- int pwm_size; /* round up to 6 or 9 for 6/9-bit PWM SIZE */
+ int pwm_size; /* round up to 6 or 9 for 6/9-bit PWM SIZE */
int clk;
int pre_div;
int pre_div_exp;
diff --git a/platform/msm8x60/panel.c b/platform/msm8x60/panel.c
old mode 100755
new mode 100644
index 57310a1..73b4b3d
--- a/platform/msm8x60/panel.c
+++ b/platform/msm8x60/panel.c
@@ -45,42 +45,42 @@
static struct qup_i2c_dev *dev = NULL;
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable);
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable);
uint8_t expander_read(uint8_t addr)
{
- uint8_t ret = 0;
- /* Create a i2c_msg buffer, that is used to put the controller into read
- mode and then to read some data. */
- struct i2c_msg msg_buf[] = {
- {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_WR, 1, &addr},
- {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_RD, 1, &ret}
- };
+ uint8_t ret = 0;
+ /* Create a i2c_msg buffer, that is used to put the controller into read
+ mode and then to read some data. */
+ struct i2c_msg msg_buf[] = {
+ {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_WR, 1, &addr},
+ {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_RD, 1, &ret}
+ };
- qup_i2c_xfer(dev, msg_buf, 2);
+ qup_i2c_xfer(dev, msg_buf, 2);
- return ret;
+ return ret;
}
uint8_t expander_write(uint8_t addr, uint8_t val)
{
- uint8_t data_buf[] = { addr, val };
+ uint8_t data_buf[] = { addr, val };
- /* Create a i2c_msg buffer, that is used to put the controller into write
- mode and then to write some data. */
- struct i2c_msg msg_buf[] = { {CORE_GPIO_EXPANDER_I2C_ADDRESS,
- I2C_M_WR, 2, data_buf}
- };
+ /* Create a i2c_msg buffer, that is used to put the controller into write
+ mode and then to write some data. */
+ struct i2c_msg msg_buf[] = { {CORE_GPIO_EXPANDER_I2C_ADDRESS,
+ I2C_M_WR, 2, data_buf}
+ };
- qup_i2c_xfer(dev, msg_buf, 1);
+ qup_i2c_xfer(dev, msg_buf, 1);
- /* Double check that the write worked. */
- if (val != expander_read(addr)) {
- return -1;
- }
+ /* Double check that the write worked. */
+ if (val != expander_read(addr)) {
+ return -1;
+ }
- return 0;
+ return 0;
}
void panel_backlight(int on)
@@ -93,31 +93,31 @@
static int lcd_power_on()
{
- uint8_t buffer = 0x0, mask = 0x0, prev_val = 0x0;
- int ret = 0;
+ uint8_t buffer = 0x0, mask = 0x0, prev_val = 0x0;
+ int ret = 0;
- /* Configure LDO L2 TEST Bank 2, to Range Select 0 */
- /* Not updating reference voltage */
- buffer = (0x80); /* Write mode */
- buffer |= (PM8901_LDO_TEST_BANK(2)); /* Test Bank 2 */
- mask = buffer | LDO_TEST_RANGE_SELECT_MASK;
+ /* Configure LDO L2 TEST Bank 2, to Range Select 0 */
+ /* Not updating reference voltage */
+ buffer = (0x80); /* Write mode */
+ buffer |= (PM8901_LDO_TEST_BANK(2)); /* Test Bank 2 */
+ mask = buffer | LDO_TEST_RANGE_SELECT_MASK;
- if ((ret = pm8901_test_bank_read(&prev_val,
- PM8901_LDO_TEST_BANK(2),
- PM8901_LDO_L2_TEST_BANK))) {
- return ret;
- }
- if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
- prev_val))) {
- return ret;
- }
+ if ((ret = pm8901_test_bank_read(&prev_val,
+ PM8901_LDO_TEST_BANK(2),
+ PM8901_LDO_L2_TEST_BANK))) {
+ return ret;
+ }
+ if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+ prev_val))) {
+ return ret;
+ }
- /* Enable LDO L2 at Max Voltage (should be around 3.3v) */
- buffer = (0x0 << PM8901_LDO_CTL_ENABLE__S);
- /* Disable Pull Down */
- buffer |= (0x1 << PM8901_LDO_CTL_PULL_DOWN__S);
- /* Put LDO into normal mode instead of low power mode */
- buffer |= (0x0 << PM8901_LDO_CTL_MODE__S);
+ /* Enable LDO L2 at Max Voltage (should be around 3.3v) */
+ buffer = (0x0 << PM8901_LDO_CTL_ENABLE__S);
+ /* Disable Pull Down */
+ buffer |= (0x1 << PM8901_LDO_CTL_PULL_DOWN__S);
+ /* Put LDO into normal mode instead of low power mode */
+ buffer |= (0x0 << PM8901_LDO_CTL_MODE__S);
/* Set voltage programming to 3.3V or 2.85V(8660 fluid) */
if (board_machtype() == LINUX_MACHTYPE_8660_FLUID)
@@ -125,59 +125,59 @@
else
buffer |= (0xF);
- mask = buffer | LDO_CTL_ENABLE_MASK |
- LDO_CTL_PULL_DOWN_MASK |
- LDO_CTL_NORMAL_POWER_MODE_MASK | LDO_CTL_VOLTAGE_SET_MASK;
+ mask = buffer | LDO_CTL_ENABLE_MASK |
+ LDO_CTL_PULL_DOWN_MASK |
+ LDO_CTL_NORMAL_POWER_MODE_MASK | LDO_CTL_VOLTAGE_SET_MASK;
- /* Do a normal read here, as to not destroy the value in LDO control */
- if ((ret = pm8901_read(&prev_val, 1, PM8901_LDO_L2))) {
- return ret;
- }
- /* Configure the LDO2 for 3.3V or 2.85V(8660 fluid) */
- ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2, prev_val);
+ /* Do a normal read here, as to not destroy the value in LDO control */
+ if ((ret = pm8901_read(&prev_val, 1, PM8901_LDO_L2))) {
+ return ret;
+ }
+ /* Configure the LDO2 for 3.3V or 2.85V(8660 fluid) */
+ ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2, prev_val);
- /* Configure LDO L2 TEST Bank 4, for High Range Mode */
- buffer = (0x80); /* Write mode */
- buffer |= (PM8901_LDO_TEST_BANK(4)); /* Test Bank 4 */
- buffer |= (0x01); /* Put into High Range Mode */
- mask = buffer | LDO_TEST_OUTPUT_RANGE_MASK;
+ /* Configure LDO L2 TEST Bank 4, for High Range Mode */
+ buffer = (0x80); /* Write mode */
+ buffer |= (PM8901_LDO_TEST_BANK(4)); /* Test Bank 4 */
+ buffer |= (0x01); /* Put into High Range Mode */
+ mask = buffer | LDO_TEST_OUTPUT_RANGE_MASK;
- if ((ret = pm8901_test_bank_read(&prev_val,
- PM8901_LDO_TEST_BANK(4),
- PM8901_LDO_L2_TEST_BANK))) {
- return ret;
- }
- if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
- prev_val))) {
- return ret;
- }
+ if ((ret = pm8901_test_bank_read(&prev_val,
+ PM8901_LDO_TEST_BANK(4),
+ PM8901_LDO_L2_TEST_BANK))) {
+ return ret;
+ }
+ if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+ prev_val))) {
+ return ret;
+ }
- /* Configure LDO L2 TEST Bank 2, to Range Select 0 */
- buffer = (0x80); /* Write mode */
- buffer |= (PM8901_LDO_TEST_BANK(2)); /* Test Bank 2 */
- buffer |= (1<<1); /* For fine step 50 mV */
- buffer |= (1<<3); /* to update reference voltage */
- mask = buffer | LDO_TEST_RANGE_SELECT_MASK;
- mask |= (1<<2); /* Setting mask to make ref voltage as 1.25 V */
+ /* Configure LDO L2 TEST Bank 2, to Range Select 0 */
+ buffer = (0x80); /* Write mode */
+ buffer |= (PM8901_LDO_TEST_BANK(2)); /* Test Bank 2 */
+ buffer |= (1 << 1); /* For fine step 50 mV */
+ buffer |= (1 << 3); /* to update reference voltage */
+ mask = buffer | LDO_TEST_RANGE_SELECT_MASK;
+ mask |= (1 << 2); /* Setting mask to make ref voltage as 1.25 V */
- if ((ret = pm8901_test_bank_read(&prev_val,
- PM8901_LDO_TEST_BANK(2),
- PM8901_LDO_L2_TEST_BANK))) {
- return ret;
- }
- if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
- prev_val))) {
- return ret;
- }
+ if ((ret = pm8901_test_bank_read(&prev_val,
+ PM8901_LDO_TEST_BANK(2),
+ PM8901_LDO_L2_TEST_BANK))) {
+ return ret;
+ }
+ if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+ prev_val))) {
+ return ret;
+ }
- /* Enable PMR for LDO L2 */
- buffer = 0x7F;
- mask = 0x7F;
- if ((ret = pm8901_read(&prev_val, 1, PM8901_PMR_7))) {
- return ret;
- }
- ret = pm8901_vreg_write(&buffer, mask, PM8901_PMR_7, prev_val);
- return ret;
+ /* Enable PMR for LDO L2 */
+ buffer = 0x7F;
+ mask = 0x7F;
+ if ((ret = pm8901_read(&prev_val, 1, PM8901_PMR_7))) {
+ return ret;
+ }
+ ret = pm8901_vreg_write(&buffer, mask, PM8901_PMR_7, prev_val);
+ return ret;
}
/* Configures the GPIO that are needed to enable LCD.
@@ -185,54 +185,54 @@
*/
static void lcd_gpio_cfg(uint8_t on)
{
- uint32_t func;
- uint32_t pull;
- uint32_t dir;
- uint32_t enable = 0; /* not used in gpio_tlmm_config */
- uint32_t drv;
- if (on) {
- func = 1; /* Configure GPIO for LCDC function */
- pull = GPIO_NO_PULL;
- dir = 1; /* doesn't matter since it is not configured as
- GPIO */
- drv = GPIO_16MA;
- } else {
- /* As discussed in the MSM8660 FFA HW SW Control Doc configure these
- GPIO as input and pull down. */
- func = 0; /* GPIO */
- pull = GPIO_PULL_DOWN;
- dir = 0; /* Input */
- drv = 0; /* does not matter configured as input */
- }
+ uint32_t func;
+ uint32_t pull;
+ uint32_t dir;
+ uint32_t enable = 0; /* not used in gpio_tlmm_config */
+ uint32_t drv;
+ if (on) {
+ func = 1; /* Configure GPIO for LCDC function */
+ pull = GPIO_NO_PULL;
+ dir = 1; /* doesn't matter since it is not configured as
+ GPIO */
+ drv = GPIO_16MA;
+ } else {
+ /* As discussed in the MSM8660 FFA HW SW Control Doc configure these
+ GPIO as input and pull down. */
+ func = 0; /* GPIO */
+ pull = GPIO_PULL_DOWN;
+ dir = 0; /* Input */
+ drv = 0; /* does not matter configured as input */
+ }
- gpio_tlmm_config(0, func, dir, pull, drv, enable); /* lcdc_pclk */
- gpio_tlmm_config(1, func, dir, pull, drv, enable); /* lcdc_hsync */
- gpio_tlmm_config(2, func, dir, pull, drv, enable); /* lcdc_vsync */
- gpio_tlmm_config(3, func, dir, pull, drv, enable); /* lcdc_den */
- gpio_tlmm_config(4, func, dir, pull, drv, enable); /* lcdc_red7 */
- gpio_tlmm_config(5, func, dir, pull, drv, enable); /* lcdc_red6 */
- gpio_tlmm_config(6, func, dir, pull, drv, enable); /* lcdc_red5 */
- gpio_tlmm_config(7, func, dir, pull, drv, enable); /* lcdc_red4 */
- gpio_tlmm_config(8, func, dir, pull, drv, enable); /* lcdc_red3 */
- gpio_tlmm_config(9, func, dir, pull, drv, enable); /* lcdc_red2 */
- gpio_tlmm_config(10, func, dir, pull, drv, enable); /* lcdc_red1 */
- gpio_tlmm_config(11, func, dir, pull, drv, enable); /* lcdc_red0 */
- gpio_tlmm_config(12, func, dir, pull, drv, enable); /* lcdc_rgn7 */
- gpio_tlmm_config(13, func, dir, pull, drv, enable); /* lcdc_rgn6 */
- gpio_tlmm_config(14, func, dir, pull, drv, enable); /* lcdc_rgn5 */
- gpio_tlmm_config(15, func, dir, pull, drv, enable); /* lcdc_rgn4 */
- gpio_tlmm_config(16, func, dir, pull, drv, enable); /* lcdc_rgn3 */
- gpio_tlmm_config(17, func, dir, pull, drv, enable); /* lcdc_rgn2 */
- gpio_tlmm_config(18, func, dir, pull, drv, enable); /* lcdc_rgn1 */
- gpio_tlmm_config(19, func, dir, pull, drv, enable); /* lcdc_rgn0 */
- gpio_tlmm_config(20, func, dir, pull, drv, enable); /* lcdc_blu7 */
- gpio_tlmm_config(21, func, dir, pull, drv, enable); /* lcdc_blu6 */
- gpio_tlmm_config(22, func, dir, pull, drv, enable); /* lcdc_blu5 */
- gpio_tlmm_config(23, func, dir, pull, drv, enable); /* lcdc_blu4 */
- gpio_tlmm_config(24, func, dir, pull, drv, enable); /* lcdc_blu3 */
- gpio_tlmm_config(25, func, dir, pull, drv, enable); /* lcdc_blu2 */
- gpio_tlmm_config(26, func, dir, pull, drv, enable); /* lcdc_blu1 */
- gpio_tlmm_config(27, func, dir, pull, drv, enable); /* lcdc_blu0 */
+ gpio_tlmm_config(0, func, dir, pull, drv, enable); /* lcdc_pclk */
+ gpio_tlmm_config(1, func, dir, pull, drv, enable); /* lcdc_hsync */
+ gpio_tlmm_config(2, func, dir, pull, drv, enable); /* lcdc_vsync */
+ gpio_tlmm_config(3, func, dir, pull, drv, enable); /* lcdc_den */
+ gpio_tlmm_config(4, func, dir, pull, drv, enable); /* lcdc_red7 */
+ gpio_tlmm_config(5, func, dir, pull, drv, enable); /* lcdc_red6 */
+ gpio_tlmm_config(6, func, dir, pull, drv, enable); /* lcdc_red5 */
+ gpio_tlmm_config(7, func, dir, pull, drv, enable); /* lcdc_red4 */
+ gpio_tlmm_config(8, func, dir, pull, drv, enable); /* lcdc_red3 */
+ gpio_tlmm_config(9, func, dir, pull, drv, enable); /* lcdc_red2 */
+ gpio_tlmm_config(10, func, dir, pull, drv, enable); /* lcdc_red1 */
+ gpio_tlmm_config(11, func, dir, pull, drv, enable); /* lcdc_red0 */
+ gpio_tlmm_config(12, func, dir, pull, drv, enable); /* lcdc_rgn7 */
+ gpio_tlmm_config(13, func, dir, pull, drv, enable); /* lcdc_rgn6 */
+ gpio_tlmm_config(14, func, dir, pull, drv, enable); /* lcdc_rgn5 */
+ gpio_tlmm_config(15, func, dir, pull, drv, enable); /* lcdc_rgn4 */
+ gpio_tlmm_config(16, func, dir, pull, drv, enable); /* lcdc_rgn3 */
+ gpio_tlmm_config(17, func, dir, pull, drv, enable); /* lcdc_rgn2 */
+ gpio_tlmm_config(18, func, dir, pull, drv, enable); /* lcdc_rgn1 */
+ gpio_tlmm_config(19, func, dir, pull, drv, enable); /* lcdc_rgn0 */
+ gpio_tlmm_config(20, func, dir, pull, drv, enable); /* lcdc_blu7 */
+ gpio_tlmm_config(21, func, dir, pull, drv, enable); /* lcdc_blu6 */
+ gpio_tlmm_config(22, func, dir, pull, drv, enable); /* lcdc_blu5 */
+ gpio_tlmm_config(23, func, dir, pull, drv, enable); /* lcdc_blu4 */
+ gpio_tlmm_config(24, func, dir, pull, drv, enable); /* lcdc_blu3 */
+ gpio_tlmm_config(25, func, dir, pull, drv, enable); /* lcdc_blu2 */
+ gpio_tlmm_config(26, func, dir, pull, drv, enable); /* lcdc_blu1 */
+ gpio_tlmm_config(27, func, dir, pull, drv, enable); /* lcdc_blu0 */
}
/* API to set backlight level configuring PWM in PM8058 */
@@ -242,133 +242,129 @@
int rc = -1;
uint32_t duty_us, period_us;
- if((bt_level <= 0) || (bt_level > 15))
- {
+ if ((bt_level <= 0) || (bt_level > 15)) {
dprintf(CRITICAL, "Error in brightness level (1-15 allowed)\n");
goto bail_out;
}
- duty_us = bt_level*PWM_DUTY_LEVEL;
+ duty_us = bt_level * PWM_DUTY_LEVEL;
period_us = PWM_PERIOD_USEC;
rc = pm_pwm_config(0, duty_us, period_us);
- if(rc)
- {
+ if (rc) {
dprintf(CRITICAL, "Error in pwm_config0\n");
goto bail_out;
}
- duty_us = PWM_PERIOD_USEC - (bt_level*PWM_DUTY_LEVEL);
+ duty_us = PWM_PERIOD_USEC - (bt_level * PWM_DUTY_LEVEL);
period_us = PWM_PERIOD_USEC;
rc = pm_pwm_config(1, duty_us, period_us);
- if(rc)
- {
+ if (rc) {
dprintf(CRITICAL, "Error in pwm_config1\n");
goto bail_out;
}
rc = pm_pwm_enable(0);
- if(rc)
- {
+ if (rc) {
dprintf(CRITICAL, "Error in pwm_enable0\n");
goto bail_out;
}
rc = pm_pwm_enable(1);
- if(rc)
+ if (rc)
dprintf(CRITICAL, "Error in pwm_enable1\n");
-bail_out:
+ bail_out:
return rc;
}
void bl_gpio_init(void)
{
/* Configure PM8058 GPIO24 as a PWM driver (LPG ch0) for chain 1 of 6 LEDs */
- pm8058_write_one(0x81, GPIO24_GPIO_CNTRL); /* Write, Bank0, VIN0, Mode
- selection enabled */
- pm8058_write_one(0x98, GPIO24_GPIO_CNTRL); /* Write, Bank1, OutOn/InOff,
- CMOS, Don't Invert Output */
- pm8058_write_one(0xAA, GPIO24_GPIO_CNTRL); /* Write, Bank2, GPIO no pull */
- pm8058_write_one(0xB4, GPIO24_GPIO_CNTRL); /* Write, Bank3, high drv
- strength */
- pm8058_write_one(0xC6, GPIO24_GPIO_CNTRL); /* Write, Bank4, Src: LPG_DRV1
- (Spec. Fnc 2) */
- pm8058_write_one(0xD8, GPIO24_GPIO_CNTRL); /* Write, Bank5, Interrupt
- polarity noninversion */
+ pm8058_write_one(0x81, GPIO24_GPIO_CNTRL); /* Write, Bank0, VIN0, Mode
+ selection enabled */
+ pm8058_write_one(0x98, GPIO24_GPIO_CNTRL); /* Write, Bank1, OutOn/InOff,
+ CMOS, Don't Invert Output */
+ pm8058_write_one(0xAA, GPIO24_GPIO_CNTRL); /* Write, Bank2, GPIO no pull */
+ pm8058_write_one(0xB4, GPIO24_GPIO_CNTRL); /* Write, Bank3, high drv
+ strength */
+ pm8058_write_one(0xC6, GPIO24_GPIO_CNTRL); /* Write, Bank4, Src: LPG_DRV1
+ (Spec. Fnc 2) */
+ pm8058_write_one(0xD8, GPIO24_GPIO_CNTRL); /* Write, Bank5, Interrupt
+ polarity noninversion */
/* Configure PM8058 GPIO25 as a PWM driver (LPG ch1) for chain 2 of 5 LEDs */
- pm8058_write_one(0x81, GPIO25_GPIO_CNTRL); /* Write, Bank0, VIN0, Mode
- selection enabled */
- pm8058_write_one(0x98, GPIO25_GPIO_CNTRL); /* Write, Bank1, OutOn/InOff,
- CMOS, Don't Invert Output */
- pm8058_write_one(0xAA, GPIO25_GPIO_CNTRL); /* Write, Bank2, GPIO no pull */
- pm8058_write_one(0xB4, GPIO25_GPIO_CNTRL); /* Write, Bank3, high drv
- strength */
- pm8058_write_one(0xC6, GPIO25_GPIO_CNTRL); /* Write, Bank4, Src: LPG_DRV2
- (Spec. Fnc 2) */
- pm8058_write_one(0xD8, GPIO25_GPIO_CNTRL); /* Write, Bank5, Interrupt
- polarity noninversion */
+ pm8058_write_one(0x81, GPIO25_GPIO_CNTRL); /* Write, Bank0, VIN0, Mode
+ selection enabled */
+ pm8058_write_one(0x98, GPIO25_GPIO_CNTRL); /* Write, Bank1, OutOn/InOff,
+ CMOS, Don't Invert Output */
+ pm8058_write_one(0xAA, GPIO25_GPIO_CNTRL); /* Write, Bank2, GPIO no pull */
+ pm8058_write_one(0xB4, GPIO25_GPIO_CNTRL); /* Write, Bank3, high drv
+ strength */
+ pm8058_write_one(0xC6, GPIO25_GPIO_CNTRL); /* Write, Bank4, Src: LPG_DRV2
+ (Spec. Fnc 2) */
+ pm8058_write_one(0xD8, GPIO25_GPIO_CNTRL); /* Write, Bank5, Interrupt
+ polarity noninversion */
}
void board_lcd_enable(void)
{
- int rc = -1;
- dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
+ int rc = -1;
+ dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
- /* Make sure dev is created and initialized properly */
- if (!dev) {
- while (1) ;
- return;
- }
+ /* Make sure dev is created and initialized properly */
+ if (!dev) {
+ while (1) ;
+ return;
+ }
- /* Store current value of these registers as to not destroy their previous
- state. */
- uint8_t open_drain_a = expander_read(GPIO_EXPANDER_REG_OPEN_DRAIN_A);
- uint8_t dir_b = expander_read(GPIO_EXPANDER_REG_DIR_B);
- uint8_t dir_a = expander_read(GPIO_EXPANDER_REG_DIR_A);
- uint8_t data_b = expander_read(GPIO_EXPANDER_REG_DATA_B);
- uint8_t data_a = expander_read(GPIO_EXPANDER_REG_DATA_A);
+ /* Store current value of these registers as to not destroy their previous
+ state. */
+ uint8_t open_drain_a = expander_read(GPIO_EXPANDER_REG_OPEN_DRAIN_A);
+ uint8_t dir_b = expander_read(GPIO_EXPANDER_REG_DIR_B);
+ uint8_t dir_a = expander_read(GPIO_EXPANDER_REG_DIR_A);
+ uint8_t data_b = expander_read(GPIO_EXPANDER_REG_DATA_B);
+ uint8_t data_a = expander_read(GPIO_EXPANDER_REG_DATA_A);
- /* Set the LVDS_SHUTDOWN_N to open drain and output low. */
- dprintf(INFO, "Enable lvds_shutdown_n line for Open Drain.\n");
- expander_write(GPIO_EXPANDER_REG_OPEN_DRAIN_A, 0x04 | open_drain_a);
+ /* Set the LVDS_SHUTDOWN_N to open drain and output low. */
+ dprintf(INFO, "Enable lvds_shutdown_n line for Open Drain.\n");
+ expander_write(GPIO_EXPANDER_REG_OPEN_DRAIN_A, 0x04 | open_drain_a);
- dprintf(INFO, "Enable lvds_shutdown_n line for output.\n");
- expander_write(GPIO_EXPANDER_REG_DIR_A, ~0x04 & dir_a);
+ dprintf(INFO, "Enable lvds_shutdown_n line for output.\n");
+ expander_write(GPIO_EXPANDER_REG_DIR_A, ~0x04 & dir_a);
- dprintf(INFO, "Drive the LVDS_SHUTDOWN_N pin high here.\n");
- expander_write(GPIO_EXPANDER_REG_DATA_A, 0x04 | data_a);
+ dprintf(INFO, "Drive the LVDS_SHUTDOWN_N pin high here.\n");
+ expander_write(GPIO_EXPANDER_REG_DATA_A, 0x04 | data_a);
- /* Turn on the VREG_L2B to 3.3V. */
+ /* Turn on the VREG_L2B to 3.3V. */
- /* Power on the appropiate PMIC LDO power rails */
- if (lcd_power_on())
- return;
+ /* Power on the appropiate PMIC LDO power rails */
+ if (lcd_power_on())
+ return;
- /* Enable the GPIO as LCDC mode LCD. */
- lcd_gpio_cfg(1);
+ /* Enable the GPIO as LCDC mode LCD. */
+ lcd_gpio_cfg(1);
- /* Arbitrary delay */
- udelay(20000);
+ /* Arbitrary delay */
+ udelay(20000);
- /* Set the GPIOs needed for backlight */
- bl_gpio_init();
- /* Set backlight level with API (to 8 by default) */
- rc = panel_set_backlight(8);
- if(rc)
- dprintf(CRITICAL,"Error in setting panel backlight\n");
+ /* Set the GPIOs needed for backlight */
+ bl_gpio_init();
+ /* Set backlight level with API (to 8 by default) */
+ rc = panel_set_backlight(8);
+ if (rc)
+ dprintf(CRITICAL, "Error in setting panel backlight\n");
- dprintf(INFO, "Enable BACKLIGHT_EN line for output.\n");
- expander_write(GPIO_EXPANDER_REG_DIR_B, ~0x10 & dir_b);
+ dprintf(INFO, "Enable BACKLIGHT_EN line for output.\n");
+ expander_write(GPIO_EXPANDER_REG_DIR_B, ~0x10 & dir_b);
- dprintf(INFO, "Drive BACKLIGHT_EN to high\n");
- expander_write(GPIO_EXPANDER_REG_DATA_B, 0x10 | data_b);
+ dprintf(INFO, "Drive BACKLIGHT_EN to high\n");
+ expander_write(GPIO_EXPANDER_REG_DATA_B, 0x10 | data_b);
}
void lcdc_on(void)
{
- board_lcd_enable();
+ board_lcd_enable();
}
void auo_board_lcd_enable(void)
@@ -388,7 +384,7 @@
expander_write(GPIO_EXPANDER_REG_DIR_A, ~0x04 & dir_a);
expander_write(GPIO_EXPANDER_REG_DATA_A, ~0x04 & data_a);
- /* Power on the appropiate PMIC LDO power rails */
+ /* Power on the appropiate PMIC LDO power rails */
if (lcd_power_on())
return;
@@ -409,12 +405,9 @@
void panel_poweron(void)
{
- if (board_machtype() == LINUX_MACHTYPE_8660_FLUID)
- {
+ if (board_machtype() == LINUX_MACHTYPE_8660_FLUID) {
auo_board_lcd_enable();
- }
- else
- {
+ } else {
panel_backlight(1);
lcdc_on();
}
@@ -422,7 +415,7 @@
struct lcdc_timing_parameters *get_lcd_timing(void)
{
- if (board_machtype() == LINUX_MACHTYPE_8660_FLUID)
+ if (board_machtype() == LINUX_MACHTYPE_8660_FLUID)
return auo_timing_param();
else
return DEFAULT_LCD_TIMING;
diff --git a/platform/msm8x60/panel_auo_wvga.c b/platform/msm8x60/panel_auo_wvga.c
old mode 100755
new mode 100644
index cb0c8b5..e6ad539
--- a/platform/msm8x60/panel_auo_wvga.c
+++ b/platform/msm8x60/panel_auo_wvga.c
@@ -52,22 +52,23 @@
/* timing info */
static struct lcdc_timing_parameters param = {
- .lcdc_fb_width = 480,
- .lcdc_fb_height = 800,
- .lcdc_hsync_pulse_width_dclk = 2,
- .lcdc_hsync_back_porch_dclk = 14,
- .lcdc_hsync_front_porch_dclk = 16,
- .lcdc_hsync_skew_dclk = 0,
+ .lcdc_fb_width = 480,
+ .lcdc_fb_height = 800,
+ .lcdc_hsync_pulse_width_dclk = 2,
+ .lcdc_hsync_back_porch_dclk = 14,
+ .lcdc_hsync_front_porch_dclk = 16,
+ .lcdc_hsync_skew_dclk = 0,
- .lcdc_vsync_pulse_width_lines = 2,
- .lcdc_vsync_back_porch_lines = 1,
- .lcdc_vsync_front_porch_lines = 28,
+ .lcdc_vsync_pulse_width_lines = 2,
+ .lcdc_vsync_back_porch_lines = 1,
+ .lcdc_vsync_front_porch_lines = 28,
};
struct lcdc_timing_parameters *auo_timing_param()
{
return ¶m;
}
+
/* spi commands */
static void auo_spi_write_byte(uint32_t data)
{
@@ -87,7 +88,7 @@
GPIO_SET_OUT_VAL(LCDC_SPI_GPIO_MOSI, 0);
}
-static uint32_t auo_serigo(uint32_t *input_data, uint32_t input_len)
+static uint32_t auo_serigo(uint32_t * input_data, uint32_t input_len)
{
uint32_t i;
@@ -104,25 +105,25 @@
return 0;
}
-static void auo_write_cmd(uint32_t cmd)
+static void auo_write_cmd(uint32_t cmd)
{
- uint32_t local_data[4];
+ uint32_t local_data[4];
local_data[0] = 0x20;
- local_data[1] = (uint32_t)(cmd >> 8);
+ local_data[1] = (uint32_t) (cmd >> 8);
local_data[2] = 0;
- local_data[3] = (uint32_t)cmd;
+ local_data[3] = (uint32_t) cmd;
auo_serigo(local_data, 4);
}
-static void auo_write_cmd_param(uint32_t cmd, uint32_t param)
+static void auo_write_cmd_param(uint32_t cmd, uint32_t param)
{
uint32_t local_data[6];
local_data[0] = 0x20;
- local_data[1] = (uint32_t)(cmd >> 8);
+ local_data[1] = (uint32_t) (cmd >> 8);
local_data[2] = 0;
- local_data[3] = (uint32_t)cmd;
+ local_data[3] = (uint32_t) cmd;
local_data[4] = 0x40;
local_data[5] = param;
auo_serigo(local_data, 6);
@@ -130,9 +131,12 @@
static void auo_spi_init(void)
{
- gpio_tlmm_config(LCDC_SPI_GPIO_CLK, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA, 1);
- gpio_tlmm_config(LCDC_SPI_GPIO_CS, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA, 1);
- gpio_tlmm_config(LCDC_SPI_GPIO_MOSI, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA, 1);
+ gpio_tlmm_config(LCDC_SPI_GPIO_CLK, 0, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_2MA, 1);
+ gpio_tlmm_config(LCDC_SPI_GPIO_CS, 0, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_2MA, 1);
+ gpio_tlmm_config(LCDC_SPI_GPIO_MOSI, 0, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_2MA, 1);
/* Set the output so that we don't disturb the slave device */
GPIO_SET_OUT_VAL(LCDC_SPI_GPIO_CLK, 1);
@@ -178,4 +182,3 @@
auo_spi_init();
auo_panel_init();
}
-
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
index 5382db2..e1d329c 100644
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -51,7 +51,6 @@
#define MB (1024*1024)
-
/* LK memory - cacheable, write through */
#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE)
@@ -68,15 +67,14 @@
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_NON_SHARED | \
MMU_MEMORY_AP_READ_WRITE)
-
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
mmu_section_t mmu_section_table[] = {
/* Physical addr, Virtual addr, Size (in MB), Flags */
- {MEMBASE, MEMBASE, (MEMSIZE/MB), LK_MEMORY},
- {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
- {SCRATCH_ADDR, SCRATCH_ADDR, 128, SCRATCH_MEMORY},
- {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ {MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
+ {SCRATCH_ADDR, SCRATCH_ADDR, 128, SCRATCH_MEMORY},
+ {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
};
#define CONVERT_ENDIAN_U32(val) \
@@ -91,147 +89,146 @@
/* Configuration Data Table */
#define CDT_MAGIC_NUMBER 0x43445400
-struct cdt_header
-{
- uint32_t magic; /* Magic number */
- uint16_t version; /* Version number */
- uint32_t reserved1;
- uint32_t reserved2;
-}__attribute__((packed));
+struct cdt_header {
+ uint32_t magic; /* Magic number */
+ uint16_t version; /* Version number */
+ uint32_t reserved1;
+ uint32_t reserved2;
+} __attribute__ ((packed));
void platform_init_timer();
-
struct fbcon_config *lcdc_init(void);
/* CRCI - mmc slot mapping.
* mmc slot numbering start from 1.
* entry at index 0 is just dummy.
*/
-uint8_t sdc_crci_map[5] = {0, 1, 4, 2, 5};
+uint8_t sdc_crci_map[5] = { 0, 1, 4, 2, 5 };
void platform_early_init(void)
{
- uart_init(target_uart_gsbi());
- qgic_init();
- platform_init_timer();
+ uart_init(target_uart_gsbi());
+ qgic_init();
+ platform_init_timer();
}
void platform_init(void)
{
- dprintf(INFO, "platform_init()\n");
+ dprintf(INFO, "platform_init()\n");
}
void display_init(void)
{
- struct fbcon_config *fb_cfg;
+ struct fbcon_config *fb_cfg;
#if DISPLAY_TYPE_LCDC
- struct lcdc_timing_parameters *lcd_timing;
- mdp_clock_init();
- if (board_machtype() == LINUX_MACHTYPE_8660_FLUID) {
- mmss_pixel_clock_configure(PIXEL_CLK_INDEX_25M);
- } else {
- mmss_pixel_clock_configure(PIXEL_CLK_INDEX_54M);
- }
- lcd_timing = get_lcd_timing();
- fb_cfg = lcdc_init_set( lcd_timing );
- fbcon_setup(fb_cfg);
- fbcon_clear();
- panel_poweron();
+ struct lcdc_timing_parameters *lcd_timing;
+ mdp_clock_init();
+ if (board_machtype() == LINUX_MACHTYPE_8660_FLUID) {
+ mmss_pixel_clock_configure(PIXEL_CLK_INDEX_25M);
+ } else {
+ mmss_pixel_clock_configure(PIXEL_CLK_INDEX_54M);
+ }
+ lcd_timing = get_lcd_timing();
+ fb_cfg = lcdc_init_set(lcd_timing);
+ fbcon_setup(fb_cfg);
+ fbcon_clear();
+ panel_poweron();
#endif
#if DISPLAY_TYPE_MIPI
- mdp_clock_init();
- configure_dsicore_dsiclk();
- configure_dsicore_byteclk();
- configure_dsicore_pclk();
+ mdp_clock_init();
+ configure_dsicore_dsiclk();
+ configure_dsicore_byteclk();
+ configure_dsicore_pclk();
- fb_cfg = mipi_init();
- fbcon_setup(fb_cfg);
+ fb_cfg = mipi_init();
+ fbcon_setup(fb_cfg);
#endif
#if DISPLAY_TYPE_HDMI
- struct hdmi_disp_mode_timing_type *hdmi_timing;
- mdp_clock_init();
- hdmi_display_init();
- hdmi_timing = hdmi_common_init_panel_info();
- fb_cfg = hdmi_dtv_init(hdmi_timing);
- fbcon_setup(fb_cfg);
+ struct hdmi_disp_mode_timing_type *hdmi_timing;
+ mdp_clock_init();
+ hdmi_display_init();
+ hdmi_timing = hdmi_common_init_panel_info();
+ fb_cfg = hdmi_dtv_init(hdmi_timing);
+ fbcon_setup(fb_cfg);
#endif
}
void display_shutdown(void)
{
#if DISPLAY_TYPE_LCDC
- /* Turning off LCDC */
- lcdc_shutdown();
+ /* Turning off LCDC */
+ lcdc_shutdown();
#endif
#if DISPLAY_TYPE_MIPI
- mipi_dsi_shutdown();
+ mipi_dsi_shutdown();
#endif
#if DISPLAY_TYPE_HDMI
- hdmi_display_shutdown();
+ hdmi_display_shutdown();
#endif
}
-static struct qup_i2c_dev* dev = NULL;
+static struct qup_i2c_dev *dev = NULL;
-uint32_t eprom_read (uint16_t addr, uint8_t count) {
- uint32_t ret = 0;
- if(!dev){
- return ret;
- }
- /* Create a i2c_msg buffer, that is used to put the controller into
- * read mode and then to read some data.
- */
- struct i2c_msg msg_buf[] = {
- {EEPROM_I2C_ADDRESS, I2C_M_WR, 2, &addr},
- {EEPROM_I2C_ADDRESS, I2C_M_RD, count, &ret}
- };
+uint32_t eprom_read(uint16_t addr, uint8_t count)
+{
+ uint32_t ret = 0;
+ if (!dev) {
+ return ret;
+ }
+ /* Create a i2c_msg buffer, that is used to put the controller into
+ * read mode and then to read some data.
+ */
+ struct i2c_msg msg_buf[] = {
+ {EEPROM_I2C_ADDRESS, I2C_M_WR, 2, &addr},
+ {EEPROM_I2C_ADDRESS, I2C_M_RD, count, &ret}
+ };
- qup_i2c_xfer(dev, msg_buf, 2);
- return ret;
+ qup_i2c_xfer(dev, msg_buf, 2);
+ return ret;
}
/* Read EEPROM to find out product id. Return 0 in case of failure */
-uint32_t platform_id_read (void)
+uint32_t platform_id_read(void)
{
- uint32_t id = 0;
- uint16_t offset = 0;
- dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
- if(!dev){
- return id;
- }
- /* Check if EPROM is valid */
- if (CONVERT_ENDIAN_U32(eprom_read(0, 4)) == CDT_MAGIC_NUMBER)
- {
- /* Get offset for platform ID info from Meta Data block 0 */
- offset = eprom_read(CONVERT_ENDIAN_U16(0 +
- sizeof(struct cdt_header)), 2);
- /* Read platform ID */
- id = eprom_read(CONVERT_ENDIAN_U16(offset), 4);
- id = CONVERT_ENDIAN_U32(id);
- id = (id & 0x00FF0000) >> 16;
- }
- return id;
+ uint32_t id = 0;
+ uint16_t offset = 0;
+ dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
+ if (!dev) {
+ return id;
+ }
+ /* Check if EPROM is valid */
+ if (CONVERT_ENDIAN_U32(eprom_read(0, 4)) == CDT_MAGIC_NUMBER) {
+ /* Get offset for platform ID info from Meta Data block 0 */
+ offset = eprom_read(CONVERT_ENDIAN_U16(0 +
+ sizeof(struct
+ cdt_header)), 2);
+ /* Read platform ID */
+ id = eprom_read(CONVERT_ENDIAN_U16(offset), 4);
+ id = CONVERT_ENDIAN_U32(id);
+ id = (id & 0x00FF0000) >> 16;
+ }
+ return id;
}
/* Setup memory for this platform */
void platform_init_mmu_mappings(void)
{
- uint32_t i;
- uint32_t sections;
- uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- for (i = 0; i < table_size; i++)
- {
- sections = mmu_section_table[i].num_of_sections;
+ for (i = 0; i < table_size; i++) {
+ sections = mmu_section_table[i].num_of_sections;
- while (sections--)
- {
- arm_mmu_map_section(mmu_section_table[i].paddress + sections*MB,
- mmu_section_table[i].vaddress + sections*MB,
- mmu_section_table[i].flags);
- }
- }
+ while (sections--) {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
}
/* Do any platform specific cleanup just before kernel entry */
@@ -261,7 +258,7 @@
*/
writel(3, DGT_CLK_CTL);
- ticks_per_sec = 6750000; /* (27 MHz / 4) */
+ ticks_per_sec = 6750000; /* (27 MHz / 4) */
}
/* Returns timer ticks per sec */
diff --git a/platform/msm8x60/pmic.c b/platform/msm8x60/pmic.c
old mode 100755
new mode 100644
index 8d9a886..6e5c83f
--- a/platform/msm8x60/pmic.c
+++ b/platform/msm8x60/pmic.c
@@ -89,72 +89,68 @@
#define PM8058_HDMI_L16_CTRL 0x08A
typedef int (*pm8058_write_func) (unsigned char *, unsigned short,
- unsigned short);
+ unsigned short);
extern int pa1_ssbi2_write_bytes(unsigned char *buffer, unsigned short length,
- unsigned short slave_addr);
+ unsigned short slave_addr);
extern int pa1_ssbi2_read_bytes(unsigned char *buffer, unsigned short length,
- unsigned short slave_addr);
+ unsigned short slave_addr);
extern int pa2_ssbi2_write_bytes(unsigned char *buffer, unsigned short length,
- unsigned short slave_addr);
+ unsigned short slave_addr);
extern int pa2_ssbi2_read_bytes(unsigned char *buffer, unsigned short length,
- unsigned short slave_addr);
+ unsigned short slave_addr);
/* PM8058 APIs */
-int pm8058_write(uint16_t addr, uint8_t *data, uint16_t length)
+int pm8058_write(uint16_t addr, uint8_t * data, uint16_t length)
{
- return pa1_ssbi2_write_bytes(data, length, addr);
+ return pa1_ssbi2_write_bytes(data, length, addr);
}
-int pm8058_read(uint16_t addr, uint8_t *data, uint16_t length)
+int pm8058_read(uint16_t addr, uint8_t * data, uint16_t length)
{
- return pa1_ssbi2_read_bytes(data, length, addr);
+ return pa1_ssbi2_read_bytes(data, length, addr);
}
void pm8058_write_one(unsigned data, unsigned address)
{
- pm8058_write_func wr_function = &pa1_ssbi2_write_bytes;
- if (wr_function == NULL)
- return;
- if ((*wr_function) (&data, 1, address))
- dprintf(CRITICAL, "Error in initializing register\n");
+ pm8058_write_func wr_function = &pa1_ssbi2_write_bytes;
+ if (wr_function == NULL)
+ return;
+ if ((*wr_function) (&data, 1, address))
+ dprintf(CRITICAL, "Error in initializing register\n");
}
-int pm8058_get_irq_status( pm_irq_id_type irq, bool *rt_status)
+int pm8058_get_irq_status(pm_irq_id_type irq, bool * rt_status)
{
- unsigned block_index, reg_data, reg_mask;
- int errFlag;
+ unsigned block_index, reg_data, reg_mask;
+ int errFlag;
- block_index = PM_IRQ_ID_TO_BLOCK_INDEX(irq);
+ block_index = PM_IRQ_ID_TO_BLOCK_INDEX(irq);
- /* select the irq block */
- errFlag =pa1_ssbi2_write_bytes(&block_index,1,IRQ_BLOCK_SEL_USR_ADDR);
- if(errFlag)
- {
- dprintf(INFO,"Device Timeout");
- return 1;
- }
+ /* select the irq block */
+ errFlag =
+ pa1_ssbi2_write_bytes(&block_index, 1, IRQ_BLOCK_SEL_USR_ADDR);
+ if (errFlag) {
+ dprintf(INFO, "Device Timeout");
+ return 1;
+ }
- /* read real time status */
- errFlag =pa1_ssbi2_read_bytes(®_data,1,IRQ_STATUS_RT_USR_ADDR);
- if(errFlag)
- {
- dprintf(INFO,"Device Timeout");
- return 1;
- }
- reg_mask = PM_IRQ_ID_TO_BIT_MASK(irq);
+ /* read real time status */
+ errFlag = pa1_ssbi2_read_bytes(®_data, 1, IRQ_STATUS_RT_USR_ADDR);
+ if (errFlag) {
+ dprintf(INFO, "Device Timeout");
+ return 1;
+ }
+ reg_mask = PM_IRQ_ID_TO_BIT_MASK(irq);
- if ((reg_data & reg_mask) == reg_mask )
- {
- /* The RT Status is high. */
- *rt_status = TRUE;
- }
- else
- {
- /* The RT Status is low. */
- *rt_status = FALSE;
- }
- return 0;
+ if ((reg_data & reg_mask) == reg_mask) {
+ /* The RT Status is high. */
+ *rt_status = TRUE;
+ } else {
+ /* The RT Status is low. */
+ *rt_status = FALSE;
+ }
+ return 0;
}
bool pm8058_gpio_get(unsigned int gpio)
@@ -166,14 +162,13 @@
gpio_irq = gpio + PM_GPIO01_CHGED_ST_IRQ_ID;
ret = pm8058_get_irq_status(gpio_irq, &status);
- if(ret)
- dprintf(CRITICAL,"pm8058_gpio_get failed\n");
+ if (ret)
+ dprintf(CRITICAL, "pm8058_gpio_get failed\n");
return status;
}
-int pm8058_mwrite(uint16_t addr, uint8_t val, uint8_t mask,
- uint8_t *reg_save)
+int pm8058_mwrite(uint16_t addr, uint8_t val, uint8_t mask, uint8_t * reg_save)
{
int rc = 0;
uint8_t reg;
@@ -182,7 +177,8 @@
if (reg != *reg_save)
rc = pm8058_write(addr, ®, 1);
if (rc)
- dprintf(CRITICAL,"pm8058_write failed; addr=%03X, rc=%d\n", addr, rc);
+ dprintf(CRITICAL, "pm8058_write failed; addr=%03X, rc=%d\n",
+ addr, rc);
else
*reg_save = reg;
return rc;
@@ -192,9 +188,10 @@
{
int ret = 0;
unsigned vprog = 0x00000110;
- ret = pm8058_mwrite(PM8058_HDMI_L16_CTRL,vprog,LDO_CTRL_VPROG_MASK,0);
- if(ret) {
- dprintf(SPEW,"Failed to set voltage for l16 regulator\n");
+ ret =
+ pm8058_mwrite(PM8058_HDMI_L16_CTRL, vprog, LDO_CTRL_VPROG_MASK, 0);
+ if (ret) {
+ dprintf(SPEW, "Failed to set voltage for l16 regulator\n");
}
return ret;
}
@@ -202,9 +199,11 @@
int pm8058_vreg_enable()
{
int ret = 0;
- ret = pm8058_mwrite(PM8058_HDMI_L16_CTRL,REGULATOR_EN_MASK,REGULATOR_EN_MASK,0);
- if(ret) {
- dprintf(SPEW,"Vreg enable failed for PM 8058\n");
+ ret =
+ pm8058_mwrite(PM8058_HDMI_L16_CTRL, REGULATOR_EN_MASK,
+ REGULATOR_EN_MASK, 0);
+ if (ret) {
+ dprintf(SPEW, "Vreg enable failed for PM 8058\n");
}
return ret;
}
@@ -217,7 +216,7 @@
*/
int pm8901_write(uint8_t * buffer, uint32_t length, uint32_t slave_addr)
{
- return pa2_ssbi2_write_bytes(buffer, length, slave_addr);
+ return pa2_ssbi2_write_bytes(buffer, length, slave_addr);
}
/*
@@ -226,7 +225,7 @@
*/
int pm8901_read(uint8_t * buffer, uint32_t length, uint32_t slave_addr)
{
- return pa2_ssbi2_read_bytes(buffer, length, slave_addr);
+ return pa2_ssbi2_read_bytes(buffer, length, slave_addr);
}
/*
@@ -234,28 +233,28 @@
*/
int pm8901_test_bank_read(uint8_t * buffer, uint8_t bank, uint16_t addr)
{
- int ret = pm8901_write(&bank, 1, addr);
- /* if the write does not work we can't read. */
- if (ret) {
- return ret;
- }
+ int ret = pm8901_write(&bank, 1, addr);
+ /* if the write does not work we can't read. */
+ if (ret) {
+ return ret;
+ }
- return pm8901_read(buffer, 1, addr);
+ return pm8901_read(buffer, 1, addr);
}
/*
* PMIC 8901 LDO vreg write.
*/
int pm8901_vreg_write(uint8_t * buffer, uint8_t mask, uint16_t addr,
- uint8_t prev_val)
+ uint8_t prev_val)
{
- uint8_t reg;
+ uint8_t reg;
- /* Clear the bits we want to try and set. */
- reg = (prev_val & ~mask);
- /* Set the bits we want to set, before writing them to addr */
- reg |= (*buffer & mask);
- return pm8901_write(®, 1, addr);
+ /* Clear the bits we want to try and set. */
+ reg = (prev_val & ~mask);
+ /* Set the bits we want to set, before writing them to addr */
+ reg |= (*buffer & mask);
+ return pm8901_write(®, 1, addr);
}
int pm8901_reset_pwr_off(int reset)
@@ -287,7 +286,7 @@
}
}
-get_out:
+ get_out:
return rc;
}
@@ -309,7 +308,7 @@
if (rc) {
}
-get_out3:
+ get_out3:
if (!reset) {
/* Only modify the SLEEP_CNTL reg if shutdown is desired. */
rc = pm8058_read(SSBI_REG_ADDR_SLEEP_CNTL, &smpl, 1);
@@ -321,12 +320,11 @@
smpl |= PM8058_SLEEP_SMPL_EN_PWR_OFF;
rc = pm8058_write(SSBI_REG_ADDR_SLEEP_CNTL, &smpl, 1);
- if (rc)
- {
+ if (rc) {
}
}
-get_out2:
+ get_out2:
rc = pm8058_read(SSBI_REG_ADDR_PON_CNTL_1, &pon, 1);
if (rc) {
goto get_out;
@@ -343,7 +341,7 @@
goto get_out;
}
-get_out:
+ get_out:
return rc;
}
@@ -353,8 +351,7 @@
uint8_t reg;
rc = pm8058_read(PM8058_RTC_CTRL, ®, 1);
- if (rc)
- {
+ if (rc) {
return rc;
}
reg = (reg & ~PM8058_RTC_ALARM_ENABLE);
@@ -369,17 +366,17 @@
int pm8901_mpp_enable()
{
- uint8_t prevval= 0x0;
+ uint8_t prevval = 0x0;
uint16_t mask;
uint8_t conf;
int ret = 0;
conf = PM8901_MPP0_CTRL_VAL;
mask = PM8901_MPP_TYPE_MASK | PM8901_MPP_CONFIG_LVL_MASK |
- PM8901_MPP_CONFIG_CTL_MASK;
+ PM8901_MPP_CONFIG_CTL_MASK;
- if (ret = pm8901_vreg_write(&conf,mask,SSBI_MPP_CNTRL(0),prevval)) {
- dprintf(SPEW,"PM8901 MPP failed\n");
+ if (ret = pm8901_vreg_write(&conf, mask, SSBI_MPP_CNTRL(0), prevval)) {
+ dprintf(SPEW, "PM8901 MPP failed\n");
}
return ret;
}
@@ -387,17 +384,23 @@
int pm8901_vs_enable()
{
uint8_t val = VREG_PMR_STATE_HPM;
- int prevval=0x0;
+ int prevval = 0x0;
int ret = 0;
- if (ret = pm8901_vreg_write(&val,VREG_PMR_STATE_HPM,PM8901_HDMI_MVS_PMR,prevval)) {
- dprintf(SPEW,"pm8901_vreg_write failed for MVS PMR register\n");
+ if (ret =
+ pm8901_vreg_write(&val, VREG_PMR_STATE_HPM, PM8901_HDMI_MVS_PMR,
+ prevval)) {
+ dprintf(SPEW,
+ "pm8901_vreg_write failed for MVS PMR register\n");
return ret;
}
val = VS_CTRL_USE_PMR;
- if (ret = pm8901_vreg_write(&val,VS_CTRL_ENABLE_MASK,PM8901_HDMI_MVS_CTRL,prevval)) {
- dprintf(SPEW,"pm8901_vreg_write failed for MVS ctrl register\n");
+ if (ret =
+ pm8901_vreg_write(&val, VS_CTRL_ENABLE_MASK, PM8901_HDMI_MVS_CTRL,
+ prevval)) {
+ dprintf(SPEW,
+ "pm8901_vreg_write failed for MVS ctrl register\n");
return ret;
}
return ret;
diff --git a/platform/msm8x60/pmic_batt_alarm.c b/platform/msm8x60/pmic_batt_alarm.c
index a3bd93b..884d589 100644
--- a/platform/msm8x60/pmic_batt_alarm.c
+++ b/platform/msm8x60/pmic_batt_alarm.c
@@ -37,14 +37,15 @@
*/
static int pm_batt_alarm_threshold_set(uint32_t lower_threshold_mV,
- uint32_t upper_threshold_mV)
+ uint32_t upper_threshold_mV)
{
uint32_t step, fine_step, rc = -1;
uint8_t reg_threshold = 0, reg_ctrl2 = 0;
if (lower_threshold_mV < THRESHOLD_MIN_MV
|| lower_threshold_mV > THRESHOLD_MAX_MV) {
- dprintf(CRITICAL,"lower threshold value, %d mV, is outside of allowable "
+ dprintf(CRITICAL,
+ "lower threshold value, %d mV, is outside of allowable "
"range: [%d, %d] mV\n", lower_threshold_mV,
THRESHOLD_MIN_MV, THRESHOLD_MAX_MV);
goto bail;
@@ -52,14 +53,16 @@
if (upper_threshold_mV < THRESHOLD_MIN_MV
|| upper_threshold_mV > THRESHOLD_MAX_MV) {
- dprintf(CRITICAL,"upper threshold value, %d mV, is outside of allowable "
+ dprintf(CRITICAL,
+ "upper threshold value, %d mV, is outside of allowable "
"range: [%d, %d] mV\n", upper_threshold_mV,
THRESHOLD_MIN_MV, THRESHOLD_MAX_MV);
goto bail;
}
if (upper_threshold_mV < lower_threshold_mV) {
- dprintf(CRITICAL,"lower threshold value, %d mV, must be <= upper "
+ dprintf(CRITICAL,
+ "lower threshold value, %d mV, must be <= upper "
"threshold value, %d mV\n", lower_threshold_mV,
upper_threshold_mV);
goto bail;
@@ -71,7 +74,7 @@
reg_ctrl2 |= CTRL2_RANGE_EXT_LOWER_MASK;
step = (lower_threshold_mV - THRESHOLD_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
/* Extended low range is for steps 0 to 2 */
@@ -82,7 +85,7 @@
reg_ctrl2 |= CTRL2_RANGE_EXT_LOWER_MASK;
step = (lower_threshold_mV - THRESHOLD_EXT_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
/* Extended high range is for steps 3 to 15 */
@@ -91,7 +94,7 @@
} else {
/* Basic range */
step = (lower_threshold_mV - THRESHOLD_BASIC_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
step >>= 2;
@@ -107,7 +110,7 @@
reg_ctrl2 |= CTRL2_RANGE_EXT_UPPER_MASK;
step = (upper_threshold_mV - THRESHOLD_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
/* Extended low range is for steps 0 to 2 */
@@ -118,7 +121,7 @@
reg_ctrl2 |= CTRL2_RANGE_EXT_UPPER_MASK;
step = (upper_threshold_mV - THRESHOLD_EXT_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
/* Extended high range is for steps 3 to 15 */
@@ -127,7 +130,7 @@
} else {
/* Basic range */
step = (upper_threshold_mV - THRESHOLD_BASIC_MIN_MV)
- / THRESHOLD_STEP_MV;
+ / THRESHOLD_STEP_MV;
fine_step = step & 0x3;
step >>= 2;
@@ -138,22 +141,23 @@
reg_ctrl2 |= (fine_step << CTRL2_FINE_STEP_UPPER_SHIFT);
rc = pm8058_mwrite(PM8058_REG_THRESHOLD, reg_threshold,
- THRESHOLD_LOWER_MASK | THRESHOLD_UPPER_MASK,
- &battdev.reg_threshold);
+ THRESHOLD_LOWER_MASK | THRESHOLD_UPPER_MASK,
+ &battdev.reg_threshold);
if (rc) {
dprintf(CRITICAL, "Error in pm8058_mwrite THRESHOLD\n");
goto bail;
}
rc = pm8058_mwrite(PM8058_REG_CTRL2, reg_ctrl2,
- CTRL2_FINE_STEP_LOWER_MASK | CTRL2_FINE_STEP_UPPER_MASK
- | CTRL2_RANGE_EXT_LOWER_MASK | CTRL2_RANGE_EXT_UPPER_MASK,
- &battdev.reg_ctrl2);
+ CTRL2_FINE_STEP_LOWER_MASK |
+ CTRL2_FINE_STEP_UPPER_MASK |
+ CTRL2_RANGE_EXT_LOWER_MASK |
+ CTRL2_RANGE_EXT_UPPER_MASK, &battdev.reg_ctrl2);
if (rc)
dprintf(CRITICAL, "Error in pm8058_mwrite CTRL2\n");
-bail:
+ bail:
return rc;
}
@@ -166,10 +170,10 @@
int rc = -1;
uint8_t reg_ctrl1 = 0;
- if (hold_time < CTRL1_HOLD_TIME_MIN
- || hold_time > CTRL1_HOLD_TIME_MAX) {
+ if (hold_time < CTRL1_HOLD_TIME_MIN || hold_time > CTRL1_HOLD_TIME_MAX) {
- dprintf(CRITICAL,"hold time, %d, is outside of allowable range: "
+ dprintf(CRITICAL,
+ "hold time, %d, is outside of allowable range: "
"[%d, %d]\n", hold_time, CTRL1_HOLD_TIME_MIN,
CTRL1_HOLD_TIME_MAX);
goto bail;
@@ -178,12 +182,12 @@
reg_ctrl1 = hold_time << CTRL1_HOLD_TIME_SHIFT;
rc = pm8058_mwrite(PM8058_REG_CTRL1, reg_ctrl1,
- CTRL1_HOLD_TIME_MASK, &battdev.reg_ctrl1);
+ CTRL1_HOLD_TIME_MASK, &battdev.reg_ctrl1);
- if(rc)
+ if (rc)
dprintf(CRITICAL, "Error in pm8058_mwrite CTRL1\n");
-bail:
+ bail:
return rc;
}
@@ -192,41 +196,43 @@
*/
static int pm_batt_alarm_pwm_rate_set(pm_batt_alarm_pwm_ctrl pwm_ctrl_select,
- uint32_t clock_scaler, uint32_t clock_divider)
+ uint32_t clock_scaler,
+ uint32_t clock_divider)
{
int rc = -1;
uint8_t reg_pwm_ctrl = 0, mask = 0;
- if(pwm_ctrl_select == ALARM_EN_PWM) {
+ if (pwm_ctrl_select == ALARM_EN_PWM) {
if (clock_scaler < PWM_CTRL_PRE_INPUT_MIN
- || clock_scaler > PWM_CTRL_PRE_INPUT_MAX) {
- dprintf(CRITICAL,"PWM clock scaler, %d, is outside of allowable range: "
- "[%d, %d]\n", clock_scaler, PWM_CTRL_PRE_INPUT_MIN,
- PWM_CTRL_PRE_INPUT_MAX);
+ || clock_scaler > PWM_CTRL_PRE_INPUT_MAX) {
+ dprintf(CRITICAL,
+ "PWM clock scaler, %d, is outside of allowable range: "
+ "[%d, %d]\n", clock_scaler,
+ PWM_CTRL_PRE_INPUT_MIN, PWM_CTRL_PRE_INPUT_MAX);
goto bail;
}
if (clock_divider < PWM_CTRL_DIV_INPUT_MIN
- || clock_divider > PWM_CTRL_DIV_INPUT_MAX) {
- dprintf(CRITICAL,"PWM clock divider, %d, is outside of allowable range: "
- "[%d, %d]\n", clock_divider, PWM_CTRL_DIV_INPUT_MIN,
- PWM_CTRL_DIV_INPUT_MAX);
+ || clock_divider > PWM_CTRL_DIV_INPUT_MAX) {
+ dprintf(CRITICAL,
+ "PWM clock divider, %d, is outside of allowable range: "
+ "[%d, %d]\n", clock_divider,
+ PWM_CTRL_DIV_INPUT_MIN, PWM_CTRL_DIV_INPUT_MAX);
goto bail;
}
/* Use PWM control. */
reg_pwm_ctrl = PWM_CTRL_ALARM_EN_PWM;
mask = PWM_CTRL_ALARM_EN_MASK | PWM_CTRL_PRE_MASK
- | PWM_CTRL_DIV_MASK;
+ | PWM_CTRL_DIV_MASK;
clock_scaler -= PWM_CTRL_PRE_INPUT_MIN - PWM_CTRL_PRE_MIN;
clock_divider -= PWM_CTRL_DIV_INPUT_MIN - PWM_CTRL_DIV_MIN;
reg_pwm_ctrl |= (clock_scaler << PWM_CTRL_PRE_SHIFT);
reg_pwm_ctrl |= (clock_divider << PWM_CTRL_DIV_SHIFT);
- }
- else {
- if(pwm_ctrl_select == ALARM_EN_ALWAYS) {
+ } else {
+ if (pwm_ctrl_select == ALARM_EN_ALWAYS) {
reg_pwm_ctrl = PWM_CTRL_ALARM_EN_ALWAYS;
} else if (pwm_ctrl_select == ALARM_EN_NEVER) {
reg_pwm_ctrl = PWM_CTRL_ALARM_EN_NEVER;
@@ -236,12 +242,12 @@
}
rc = pm8058_mwrite(PM8058_REG_PWM_CTRL, reg_pwm_ctrl,
- mask, &battdev.reg_pwm_ctrl);
+ mask, &battdev.reg_pwm_ctrl);
- if(rc)
+ if (rc)
dprintf(CRITICAL, "Error in pm8058_mwrite PWM_CTRL\n");
-bail:
+ bail:
return rc;
}
@@ -250,7 +256,7 @@
*/
static int pm_batt_alarm_state_set(uint8_t enable_lower_comparator,
- uint8_t enable_upper_comparator)
+ uint8_t enable_upper_comparator)
{
int rc = -1;
uint8_t reg_ctrl1 = 0, reg_ctrl2 = 0;
@@ -264,20 +270,20 @@
reg_ctrl1 = CTRL1_BATT_ALARM_EN_MASK;
rc = pm8058_mwrite(PM8058_REG_CTRL1, reg_ctrl1,
- CTRL1_BATT_ALARM_EN_MASK, &battdev.reg_ctrl1);
+ CTRL1_BATT_ALARM_EN_MASK, &battdev.reg_ctrl1);
if (rc) {
dprintf(CRITICAL, "Error in pm8058_mwrite CTRL1\n");
goto bail;
}
rc = pm8058_mwrite(PM8058_REG_CTRL2, reg_ctrl2,
- CTRL2_COMP_LOWER_DISABLE_MASK | CTRL2_COMP_UPPER_DISABLE_MASK,
- &battdev.reg_ctrl2);
+ CTRL2_COMP_LOWER_DISABLE_MASK |
+ CTRL2_COMP_UPPER_DISABLE_MASK, &battdev.reg_ctrl2);
if (rc)
dprintf(CRITICAL, "Error in pm8058_mwrite CTRL2\n");
-bail:
+ bail:
return rc;
}
@@ -285,7 +291,7 @@
* Function to read alarm status for battery alarm
*/
-int pm_batt_alarm_status_read(uint8_t *status)
+int pm_batt_alarm_status_read(uint8_t * status)
{
int rc = -1;
@@ -296,29 +302,29 @@
}
*status = ((battdev.reg_ctrl1 & CTRL1_STATUS_LOWER_MASK)
- ? PM_BATT_ALARM_STATUS_BELOW_LOWER : 0)
- | ((battdev.reg_ctrl1 & CTRL1_STATUS_UPPER_MASK)
- ? PM_BATT_ALARM_STATUS_ABOVE_UPPER : 0);
+ ? PM_BATT_ALARM_STATUS_BELOW_LOWER : 0)
+ | ((battdev.reg_ctrl1 & CTRL1_STATUS_UPPER_MASK)
+ ? PM_BATT_ALARM_STATUS_ABOVE_UPPER : 0);
/* Disabling Battery alarm below just for power savings. This can be
* removed if this does not matter
*/
/* After reading, disabling the comparators and BATT_ALARM_EN */
- rc = pm_batt_alarm_state_set(LOWER_COMP_DISABLE,UPPER_COMP_DISABLE);
+ rc = pm_batt_alarm_state_set(LOWER_COMP_DISABLE, UPPER_COMP_DISABLE);
if (rc) {
- dprintf(CRITICAL,"state_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "state_set failed, rc=%d\n", rc);
goto bail;
}
rc = pm_batt_alarm_pwm_rate_set(ALARM_EN_NEVER, DEFAULT_PWM_SCALER,
- DEFAULT_PWM_DIVIDER);
+ DEFAULT_PWM_DIVIDER);
if (rc) {
- dprintf(CRITICAL,"state_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "state_set failed, rc=%d\n", rc);
goto bail;
}
-bail:
+ bail:
return rc;
}
@@ -330,28 +336,29 @@
{
int rc = -1;
- if(battdev)
- {
- rc = pm8058_read(PM8058_REG_THRESHOLD, &battdev->reg_threshold, 1);
- if(rc)
+ if (battdev) {
+ rc = pm8058_read(PM8058_REG_THRESHOLD, &battdev->reg_threshold,
+ 1);
+ if (rc)
goto done;
rc = pm8058_read(PM8058_REG_CTRL1, &battdev->reg_ctrl1, 1);
- if(rc)
+ if (rc)
goto done;
rc = pm8058_read(PM8058_REG_CTRL2, &battdev->reg_ctrl2, 1);
- if(rc)
+ if (rc)
goto done;
- rc = pm8058_read(PM8058_REG_PWM_CTRL, &battdev->reg_pwm_ctrl, 1);
- if(rc)
+ rc = pm8058_read(PM8058_REG_PWM_CTRL, &battdev->reg_pwm_ctrl,
+ 1);
+ if (rc)
goto done;
}
-done:
- if(rc)
- dprintf(CRITICAL,"pm_batt_alarm_read_regs read error\n");
+ done:
+ if (rc)
+ dprintf(CRITICAL, "pm_batt_alarm_read_regs read error\n");
return rc;
}
@@ -365,35 +372,35 @@
rc = pm_batt_alarm_read_regs(&battdev);
if (rc) {
- dprintf(CRITICAL,"read_regs failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "read_regs failed, rc=%d\n", rc);
goto bail;
}
rc = pm_batt_alarm_threshold_set(DEFAULT_THRESHOLD_LOWER,
- DEFAULT_THRESHOLD_UPPER);
+ DEFAULT_THRESHOLD_UPPER);
if (rc) {
- dprintf(CRITICAL,"threshold_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "threshold_set failed, rc=%d\n", rc);
goto bail;
}
rc = pm_batt_alarm_hold_time_set(DEFAULT_HOLD_TIME);
if (rc) {
- dprintf(CRITICAL,"hold_time_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "hold_time_set failed, rc=%d\n", rc);
goto bail;
}
rc = pm_batt_alarm_pwm_rate_set(ALARM_EN_NEVER, DEFAULT_PWM_SCALER,
- DEFAULT_PWM_DIVIDER);
+ DEFAULT_PWM_DIVIDER);
if (rc) {
- dprintf(CRITICAL,"pwm_rate_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "pwm_rate_set failed, rc=%d\n", rc);
goto bail;
}
- rc = pm_batt_alarm_state_set(LOWER_COMP_DISABLE,UPPER_COMP_DISABLE);
+ rc = pm_batt_alarm_state_set(LOWER_COMP_DISABLE, UPPER_COMP_DISABLE);
if (rc)
- dprintf(CRITICAL,"state_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "state_set failed, rc=%d\n", rc);
-bail:
+ bail:
return rc;
}
@@ -401,28 +408,29 @@
* Function to configure voltages and change alarm state
*/
-int pm_batt_alarm_set_voltage(uint32_t lower_threshold, uint32_t upper_threshold)
+int pm_batt_alarm_set_voltage(uint32_t lower_threshold,
+ uint32_t upper_threshold)
{
int rc = -1;
- rc = pm_batt_alarm_threshold_set(lower_threshold,upper_threshold);
+ rc = pm_batt_alarm_threshold_set(lower_threshold, upper_threshold);
if (rc) {
- dprintf(CRITICAL,"threshold_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "threshold_set failed, rc=%d\n", rc);
goto bail;
}
rc = pm_batt_alarm_pwm_rate_set(ALARM_EN_ALWAYS, DEFAULT_PWM_SCALER,
- DEFAULT_PWM_DIVIDER);
+ DEFAULT_PWM_DIVIDER);
if (rc) {
- dprintf(CRITICAL,"pwm_rate_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "pwm_rate_set failed, rc=%d\n", rc);
goto bail;
}
- rc = pm_batt_alarm_state_set(LOWER_COMP_ENABLE,UPPER_COMP_ENABLE);
+ rc = pm_batt_alarm_state_set(LOWER_COMP_ENABLE, UPPER_COMP_ENABLE);
if (rc)
- dprintf(CRITICAL,"state_set failed, rc=%d\n", rc);
+ dprintf(CRITICAL, "state_set failed, rc=%d\n", rc);
-bail:
+ bail:
return rc;
}
@@ -436,23 +444,23 @@
uint8_t batt_status = 0;
rc = pm_batt_alarm_init();
- if(rc)
- dprintf(CRITICAL,"pm_batt_alarm_init error\n");
+ if (rc)
+ dprintf(CRITICAL, "pm_batt_alarm_init error\n");
/* wait till hold time */
mdelay(16);
/* 0xe74-> 3700mV, 0x1004-> 4100mv */
rc = pm_batt_alarm_set_voltage(0xe74, 0x1004);
- if(rc)
- dprintf(CRITICAL,"pm_batt_alarm_set_voltage error\n");
+ if (rc)
+ dprintf(CRITICAL, "pm_batt_alarm_set_voltage error\n");
/* wait till hold time */
mdelay(16);
rc = pm_batt_alarm_status_read(&batt_status);
- if(rc)
- dprintf(CRITICAL,"pm_batt_alarm_status_read error\n");
+ if (rc)
+ dprintf(CRITICAL, "pm_batt_alarm_status_read error\n");
else
- dprintf(ALWAYS,"batt status: %d\n",batt_status);
+ dprintf(ALWAYS, "batt status: %d\n", batt_status);
}
diff --git a/platform/msm8x60/pmic_pwm.c b/platform/msm8x60/pmic_pwm.c
index 4847612..5e5cc2f 100644
--- a/platform/msm8x60/pmic_pwm.c
+++ b/platform/msm8x60/pmic_pwm.c
@@ -40,18 +40,18 @@
};
static unsigned int pt_t[NUM_PRE_DIVIDE][NUM_CLOCKS] = {
- { PRE_DIVIDE_0 * NSEC_1000HZ,
- PRE_DIVIDE_0 * NSEC_32768HZ,
- PRE_DIVIDE_0 * NSEC_19P2MHZ,
- },
- { PRE_DIVIDE_1 * NSEC_1000HZ,
- PRE_DIVIDE_1 * NSEC_32768HZ,
- PRE_DIVIDE_1 * NSEC_19P2MHZ,
- },
- { PRE_DIVIDE_2 * NSEC_1000HZ,
- PRE_DIVIDE_2 * NSEC_32768HZ,
- PRE_DIVIDE_2 * NSEC_19P2MHZ,
- },
+ {PRE_DIVIDE_0 * NSEC_1000HZ,
+ PRE_DIVIDE_0 * NSEC_32768HZ,
+ PRE_DIVIDE_0 * NSEC_19P2MHZ,
+ },
+ {PRE_DIVIDE_1 * NSEC_1000HZ,
+ PRE_DIVIDE_1 * NSEC_32768HZ,
+ PRE_DIVIDE_1 * NSEC_19P2MHZ,
+ },
+ {PRE_DIVIDE_2 * NSEC_1000HZ,
+ PRE_DIVIDE_2 * NSEC_32768HZ,
+ PRE_DIVIDE_2 * NSEC_19P2MHZ,
+ },
};
static uint16_t duty_msec[PM_PWM_1KHZ_COUNT_MAX + 1] = {
@@ -70,7 +70,7 @@
/* Function to get the PWM size, divider, clock for the given period */
static void pm_pwm_calc_period(uint32_t period_us,
- struct pm_pwm_config *pwm_conf)
+ struct pm_pwm_config *pwm_conf)
{
int n, m, clk, div;
int best_m, best_div, best_clk;
@@ -100,11 +100,14 @@
if (tmp_p <= pt_t[div][clk]) {
/* Found local best */
if (!m) {
- better_err = pt_t[div][clk] - tmp_p;
+ better_err =
+ pt_t[div][clk] - tmp_p;
better_m = m;
} else {
- last_err = last_p - pt_t[div][clk];
- cur_err = pt_t[div][clk] - tmp_p;
+ last_err =
+ last_p - pt_t[div][clk];
+ cur_err =
+ pt_t[div][clk] - tmp_p;
if (cur_err < last_err) {
better_err = cur_err;
@@ -147,9 +150,9 @@
pwm_conf->pwm_ctl[5] = reg;
reg = ((pwm_conf->clk + 1) << PM_PWM_CLK_SEL_SHIFT)
- & PM_PWM_CLK_SEL_MASK;
+ & PM_PWM_CLK_SEL_MASK;
reg |= (pwm_conf->pre_div << PM_PWM_PREDIVIDE_SHIFT)
- & PM_PWM_PREDIVIDE_MASK;
+ & PM_PWM_PREDIVIDE_MASK;
reg |= pwm_conf->pre_div_exp & PM_PWM_M_MASK;
pwm_conf->pwm_ctl[4] = reg;
@@ -162,38 +165,38 @@
if (pwm_conf->pwm_size > 6) {
pwm_conf->pwm_ctl[3] = pwm_conf->pwm_value
- & PM_PWM_VALUE_BIT7_0;
+ & PM_PWM_VALUE_BIT7_0;
pwm_conf->pwm_ctl[4] |= (pwm_conf->pwm_value >> 1)
- & PM_PWM_VALUE_BIT8;
+ & PM_PWM_VALUE_BIT8;
} else {
pwm_conf->pwm_ctl[3] = pwm_conf->pwm_value
- & PM_PWM_VALUE_BIT5_0;
+ & PM_PWM_VALUE_BIT5_0;
}
len = 6;
- }
- else
- {
+ } else {
/* Right now, we are not using LUT */
goto bail_out;
}
/* Selecting the bank */
rc = pm8058_write(PM8058_LPG_BANK_SEL, &pwm_id, 1);
- if(rc)
+ if (rc)
goto bail_out;
for (i = 0; i < len; i++) {
- rc = pm8058_write(PM8058_LPG_CTL(i),&pwm_conf->pwm_ctl[i], 1);
+ rc = pm8058_write(PM8058_LPG_CTL(i), &pwm_conf->pwm_ctl[i], 1);
if (rc) {
- dprintf(CRITICAL,"pm8058_write() failed in pwm_configure %d\n", rc);
+ dprintf(CRITICAL,
+ "pm8058_write() failed in pwm_configure %d\n",
+ rc);
break;
}
}
-bail_out:
- if(rc)
- dprintf(CRITICAL,"Error in pm_pwm_configure()\n");
+ bail_out:
+ if (rc)
+ dprintf(CRITICAL, "Error in pm_pwm_configure()\n");
return rc;
}
@@ -205,10 +208,9 @@
uint32_t max_pwm_value, tmp;
int rc = -1;
- if((duty_us > period_us) || (period_us > PM_PWM_PERIOD_MAX) ||
- (period_us < PM_PWM_PERIOD_MIN))
- {
- dprintf(CRITICAL,"Error in duty cycle and period\n");
+ if ((duty_us > period_us) || (period_us > PM_PWM_PERIOD_MAX) ||
+ (period_us < PM_PWM_PERIOD_MIN)) {
+ dprintf(CRITICAL, "Error in duty cycle and period\n");
return -1;
}
@@ -231,13 +233,12 @@
/* Bypassing LUT */
pwm_conf.bypass_lut = 1;
- dprintf(SPEW,"duty/period=%u/%u usec: pwm_value=%d (of %d)\n",
- duty_us, period_us,pwm_conf.pwm_value,
- 1 << pwm_conf.pwm_size);
+ dprintf(SPEW, "duty/period=%u/%u usec: pwm_value=%d (of %d)\n",
+ duty_us, period_us, pwm_conf.pwm_value, 1 << pwm_conf.pwm_size);
rc = pm_pwm_configure(pwm_id, &pwm_conf);
- if(rc)
- dprintf(CRITICAL,"Error in pwm_config()\n");
+ if (rc)
+ dprintf(CRITICAL, "Error in pwm_config()\n");
return rc;
}
@@ -251,31 +252,31 @@
/* Read it before enabling other bank */
rc = pm8058_read(PM8058_LPG_BANK_ENABLE, ®, 1);
- if(rc)
+ if (rc)
goto bail_out;
reg |= (1 << pwm_id);
- rc = pm8058_write(PM8058_LPG_BANK_ENABLE,®,1);
- if(rc)
+ rc = pm8058_write(PM8058_LPG_BANK_ENABLE, ®, 1);
+ if (rc)
goto bail_out;
/* Selecting the bank */
rc = pm8058_write(PM8058_LPG_BANK_SEL, &pwm_id, 1);
- if(rc)
+ if (rc)
goto bail_out;
/* Read it before setting PWM start */
rc = pm8058_read(PM8058_LPG_CTL(0), ®, 1);
- if(rc)
+ if (rc)
goto bail_out;
reg |= PM_PWM_PWM_START;
reg &= ~PM_PWM_RAMP_GEN_START;
- rc = pm8058_write(PM8058_LPG_CTL(0),®, 1);
+ rc = pm8058_write(PM8058_LPG_CTL(0), ®, 1);
-bail_out:
- if(rc)
+ bail_out:
+ if (rc)
dprintf(CRITICAL, "Error in pwm_enable()\n");
return rc;
}
diff --git a/platform/msm8x60/rules.mk b/platform/msm8x60/rules.mk
old mode 100755
new mode 100644
diff --git a/platform/msm8x60/scm-io.c b/platform/msm8x60/scm-io.c
index 5aa8baa..9a1aac4 100644
--- a/platform/msm8x60/scm-io.c
+++ b/platform/msm8x60/scm-io.c
@@ -43,19 +43,16 @@
uint32_t secure_readl(uint32_t c)
{
- if ((BETWEEN((void *) c, MSM_MMSS_CLK_CTL_BASE, MSM_MMSS_CLK_CTL_SIZE)) ||
- (BETWEEN((void *) c, MSM_TCSR_BASE, MSM_TCSR_SIZE)))
- {
+ if ((BETWEEN((void *)c, MSM_MMSS_CLK_CTL_BASE, MSM_MMSS_CLK_CTL_SIZE))
+ || (BETWEEN((void *)c, MSM_TCSR_BASE, MSM_TCSR_SIZE))) {
uint32_t context_id;
register uint32_t r0 __asm__("r0") = SCM_IO_READ;
- register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t) & context_id;
register uint32_t r2 __asm__("r2") = c;
- __asm__(
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- );
+ __asm__("smc #0 @ switch to secure world\n":"=r"(r0)
+ : "r"(r0), "r"(r1), "r"(r2)
+ );
dmb();
return r0;
}
@@ -64,19 +61,17 @@
void secure_writel(uint32_t v, uint32_t c)
{
- if ((BETWEEN((void *) c, MSM_MMSS_CLK_CTL_BASE, MSM_MMSS_CLK_CTL_SIZE)) ||
- (BETWEEN((void *) c, MSM_TCSR_BASE, MSM_TCSR_SIZE))) {
+ if ((BETWEEN((void *)c, MSM_MMSS_CLK_CTL_BASE, MSM_MMSS_CLK_CTL_SIZE))
+ || (BETWEEN((void *)c, MSM_TCSR_BASE, MSM_TCSR_SIZE))) {
uint32_t context_id;
register uint32_t r0 __asm__("r0") = SCM_IO_WRITE;
- register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t) & context_id;
register uint32_t r2 __asm__("r2") = c;
register uint32_t r3 __asm__("r3") = v;
dmb();
- __asm__(
- "smc #0 @ switch to secure world\n"
- : /* No return value */
- : "r" (r0), "r" (r1), "r" (r2), "r" (r3)
- );
+ __asm__("smc #0 @ switch to secure world\n": /* No return value */
+ :"r"(r0), "r"(r1), "r"(r2), "r"(r3)
+ );
} else
writel(v, c);
}
diff --git a/platform/msm_shared/adm.c b/platform/msm_shared/adm.c
old mode 100755
new mode 100644
index c5bf140..a06e77a
--- a/platform/msm_shared/adm.c
+++ b/platform/msm_shared/adm.c
@@ -27,7 +27,6 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
#include <stdlib.h>
#include <reg.h>
@@ -39,7 +38,6 @@
* by other peripherals such as usb/uart/nand/display etc.
*/
-
/* TODO:
* adm module shouldn't have to include mmc.h.
* clean this up when generic adm interface is implemented.
@@ -59,24 +57,22 @@
* Must be aligned on 8 byte boundary.
*/
static uint32_t adm_cmd_ptr_list[8] __attribute__ ((aligned(8)));
-static uint32_t box_mode_entry[8] __attribute__ ((aligned(8)));
+static uint32_t box_mode_entry[8] __attribute__ ((aligned(8)));
-adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t *cmd_ptr_list);
-
+adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t * cmd_ptr_list);
/* CRCI - mmc slot mapping. */
extern uint8_t sdc_crci_map[5];
-
/* TODO:
* This interface is very specific to MMC.
* We need a generic ADM interface that can be easily
* used by other modules such as usb/uart/nand.
*/
-adm_result_t adm_transfer_mmc_data(unsigned char slot,
- unsigned char* data_ptr,
- unsigned int data_len,
- unsigned char direction)
+adm_result_t
+adm_transfer_mmc_data(unsigned char slot,
+ unsigned char *data_ptr,
+ unsigned int data_len, unsigned char direction)
{
uint32_t num_rows;
uint16_t row_len;
@@ -85,33 +81,26 @@
uint32_t adm_crci_num;
adm_result_t result = ADM_RESULT_SUCCESS;
-
/* Make sure slot value is in the range 1..4 */
- ASSERT( (slot >= 1) && (slot <= 4));
+ ASSERT((slot >= 1) && (slot <= 4));
- adm_crci_num = sdc_crci_map[slot];
- row_len = MMC_BOOT_MCI_FIFO_SIZE;
- num_rows = data_len/MMC_BOOT_MCI_FIFO_SIZE;
-
+ adm_crci_num = sdc_crci_map[slot];
+ row_len = MMC_BOOT_MCI_FIFO_SIZE;
+ num_rows = data_len / MMC_BOOT_MCI_FIFO_SIZE;
/* While there is data to be transferred */
- while(data_len)
- {
- if(data_len <= MAX_ROW_LEN)
- {
- row_len = data_len;
+ while (data_len) {
+ if (data_len <= MAX_ROW_LEN) {
+ row_len = data_len;
row_offset = 0;
- row_num = 1;
- }
- else
- {
- row_len = MAX_ROW_LEN;
+ row_num = 1;
+ } else {
+ row_len = MAX_ROW_LEN;
row_offset = MAX_ROW_LEN;
- row_num = data_len/MAX_ROW_LEN;
+ row_num = data_len / MAX_ROW_LEN;
/* Limit the number of row to the max value allowed */
- if(row_num > MAX_ROW_NUM)
- {
+ if (row_num > MAX_ROW_NUM) {
row_num = MAX_ROW_NUM;
}
}
@@ -119,52 +108,47 @@
/* Program ADM registers and initiate data transfer */
/* Initialize the Box Mode command entry (single entry) */
- box_mode_entry[0] = ( ADM_CMD_LIST_LC |
- (adm_crci_num << 3) |
- ADM_ADDR_MODE_BOX);
+ box_mode_entry[0] = (ADM_CMD_LIST_LC |
+ (adm_crci_num << 3) | ADM_ADDR_MODE_BOX);
- if(direction == ADM_MMC_READ)
- {
- box_mode_entry[1] = MMC_BOOT_MCI_FIFO; /* SRC addr */
- box_mode_entry[2] = (uint32_t) data_ptr; /* DST addr */
- box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
- (row_len << 0)); /* DST row len */
- box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
- (row_num << 0)); /* DST row # */
- box_mode_entry[5] = ((0 << 16) | /* SRC offset */
- (row_offset << 0)); /* DST offset */
- }
- else
- {
- box_mode_entry[1] = (uint32_t) data_ptr; /* SRC addr */
- box_mode_entry[2] = MMC_BOOT_MCI_FIFO; /* DST addr */
- box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
- (row_len << 0)); /* DST row len */
- box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
- (row_num << 0)); /* DST row # */
- box_mode_entry[5] = ((row_offset << 16)| /* SRC offset */
- (0 << 0)); /* DST offset */
+ if (direction == ADM_MMC_READ) {
+ box_mode_entry[1] = MMC_BOOT_MCI_FIFO; /* SRC addr */
+ box_mode_entry[2] = (uint32_t) data_ptr; /* DST addr */
+ box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
+ (row_len << 0)); /* DST row len */
+ box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
+ (row_num << 0)); /* DST row # */
+ box_mode_entry[5] = ((0 << 16) | /* SRC offset */
+ (row_offset << 0)); /* DST offset */
+ } else {
+ box_mode_entry[1] = (uint32_t) data_ptr; /* SRC addr */
+ box_mode_entry[2] = MMC_BOOT_MCI_FIFO; /* DST addr */
+ box_mode_entry[3] = ((row_len << 16) | /* SRC row len */
+ (row_len << 0)); /* DST row len */
+ box_mode_entry[4] = ((row_num << 16) | /* SRC row # */
+ (row_num << 0)); /* DST row # */
+ box_mode_entry[5] = ((row_offset << 16) | /* SRC offset */
+ (0 << 0)); /* DST offset */
}
/* Initialize the ADM Command Pointer List (single entry) */
adm_cmd_ptr_list[0] = (ADM_CMD_PTR_LP |
ADM_CMD_PTR_CMD_LIST |
- (((uint32_t)(&box_mode_entry[0])) >> 3));
-
+ (((uint32_t) (&box_mode_entry[0])) >>
+ 3));
/* Start ADM transfer, this is a blocking call. */
result = adm_transfer_start(ADM_CHN, adm_cmd_ptr_list);
- if(result != ADM_RESULT_SUCCESS)
- {
+ if (result != ADM_RESULT_SUCCESS) {
break;
}
/* Update the data ptr and data len by the amount
* we just transferred.
*/
- data_ptr += (row_len*row_num);
- data_len -= (row_len*row_num);
+ data_ptr += (row_len * row_num);
+ data_len -= (row_len * row_num);
}
return result;
@@ -174,32 +158,29 @@
* Start the ADM data transfer and return the result of the transfer.
* Blocks until transfer is completed.
*/
-adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t *cmd_ptr_list)
+adm_result_t adm_transfer_start(uint32_t adm_chn, uint32_t * cmd_ptr_list)
{
uint32_t reg_value;
- uint32_t timeout = 1;
+ uint32_t timeout = 1;
uint32_t delay_count = 100;
-
/* Memory barrier to ensure that all ADM command list structure
* writes have completed before starting the ADM transfer.
*/
dmb();
/* Start the ADM transfer by writing the command ptr */
- writel( ((uint32_t)cmd_ptr_list) >> 3,
- ADM_REG_CMD_PTR(adm_chn, ADM_SD));
+ writel(((uint32_t) cmd_ptr_list) >> 3,
+ ADM_REG_CMD_PTR(adm_chn, ADM_SD));
/* Poll the status register to check for transfer complete.
* Bail out if transfer is not finished within 1 sec.
* Note: This time depends on the amount of data being transferred.
* Increase the delay_count if this is not sufficient.
*/
- do
- {
+ do {
reg_value = readl(ADM_REG_STATUS(adm_chn, ADM_SD));
- if((reg_value & ADM_REG_STATUS__RSLT_VLD___M) != 0)
- {
+ if ((reg_value & ADM_REG_STATUS__RSLT_VLD___M) != 0) {
timeout = 0;
break;
}
@@ -207,7 +188,8 @@
/* 10ms wait */
mdelay(10);
- } while(delay_count--);
+ }
+ while (delay_count--);
/* Read out the IRQ register to clear the interrupt.
* Even though we are not using interrupts,
@@ -216,20 +198,16 @@
*/
reg_value = readl(ADM_REG_IRQ(ADM_SD));
- if(timeout)
- {
+ if (timeout) {
return ADM_RESULT_TIMEOUT;
- }
- else
- {
+ } else {
/* Get the result from the RSLT FIFO */
reg_value = readl(ADM_REG_RSLT(adm_chn, ADM_SD));
/* Check for any error */
- if(((reg_value & ADM_REG_RSLT__ERR___M) != 0) ||
- ((reg_value & ADM_REG_RSLT__TPD___M) == 0) ||
- ((reg_value & ADM_REG_RSLT__V___M) == 0))
- {
+ if (((reg_value & ADM_REG_RSLT__ERR___M) != 0) ||
+ ((reg_value & ADM_REG_RSLT__TPD___M) == 0) ||
+ ((reg_value & ADM_REG_RSLT__V___M) == 0)) {
return ADM_RESULT_FAILURE;
}
}
diff --git a/platform/msm_shared/adm.h b/platform/msm_shared/adm.h
old mode 100755
new mode 100644
index bcf2ee3..52f97a3
--- a/platform/msm_shared/adm.h
+++ b/platform/msm_shared/adm.h
@@ -32,7 +32,6 @@
#include <platform/iomap.h>
-
/* ADM base address for channel (n) and security_domain (s) */
#define ADM_BASE_ADDR(n, s) (MSM_ADM_BASE + 4*(n) + ((MSM_ADM_SD_OFFSET)*(s)))
@@ -50,44 +49,36 @@
/* Status reg bit masks */
#define ADM_REG_STATUS__RSLT_VLD___M (1 << 1)
-
/* Command Pointer List Entry bit masks */
-#define ADM_CMD_PTR_LP (1 << 31) /* Last pointer */
-#define ADM_CMD_PTR_CMD_LIST (0 << 29) /* Command List */
+#define ADM_CMD_PTR_LP (1 << 31) /* Last pointer */
+#define ADM_CMD_PTR_CMD_LIST (0 << 29) /* Command List */
/* Command List bit masks */
-#define ADM_CMD_LIST_LC (1 << 31) /* Last command */
-#define ADM_CMD_LIST_OCU (1 << 21) /* Other channel unblock */
-#define ADM_CMD_LIST_OCB (1 << 20) /* Other channel block */
-#define ADM_CMD_LIST_TCB (1 << 19) /* This channel block */
-#define ADM_ADDR_MODE_BOX (3 << 0) /* Box address mode */
-#define ADM_ADDR_MODE_SI (0 << 0) /* Single item address mode */
-
+#define ADM_CMD_LIST_LC (1 << 31) /* Last command */
+#define ADM_CMD_LIST_OCU (1 << 21) /* Other channel unblock */
+#define ADM_CMD_LIST_OCB (1 << 20) /* Other channel block */
+#define ADM_CMD_LIST_TCB (1 << 19) /* This channel block */
+#define ADM_ADDR_MODE_BOX (3 << 0) /* Box address mode */
+#define ADM_ADDR_MODE_SI (0 << 0) /* Single item address mode */
/* ADM external inteface */
/* result type */
-typedef enum
-{
+typedef enum {
- ADM_RESULT_SUCCESS = 0,
- ADM_RESULT_FAILURE = 1,
- ADM_RESULT_TIMEOUT = 2
-
+ ADM_RESULT_SUCCESS = 0,
+ ADM_RESULT_FAILURE = 1,
+ ADM_RESULT_TIMEOUT = 2
} adm_result_t;
-
/* direction type */
-typedef enum
-{
+typedef enum {
- ADM_MMC_READ = 0,
- ADM_MMC_WRITE
-
+ ADM_MMC_READ = 0,
+ ADM_MMC_WRITE
} adm_dir_t;
adm_result_t adm_transfer_mmc_data(unsigned char slot,
- unsigned char* data_ptr,
- unsigned int data_len,
- adm_dir_t dir);
+ unsigned char *data_ptr,
+ unsigned int data_len, adm_dir_t dir);
#endif
diff --git a/platform/msm_shared/certificate.c b/platform/msm_shared/certificate.c
index 81d3746..4a5b1a0 100644
--- a/platform/msm_shared/certificate.c
+++ b/platform/msm_shared/certificate.c
@@ -28,95 +28,141 @@
*/
#include <certificate.h>
-const char certBuffer [CERTIFICATE_SIZE] ={
-0x30, 0x82, 0x02, 0xd0, 0x30, 0x82, 0x01, 0xb8, 0x02, 0x01, 0x05, 0x30, 0x0d,
- 0x06, 0x09, 0x2a,
-0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x05, 0x05, 0x00, 0x30, 0x2f, 0x31,
- 0x0b, 0x30, 0x09,
-0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x0b, 0x30, 0x09,
- 0x06, 0x03, 0x55,
-0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55,
- 0x04, 0x0a, 0x0c,
-0x0a, 0x41, 0x6e, 0x64, 0x72, 0x6f, 0x69, 0x64, 0x20, 0x4c, 0x4b, 0x30, 0x1e,
- 0x17, 0x0d, 0x31,
-0x31, 0x30, 0x38, 0x30, 0x31, 0x31, 0x34, 0x35, 0x35, 0x33, 0x35, 0x5a, 0x17,
- 0x0d, 0x33, 0x32,
-0x30, 0x32, 0x31, 0x32, 0x31, 0x34, 0x35, 0x35, 0x33, 0x35, 0x5a, 0x30, 0x2f,
- 0x31, 0x0b, 0x30,
-0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x0b, 0x30,
- 0x09, 0x06, 0x03,
-0x55, 0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03,
- 0x55, 0x04, 0x0a,
-0x0c, 0x0a, 0x41, 0x6e, 0x64, 0x72, 0x6f, 0x69, 0x64, 0x20, 0x4c, 0x4b, 0x30,
- 0x82, 0x01, 0x20,
-0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01,
- 0x05, 0x00, 0x03,
-0x82, 0x01, 0x0d, 0x00, 0x30, 0x82, 0x01, 0x08, 0x02, 0x82, 0x01, 0x01, 0x00,
- 0xc8, 0x82, 0x09,
-0x43, 0x84, 0x33, 0x91, 0xfa, 0xca, 0xa1, 0x43, 0xc1, 0x92, 0xa9, 0x26, 0x0c,
- 0xe2, 0x15, 0xab,
-0x71, 0xfa, 0x85, 0x97, 0x5f, 0xf0, 0xcd, 0x66, 0xeb, 0x7f, 0x0b, 0xc1, 0x01,
- 0x8e, 0x8e, 0x1b,
-0xfa, 0xaa, 0x82, 0x21, 0xd3, 0x1d, 0x3b, 0x0a, 0x91, 0x0e, 0xcd, 0x85, 0xa0,
- 0x4d, 0xd7, 0xed,
-0x27, 0x72, 0xa6, 0xb1, 0x26, 0x8e, 0xe9, 0x5f, 0x57, 0x77, 0x3d, 0x93, 0x79,
- 0x38, 0xde, 0xac,
-0xa1, 0xc9, 0xd1, 0xcc, 0x42, 0x04, 0x53, 0x88, 0x64, 0xac, 0xaa, 0xab, 0xfc,
- 0xb7, 0xf0, 0x32,
-0x2d, 0xb0, 0xf4, 0xe1, 0x35, 0x58, 0xdf, 0x5e, 0x8a, 0x47, 0x28, 0x2b, 0xa9,
- 0xda, 0x54, 0xd3,
-0xbc, 0x0a, 0x12, 0x5f, 0x76, 0x5e, 0x16, 0xab, 0xf5, 0x9d, 0x11, 0x8f, 0x36,
- 0x99, 0x3a, 0x1c,
-0x76, 0x95, 0x31, 0xa9, 0x92, 0x86, 0x81, 0xcc, 0x56, 0x56, 0x52, 0xe2, 0x70,
- 0xf4, 0xb3, 0x99,
-0xe7, 0x2e, 0xdd, 0x9d, 0x33, 0xad, 0x22, 0x8a, 0x10, 0x17, 0x53, 0xf2, 0x6a,
- 0x85, 0x80, 0xad,
-0x14, 0xd3, 0xa2, 0xd3, 0xe2, 0x37, 0x8a, 0x4c, 0xdd, 0xa2, 0xdb, 0x46, 0x32,
- 0xa9, 0x23, 0x46,
-0x1a, 0xd5, 0x86, 0xec, 0x39, 0x98, 0x06, 0xd0, 0x4f, 0xe8, 0x6f, 0x02, 0x90,
- 0x05, 0x76, 0x3b,
-0x8b, 0xfc, 0x86, 0x8d, 0xa1, 0x3d, 0x58, 0x80, 0xc7, 0x9e, 0x53, 0xd0, 0xa2,
- 0xb8, 0xbb, 0xc7,
-0x13, 0x35, 0xcd, 0x6f, 0xc2, 0x07, 0xad, 0xa2, 0xe1, 0x82, 0x12, 0xf1, 0xbc,
- 0x4f, 0x19, 0x00,
-0x0f, 0x9d, 0x9f, 0x9d, 0x01, 0x43, 0x24, 0xac, 0xe6, 0x30, 0x11, 0x38, 0xae,
- 0xa6, 0xb7, 0x47,
-0xb3, 0x71, 0x8b, 0x79, 0x46, 0xd4, 0x3b, 0x7d, 0xf0, 0x6c, 0x84, 0xa2, 0x58,
- 0xb4, 0xe3, 0x86,
-0x8f, 0xb8, 0xfc, 0xf9, 0xcb, 0x1c, 0x30, 0x17, 0x1e, 0x34, 0xc3, 0x98, 0xa3,
- 0x02, 0x01, 0x03,
-0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x05,
- 0x05, 0x00, 0x03,
-0x82, 0x01, 0x01, 0x00, 0x21, 0xe0, 0x4c, 0x79, 0x9c, 0x54, 0x81, 0x0b, 0x76,
- 0xe6, 0x0d, 0x6d,
-0x14, 0xba, 0x47, 0x2f, 0xb1, 0x3d, 0xdf, 0x00, 0xbe, 0xa6, 0x0b, 0xb2, 0x6e,
- 0x7e, 0x1c, 0x8b,
-0x4d, 0x77, 0xd3, 0xdb, 0x48, 0x1e, 0xa0, 0x6a, 0x3d, 0x01, 0x63, 0x97, 0xde,
- 0xfa, 0xdd, 0xc1,
-0xf9, 0x4d, 0x22, 0xdf, 0xcf, 0xb1, 0x7c, 0x30, 0x32, 0xd5, 0xe9, 0xb3, 0x72,
- 0x9f, 0xfe, 0x1d,
-0x9a, 0x71, 0x6d, 0x24, 0x54, 0x39, 0xaf, 0xf1, 0x6c, 0x24, 0x0f, 0xfd, 0x08,
- 0x88, 0x84, 0x4d,
-0x2e, 0x7b, 0x11, 0xc2, 0x4d, 0xfd, 0x9b, 0x00, 0x3e, 0x02, 0x9f, 0x23, 0x76,
- 0x3d, 0xef, 0x6a,
-0x66, 0x64, 0x34, 0x3e, 0x3b, 0xa6, 0x31, 0x5f, 0x69, 0xeb, 0xf0, 0xcd, 0x89,
- 0xc1, 0xe9, 0x1c,
-0xe0, 0x8d, 0xed, 0x05, 0x68, 0x5b, 0xc1, 0xe7, 0x79, 0xac, 0x83, 0x29, 0xc9,
- 0x60, 0x13, 0xe6,
-0x66, 0x36, 0xb1, 0xf0, 0x04, 0x0d, 0x88, 0x7c, 0x89, 0xb1, 0xf4, 0xc1, 0xca,
- 0x5a, 0x25, 0x13,
-0xc1, 0xaf, 0x8c, 0x45, 0x1b, 0x59, 0xbe, 0x35, 0xe0, 0xbe, 0x9c, 0x4c, 0xc6,
- 0xb0, 0x59, 0x27,
-0xd9, 0xac, 0x6e, 0xf8, 0x35, 0x0c, 0xf7, 0x8a, 0xcc, 0xba, 0x39, 0x48, 0x6e,
- 0x04, 0xd9, 0x6d,
-0x41, 0x4a, 0x81, 0x32, 0x96, 0x29, 0xc6, 0xe2, 0x20, 0xca, 0xed, 0xc0, 0x44,
- 0x6c, 0xd3, 0xe9,
-0xea, 0x52, 0xa8, 0x1d, 0x5b, 0x9f, 0x84, 0xe8, 0x57, 0xd7, 0x21, 0xa9, 0xa8,
- 0x0d, 0x9d, 0x05,
-0xa4, 0xd2, 0xb2, 0x54, 0xec, 0x07, 0x22, 0x3c, 0x64, 0x54, 0xa4, 0xfd, 0xb0,
- 0x8d, 0xe4, 0xf7,
-0x40, 0xe1, 0x41, 0xdc, 0xf7, 0x98, 0x65, 0x3d, 0x9f, 0xd1, 0x28, 0x23, 0x03,
- 0x91, 0x6b, 0xab,
-0x52, 0x04, 0x3b, 0xe1, 0x4e, 0x64, 0xea, 0x3b, 0xea, 0x6f, 0x30, 0xad, 0x2c,
- 0x4a, 0x0e, 0xe2,
-0x79, 0x9c, 0xd3, 0x83};
+const char certBuffer[CERTIFICATE_SIZE] = {
+ 0x30, 0x82, 0x02, 0xd0, 0x30, 0x82, 0x01, 0xb8, 0x02, 0x01, 0x05, 0x30,
+ 0x0d,
+ 0x06, 0x09, 0x2a,
+ 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x05, 0x05, 0x00, 0x30, 0x2f,
+ 0x31,
+ 0x0b, 0x30, 0x09,
+ 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x0b, 0x30,
+ 0x09,
+ 0x06, 0x03, 0x55,
+ 0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03,
+ 0x55,
+ 0x04, 0x0a, 0x0c,
+ 0x0a, 0x41, 0x6e, 0x64, 0x72, 0x6f, 0x69, 0x64, 0x20, 0x4c, 0x4b, 0x30,
+ 0x1e,
+ 0x17, 0x0d, 0x31,
+ 0x31, 0x30, 0x38, 0x30, 0x31, 0x31, 0x34, 0x35, 0x35, 0x33, 0x35, 0x5a,
+ 0x17,
+ 0x0d, 0x33, 0x32,
+ 0x30, 0x32, 0x31, 0x32, 0x31, 0x34, 0x35, 0x35, 0x33, 0x35, 0x5a, 0x30,
+ 0x2f,
+ 0x31, 0x0b, 0x30,
+ 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x0b,
+ 0x30,
+ 0x09, 0x06, 0x03,
+ 0x55, 0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, 0x31, 0x13, 0x30, 0x11, 0x06,
+ 0x03,
+ 0x55, 0x04, 0x0a,
+ 0x0c, 0x0a, 0x41, 0x6e, 0x64, 0x72, 0x6f, 0x69, 0x64, 0x20, 0x4c, 0x4b,
+ 0x30,
+ 0x82, 0x01, 0x20,
+ 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01,
+ 0x01,
+ 0x05, 0x00, 0x03,
+ 0x82, 0x01, 0x0d, 0x00, 0x30, 0x82, 0x01, 0x08, 0x02, 0x82, 0x01, 0x01,
+ 0x00,
+ 0xc8, 0x82, 0x09,
+ 0x43, 0x84, 0x33, 0x91, 0xfa, 0xca, 0xa1, 0x43, 0xc1, 0x92, 0xa9, 0x26,
+ 0x0c,
+ 0xe2, 0x15, 0xab,
+ 0x71, 0xfa, 0x85, 0x97, 0x5f, 0xf0, 0xcd, 0x66, 0xeb, 0x7f, 0x0b, 0xc1,
+ 0x01,
+ 0x8e, 0x8e, 0x1b,
+ 0xfa, 0xaa, 0x82, 0x21, 0xd3, 0x1d, 0x3b, 0x0a, 0x91, 0x0e, 0xcd, 0x85,
+ 0xa0,
+ 0x4d, 0xd7, 0xed,
+ 0x27, 0x72, 0xa6, 0xb1, 0x26, 0x8e, 0xe9, 0x5f, 0x57, 0x77, 0x3d, 0x93,
+ 0x79,
+ 0x38, 0xde, 0xac,
+ 0xa1, 0xc9, 0xd1, 0xcc, 0x42, 0x04, 0x53, 0x88, 0x64, 0xac, 0xaa, 0xab,
+ 0xfc,
+ 0xb7, 0xf0, 0x32,
+ 0x2d, 0xb0, 0xf4, 0xe1, 0x35, 0x58, 0xdf, 0x5e, 0x8a, 0x47, 0x28, 0x2b,
+ 0xa9,
+ 0xda, 0x54, 0xd3,
+ 0xbc, 0x0a, 0x12, 0x5f, 0x76, 0x5e, 0x16, 0xab, 0xf5, 0x9d, 0x11, 0x8f,
+ 0x36,
+ 0x99, 0x3a, 0x1c,
+ 0x76, 0x95, 0x31, 0xa9, 0x92, 0x86, 0x81, 0xcc, 0x56, 0x56, 0x52, 0xe2,
+ 0x70,
+ 0xf4, 0xb3, 0x99,
+ 0xe7, 0x2e, 0xdd, 0x9d, 0x33, 0xad, 0x22, 0x8a, 0x10, 0x17, 0x53, 0xf2,
+ 0x6a,
+ 0x85, 0x80, 0xad,
+ 0x14, 0xd3, 0xa2, 0xd3, 0xe2, 0x37, 0x8a, 0x4c, 0xdd, 0xa2, 0xdb, 0x46,
+ 0x32,
+ 0xa9, 0x23, 0x46,
+ 0x1a, 0xd5, 0x86, 0xec, 0x39, 0x98, 0x06, 0xd0, 0x4f, 0xe8, 0x6f, 0x02,
+ 0x90,
+ 0x05, 0x76, 0x3b,
+ 0x8b, 0xfc, 0x86, 0x8d, 0xa1, 0x3d, 0x58, 0x80, 0xc7, 0x9e, 0x53, 0xd0,
+ 0xa2,
+ 0xb8, 0xbb, 0xc7,
+ 0x13, 0x35, 0xcd, 0x6f, 0xc2, 0x07, 0xad, 0xa2, 0xe1, 0x82, 0x12, 0xf1,
+ 0xbc,
+ 0x4f, 0x19, 0x00,
+ 0x0f, 0x9d, 0x9f, 0x9d, 0x01, 0x43, 0x24, 0xac, 0xe6, 0x30, 0x11, 0x38,
+ 0xae,
+ 0xa6, 0xb7, 0x47,
+ 0xb3, 0x71, 0x8b, 0x79, 0x46, 0xd4, 0x3b, 0x7d, 0xf0, 0x6c, 0x84, 0xa2,
+ 0x58,
+ 0xb4, 0xe3, 0x86,
+ 0x8f, 0xb8, 0xfc, 0xf9, 0xcb, 0x1c, 0x30, 0x17, 0x1e, 0x34, 0xc3, 0x98,
+ 0xa3,
+ 0x02, 0x01, 0x03,
+ 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01,
+ 0x05,
+ 0x05, 0x00, 0x03,
+ 0x82, 0x01, 0x01, 0x00, 0x21, 0xe0, 0x4c, 0x79, 0x9c, 0x54, 0x81, 0x0b,
+ 0x76,
+ 0xe6, 0x0d, 0x6d,
+ 0x14, 0xba, 0x47, 0x2f, 0xb1, 0x3d, 0xdf, 0x00, 0xbe, 0xa6, 0x0b, 0xb2,
+ 0x6e,
+ 0x7e, 0x1c, 0x8b,
+ 0x4d, 0x77, 0xd3, 0xdb, 0x48, 0x1e, 0xa0, 0x6a, 0x3d, 0x01, 0x63, 0x97,
+ 0xde,
+ 0xfa, 0xdd, 0xc1,
+ 0xf9, 0x4d, 0x22, 0xdf, 0xcf, 0xb1, 0x7c, 0x30, 0x32, 0xd5, 0xe9, 0xb3,
+ 0x72,
+ 0x9f, 0xfe, 0x1d,
+ 0x9a, 0x71, 0x6d, 0x24, 0x54, 0x39, 0xaf, 0xf1, 0x6c, 0x24, 0x0f, 0xfd,
+ 0x08,
+ 0x88, 0x84, 0x4d,
+ 0x2e, 0x7b, 0x11, 0xc2, 0x4d, 0xfd, 0x9b, 0x00, 0x3e, 0x02, 0x9f, 0x23,
+ 0x76,
+ 0x3d, 0xef, 0x6a,
+ 0x66, 0x64, 0x34, 0x3e, 0x3b, 0xa6, 0x31, 0x5f, 0x69, 0xeb, 0xf0, 0xcd,
+ 0x89,
+ 0xc1, 0xe9, 0x1c,
+ 0xe0, 0x8d, 0xed, 0x05, 0x68, 0x5b, 0xc1, 0xe7, 0x79, 0xac, 0x83, 0x29,
+ 0xc9,
+ 0x60, 0x13, 0xe6,
+ 0x66, 0x36, 0xb1, 0xf0, 0x04, 0x0d, 0x88, 0x7c, 0x89, 0xb1, 0xf4, 0xc1,
+ 0xca,
+ 0x5a, 0x25, 0x13,
+ 0xc1, 0xaf, 0x8c, 0x45, 0x1b, 0x59, 0xbe, 0x35, 0xe0, 0xbe, 0x9c, 0x4c,
+ 0xc6,
+ 0xb0, 0x59, 0x27,
+ 0xd9, 0xac, 0x6e, 0xf8, 0x35, 0x0c, 0xf7, 0x8a, 0xcc, 0xba, 0x39, 0x48,
+ 0x6e,
+ 0x04, 0xd9, 0x6d,
+ 0x41, 0x4a, 0x81, 0x32, 0x96, 0x29, 0xc6, 0xe2, 0x20, 0xca, 0xed, 0xc0,
+ 0x44,
+ 0x6c, 0xd3, 0xe9,
+ 0xea, 0x52, 0xa8, 0x1d, 0x5b, 0x9f, 0x84, 0xe8, 0x57, 0xd7, 0x21, 0xa9,
+ 0xa8,
+ 0x0d, 0x9d, 0x05,
+ 0xa4, 0xd2, 0xb2, 0x54, 0xec, 0x07, 0x22, 0x3c, 0x64, 0x54, 0xa4, 0xfd,
+ 0xb0,
+ 0x8d, 0xe4, 0xf7,
+ 0x40, 0xe1, 0x41, 0xdc, 0xf7, 0x98, 0x65, 0x3d, 0x9f, 0xd1, 0x28, 0x23,
+ 0x03,
+ 0x91, 0x6b, 0xab,
+ 0x52, 0x04, 0x3b, 0xe1, 0x4e, 0x64, 0xea, 0x3b, 0xea, 0x6f, 0x30, 0xad,
+ 0x2c,
+ 0x4a, 0x0e, 0xe2,
+ 0x79, 0x9c, 0xd3, 0x83
+};
diff --git a/platform/msm_shared/crypto4_eng.c b/platform/msm_shared/crypto4_eng.c
index 59562c4..2f7cdc5 100644
--- a/platform/msm_shared/crypto4_eng.c
+++ b/platform/msm_shared/crypto4_eng.c
@@ -56,74 +56,70 @@
{
unsigned int val;
val = (AUTO_SHUTDOWN_EN | MASK_ERR_INTR | MASK_DIN_INTR |
- MASK_DOUT_INTR | HIGH_SPD_IN_EN_N | HIGH_SPD_OUT_EN_N);
+ MASK_DOUT_INTR | HIGH_SPD_IN_EN_N | HIGH_SPD_OUT_EN_N);
val |= MASK_OP_DONE_INTR;
- wr_ce(val,CRYPTO_CONFIG);
+ wr_ce(val, CRYPTO_CONFIG);
}
/*
* Function to set various SHAx registers in CRYPTO based on algorithm type.
*/
-void crypto_set_sha_ctx(void *ctx_ptr, unsigned int bytes_to_write,
- crypto_auth_alg_type auth_alg, bool first, bool last)
+void
+crypto_set_sha_ctx(void *ctx_ptr, unsigned int bytes_to_write,
+ crypto_auth_alg_type auth_alg, bool first, bool last)
{
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
- crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx*)ctx_ptr;
- unsigned int i=0;
- unsigned int iv_len=0;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
+ unsigned int i = 0;
+ unsigned int iv_len = 0;
unsigned int *auth_iv;
unsigned int seg_cfg_val;
seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA1;
- if(last)
- {
+ if (last) {
seg_cfg_val |= SEG_CFG_LAST;
}
iv_len = SHA1_INIT_VECTOR_SIZE;
auth_iv = sha1_ctx->auth_iv;
- }
- else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
- if(last)
- {
+ if (last) {
seg_cfg_val |= SEG_CFG_LAST;
}
iv_len = SHA256_INIT_VECTOR_SIZE;
auth_iv = sha256_ctx->auth_iv;
- }
- else
- {
- dprintf(CRITICAL, "crypto_set_sha_ctx invalid auth algorithm\n");
+ } else {
+ dprintf(CRITICAL,
+ "crypto_set_sha_ctx invalid auth algorithm\n");
return;
}
- for(i=0; i<iv_len; i++)
- {
- wr_ce(*(auth_iv+i),CRYPTO_AUTH_IVn(i));
+ for (i = 0; i < iv_len; i++) {
+ wr_ce(*(auth_iv + i), CRYPTO_AUTH_IVn(i));
}
- wr_ce(seg_cfg_val,CRYPTO_AUTH_SEG_CFG);
+ wr_ce(seg_cfg_val, CRYPTO_AUTH_SEG_CFG);
/* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt in both
crypto_SHA1_ctx and crypto_SHA256_ctx are same */
- wr_ce(((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[0],CRYPTO_AUTH_BYTECNTn(0));
- wr_ce(((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[1],CRYPTO_AUTH_BYTECNTn(1));
+ wr_ce(((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0],
+ CRYPTO_AUTH_BYTECNTn(0));
+ wr_ce(((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1],
+ CRYPTO_AUTH_BYTECNTn(1));
- wr_ce(bytes_to_write,CRYPTO_AUTH_SEG_SIZE);
+ wr_ce(bytes_to_write, CRYPTO_AUTH_SEG_SIZE);
- wr_ce(bytes_to_write,CRYPTO_SEG_SIZE);
+ wr_ce(bytes_to_write, CRYPTO_SEG_SIZE);
/*
* Ensure previous instructions (any writes to config registers)
@@ -133,7 +129,7 @@
*/
dsb();
- wr_ce(GOPROC_GO,CRYPTO_GOPROC);
+ wr_ce(GOPROC_GO, CRYPTO_GOPROC);
return;
}
@@ -143,22 +139,22 @@
* polling to send the requested amount of data.
*/
-void crypto_send_data(void *ctx_ptr, unsigned char *data_ptr,
- unsigned int buff_size, unsigned int bytes_to_write,
- unsigned int *ret_status)
+void
+crypto_send_data(void *ctx_ptr, unsigned char *data_ptr,
+ unsigned int buff_size, unsigned int bytes_to_write,
+ unsigned int *ret_status)
{
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
- unsigned int bytes_left=0;
- unsigned int i=0;
- unsigned int ce_status=0;
- unsigned int ce_err_bmsk=0;
- unsigned int is_not_aligned=FALSE;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ unsigned int bytes_left = 0;
+ unsigned int i = 0;
+ unsigned int ce_status = 0;
+ unsigned int ce_err_bmsk = 0;
+ unsigned int is_not_aligned = FALSE;
unsigned char data[4];
- unsigned char *buff_ptr=data_ptr;
+ unsigned char *buff_ptr = data_ptr;
/* Check if the buff_ptr is aligned */
- if(!(IS_ALIGNED(buff_ptr)))
- {
+ if (!(IS_ALIGNED(buff_ptr))) {
is_not_aligned = TRUE;
}
@@ -167,36 +163,31 @@
buff_ptr. We will update bytes_left and buff_ptr in the while loop
once are done writing all the data from saved_buff. */
- if(sha1_ctx->saved_buff_indx != 0)
- {
- memcpy(sha1_ctx->saved_buff + sha1_ctx->saved_buff_indx, buff_ptr,
- (((buff_size + sha1_ctx->saved_buff_indx) <= CRYPTO_SHA_BLOCK_SIZE)
- ? buff_size : (CRYPTO_SHA_BLOCK_SIZE - sha1_ctx->saved_buff_indx)));
+ if (sha1_ctx->saved_buff_indx != 0) {
+ memcpy(sha1_ctx->saved_buff + sha1_ctx->saved_buff_indx,
+ buff_ptr,
+ (((buff_size + sha1_ctx->saved_buff_indx) <=
+ CRYPTO_SHA_BLOCK_SIZE)
+ ? buff_size : (CRYPTO_SHA_BLOCK_SIZE -
+ sha1_ctx->saved_buff_indx)));
- if(bytes_to_write >= CRYPTO_SHA_BLOCK_SIZE)
- {
+ if (bytes_to_write >= CRYPTO_SHA_BLOCK_SIZE) {
bytes_left = CRYPTO_SHA_BLOCK_SIZE;
- }
- else
- {
+ } else {
bytes_left = bytes_to_write;
}
- }
- else
- {
+ } else {
bytes_left = bytes_to_write;
}
/* Error bitmask to check crypto engine status */
ce_err_bmsk = (SW_ERR | DIN_RDY | DIN_SIZE_AVAIL);
- while(bytes_left >= 4)
- {
+ while (bytes_left >= 4) {
ce_status = rd_ce(CRYPTO_STATUS);
ce_status &= ce_err_bmsk;
- if(ce_status & SW_ERR)
- {
+ if (ce_status & SW_ERR) {
/* If there is SW_ERR, reset the engine */
crypto_eng_reset();
*ret_status = CRYPTO_ERR_FAIL;
@@ -205,48 +196,51 @@
}
/* We can write data now - 4 bytes at a time in network byte order */
- if((ce_status & DIN_RDY) && ((ce_status & DIN_SIZE_AVAIL) >= 4))
- {
- if(sha1_ctx->saved_buff_indx != 0)
- {
+ if ((ce_status & DIN_RDY)
+ && ((ce_status & DIN_SIZE_AVAIL) >= 4)) {
+ if (sha1_ctx->saved_buff_indx != 0) {
/* Write from saved_buff */
- wr_ce(htonl(*((unsigned int *)(sha1_ctx->saved_buff)+i)),CRYPTO_DATA_IN);
- }
- else
- {
- if(!is_not_aligned)
- {
+ wr_ce(htonl
+ (*
+ ((unsigned int *)(sha1_ctx->saved_buff) +
+ i)), CRYPTO_DATA_IN);
+ } else {
+ if (!is_not_aligned) {
/* Write from buff_ptr aligned */
- wr_ce(htonl(*((unsigned int *)buff_ptr+i)),CRYPTO_DATA_IN);
- }
- else
- {
+ wr_ce(htonl
+ (*((unsigned int *)buff_ptr + i)),
+ CRYPTO_DATA_IN);
+ } else {
/* If buff_ptr is not aligned write byte by byte */
- data[0] = *(buff_ptr+i);
- data[1] = *(buff_ptr+i+1);
- data[2] = *(buff_ptr+i+2);
- data[3] = *(buff_ptr+i+3);
+ data[0] = *(buff_ptr + i);
+ data[1] = *(buff_ptr + i + 1);
+ data[2] = *(buff_ptr + i + 2);
+ data[3] = *(buff_ptr + i + 3);
/* i will incremented by 1 in outside block */
- i+=3;
- wr_ce(htonl(*(unsigned int *)data),CRYPTO_DATA_IN);
- memset(data,0,4);
+ i += 3;
+ wr_ce(htonl(*(unsigned int *)data),
+ CRYPTO_DATA_IN);
+ memset(data, 0, 4);
}
}
i++;
- bytes_left -=4;
+ bytes_left -= 4;
/* Check if we have written from saved_buff. Adjust buff_ptr and
bytes_left accordingly */
- if((sha1_ctx->saved_buff_indx != 0) && (bytes_left == 0) &&
- (bytes_to_write > CRYPTO_SHA_BLOCK_SIZE))
- {
- bytes_left = (bytes_to_write - CRYPTO_SHA_BLOCK_SIZE);
- buff_ptr = (unsigned char *)((unsigned char *)data_ptr +
- CRYPTO_SHA_BLOCK_SIZE - sha1_ctx->saved_buff_indx);
+ if ((sha1_ctx->saved_buff_indx != 0)
+ && (bytes_left == 0)
+ && (bytes_to_write > CRYPTO_SHA_BLOCK_SIZE)) {
+ bytes_left =
+ (bytes_to_write - CRYPTO_SHA_BLOCK_SIZE);
+ buff_ptr =
+ (unsigned char *)((unsigned char *)data_ptr
+ + CRYPTO_SHA_BLOCK_SIZE -
+ sha1_ctx->
+ saved_buff_indx);
i = 0;
sha1_ctx->saved_buff_indx = 0;
- if(!(IS_ALIGNED(buff_ptr)))
- {
+ if (!(IS_ALIGNED(buff_ptr))) {
is_not_aligned = TRUE;
}
}
@@ -254,33 +248,31 @@
}
/* We might have bytes_left < 4. Write them now if available */
- if(bytes_left)
- {
- memset(data,0,sizeof(unsigned int));
+ if (bytes_left) {
+ memset(data, 0, sizeof(unsigned int));
- if(sha1_ctx->saved_buff_indx)
+ if (sha1_ctx->saved_buff_indx)
buff_ptr = (sha1_ctx->saved_buff + bytes_to_write - 1);
else
- buff_ptr = (((unsigned char *)data_ptr) + buff_size - 1);
+ buff_ptr =
+ (((unsigned char *)data_ptr) + buff_size - 1);
- for(i=0;i<bytes_left;i++)
- {
- data[3-i] = *(buff_ptr-bytes_left+i+1);
+ for (i = 0; i < bytes_left; i++) {
+ data[3 - i] = *(buff_ptr - bytes_left + i + 1);
}
ce_status = rd_ce(CRYPTO_STATUS);
ce_status &= ce_err_bmsk;
- if(ce_status & SW_ERR)
- {
+ if (ce_status & SW_ERR) {
crypto_eng_reset();
*ret_status = CRYPTO_ERR_FAIL;
dprintf(CRITICAL, "crypto_send_data sw error 2\n");
return;
}
- if((ce_status & DIN_RDY) && ((ce_status & DIN_SIZE_AVAIL) >= 4))
- {
- wr_ce(*(unsigned int *)data,CRYPTO_DATA_IN);
+ if ((ce_status & DIN_RDY)
+ && ((ce_status & DIN_SIZE_AVAIL) >= 4)) {
+ wr_ce(*(unsigned int *)data, CRYPTO_DATA_IN);
}
}
*ret_status = CRYPTO_ERR_NONE;
@@ -291,24 +283,24 @@
* Function to get digest from CRYPTO. We poll for AUTH_DONE from CRYPTO.
*/
-void crypto_get_digest(unsigned char *digest_ptr, unsigned int *ret_status,
- crypto_auth_alg_type auth_alg, bool last)
+void
+crypto_get_digest(unsigned char *digest_ptr, unsigned int *ret_status,
+ crypto_auth_alg_type auth_alg, bool last)
{
- unsigned int ce_status=0;
- unsigned int ce_err_bmsk=0;
- unsigned int i=0;
- unsigned int digest_len=0;
+ unsigned int ce_status = 0;
+ unsigned int ce_err_bmsk = 0;
+ unsigned int i = 0;
+ unsigned int digest_len = 0;
ce_err_bmsk = (OPERATION_DONE | SW_ERR);
- do
- {
+ do {
ce_status = rd_ce(CRYPTO_STATUS);
ce_status &= ce_err_bmsk;
- }while (ce_status == 0);
+ }
+ while (ce_status == 0);
- if(ce_status & SW_ERR)
- {
+ if (ce_status & SW_ERR) {
crypto_eng_reset();
*ret_status = CRYPTO_ERR_FAIL;
dprintf(CRITICAL, "crypto_get_digest sw error\n");
@@ -317,27 +309,20 @@
/* Digest length depends on auth_alg */
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
digest_len = SHA1_INIT_VECTOR_SIZE;
- }
- else if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
digest_len = SHA256_INIT_VECTOR_SIZE;
}
/* Retrieve digest from CRYPTO */
- for(i=0; i < digest_len;i++)
- {
+ for (i = 0; i < digest_len; i++) {
unsigned int auth_iv = rd_ce(CRYPTO_AUTH_IVn(i));
- if(last)
- {
+ if (last) {
*((unsigned int *)digest_ptr + i) = htonl(auth_iv);
- }
- else
- {
+ } else {
*((unsigned int *)digest_ptr + i) = auth_iv;
}
}
@@ -349,7 +334,9 @@
void crypto_get_ctx(void *ctx_ptr)
{
- ((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[0] = rd_ce(CRYPTO_AUTH_BYTECNTn(0));
- ((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[1] = rd_ce(CRYPTO_AUTH_BYTECNTn(1));
+ ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0] =
+ rd_ce(CRYPTO_AUTH_BYTECNTn(0));
+ ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1] =
+ rd_ce(CRYPTO_AUTH_BYTECNTn(1));
return;
}
diff --git a/platform/msm_shared/crypto_eng.c b/platform/msm_shared/crypto_eng.c
index d36c9a4..4360742 100644
--- a/platform/msm_shared/crypto_eng.c
+++ b/platform/msm_shared/crypto_eng.c
@@ -40,7 +40,7 @@
void crypto_eng_reset(void)
{
- wr_ce(SW_RST,CRYPTO3_CONFIG);
+ wr_ce(SW_RST, CRYPTO3_CONFIG);
}
/*
@@ -51,88 +51,84 @@
void crypto_eng_init(void)
{
- unsigned int val;
- val = (AUTO_SHUTDOWN_EN | MASK_ERR_INTR | MASK_AUTH_DONE_INTR |
- MASK_DIN_INTR | MASK_DOUT_INTR | HIGH_SPD_IN_EN_N |
- HIGH_SPD_OUT_EN_N | HIGH_SPD_HASH_EN_N);
+ unsigned int val;
+ val = (AUTO_SHUTDOWN_EN | MASK_ERR_INTR | MASK_AUTH_DONE_INTR |
+ MASK_DIN_INTR | MASK_DOUT_INTR | HIGH_SPD_IN_EN_N |
+ HIGH_SPD_OUT_EN_N | HIGH_SPD_HASH_EN_N);
- wr_ce(val,CRYPTO3_CONFIG);
+ wr_ce(val, CRYPTO3_CONFIG);
}
/*
* Function to set various SHAx registers in CRYPTO3 based on algorithm type.
*/
-void crypto_set_sha_ctx(void *ctx_ptr, unsigned int bytes_to_write,
- crypto_auth_alg_type auth_alg, bool first, bool last)
+void
+crypto_set_sha_ctx(void *ctx_ptr, unsigned int bytes_to_write,
+ crypto_auth_alg_type auth_alg, bool first, bool last)
{
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
- crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx*)ctx_ptr;
- unsigned int i=0;
- unsigned int iv_len=0;
- unsigned int *auth_iv;
- unsigned int seg_cfg_val;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
+ unsigned int i = 0;
+ unsigned int iv_len = 0;
+ unsigned int *auth_iv;
+ unsigned int seg_cfg_val;
- seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
+ seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
- seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA1;
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
+ seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA1;
- if((first) || ((sha1_ctx->saved_buff_indx != 0) &&
- (sha1_ctx->auth_bytecnt[0] != 0 || sha1_ctx->auth_bytecnt[1] != 0)))
- {
- seg_cfg_val |= SEG_CFG_FIRST;
- }
- if(last)
- {
- seg_cfg_val |= SEG_CFG_LAST;
- }
+ if ((first) || ((sha1_ctx->saved_buff_indx != 0) &&
+ (sha1_ctx->auth_bytecnt[0] != 0
+ || sha1_ctx->auth_bytecnt[1] != 0))) {
+ seg_cfg_val |= SEG_CFG_FIRST;
+ }
+ if (last) {
+ seg_cfg_val |= SEG_CFG_LAST;
+ }
- iv_len = SHA1_INIT_VECTOR_SIZE;
- auth_iv = sha1_ctx->auth_iv;
- }
- else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
- seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
+ iv_len = SHA1_INIT_VECTOR_SIZE;
+ auth_iv = sha1_ctx->auth_iv;
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
+ seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
- if((first) || ((sha256_ctx->saved_buff_indx != 0) &&
- (sha256_ctx->auth_bytecnt[0] != 0 || sha256_ctx->auth_bytecnt[1] != 0)))
- {
- seg_cfg_val |= SEG_CFG_FIRST;
- }
- if(last)
- {
- seg_cfg_val |= SEG_CFG_LAST;
- }
+ if ((first) || ((sha256_ctx->saved_buff_indx != 0) &&
+ (sha256_ctx->auth_bytecnt[0] != 0
+ || sha256_ctx->auth_bytecnt[1] != 0))) {
+ seg_cfg_val |= SEG_CFG_FIRST;
+ }
+ if (last) {
+ seg_cfg_val |= SEG_CFG_LAST;
+ }
- iv_len = SHA256_INIT_VECTOR_SIZE;
- auth_iv = sha256_ctx->auth_iv;
- }
- else
- {
- dprintf(CRITICAL, "crypto_set_sha_ctx invalid auth algorithm\n");
- return;
- }
+ iv_len = SHA256_INIT_VECTOR_SIZE;
+ auth_iv = sha256_ctx->auth_iv;
+ } else {
+ dprintf(CRITICAL,
+ "crypto_set_sha_ctx invalid auth algorithm\n");
+ return;
+ }
- for(i=0; i<iv_len; i++)
- {
- wr_ce(*(auth_iv+i),CRYPTO3_AUTH_IVn(i));
- }
+ for (i = 0; i < iv_len; i++) {
+ wr_ce(*(auth_iv + i), CRYPTO3_AUTH_IVn(i));
+ }
- wr_ce(seg_cfg_val,CRYPTO3_SEG_CFG);
+ wr_ce(seg_cfg_val, CRYPTO3_SEG_CFG);
- /* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt in both
- crypto_SHA1_ctx and crypto_SHA256_ctx are same */
+ /* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt in both
+ crypto_SHA1_ctx and crypto_SHA256_ctx are same */
- wr_ce(((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[0],CRYPTO3_AUTH_BYTECNTn(0));
- wr_ce(((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[1],CRYPTO3_AUTH_BYTECNTn(1));
+ wr_ce(((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0],
+ CRYPTO3_AUTH_BYTECNTn(0));
+ wr_ce(((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1],
+ CRYPTO3_AUTH_BYTECNTn(1));
- wr_ce((bytes_to_write << AUTH_SEG_CFG_AUTH_SIZE),CRYPTO3_AUTH_SEG_CFG);
- wr_ce(bytes_to_write,CRYPTO3_SEG_SIZE);
- wr_ce(GOPROC_GO,CRYPTO3_GOPROC);
+ wr_ce((bytes_to_write << AUTH_SEG_CFG_AUTH_SIZE), CRYPTO3_AUTH_SEG_CFG);
+ wr_ce(bytes_to_write, CRYPTO3_SEG_SIZE);
+ wr_ce(GOPROC_GO, CRYPTO3_GOPROC);
- return;
+ return;
}
/*
@@ -140,211 +136,202 @@
* polling to send the requested amount of data.
*/
-void crypto_send_data(void *ctx_ptr, unsigned char *data_ptr,
- unsigned int buff_size, unsigned int bytes_to_write,
- unsigned int *ret_status)
+void
+crypto_send_data(void *ctx_ptr, unsigned char *data_ptr,
+ unsigned int buff_size, unsigned int bytes_to_write,
+ unsigned int *ret_status)
{
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
- unsigned int bytes_left=0;
- unsigned int i=0;
- unsigned int ce_status=0;
- unsigned int ce_err_bmsk=0;
- unsigned int is_not_aligned=FALSE;
- unsigned char data[4];
- unsigned char *buff_ptr=data_ptr;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
+ unsigned int bytes_left = 0;
+ unsigned int i = 0;
+ unsigned int ce_status = 0;
+ unsigned int ce_err_bmsk = 0;
+ unsigned int is_not_aligned = FALSE;
+ unsigned char data[4];
+ unsigned char *buff_ptr = data_ptr;
- /* Check if the buff_ptr is aligned */
- if(!(IS_ALIGNED(buff_ptr)))
- {
- is_not_aligned = TRUE;
- }
+ /* Check if the buff_ptr is aligned */
+ if (!(IS_ALIGNED(buff_ptr))) {
+ is_not_aligned = TRUE;
+ }
- /* Fill the saved_buff with data from buff_ptr. First we have to write
- all the data from the saved_buff and then we will write data from
- buff_ptr. We will update bytes_left and buff_ptr in the while loop
- once are done writing all the data from saved_buff. */
+ /* Fill the saved_buff with data from buff_ptr. First we have to write
+ all the data from the saved_buff and then we will write data from
+ buff_ptr. We will update bytes_left and buff_ptr in the while loop
+ once are done writing all the data from saved_buff. */
- if(sha1_ctx->saved_buff_indx != 0)
- {
- memcpy(sha1_ctx->saved_buff + sha1_ctx->saved_buff_indx, buff_ptr,
- (((buff_size + sha1_ctx->saved_buff_indx) <= CRYPTO_SHA_BLOCK_SIZE)
- ? buff_size : (CRYPTO_SHA_BLOCK_SIZE - sha1_ctx->saved_buff_indx)));
+ if (sha1_ctx->saved_buff_indx != 0) {
+ memcpy(sha1_ctx->saved_buff + sha1_ctx->saved_buff_indx,
+ buff_ptr,
+ (((buff_size + sha1_ctx->saved_buff_indx) <=
+ CRYPTO_SHA_BLOCK_SIZE)
+ ? buff_size : (CRYPTO_SHA_BLOCK_SIZE -
+ sha1_ctx->saved_buff_indx)));
- if(bytes_to_write >= CRYPTO_SHA_BLOCK_SIZE)
- {
- bytes_left = CRYPTO_SHA_BLOCK_SIZE;
- }
- else
- {
- bytes_left = bytes_to_write;
- }
- }
- else
- {
- bytes_left = bytes_to_write;
- }
+ if (bytes_to_write >= CRYPTO_SHA_BLOCK_SIZE) {
+ bytes_left = CRYPTO_SHA_BLOCK_SIZE;
+ } else {
+ bytes_left = bytes_to_write;
+ }
+ } else {
+ bytes_left = bytes_to_write;
+ }
- /* Error bitmask to check crypto engine status */
- ce_err_bmsk = (SW_ERR | DIN_RDY | DIN_SIZE_AVAIL);
+ /* Error bitmask to check crypto engine status */
+ ce_err_bmsk = (SW_ERR | DIN_RDY | DIN_SIZE_AVAIL);
- while(bytes_left >= 4)
- {
- ce_status = rd_ce(CRYPTO3_STATUS);
- ce_status &= ce_err_bmsk;
+ while (bytes_left >= 4) {
+ ce_status = rd_ce(CRYPTO3_STATUS);
+ ce_status &= ce_err_bmsk;
- if(ce_status & SW_ERR)
- {
- /* If there is SW_ERR, reset the engine */
- crypto_eng_reset();
- *ret_status = CRYPTO_ERR_FAIL;
- dprintf(CRITICAL, "crypto_send_data sw error\n");
- return;
- }
+ if (ce_status & SW_ERR) {
+ /* If there is SW_ERR, reset the engine */
+ crypto_eng_reset();
+ *ret_status = CRYPTO_ERR_FAIL;
+ dprintf(CRITICAL, "crypto_send_data sw error\n");
+ return;
+ }
- /* We can write data now - 4 bytes at a time in network byte order */
- if((ce_status & DIN_RDY) && ((ce_status & DIN_SIZE_AVAIL) >= 4))
- {
- if(sha1_ctx->saved_buff_indx != 0)
- {
- /* Write from saved_buff */
- wr_ce(htonl(*((unsigned int *)(sha1_ctx->saved_buff)+i)),CRYPTO3_DATA_IN);
- }
- else
- {
- if(!is_not_aligned)
- {
- /* Write from buff_ptr aligned */
- wr_ce(htonl(*((unsigned int *)buff_ptr+i)),CRYPTO3_DATA_IN);
- }
- else
- {
- /* If buff_ptr is not aligned write byte by byte */
- data[0] = *(buff_ptr+i);
- data[1] = *(buff_ptr+i+1);
- data[2] = *(buff_ptr+i+2);
- data[3] = *(buff_ptr+i+3);
- /* i will incremented by 1 in outside block */
- i+=3;
- wr_ce(htonl(*(unsigned int *)data),CRYPTO3_DATA_IN);
- memset(data,0,4);
- }
- }
- i++;
- bytes_left -=4;
+ /* We can write data now - 4 bytes at a time in network byte order */
+ if ((ce_status & DIN_RDY)
+ && ((ce_status & DIN_SIZE_AVAIL) >= 4)) {
+ if (sha1_ctx->saved_buff_indx != 0) {
+ /* Write from saved_buff */
+ wr_ce(htonl
+ (*
+ ((unsigned int *)(sha1_ctx->saved_buff) +
+ i)), CRYPTO3_DATA_IN);
+ } else {
+ if (!is_not_aligned) {
+ /* Write from buff_ptr aligned */
+ wr_ce(htonl
+ (*((unsigned int *)buff_ptr + i)),
+ CRYPTO3_DATA_IN);
+ } else {
+ /* If buff_ptr is not aligned write byte by byte */
+ data[0] = *(buff_ptr + i);
+ data[1] = *(buff_ptr + i + 1);
+ data[2] = *(buff_ptr + i + 2);
+ data[3] = *(buff_ptr + i + 3);
+ /* i will incremented by 1 in outside block */
+ i += 3;
+ wr_ce(htonl(*(unsigned int *)data),
+ CRYPTO3_DATA_IN);
+ memset(data, 0, 4);
+ }
+ }
+ i++;
+ bytes_left -= 4;
- /* Check if we have written from saved_buff. Adjust buff_ptr and
- bytes_left accordingly */
- if((sha1_ctx->saved_buff_indx != 0) && (bytes_left == 0) &&
- (bytes_to_write > CRYPTO_SHA_BLOCK_SIZE))
- {
- bytes_left = (bytes_to_write - CRYPTO_SHA_BLOCK_SIZE);
- buff_ptr = (unsigned char *)((unsigned char *)data_ptr +
- CRYPTO_SHA_BLOCK_SIZE - sha1_ctx->saved_buff_indx);
- i = 0;
- sha1_ctx->saved_buff_indx = 0;
- if(!(IS_ALIGNED(buff_ptr)))
- {
- is_not_aligned = TRUE;
- }
- }
- }
- }
+ /* Check if we have written from saved_buff. Adjust buff_ptr and
+ bytes_left accordingly */
+ if ((sha1_ctx->saved_buff_indx != 0)
+ && (bytes_left == 0)
+ && (bytes_to_write > CRYPTO_SHA_BLOCK_SIZE)) {
+ bytes_left =
+ (bytes_to_write - CRYPTO_SHA_BLOCK_SIZE);
+ buff_ptr =
+ (unsigned char *)((unsigned char *)data_ptr
+ + CRYPTO_SHA_BLOCK_SIZE -
+ sha1_ctx->
+ saved_buff_indx);
+ i = 0;
+ sha1_ctx->saved_buff_indx = 0;
+ if (!(IS_ALIGNED(buff_ptr))) {
+ is_not_aligned = TRUE;
+ }
+ }
+ }
+ }
- /* We might have bytes_left < 4. Write them now if available */
- if(bytes_left)
- {
- memset(data,0,sizeof(unsigned int));
+ /* We might have bytes_left < 4. Write them now if available */
+ if (bytes_left) {
+ memset(data, 0, sizeof(unsigned int));
- if(sha1_ctx->saved_buff_indx)
- buff_ptr = (sha1_ctx->saved_buff + bytes_to_write - 1);
- else
- buff_ptr = (((unsigned char *)data_ptr) + buff_size - 1);
+ if (sha1_ctx->saved_buff_indx)
+ buff_ptr = (sha1_ctx->saved_buff + bytes_to_write - 1);
+ else
+ buff_ptr =
+ (((unsigned char *)data_ptr) + buff_size - 1);
- for(i=0;i<bytes_left;i++)
- {
- data[3-i] = *(buff_ptr-bytes_left+i+1);
- }
+ for (i = 0; i < bytes_left; i++) {
+ data[3 - i] = *(buff_ptr - bytes_left + i + 1);
+ }
- ce_status = rd_ce(CRYPTO3_STATUS);
- ce_status &= ce_err_bmsk;
+ ce_status = rd_ce(CRYPTO3_STATUS);
+ ce_status &= ce_err_bmsk;
- if(ce_status & SW_ERR)
- {
- crypto_eng_reset();
- *ret_status = CRYPTO_ERR_FAIL;
- dprintf(CRITICAL, "crypto_send_data sw error 2\n");
- return;
- }
- if((ce_status & DIN_RDY) && ((ce_status & DIN_SIZE_AVAIL) >= 4))
- {
- wr_ce(*(unsigned int *)data,CRYPTO3_DATA_IN);
- }
- }
- *ret_status = CRYPTO_ERR_NONE;
- return;
+ if (ce_status & SW_ERR) {
+ crypto_eng_reset();
+ *ret_status = CRYPTO_ERR_FAIL;
+ dprintf(CRITICAL, "crypto_send_data sw error 2\n");
+ return;
+ }
+ if ((ce_status & DIN_RDY)
+ && ((ce_status & DIN_SIZE_AVAIL) >= 4)) {
+ wr_ce(*(unsigned int *)data, CRYPTO3_DATA_IN);
+ }
+ }
+ *ret_status = CRYPTO_ERR_NONE;
+ return;
}
/*
* Function to get digest from CRYPTO3. We poll for AUTH_DONE from CRYPTO3.
*/
-void crypto_get_digest(unsigned char *digest_ptr, unsigned int *ret_status,
- crypto_auth_alg_type auth_alg, bool last)
+void
+crypto_get_digest(unsigned char *digest_ptr, unsigned int *ret_status,
+ crypto_auth_alg_type auth_alg, bool last)
{
- unsigned int ce_status=0;
- unsigned int ce_err_bmsk = (AUTH_DONE | SW_ERR);
- unsigned int i=0;
- unsigned int digest_len=0;
+ unsigned int ce_status = 0;
+ unsigned int ce_err_bmsk = (AUTH_DONE | SW_ERR);
+ unsigned int i = 0;
+ unsigned int digest_len = 0;
- do
- {
- ce_status = rd_ce(CRYPTO3_STATUS);
- ce_status &= ce_err_bmsk;
- }while (ce_status == 0);
+ do {
+ ce_status = rd_ce(CRYPTO3_STATUS);
+ ce_status &= ce_err_bmsk;
+ }
+ while (ce_status == 0);
- if(ce_status & SW_ERR)
- {
- crypto_eng_reset();
- *ret_status = CRYPTO_ERR_FAIL;
- dprintf(CRITICAL, "crypto_get_digest sw error\n");
- return;
- }
+ if (ce_status & SW_ERR) {
+ crypto_eng_reset();
+ *ret_status = CRYPTO_ERR_FAIL;
+ dprintf(CRITICAL, "crypto_get_digest sw error\n");
+ return;
+ }
- /* Digest length depends on auth_alg */
+ /* Digest length depends on auth_alg */
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
- digest_len = SHA1_INIT_VECTOR_SIZE;
- }
- else if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
- digest_len = SHA256_INIT_VECTOR_SIZE;
- }
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
+ digest_len = SHA1_INIT_VECTOR_SIZE;
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
+ digest_len = SHA256_INIT_VECTOR_SIZE;
+ }
- /* Retrieve digest from CRYPTO3 */
+ /* Retrieve digest from CRYPTO3 */
- for(i=0; i < digest_len;i++)
- {
- unsigned int auth_iv = rd_ce(CRYPTO3_AUTH_IVn(i));
+ for (i = 0; i < digest_len; i++) {
+ unsigned int auth_iv = rd_ce(CRYPTO3_AUTH_IVn(i));
- if(last)
- {
- *((unsigned int *)digest_ptr + i) = htonl(auth_iv);
- }
- else
- {
- *((unsigned int *)digest_ptr + i) = auth_iv;
- }
- }
- *ret_status = CRYPTO_ERR_NONE;
- return;
+ if (last) {
+ *((unsigned int *)digest_ptr + i) = htonl(auth_iv);
+ } else {
+ *((unsigned int *)digest_ptr + i) = auth_iv;
+ }
+ }
+ *ret_status = CRYPTO_ERR_NONE;
+ return;
}
/* Function to restore auth_bytecnt registers for ctx_ptr */
void crypto_get_ctx(void *ctx_ptr)
{
- ((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[0] = rd_ce(CRYPTO3_AUTH_BYTECNTn(0));
- ((crypto_SHA1_ctx*)ctx_ptr)->auth_bytecnt[1] = rd_ce(CRYPTO3_AUTH_BYTECNTn(1));
- return;
+ ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0] =
+ rd_ce(CRYPTO3_AUTH_BYTECNTn(0));
+ ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1] =
+ rd_ce(CRYPTO3_AUTH_BYTECNTn(1));
+ return;
}
diff --git a/platform/msm_shared/crypto_hash.c b/platform/msm_shared/crypto_hash.c
index bf869f5..d431f42 100644
--- a/platform/msm_shared/crypto_hash.c
+++ b/platform/msm_shared/crypto_hash.c
@@ -43,24 +43,21 @@
* It works on contiguous data and does single pass calculation.
*/
-void hash_find(unsigned char *addr, unsigned int size, unsigned char *digest,
- unsigned char auth_alg)
+void
+hash_find(unsigned char *addr, unsigned int size, unsigned char *digest,
+ unsigned char auth_alg)
{
- crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
+ crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
- if(auth_alg == 1)
- {
- ret_val = crypto_sha1(addr,size,digest);
- }
- else if(auth_alg == 2)
- {
- ret_val = crypto_sha256(addr,size,digest);
- }
+ if (auth_alg == 1) {
+ ret_val = crypto_sha1(addr, size, digest);
+ } else if (auth_alg == 2) {
+ ret_val = crypto_sha256(addr, size, digest);
+ }
- if(ret_val != CRYPTO_SHA_ERR_NONE)
- {
- dprintf(CRITICAL, "crypto_sha256 returns error %d\n",ret_val);
- }
+ if (ret_val != CRYPTO_SHA_ERR_NONE) {
+ dprintf(CRITICAL, "crypto_sha256 returns error %d\n", ret_val);
+ }
}
/*
@@ -70,78 +67,75 @@
static void crypto_init(void)
{
- if(crypto_init_done != TRUE)
- {
- ce_clock_init();
- crypto_eng_reset();
- crypto_init_done = TRUE;
- }
- crypto_eng_init();
+ if (crypto_init_done != TRUE) {
+ ce_clock_init();
+ crypto_eng_reset();
+ crypto_init_done = TRUE;
+ }
+ crypto_eng_init();
}
/*
* Function to initialize SHA256 context
*/
-static crypto_result_type crypto_sha256_init(crypto_SHA256_ctx *ctx_ptr)
+static crypto_result_type crypto_sha256_init(crypto_SHA256_ctx * ctx_ptr)
{
- unsigned int i;
- /* Standard initialization vector for SHA256 */
- unsigned int sha256_init_vector[] = { 0x6A09E667, 0xBB67AE85,
- 0x3C6EF372, 0xA54FF53A,
- 0x510E527F, 0x9B05688C,
- 0x1F83D9AB, 0x5BE0CD19 };
+ unsigned int i;
+ /* Standard initialization vector for SHA256 */
+ unsigned int sha256_init_vector[] = { 0x6A09E667, 0xBB67AE85,
+ 0x3C6EF372, 0xA54FF53A,
+ 0x510E527F, 0x9B05688C,
+ 0x1F83D9AB, 0x5BE0CD19
+ };
- if(ctx_ptr == NULL)
- {
- return CRYPTO_SHA_ERR_INVALID_PARAM;
- }
+ if (ctx_ptr == NULL) {
+ return CRYPTO_SHA_ERR_INVALID_PARAM;
+ }
- ctx_ptr->auth_bytecnt[0] = 0;
- ctx_ptr->auth_bytecnt[1] = 0;
+ ctx_ptr->auth_bytecnt[0] = 0;
+ ctx_ptr->auth_bytecnt[1] = 0;
- memset(ctx_ptr->saved_buff, 0, CRYPTO_SHA_BLOCK_SIZE);
+ memset(ctx_ptr->saved_buff, 0, CRYPTO_SHA_BLOCK_SIZE);
- for(i=0;i<SHA256_INIT_VECTOR_SIZE;i++)
- {
- ctx_ptr->auth_iv[i] = sha256_init_vector[i];
- }
+ for (i = 0; i < SHA256_INIT_VECTOR_SIZE; i++) {
+ ctx_ptr->auth_iv[i] = sha256_init_vector[i];
+ }
- ctx_ptr->saved_buff_indx = 0;
+ ctx_ptr->saved_buff_indx = 0;
- return CRYPTO_SHA_ERR_NONE;
+ return CRYPTO_SHA_ERR_NONE;
}
/*
* Function to initialize SHA1 context
*/
-static crypto_result_type crypto_sha1_init(crypto_SHA1_ctx *ctx_ptr)
+static crypto_result_type crypto_sha1_init(crypto_SHA1_ctx * ctx_ptr)
{
- unsigned int i;
- /* Standard initialization vector for SHA1 */
- unsigned int sha1_init_vector[] = { 0x67452301, 0xEFCDAB89,
- 0x98BADCFE, 0x10325476,
- 0xC3D2E1F0 };
+ unsigned int i;
+ /* Standard initialization vector for SHA1 */
+ unsigned int sha1_init_vector[] = { 0x67452301, 0xEFCDAB89,
+ 0x98BADCFE, 0x10325476,
+ 0xC3D2E1F0
+ };
- if(ctx_ptr == NULL)
- {
- return CRYPTO_SHA_ERR_INVALID_PARAM;
- }
+ if (ctx_ptr == NULL) {
+ return CRYPTO_SHA_ERR_INVALID_PARAM;
+ }
- ctx_ptr->auth_bytecnt[0] = 0;
- ctx_ptr->auth_bytecnt[1] = 0;
+ ctx_ptr->auth_bytecnt[0] = 0;
+ ctx_ptr->auth_bytecnt[1] = 0;
- memset(ctx_ptr->saved_buff, 0, CRYPTO_SHA_BLOCK_SIZE);
+ memset(ctx_ptr->saved_buff, 0, CRYPTO_SHA_BLOCK_SIZE);
- for(i=0;i<SHA1_INIT_VECTOR_SIZE;i++)
- {
- ctx_ptr->auth_iv[i] = sha1_init_vector[i];
- }
+ for (i = 0; i < SHA1_INIT_VECTOR_SIZE; i++) {
+ ctx_ptr->auth_iv[i] = sha1_init_vector[i];
+ }
- ctx_ptr->saved_buff_indx = 0;
+ ctx_ptr->saved_buff_indx = 0;
- return CRYPTO_SHA_ERR_NONE;
+ return CRYPTO_SHA_ERR_NONE;
}
/*
@@ -149,29 +143,28 @@
* It works on contiguous data and gives digest in single pass.
*/
-static crypto_result_type crypto_sha256(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr)
+static crypto_result_type
+crypto_sha256(unsigned char *buff_ptr,
+ unsigned int buff_size, unsigned char *digest_ptr)
{
- crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
+ crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
- if((!buff_size) || (buff_ptr == NULL) || (digest_ptr == NULL))
- {
- return CRYPTO_SHA_ERR_INVALID_PARAM;
- }
+ if ((!buff_size) || (buff_ptr == NULL) || (digest_ptr == NULL)) {
+ return CRYPTO_SHA_ERR_INVALID_PARAM;
+ }
- /* Initialize crypto engine hardware for a new SHA256 operation */
- crypto_init();
+ /* Initialize crypto engine hardware for a new SHA256 operation */
+ crypto_init();
- /* Now do SHA256 hashing */
- ret_val = do_sha(buff_ptr, buff_size, digest_ptr, CRYPTO_AUTH_ALG_SHA256);
+ /* Now do SHA256 hashing */
+ ret_val =
+ do_sha(buff_ptr, buff_size, digest_ptr, CRYPTO_AUTH_ALG_SHA256);
- if(ret_val != CRYPTO_SHA_ERR_NONE)
- {
- dprintf(CRITICAL, "crypto_sha256 returns error %d\n",ret_val);
- }
+ if (ret_val != CRYPTO_SHA_ERR_NONE) {
+ dprintf(CRITICAL, "crypto_sha256 returns error %d\n", ret_val);
+ }
- return ret_val;
+ return ret_val;
}
/*
@@ -179,74 +172,70 @@
* It works on contiguous data and gives digest in single pass.
*/
-static crypto_result_type crypto_sha1(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr)
+static crypto_result_type
+crypto_sha1(unsigned char *buff_ptr,
+ unsigned int buff_size, unsigned char *digest_ptr)
{
- crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
+ crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
- if((!buff_size) || (buff_ptr == NULL) || (digest_ptr == NULL))
- {
- return CRYPTO_SHA_ERR_INVALID_PARAM;
- }
+ if ((!buff_size) || (buff_ptr == NULL) || (digest_ptr == NULL)) {
+ return CRYPTO_SHA_ERR_INVALID_PARAM;
+ }
- /* Initialize crypto engine hardware for a new SHA1 operation */
- crypto_init();
+ /* Initialize crypto engine hardware for a new SHA1 operation */
+ crypto_init();
- /* Now do SHA1 hashing */
- ret_val = do_sha(buff_ptr, buff_size, digest_ptr, CRYPTO_AUTH_ALG_SHA1);
+ /* Now do SHA1 hashing */
+ ret_val = do_sha(buff_ptr, buff_size, digest_ptr, CRYPTO_AUTH_ALG_SHA1);
- if(ret_val != CRYPTO_SHA_ERR_NONE)
- {
- dprintf(CRITICAL, "crypto_sha256 returns error %d\n",ret_val);
- }
+ if (ret_val != CRYPTO_SHA_ERR_NONE) {
+ dprintf(CRITICAL, "crypto_sha256 returns error %d\n", ret_val);
+ }
- return ret_val;
+ return ret_val;
}
/*
* Common function to calculate SHA1 and SHA256 digest based on auth algorithm.
*/
-static crypto_result_type do_sha(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr,
- crypto_auth_alg_type auth_alg)
+static crypto_result_type
+do_sha(unsigned char *buff_ptr,
+ unsigned int buff_size,
+ unsigned char *digest_ptr, crypto_auth_alg_type auth_alg)
{
- void *ctx_ptr=NULL;
- crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
+ void *ctx_ptr = NULL;
+ crypto_result_type ret_val = CRYPTO_SHA_ERR_NONE;
- /* Initialize SHA context based on algorithm */
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
- crypto_sha1_init(&g_sha1_ctx);
- ctx_ptr = (void*)&g_sha1_ctx;
- }
- else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
- crypto_sha256_init(&g_sha256_ctx);
- ctx_ptr = (void*)&g_sha256_ctx;
- }
+ /* Initialize SHA context based on algorithm */
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
+ crypto_sha1_init(&g_sha1_ctx);
+ ctx_ptr = (void *)&g_sha1_ctx;
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
+ crypto_sha256_init(&g_sha256_ctx);
+ ctx_ptr = (void *)&g_sha256_ctx;
+ }
- ret_val = do_sha_update(ctx_ptr, buff_ptr, buff_size, auth_alg, TRUE, TRUE);
+ ret_val =
+ do_sha_update(ctx_ptr, buff_ptr, buff_size, auth_alg, TRUE, TRUE);
- if(ret_val != CRYPTO_SHA_ERR_NONE)
- {
- dprintf(CRITICAL, "do_sha_update returns error %d\n",ret_val);
- return ret_val;
- }
+ if (ret_val != CRYPTO_SHA_ERR_NONE) {
+ dprintf(CRITICAL, "do_sha_update returns error %d\n", ret_val);
+ return ret_val;
+ }
- /* Copy the digest value from context pointer to digest pointer */
- if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
- {
- memcpy(digest_ptr, (unsigned char*)(((crypto_SHA1_ctx*)ctx_ptr)->auth_iv), 20);
- }
- else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
- {
- memcpy(digest_ptr, (unsigned char*)(((crypto_SHA256_ctx*)ctx_ptr)->auth_iv), 32);
- }
+ /* Copy the digest value from context pointer to digest pointer */
+ if (auth_alg == CRYPTO_AUTH_ALG_SHA1) {
+ memcpy(digest_ptr,
+ (unsigned char *)(((crypto_SHA1_ctx *) ctx_ptr)->
+ auth_iv), 20);
+ } else if (auth_alg == CRYPTO_AUTH_ALG_SHA256) {
+ memcpy(digest_ptr,
+ (unsigned char *)(((crypto_SHA256_ctx *) ctx_ptr)->
+ auth_iv), 32);
+ }
- return CRYPTO_SHA_ERR_NONE;
+ return CRYPTO_SHA_ERR_NONE;
}
/*
@@ -255,140 +244,139 @@
* the digest.
*/
-static crypto_result_type do_sha_update(void *ctx_ptr,
- unsigned char *buff_ptr,
- unsigned int buff_size,
- crypto_auth_alg_type auth_alg,
- bool first, bool last)
+static crypto_result_type
+do_sha_update(void *ctx_ptr,
+ unsigned char *buff_ptr,
+ unsigned int buff_size,
+ crypto_auth_alg_type auth_alg, bool first, bool last)
{
- unsigned int ret_val = CRYPTO_ERR_NONE;
- unsigned int bytes_to_write = 0;
- unsigned int bytes_remaining = 0;
- unsigned int tmp_bytes = 0;
- unsigned int bytes_written = 0;
- unsigned int tmp_buff_size = 0;
- unsigned char *tmp_buff_ptr = NULL;
- unsigned char tmp_saved_buff_indx = 0;
- bool tmp_first;
- bool tmp_last;
+ unsigned int ret_val = CRYPTO_ERR_NONE;
+ unsigned int bytes_to_write = 0;
+ unsigned int bytes_remaining = 0;
+ unsigned int tmp_bytes = 0;
+ unsigned int bytes_written = 0;
+ unsigned int tmp_buff_size = 0;
+ unsigned char *tmp_buff_ptr = NULL;
+ unsigned char tmp_saved_buff_indx = 0;
+ bool tmp_first;
+ bool tmp_last;
- /* Type casting to SHA1 context as offset is similar for SHA256 context */
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
+ /* Type casting to SHA1 context as offset is similar for SHA256 context */
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
- bytes_to_write = calc_num_bytes_to_send(ctx_ptr, buff_size, last);
- bytes_remaining = buff_size + sha1_ctx->saved_buff_indx - bytes_to_write;
+ bytes_to_write = calc_num_bytes_to_send(ctx_ptr, buff_size, last);
+ bytes_remaining =
+ buff_size + sha1_ctx->saved_buff_indx - bytes_to_write;
- tmp_first = first;
- tmp_saved_buff_indx = sha1_ctx->saved_buff_indx;
+ tmp_first = first;
+ tmp_saved_buff_indx = sha1_ctx->saved_buff_indx;
- do
- {
- if((bytes_to_write - bytes_written) > CRYPTO_MAX_AUTH_BLOCK_SIZE)
- {
- /* Write CRYPTO_MAX_AUTH_BLOCK_SIZE bytes at a time to the CE */
- tmp_bytes = CRYPTO_MAX_AUTH_BLOCK_SIZE;
- tmp_last = FALSE;
+ do {
+ if ((bytes_to_write - bytes_written) >
+ CRYPTO_MAX_AUTH_BLOCK_SIZE) {
+ /* Write CRYPTO_MAX_AUTH_BLOCK_SIZE bytes at a time to the CE */
+ tmp_bytes = CRYPTO_MAX_AUTH_BLOCK_SIZE;
+ tmp_last = FALSE;
- if(sha1_ctx->saved_buff_indx != 0)
- {
- tmp_buff_ptr = buff_ptr;
- tmp_buff_size = tmp_bytes - sha1_ctx->saved_buff_indx;
- }
- else
- {
- tmp_buff_ptr = buff_ptr + bytes_written - tmp_saved_buff_indx;
- tmp_buff_size = tmp_bytes;
- }
- }
- else
- {
- /* Since bytes_to_write are less than CRYPTO_MAX_AUTH_BLOCK_SIZE
- write all remaining bytes now */
- if(sha1_ctx->saved_buff_indx != 0)
- {
- tmp_buff_ptr = buff_ptr;
- tmp_buff_size = bytes_to_write - bytes_written - sha1_ctx->saved_buff_indx;
- }
- else
- {
- tmp_buff_ptr = buff_ptr + bytes_written - tmp_saved_buff_indx;
- tmp_buff_size = bytes_to_write - bytes_written - tmp_saved_buff_indx;
- }
+ if (sha1_ctx->saved_buff_indx != 0) {
+ tmp_buff_ptr = buff_ptr;
+ tmp_buff_size =
+ tmp_bytes - sha1_ctx->saved_buff_indx;
+ } else {
+ tmp_buff_ptr =
+ buff_ptr + bytes_written -
+ tmp_saved_buff_indx;
+ tmp_buff_size = tmp_bytes;
+ }
+ } else {
+ /* Since bytes_to_write are less than CRYPTO_MAX_AUTH_BLOCK_SIZE
+ write all remaining bytes now */
+ if (sha1_ctx->saved_buff_indx != 0) {
+ tmp_buff_ptr = buff_ptr;
+ tmp_buff_size =
+ bytes_to_write - bytes_written -
+ sha1_ctx->saved_buff_indx;
+ } else {
+ tmp_buff_ptr =
+ buff_ptr + bytes_written -
+ tmp_saved_buff_indx;
+ tmp_buff_size =
+ bytes_to_write - bytes_written -
+ tmp_saved_buff_indx;
+ }
- tmp_bytes = (bytes_to_write - bytes_written);
- tmp_last = last;
- }
+ tmp_bytes = (bytes_to_write - bytes_written);
+ tmp_last = last;
+ }
- /* Set SHAx context in the crypto engine */
- crypto_set_sha_ctx(ctx_ptr, tmp_bytes, auth_alg, tmp_first, tmp_last);
+ /* Set SHAx context in the crypto engine */
+ crypto_set_sha_ctx(ctx_ptr, tmp_bytes, auth_alg, tmp_first,
+ tmp_last);
- /* Send data to the crypto engine */
- crypto_send_data(ctx_ptr, tmp_buff_ptr, tmp_buff_size, tmp_bytes, &ret_val);
+ /* Send data to the crypto engine */
+ crypto_send_data(ctx_ptr, tmp_buff_ptr, tmp_buff_size,
+ tmp_bytes, &ret_val);
- if(ret_val != CRYPTO_ERR_NONE)
- {
- dprintf(CRITICAL, "do_sha_update returns error from crypto_send_data\n");
- return CRYPTO_SHA_ERR_FAIL;
- }
+ if (ret_val != CRYPTO_ERR_NONE) {
+ dprintf(CRITICAL,
+ "do_sha_update returns error from crypto_send_data\n");
+ return CRYPTO_SHA_ERR_FAIL;
+ }
- /* Get the SHAx digest from the crypto engine */
- crypto_get_digest((unsigned char *)(sha1_ctx->auth_iv), &ret_val, auth_alg, tmp_last);
+ /* Get the SHAx digest from the crypto engine */
+ crypto_get_digest((unsigned char *)(sha1_ctx->auth_iv),
+ &ret_val, auth_alg, tmp_last);
- if(ret_val != CRYPTO_ERR_NONE)
- {
- dprintf(CRITICAL, "do_sha_update returns error from crypto_get_digest\n");
- return CRYPTO_SHA_ERR_FAIL;
- }
+ if (ret_val != CRYPTO_ERR_NONE) {
+ dprintf(CRITICAL,
+ "do_sha_update returns error from crypto_get_digest\n");
+ return CRYPTO_SHA_ERR_FAIL;
+ }
- if(!tmp_last)
- {
- crypto_get_ctx(ctx_ptr);
- }
+ if (!tmp_last) {
+ crypto_get_ctx(ctx_ptr);
+ }
- bytes_written += tmp_bytes;
- sha1_ctx->saved_buff_indx = 0;
+ bytes_written += tmp_bytes;
+ sha1_ctx->saved_buff_indx = 0;
- if(bytes_written != bytes_to_write)
- {
- tmp_first = FALSE;
- }
+ if (bytes_written != bytes_to_write) {
+ tmp_first = FALSE;
+ }
- }while ((bytes_to_write - bytes_written) != 0);
+ }
+ while ((bytes_to_write - bytes_written) != 0);
- /* If there are bytes remaining, copy it to saved_buff */
+ /* If there are bytes remaining, copy it to saved_buff */
- if(bytes_remaining)
- {
- memcpy(sha1_ctx->saved_buff, (buff_ptr + buff_size - bytes_remaining),
- bytes_remaining);
- sha1_ctx->saved_buff_indx = bytes_remaining;
- }
- else
- {
- sha1_ctx->saved_buff_indx = 0;
- }
+ if (bytes_remaining) {
+ memcpy(sha1_ctx->saved_buff,
+ (buff_ptr + buff_size - bytes_remaining),
+ bytes_remaining);
+ sha1_ctx->saved_buff_indx = bytes_remaining;
+ } else {
+ sha1_ctx->saved_buff_indx = 0;
+ }
- return CRYPTO_SHA_ERR_NONE;
+ return CRYPTO_SHA_ERR_NONE;
}
/*
* Function to calculate the number of bytes to be sent to crypto engine.
*/
-static unsigned int calc_num_bytes_to_send(void *ctx_ptr,
- unsigned int buff_size, bool last)
+static unsigned int
+calc_num_bytes_to_send(void *ctx_ptr, unsigned int buff_size, bool last)
{
- unsigned int bytes_to_write=0;
- crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx*)ctx_ptr;
+ unsigned int bytes_to_write = 0;
+ crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
- if(last)
- {
- bytes_to_write = buff_size + sha1_ctx->saved_buff_indx;
- }
- else
- {
- bytes_to_write = ((buff_size + sha1_ctx->saved_buff_indx)/
- CRYPTO_SHA_BLOCK_SIZE) * CRYPTO_SHA_BLOCK_SIZE;
- }
- return bytes_to_write;
+ if (last) {
+ bytes_to_write = buff_size + sha1_ctx->saved_buff_indx;
+ } else {
+ bytes_to_write = ((buff_size + sha1_ctx->saved_buff_indx) /
+ CRYPTO_SHA_BLOCK_SIZE) *
+ CRYPTO_SHA_BLOCK_SIZE;
+ }
+ return bytes_to_write;
}
diff --git a/platform/msm_shared/debug.c b/platform/msm_shared/debug.c
index 9adc4e4..3370fe3 100644
--- a/platform/msm_shared/debug.c
+++ b/platform/msm_shared/debug.c
@@ -40,9 +40,9 @@
{
#if WITH_DEBUG_DCC
if (c == '\n') {
- while (dcc_putc('\r') < 0);
+ while (dcc_putc('\r') < 0) ;
}
- while (dcc_putc(c) < 0);
+ while (dcc_putc(c) < 0) ;
#endif
#if WITH_DEBUG_UART
uart_putc(0, c);
@@ -76,6 +76,5 @@
void platform_halt(void)
{
dprintf(INFO, "HALT: spinning forever...\n");
- for(;;);
+ for (;;) ;
}
-
diff --git a/platform/msm_shared/dmov.h b/platform/msm_shared/dmov.h
index 0f8008f..d63fcce 100644
--- a/platform/msm_shared/dmov.h
+++ b/platform/msm_shared/dmov.h
@@ -32,14 +32,13 @@
#ifdef PLATFORM_MSM7X30
#define MSM_DMOV_BASE 0xAC400000
#else
-#ifdef PLATFORM_MDM9X15 //TODO: Move to IOMAP
+#ifdef PLATFORM_MDM9X15 //TODO: Move to IOMAP
#define MSM_DMOV_BASE 0x18300000
#else
#define MSM_DMOV_BASE 0xA9700000
#endif
#endif
-
#ifdef PLATFORM_MDM9X15
#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x00000 + (off) + ((ch) << 2))
#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x20800 + (off) + ((ch) << 2))
@@ -63,7 +62,6 @@
#endif
#endif
-
/* only security domain 3 is available to the ARM11
**
** SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
@@ -71,18 +69,18 @@
*/
#define DMOV_CMD_PTR(ch) DMOV_SDn(0x000, ch)
-#define DMOV_CMD_LIST (0 << 29) /* does not work */
-#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
-#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
-#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
+#define DMOV_CMD_LIST (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
#define DMOV_RSLT(ch) DMOV_SDn(0x040, ch)
-#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
#define DMOV_RSLT_ERROR (1 << 3)
#define DMOV_RSLT_FLUSH (1 << 2)
-#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
-#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
+#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
+#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
#define DMOV_FLUSH0(ch) DMOV_SDn(0x080, ch)
#define DMOV_FLUSH1(ch) DMOV_SDn(0x0C0, ch)
@@ -93,7 +91,7 @@
#define DMOV_STATUS(ch) DMOV_SDn(0x200, ch)
#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
-#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
+#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
#define DMOV_STATUS_RSLT_VALID (1 << 1)
#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
@@ -130,7 +128,6 @@
/* no client rate control ifc (eg, ram) */
#define DMOV_NONE_CRCI 0
-
/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
** is going to walk a list of 32bit pointers as described below. Each
** pointer points to a *array* of dmov_s, etc structs. The last pointer
@@ -138,56 +135,54 @@
** is marked with CMD_LC (see below).
*/
#define CMD_PTR_ADDR(addr) ((addr) >> 3)
-#define CMD_PTR_LP (1 << 31) /* last pointer */
-#define CMD_PTR_PT (3 << 29) /* ? */
-
+#define CMD_PTR_LP (1 << 31) /* last pointer */
+#define CMD_PTR_PT (3 << 29) /* ? */
/* Single Item Mode -- seems to work as expected */
typedef struct {
- unsigned cmd;
- unsigned src;
- unsigned dst;
- unsigned len;
+ unsigned cmd;
+ unsigned src;
+ unsigned dst;
+ unsigned len;
} dmov_s;
/* Scatter/Gather Mode -- does this work?*/
typedef struct {
- unsigned cmd;
- unsigned src_dscr;
- unsigned dst_dscr;
- unsigned _reserved;
+ unsigned cmd;
+ unsigned src_dscr;
+ unsigned dst_dscr;
+ unsigned _reserved;
} dmov_sg;
/* bits for the cmd field of the above structures */
-#define CMD_LC (1 << 31) /* last command */
-#define CMD_FR (1 << 22) /* force result -- does not work? */
-#define CMD_OCU (1 << 21) /* other channel unblock */
-#define CMD_OCB (1 << 20) /* other channel block */
-#define CMD_TCB (1 << 19) /* ? */
-#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
-#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
+#define CMD_LC (1 << 31) /* last command */
+#define CMD_FR (1 << 22) /* force result -- does not work? */
+#define CMD_OCU (1 << 21) /* other channel unblock */
+#define CMD_OCB (1 << 20) /* other channel block */
+#define CMD_TCB (1 << 19) /* ? */
+#define CMD_DAH (1 << 18) /* destination address hold -- does not work? */
+#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
-#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
-#define CMD_MODE_SG (1 << 0) /* untested */
-#define CMD_MODE_IND_SG (2 << 0) /* untested */
-#define CMD_MODE_BOX (3 << 0) /* untested */
+#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG (1 << 0) /* untested */
+#define CMD_MODE_IND_SG (2 << 0) /* untested */
+#define CMD_MODE_BOX (3 << 0) /* untested */
-#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
-#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
-#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
+#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
-#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
-#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
-#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
+#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
#define CMD_DST_CRCI(n) (((n) & 15) << 7)
#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
-
/* NOTES:
**
** Looks like Channels 4, 5, 6, 7, 8, 10, 11 are available to the ARM11
**
*/
-#endif /* __PLATFORM_MSM_SHARED_DMOV_H */
+#endif /* __PLATFORM_MSM_SHARED_DMOV_H */
diff --git a/platform/msm_shared/hdmi.c b/platform/msm_shared/hdmi.c
index 7974ef6..3bb1a26 100644
--- a/platform/msm_shared/hdmi.c
+++ b/platform/msm_shared/hdmi.c
@@ -52,14 +52,14 @@
uint32_t val = 0;
if (on) {
val |= 0x00000003;
- writel(val,HDMI_CTRL);
+ writel(val, HDMI_CTRL);
} else {
val &= ~0x00000002;
- writel(val,HDMI_CTRL);
+ writel(val, HDMI_CTRL);
}
}
-struct hdmi_disp_mode_timing_type* hdmi_common_init_panel_info()
+struct hdmi_disp_mode_timing_type *hdmi_common_init_panel_info()
{
return &hdmi_timing_default;
}
@@ -77,16 +77,17 @@
uint32_t vsync_active = 0;
uint32_t hdmi_frame_ctrl = 0;
uint32_t val;
- struct hdmi_disp_mode_timing_type *hdmi_timing = hdmi_common_init_panel_info();
+ struct hdmi_disp_mode_timing_type *hdmi_timing =
+ hdmi_common_init_panel_info();
hsync_total = hdmi_timing->width + hdmi_timing->hsync_porch_fp
- + hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width - 1;
+ + hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width - 1;
vsync_total = hdmi_timing->height + hdmi_timing->vsync_porch_fp
- + hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
+ + hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
hvsync_total = (vsync_total << 16) & 0x0FFF0000;
hvsync_total |= (hsync_total << 0) & 0x00000FFF;
- writel(hvsync_total,HDMI_TOTAL);
+ writel(hvsync_total, HDMI_TOTAL);
hsync_start = hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width;
hsync_end = (hsync_total + 1) - hdmi_timing->hsync_porch_fp;
@@ -94,14 +95,15 @@
hsync_active |= (hsync_start << 0) & 0x00000FFF;
writel(hsync_active, HDMI_ACTIVE_HSYNC);
- vsync_start = hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
+ vsync_start =
+ hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1;
vsync_end = vsync_total - hdmi_timing->vsync_porch_fp;
vsync_active = (vsync_end << 16) & 0x0FFF0000;
vsync_active |= (vsync_start << 0) & 0x00000FFF;
writel(vsync_active, HDMI_ACTIVE_VSYNC);
- writel(0,HDMI_VSYNC_TOTAL_F2);
- writel(0,HDMI_VSYNC_ACTIVE_F2);
+ writel(0, HDMI_VSYNC_TOTAL_F2);
+ writel(0, HDMI_VSYNC_ACTIVE_F2);
hdmi_frame_ctrl_reg();
}
@@ -112,30 +114,29 @@
// Enable clocks
val = secure_readl(MISC_CC2_REG);
val |= BIT(11);
- secure_writel(val,MISC_CC2_REG);
+ secure_writel(val, MISC_CC2_REG);
udelay(10);
val = secure_readl(MMSS_AHB_EN_REG);
val |= BIT(14);
- secure_writel(val,MMSS_AHB_EN_REG);
+ secure_writel(val, MMSS_AHB_EN_REG);
udelay(10);
val = secure_readl(MMSS_AHB_EN_REG);
val |= BIT(4);
- secure_writel(val,MMSS_AHB_EN_REG);
+ secure_writel(val, MMSS_AHB_EN_REG);
udelay(10);
- }
- else {
+ } else {
// Disable clocks
val = secure_readl(MISC_CC2_REG);
val &= ~(BIT(11));
- secure_writel(val,MISC_CC2_REG);
+ secure_writel(val, MISC_CC2_REG);
udelay(10);
val = secure_readl(MMSS_AHB_EN_REG);
val &= ~(BIT(14));
- secure_writel(val,MMSS_AHB_EN_REG);
+ secure_writel(val, MMSS_AHB_EN_REG);
udelay(10);
val = secure_readl(MMSS_AHB_EN_REG);
val &= ~(BIT(4));
- secure_writel(val,MMSS_AHB_EN_REG);
+ secure_writel(val, MMSS_AHB_EN_REG);
udelay(10);
}
}
@@ -179,15 +180,16 @@
void hdmi_msm_turn_on(void)
{
uint32_t hotplug_control;
- hdmi_msm_reset_core(); // Reset the core
+ hdmi_msm_reset_core(); // Reset the core
hdmi_msm_init_phy();
// Enable USEC REF timer
- writel(0x0001001B,HDMI_USEC_REFTIMER);
+ writel(0x0001001B, HDMI_USEC_REFTIMER);
// Video setup for HDMI
hdmi_video_setup();
// Write 1 to HDMI_CTRL to enable HDMI
hdmi_msm_set_mode(1);
- dprintf(SPEW,"HDMI Core is: %s\n",(readl(HDMI_CTRL) & 0x00000001) ? "on":"off");
+ dprintf(SPEW, "HDMI Core is: %s\n",
+ (readl(HDMI_CTRL) & 0x00000001) ? "on" : "off");
}
struct fbcon_config *hdmi_dtv_init(struct hdmi_disp_mode_timing_type *timing)
@@ -217,7 +219,7 @@
unsigned char *overlay_base;
uint32_t val;
- dprintf(SPEW,"In DTV on function\n");
+ dprintf(SPEW, "In DTV on function\n");
// Turn on all the clocks
dtv_on();
@@ -228,14 +230,14 @@
fb_cfg.base = FB_ADDR;
// MDP E config
- writel((unsigned) fb_cfg.base, MDP_BASE + 0xb0008);//FB Address
+ writel((unsigned)fb_cfg.base, MDP_BASE + 0xb0008); //FB Address
writel(((fb_cfg.height << 16) | fb_cfg.width), MDP_BASE + 0xb0004);
writel((fb_cfg.width * fb_cfg.bpp / 8), MDP_BASE + 0xb000c);
writel(0, MDP_BASE + 0xb0010);
- writel(DMA_PACK_PATTERN_RGB|DMA_DSTC0G_8BITS|DMA_DSTC1B_8BITS|DMA_DSTC2R_8BITS,
- MDP_BASE + 0xb0000);
+ writel(DMA_PACK_PATTERN_RGB | DMA_DSTC0G_8BITS | DMA_DSTC1B_8BITS |
+ DMA_DSTC2R_8BITS, MDP_BASE + 0xb0000);
writel(0xff0000, MDP_BASE + 0xb0070);
writel(0xff0000, MDP_BASE + 0xb0074);
writel(0xff0000, MDP_BASE + 0xb0078);
@@ -247,13 +249,13 @@
writel(0x0, rgb_base + 0x0004);
writel(0x0, rgb_base + 0x0008);
writel(0x0, rgb_base + 0x000c);
- writel(fb_cfg.base, rgb_base + 0x0010); //FB address
+ writel(fb_cfg.base, rgb_base + 0x0010); //FB address
writel((fb_cfg.width * fb_cfg.bpp / 8), rgb_base + 0x0040);
- writel(0x24216, rgb_base + 0x0050); //format
- writel(0x20001, rgb_base + 0x0054); //pattern
+ writel(0x24216, rgb_base + 0x0050); //format
+ writel(0x20001, rgb_base + 0x0054); //pattern
writel(0x0, rgb_base + 0x0058);
- writel(0x20000000, rgb_base + 0x005c); //phaseX
- writel(0x20000000, rgb_base + 0x0060); // phaseY
+ writel(0x20000000, rgb_base + 0x005c); //phaseX
+ writel(0x20000000, rgb_base + 0x0060); // phaseY
// mdp4 mixer setup MDP4_MIXER1
data = readl(MDP_BASE + 0x10100);
@@ -264,12 +266,12 @@
stage <<= snum;
data &= ~mask;
data |= stage;
- writel(data, MDP_BASE + 0x10100); // Overlay CFG conf
+ writel(data, MDP_BASE + 0x10100); // Overlay CFG conf
data = readl(MDP_BASE + 0x10100);
// Overlay cfg
overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;
- writel(0x0, MDP_BASE + 0x0038); //EXternal interface select
+ writel(0x0, MDP_BASE + 0x0038); //EXternal interface select
data = ((timing->height << 16) | timing->width);
writel(data, overlay_base + 0x0008);
@@ -278,24 +280,30 @@
writel(0x10, overlay_base + 0x104);
writel(0x10, overlay_base + 0x124);
writel(0x10, overlay_base + 0x144);
- writel(0x1, overlay_base + 0x0004); /* directout */
+ writel(0x1, overlay_base + 0x0004); /* directout */
-
- hsync_period = timing->hsync_width + timing->hsync_porch_bp + dtv_width + timing->hsync_porch_fp;
+ hsync_period =
+ timing->hsync_width + timing->hsync_porch_bp + dtv_width +
+ timing->hsync_porch_fp;
hsync_ctrl = (hsync_period << 16) | timing->hsync_width;
hsync_start_x = timing->hsync_width + timing->hsync_porch_bp;
hsync_end_x = hsync_period - timing->hsync_porch_fp - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
- vsync_period = (timing->vsync_width + timing->vsync_porch_bp + dtv_height + timing->vsync_porch_fp) * hsync_period;
- display_v_start = (timing->vsync_width + timing->vsync_porch_bp) * hsync_period;
- display_v_end = vsync_period - (timing->vsync_porch_bp * hsync_period) - 1;
+ vsync_period =
+ (timing->vsync_width + timing->vsync_porch_bp + dtv_height +
+ timing->vsync_porch_fp) * hsync_period;
+ display_v_start =
+ (timing->vsync_width + timing->vsync_porch_bp) * hsync_period;
+ display_v_end =
+ vsync_period - (timing->vsync_porch_bp * hsync_period) - 1;
dtv_underflow_clr |= 0x80000000;
hsync_polarity = 0;
- vsync_polarity = 0 ;
+ vsync_polarity = 0;
data_en_polarity = 0;
- ctrl_polarity = (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
+ ctrl_polarity =
+ (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4);
writel(vsync_period, MDP_BASE + DTV_BASE + 0x8);
@@ -321,7 +329,7 @@
writel(val, MDP_BASE + 0x50050);
writel(BIT(5), MDP_BASE + 0x18000);
#endif
- /* Enable DTV block*/
+ /* Enable DTV block */
writel(0x1, MDP_BASE + DTV_BASE);
val = BIT(1);
val |= BIT(5);
@@ -333,5 +341,5 @@
{
writel(0x0, MDP_BASE + DTV_BASE);
writel(0x8, MDP_BASE + 0x0038);
- writel(0x0,MDP_BASE + 0x10100);
+ writel(0x0, MDP_BASE + 0x10100);
}
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
old mode 100755
new mode 100644
index d2b7420..71410a2
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -46,18 +46,19 @@
struct udc_descriptor {
struct udc_descriptor *next;
- unsigned short tag; /* ((TYPE << 8) | NUM) */
- unsigned short len; /* total length */
+ unsigned short tag; /* ((TYPE << 8) | NUM) */
+ unsigned short len; /* total length */
unsigned char data[0];
};
-struct udc_descriptor *udc_descriptor_alloc(unsigned type, unsigned num, unsigned len)
+struct udc_descriptor *udc_descriptor_alloc(unsigned type, unsigned num,
+ unsigned len)
{
struct udc_descriptor *desc;
if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
return 0;
- if(!(desc = malloc(sizeof(struct udc_descriptor) + len)))
+ if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
return 0;
desc->next = 0;
@@ -127,8 +128,7 @@
struct ept_queue_item *item;
};
-struct udc_endpoint
-{
+struct udc_endpoint {
struct udc_endpoint *next;
unsigned bit;
struct ept_queue_head *head;
@@ -148,7 +148,8 @@
static struct udc_gadget *the_gadget;
static unsigned test_mode = 0;
-struct udc_endpoint *_udc_endpoint_alloc(unsigned num, unsigned in, unsigned max_pkt)
+struct udc_endpoint *_udc_endpoint_alloc(unsigned num, unsigned in,
+ unsigned max_pkt)
{
struct udc_endpoint *ept;
unsigned cfg;
@@ -162,11 +163,11 @@
cfg = CONFIG_MAX_PKT(max_pkt) | CONFIG_ZLT;
- if(ept->in) {
+ if (ept->in) {
ept->bit = EPT_TX(ept->num);
} else {
ept->bit = EPT_RX(ept->num);
- if(num == 0)
+ if (num == 0)
cfg |= CONFIG_IOS;
}
@@ -177,7 +178,7 @@
ept_list = ept;
DBG("ept%d %s @%p/%p max=%d bit=%x\n",
- num, in ? "in":"out", ept, ept->head, max_pkt, ept->bit);
+ num, in ? "in" : "out", ept, ept->head, max_pkt, ept->bit);
return ept;
}
@@ -219,19 +220,21 @@
{
unsigned n = readl(USB_ENDPTCTRL(ept->num));
- if(yes) {
- if(ept->in) {
+ if (yes) {
+ if (ept->in) {
n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
} else {
n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
}
- if(ept->num != 0) {
+ if (ept->num != 0) {
/* XXX should be more dynamic... */
- if(usb_highspeed) {
- ept->head->config = CONFIG_MAX_PKT(512) | CONFIG_ZLT;
+ if (usb_highspeed) {
+ ept->head->config =
+ CONFIG_MAX_PKT(512) | CONFIG_ZLT;
} else {
- ept->head->config = CONFIG_MAX_PKT(64) | CONFIG_ZLT;
+ ept->head->config =
+ CONFIG_MAX_PKT(64) | CONFIG_ZLT;
}
}
}
@@ -255,9 +258,9 @@
int udc_request_queue(struct udc_endpoint *ept, struct udc_request *_req)
{
- struct usb_request *req = (struct usb_request *) _req;
+ struct usb_request *req = (struct usb_request *)_req;
struct ept_queue_item *item = req->item;
- unsigned phys = (unsigned) req->req.buf;
+ unsigned phys = (unsigned)req->req.buf;
item->next = TERMINATE;
item->info = INFO_BYTES(req->req.length) | INFO_IOC | INFO_ACTIVE;
@@ -265,18 +268,22 @@
item->page1 = (phys & 0xfffff000) + 0x1000;
enter_critical_section();
- ept->head->next = (unsigned) item;
+ ept->head->next = (unsigned)item;
ept->head->info = 0;
ept->req = req;
- arch_clean_invalidate_cache_range((addr_t) ept, sizeof(struct udc_endpoint));
- arch_clean_invalidate_cache_range((addr_t) ept->head, sizeof(struct ept_queue_head));
- arch_clean_invalidate_cache_range((addr_t) ept->req, sizeof(struct usb_request));
- arch_clean_invalidate_cache_range((addr_t) req->req.buf, req->req.length);
- arch_clean_invalidate_cache_range((addr_t) ept->req->item, sizeof(struct ept_queue_item));
+ arch_clean_invalidate_cache_range((addr_t) ept,
+ sizeof(struct udc_endpoint));
+ arch_clean_invalidate_cache_range((addr_t) ept->head,
+ sizeof(struct ept_queue_head));
+ arch_clean_invalidate_cache_range((addr_t) ept->req,
+ sizeof(struct usb_request));
+ arch_clean_invalidate_cache_range((addr_t) req->req.buf,
+ req->req.length);
+ arch_clean_invalidate_cache_range((addr_t) ept->req->item,
+ sizeof(struct ept_queue_item));
- DBG("ept%d %s queue req=%p\n",
- ept->num, ept->in ? "in" : "out", req);
+ DBG("ept%d %s queue req=%p\n", ept->num, ept->in ? "in" : "out", req);
writel(ept->bit, USB_ENDPTPRIME);
exit_critical_section();
@@ -291,13 +298,15 @@
struct usb_request *req;
DBG("ept%d %s complete req=%p\n",
- ept->num, ept->in ? "in" : "out", ept->req);
+ ept->num, ept->in ? "in" : "out", ept->req);
- arch_clean_invalidate_cache_range((addr_t) ept, sizeof(struct udc_endpoint));
- arch_clean_invalidate_cache_range((addr_t) ept->req, sizeof(struct usb_request));
+ arch_clean_invalidate_cache_range((addr_t) ept,
+ sizeof(struct udc_endpoint));
+ arch_clean_invalidate_cache_range((addr_t) ept->req,
+ sizeof(struct usb_request));
req = ept->req;
- if(req) {
+ if (req) {
ept->req = 0;
item = req->item;
@@ -306,70 +315,86 @@
* transfer completion before the active bit has cleared.
* HACK: wait for the ACTIVE bit to clear:
*/
- do
- {
+ do {
/* Must clean/invalidate cached item data before checking
* the status every time.
*/
- arch_clean_invalidate_cache_range((addr_t) item, sizeof(struct ept_queue_item));
- } while (readl(&(item->info)) & INFO_ACTIVE);
+ arch_clean_invalidate_cache_range((addr_t) item,
+ sizeof(struct
+ ept_queue_item));
+ }
+ while (readl(&(item->info)) & INFO_ACTIVE);
- arch_clean_invalidate_cache_range((addr_t) req->req.buf, req->req.length);
+ arch_clean_invalidate_cache_range((addr_t) req->req.buf,
+ req->req.length);
- if(item->info & 0xff) {
+ if (item->info & 0xff) {
actual = 0;
status = -1;
dprintf(INFO, "EP%d/%s FAIL nfo=%x pg0=%x\n",
- ept->num, ept->in ? "in" : "out", item->info, item->page0);
+ ept->num, ept->in ? "in" : "out", item->info,
+ item->page0);
} else {
- actual = req->req.length - ((item->info >> 16) & 0x7fff);
+ actual =
+ req->req.length - ((item->info >> 16) & 0x7fff);
status = 0;
}
- if(req->req.complete)
+ if (req->req.complete)
req->req.complete(&req->req, actual, status);
}
}
static const char *reqname(unsigned r)
{
- switch(r) {
- case GET_STATUS: return "GET_STATUS";
- case CLEAR_FEATURE: return "CLEAR_FEATURE";
- case SET_FEATURE: return "SET_FEATURE";
- case SET_ADDRESS: return "SET_ADDRESS";
- case GET_DESCRIPTOR: return "GET_DESCRIPTOR";
- case SET_DESCRIPTOR: return "SET_DESCRIPTOR";
- case GET_CONFIGURATION: return "GET_CONFIGURATION";
- case SET_CONFIGURATION: return "SET_CONFIGURATION";
- case GET_INTERFACE: return "GET_INTERFACE";
- case SET_INTERFACE: return "SET_INTERFACE";
- default: return "*UNKNOWN*";
+ switch (r) {
+ case GET_STATUS:
+ return "GET_STATUS";
+ case CLEAR_FEATURE:
+ return "CLEAR_FEATURE";
+ case SET_FEATURE:
+ return "SET_FEATURE";
+ case SET_ADDRESS:
+ return "SET_ADDRESS";
+ case GET_DESCRIPTOR:
+ return "GET_DESCRIPTOR";
+ case SET_DESCRIPTOR:
+ return "SET_DESCRIPTOR";
+ case GET_CONFIGURATION:
+ return "GET_CONFIGURATION";
+ case SET_CONFIGURATION:
+ return "SET_CONFIGURATION";
+ case GET_INTERFACE:
+ return "GET_INTERFACE";
+ case SET_INTERFACE:
+ return "SET_INTERFACE";
+ default:
+ return "*UNKNOWN*";
}
}
static struct udc_endpoint *ep0in, *ep0out;
static struct udc_request *ep0req;
-static void ep0_setup_ack_complete(struct udc_endpoint *ep, struct usb_request *req)
+static void
+ep0_setup_ack_complete(struct udc_endpoint *ep, struct usb_request *req)
{
uint32_t mode;
- if(!test_mode)
+ if (!test_mode)
return;
- switch (test_mode)
- {
- case TEST_PACKET:
- dprintf(INFO,"Entering test mode for TST_PKT\n");
- mode = readl(USB_PORTSC) & (~PORTSC_PTC);
- writel(mode | PORTSC_PTC_TST_PKT, USB_PORTSC);
- break;
+ switch (test_mode) {
+ case TEST_PACKET:
+ dprintf(INFO, "Entering test mode for TST_PKT\n");
+ mode = readl(USB_PORTSC) & (~PORTSC_PTC);
+ writel(mode | PORTSC_PTC_TST_PKT, USB_PORTSC);
+ break;
- case TEST_SE0_NAK:
- dprintf(INFO, "Entering test mode for SE0-NAK\n");
- mode = readl(USB_PORTSC) & (~PORTSC_PTC);
- writel(mode | PORTSC_PTC_SE0_NAK, USB_PORTSC);
- break;
+ case TEST_SE0_NAK:
+ dprintf(INFO, "Entering test mode for SE0-NAK\n");
+ mode = readl(USB_PORTSC) & (~PORTSC_PTC);
+ writel(mode | PORTSC_PTC_SE0_NAK, USB_PORTSC);
+ break;
}
}
@@ -384,7 +409,7 @@
static void ep0in_complete(struct udc_request *req, unsigned actual, int status)
{
DBG("ep0in_complete %p %d %d\n", req, actual, status);
- if(status == 0) {
+ if (status == 0) {
req->length = 0;
req->complete = 0;
udc_request_queue(ep0out, req);
@@ -404,41 +429,43 @@
#define SETUP(type,request) (((type) << 8) | (request))
-
static void handle_setup(struct udc_endpoint *ept)
{
struct setup_packet s;
- arch_clean_invalidate_cache_range((addr_t) ept->head->setup_data, sizeof(struct ept_queue_head));
+ arch_clean_invalidate_cache_range((addr_t) ept->head->setup_data,
+ sizeof(struct ept_queue_head));
memcpy(&s, ept->head->setup_data, sizeof(s));
writel(ept->bit, USB_ENDPTSETUPSTAT);
DBG("handle_setup type=0x%02x req=0x%02x val=%d idx=%d len=%d (%s)\n",
- s.type, s.request, s.value, s.index, s.length,
- reqname(s.request));
+ s.type, s.request, s.value, s.index, s.length, reqname(s.request));
- switch (SETUP(s.type,s.request)) {
- case SETUP(DEVICE_READ, GET_STATUS): {
- unsigned zero = 0;
- if (s.length == 2) {
- setup_tx(&zero, 2);
- return;
- }
- break;
- }
- case SETUP(DEVICE_READ, GET_DESCRIPTOR): {
- struct udc_descriptor *desc;
- /* usb_highspeed? */
- for (desc = desc_list; desc; desc = desc->next) {
- if (desc->tag == s.value) {
- unsigned len = desc->len;
- if (len > s.length) len = s.length;
- setup_tx(desc->data, len);
+ switch (SETUP(s.type, s.request)) {
+ case SETUP(DEVICE_READ, GET_STATUS):
+ {
+ unsigned zero = 0;
+ if (s.length == 2) {
+ setup_tx(&zero, 2);
return;
}
+ break;
}
- break;
- }
+ case SETUP(DEVICE_READ, GET_DESCRIPTOR):
+ {
+ struct udc_descriptor *desc;
+ /* usb_highspeed? */
+ for (desc = desc_list; desc; desc = desc->next) {
+ if (desc->tag == s.value) {
+ unsigned len = desc->len;
+ if (len > s.length)
+ len = s.length;
+ setup_tx(desc->data, len);
+ return;
+ }
+ }
+ break;
+ }
case SETUP(DEVICE_READ, GET_CONFIGURATION):
/* disabling this causes data transaction failures on OSX. Why? */
if ((s.value == 0) && (s.index == 0) && (s.length == 1)) {
@@ -450,7 +477,7 @@
if (s.value == 1) {
struct udc_endpoint *ept;
/* enable endpoints */
- for (ept = ept_list; ept; ept = ept->next){
+ for (ept = ept_list; ept; ept = ept->next) {
if (ept->num == 0)
continue;
endpoint_enable(ept, s.value);
@@ -468,8 +495,8 @@
return;
case SETUP(DEVICE_WRITE, SET_ADDRESS):
/* write address delayed (will take effect
- ** after the next IN txn)
- */
+ ** after the next IN txn)
+ */
writel((s.value << 25) | (1 << 24), USB_DEVICEADDR);
setup_ack();
return;
@@ -481,54 +508,54 @@
test_mode = s.index;
setup_ack();
return;
- case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE): {
- struct udc_endpoint *ept;
- unsigned num = s.index & 15;
- unsigned in = !!(s.index & 0x80);
+ case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE):
+ {
+ struct udc_endpoint *ept;
+ unsigned num = s.index & 15;
+ unsigned in = !!(s.index & 0x80);
- if ((s.value == 0) && (s.length == 0)) {
- DBG("clr feat %d %d\n", num, in);
- for (ept = ept_list; ept; ept = ept->next) {
- if ((ept->num == num) && (ept->in == in)) {
- endpoint_enable(ept, 1);
- setup_ack();
- return;
+ if ((s.value == 0) && (s.length == 0)) {
+ DBG("clr feat %d %d\n", num, in);
+ for (ept = ept_list; ept; ept = ept->next) {
+ if ((ept->num == num)
+ && (ept->in == in)) {
+ endpoint_enable(ept, 1);
+ setup_ack();
+ return;
+ }
}
}
+ break;
}
- break;
- }
}
dprintf(INFO, "STALL %s %d %d %d %d %d\n",
reqname(s.request),
s.type, s.request, s.value, s.index, s.length);
-stall:
- writel((1<<16) | (1 << 0), USB_ENDPTCTRL(ept->num));
+ stall:
+ writel((1 << 16) | (1 << 0), USB_ENDPTCTRL(ept->num));
}
unsigned ulpi_read(unsigned reg)
{
- /* initiate read operation */
- writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
- USB_ULPI_VIEWPORT);
+ /* initiate read operation */
+ writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), USB_ULPI_VIEWPORT);
- /* wait for completion */
- while(readl(USB_ULPI_VIEWPORT) & ULPI_RUN) ;
+ /* wait for completion */
+ while (readl(USB_ULPI_VIEWPORT) & ULPI_RUN) ;
return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
}
void ulpi_write(unsigned val, unsigned reg)
{
- /* initiate write operation */
+ /* initiate write operation */
writel(ULPI_RUN | ULPI_WRITE |
- ULPI_ADDR(reg) | ULPI_DATA(val),
- USB_ULPI_VIEWPORT);
+ ULPI_ADDR(reg) | ULPI_DATA(val), USB_ULPI_VIEWPORT);
- /* wait for completion */
- while(readl(USB_ULPI_VIEWPORT) & ULPI_RUN) ;
+ /* wait for completion */
+ while (readl(USB_ULPI_VIEWPORT) & ULPI_RUN) ;
}
#define USB_CLK 0x00902910
@@ -554,47 +581,45 @@
void board_usb_init(void);
void board_ulpi_init(void)
{
- unsigned int reg;
+ unsigned int reg;
#ifdef PLATFORM_MSM7X27A
ulpi_read(0x31);
- dprintf(INFO," Value of ulpi read 0x31 is %08x\n", reg);
- /* todo : the write back value should be calculated according to
- * reg &= 0xF3 but sometimes the value that is read initially
- * doesnt look right
- */
+ dprintf(INFO, " Value of ulpi read 0x31 is %08x\n", reg);
+ /* todo : the write back value should be calculated according to
+ * reg &= 0xF3 but sometimes the value that is read initially
+ * doesnt look right
+ */
ulpi_write(0x4A, 0x31);
- reg = ulpi_read(0x31);
- dprintf(INFO," Value of ulpi read 0x31 after write is %08x\n", reg);
+ reg = ulpi_read(0x31);
+ dprintf(INFO, " Value of ulpi read 0x31 after write is %08x\n", reg);
reg = ulpi_read(0x32);
- dprintf(INFO," Value of ulpi read 0x32 is %08x\n", reg);
- ulpi_write(0x30,0x32);
+ dprintf(INFO, " Value of ulpi read 0x32 is %08x\n", reg);
+ ulpi_write(0x30, 0x32);
reg = ulpi_read(0x32);
- dprintf(INFO," Value of ulpi read 0x32 after write is %08x\n", reg);
-
+ dprintf(INFO, " Value of ulpi read 0x32 after write is %08x\n", reg);
reg = ulpi_read(0x36);
- dprintf(INFO," Value of ulpi read 0x36 is %08x\n", reg);
- ulpi_write(reg|0x2,0x36);
+ dprintf(INFO, " Value of ulpi read 0x36 is %08x\n", reg);
+ ulpi_write(reg | 0x2, 0x36);
reg = ulpi_read(0x36);
- dprintf(INFO," Value of ulpi read 0x36 after write is %08x\n", reg);
+ dprintf(INFO, " Value of ulpi read 0x36 after write is %08x\n", reg);
#endif
#ifdef PLATFORM_MSM8X60
- reg = ulpi_read(0x32);
- dprintf(INFO," Value of ulpi read 0x32 is %08x\n", reg);
- ulpi_write(0x30,0x32);
- reg = ulpi_read(0x32);
- dprintf(INFO," Value of ulpi read 0x32 after write is %08x\n", reg);
+ reg = ulpi_read(0x32);
+ dprintf(INFO, " Value of ulpi read 0x32 is %08x\n", reg);
+ ulpi_write(0x30, 0x32);
+ reg = ulpi_read(0x32);
+ dprintf(INFO, " Value of ulpi read 0x32 after write is %08x\n", reg);
-
- reg = ulpi_read(0x36);
- dprintf(INFO," Value of ulpi read 0x36 is %08x\n", reg);
- ulpi_write(reg|0x2,0x36);
- reg = ulpi_read(0x36);
- dprintf(INFO," Value of ulpi read 0x36 aafter write is %08x\n", reg);
+ reg = ulpi_read(0x36);
+ dprintf(INFO, " Value of ulpi read 0x36 is %08x\n", reg);
+ ulpi_write(reg | 0x2, 0x36);
+ reg = ulpi_read(0x36);
+ dprintf(INFO, " Value of ulpi read 0x36 aafter write is %08x\n", reg);
#endif
}
@@ -613,27 +638,28 @@
dprintf(INFO, "USB init ept @ %p\n", epts);
memset(epts, 0, 32 * sizeof(struct ept_queue_head));
- arch_clean_invalidate_cache_range((addr_t) epts, 32 * sizeof(struct ept_queue_head));
+ arch_clean_invalidate_cache_range((addr_t) epts,
+ 32 * sizeof(struct ept_queue_head));
//dprintf(INFO, "USB ID %08x\n", readl(USB_ID));
// board_usb_init();
- /* select ULPI phy */
+ /* select ULPI phy */
#ifdef PLATFORM_MSM8X60
msm_otg_xceiv_reset();
#else
writel(0x81000000, USB_PORTSC);
#endif
- /* RESET */
+ /* RESET */
writel(0x00080002, USB_USBCMD);
thread_sleep(20);
- board_ulpi_init();
+ board_ulpi_init();
- writel((unsigned) epts, USB_ENDPOINTLISTADDR);
+ writel((unsigned)epts, USB_ENDPOINTLISTADDR);
- /* select DEVICE mode */
+ /* select DEVICE mode */
writel(0x02, USB_USBMODE);
writel(0xffffffff, USB_ENDPTFLUSH);
@@ -647,7 +673,8 @@
{
/* create and register a language table descriptor */
/* language 0x0409 is US English */
- struct udc_descriptor *desc = udc_descriptor_alloc(TYPE_STRING, 0, 4);
+ struct udc_descriptor *desc =
+ udc_descriptor_alloc(TYPE_STRING, 0, 4);
desc->data[2] = 0x09;
desc->data[3] = 0x04;
udc_descriptor_register(desc);
@@ -703,7 +730,7 @@
if (n & STS_PCI) {
dprintf(INFO, "-- portchange --\n");
unsigned spd = (readl(USB_PORTSC) >> 26) & 3;
- if(spd == 2) {
+ if (spd == 2) {
usb_highspeed = 1;
} else {
usb_highspeed = 0;
@@ -715,11 +742,16 @@
}
#if 0
DBG("STS: ");
- if (n & STS_UEI) DBG("ERROR ");
- if (n & STS_SLI) DBG("SUSPEND ");
- if (n & STS_URI) DBG("RESET ");
- if (n & STS_PCI) DBG("PORTCHANGE ");
- if (n & STS_UI) DBG("USB ");
+ if (n & STS_UEI)
+ DBG("ERROR ");
+ if (n & STS_SLI)
+ DBG("SUSPEND ");
+ if (n & STS_URI)
+ DBG("RESET ");
+ if (n & STS_PCI)
+ DBG("PORTCHANGE ");
+ if (n & STS_UI)
+ DBG("USB ");
DBG("\n");
#endif
if ((n & STS_UI) || (n & STS_UEI)) {
@@ -735,7 +767,7 @@
writel(n, USB_ENDPTCOMPLETE);
}
- for (ept = ept_list; ept; ept = ept->next){
+ for (ept = ept_list; ept; ept = ept->next) {
if (n & ept->bit) {
handle_ept_complete(ept);
ret = INT_RESCHEDULE;
@@ -760,7 +792,7 @@
data[0] = 7;
data[1] = TYPE_ENDPOINT;
data[2] = ept->num | (ept->in ? 0x80 : 0x00);
- data[3] = 0x02; /* bulk -- the only kind we support */
+ data[3] = 0x02; /* bulk -- the only kind we support */
data[4] = ept->maxpkt;
data[5] = ept->maxpkt >> 8;
data[6] = ept->in ? 0x00 : 0x01;
@@ -777,8 +809,8 @@
data[0] = 0x09;
data[1] = TYPE_INTERFACE;
- data[2] = 0x00; /* ifc number */
- data[3] = 0x00; /* alt number */
+ data[2] = 0x00; /* ifc number */
+ data[3] = 0x00; /* alt number */
data[4] = g->ifc_endpoints;
data[5] = g->ifc_class;
data[6] = g->ifc_subclass;
@@ -812,19 +844,19 @@
/* create our device descriptor */
desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18);
data = desc->data;
- data[2] = 0x00; /* usb spec minor rev */
- data[3] = 0x02; /* usb spec major rev */
- data[4] = 0x00; /* class */
- data[5] = 0x00; /* subclass */
- data[6] = 0x00; /* protocol */
- data[7] = 0x40; /* max packet size on ept 0 */
+ data[2] = 0x00; /* usb spec minor rev */
+ data[3] = 0x02; /* usb spec major rev */
+ data[4] = 0x00; /* class */
+ data[5] = 0x00; /* subclass */
+ data[6] = 0x00; /* protocol */
+ data[7] = 0x40; /* max packet size on ept 0 */
memcpy(data + 8, &the_device->vendor_id, sizeof(short));
memcpy(data + 10, &the_device->product_id, sizeof(short));
memcpy(data + 12, &the_device->version_id, sizeof(short));
data[14] = udc_string_desc_alloc(the_device->manufacturer);
data[15] = udc_string_desc_alloc(the_device->product);
data[16] = udc_string_desc_alloc(the_device->serialno);
- data[17] = 1; /* number of configurations */
+ data[17] = 1; /* number of configurations */
udc_descriptor_register(desc);
/* create our configuration descriptor */
@@ -834,22 +866,21 @@
data[0] = 0x09;
data[2] = size;
data[3] = size >> 8;
- data[4] = 0x01; /* number of interfaces */
- data[5] = 0x01; /* configuration value */
- data[6] = 0x00; /* configuration string */
- data[7] = 0x80; /* attributes */
- data[8] = 0x80; /* max power (250ma) -- todo fix this */
+ data[4] = 0x01; /* number of interfaces */
+ data[5] = 0x01; /* configuration value */
+ data[6] = 0x00; /* configuration string */
+ data[7] = 0x80; /* attributes */
+ data[8] = 0x80; /* max power (250ma) -- todo fix this */
udc_ifc_desc_fill(the_gadget, data + 9);
udc_descriptor_register(desc);
- register_int_handler(INT_USB_HS, udc_interrupt, (void*) 0);
+ register_int_handler(INT_USB_HS, udc_interrupt, (void *)0);
writel(STS_URI | STS_SLI | STS_UI | STS_PCI, USB_USBINTR);
unmask_interrupt(INT_USB_HS);
- /* go to RUN mode (D+ pullup enable) */
+ /* go to RUN mode (D+ pullup enable) */
writel(0x00080001, USB_USBCMD);
-
return 0;
}
@@ -858,19 +889,18 @@
#ifdef PLATFORM_MSM8X60
int val;
#endif
- writel(0, USB_USBINTR);
+ writel(0, USB_USBINTR);
mask_interrupt(INT_USB_HS);
- /* disable pullup */
+ /* disable pullup */
writel(0x00080000, USB_USBCMD);
#ifdef PLATFORM_MSM8X60
/* Voting down PLL8 */
val = readl(0x009034C0);
- val &= ~(1<<8);
+ val &= ~(1 << 8);
writel(val, 0x009034C0);
#endif
thread_sleep(10);
return 0;
}
-
diff --git a/platform/msm_shared/hsusb.h b/platform/msm_shared/hsusb.h
index 5efa304..6d24e39 100644
--- a/platform/msm_shared/hsusb.h
+++ b/platform/msm_shared/hsusb.h
@@ -43,11 +43,11 @@
#define USB_HWRXBUF (MSM_USB_BASE + 0x0014)
#define USB_SBUSCFG (MSM_USB_BASE + 0x0090)
-#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
-#define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */
+#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
+#define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */
#define USB_HCSPARAMS (MSM_USB_BASE + 0x0104)
#define USB_HCCPARAMS (MSM_USB_BASE + 0x0108)
-#define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */
+#define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */
#define USB_USBCMD (MSM_USB_BASE + 0x0140)
#define USB_USBSTS (MSM_USB_BASE + 0x0144)
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
@@ -69,49 +69,46 @@
#define USB_ENDPTCOMPLETE (MSM_USB_BASE + 0x01BC)
#define USB_ENDPTCTRL(n) (MSM_USB_BASE + 0x01C0 + (4 * (n)))
-
#define USBCMD_RESET 2
#define USBCMD_ATTACH 1
#define USBMODE_DEVICE 2
#define USBMODE_HOST 3
-struct ept_queue_head
-{
- unsigned config;
- unsigned current; /* read-only */
+struct ept_queue_head {
+ unsigned config;
+ unsigned current; /* read-only */
- unsigned next;
- unsigned info;
- unsigned page0;
- unsigned page1;
- unsigned page2;
- unsigned page3;
- unsigned page4;
- unsigned reserved_0;
-
- unsigned char setup_data[8];
-
- unsigned reserved_1;
- unsigned reserved_2;
- unsigned reserved_3;
- unsigned reserved_4;
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved_0;
+
+ unsigned char setup_data[8];
+
+ unsigned reserved_1;
+ unsigned reserved_2;
+ unsigned reserved_3;
+ unsigned reserved_4;
};
#define CONFIG_MAX_PKT(n) ((n) << 16)
-#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
-#define CONFIG_IOS (1 << 15) /* IRQ on setup */
+#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
+#define CONFIG_IOS (1 << 15) /* IRQ on setup */
-struct ept_queue_item
-{
- unsigned next;
- unsigned info;
- unsigned page0;
- unsigned page1;
- unsigned page2;
- unsigned page3;
- unsigned page4;
- unsigned reserved;
+struct ept_queue_item {
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved;
};
#define TERMINATE 1
@@ -123,22 +120,19 @@
#define INFO_BUFFER_ERROR (1 << 5)
#define INFO_TX_ERROR (1 << 3)
-
-#define STS_NAKI (1 << 16) /* */
-#define STS_SLI (1 << 8) /* R/WC - suspend state entered */
-#define STS_SRI (1 << 7) /* R/WC - SOF recv'd */
-#define STS_URI (1 << 6) /* R/WC - RESET recv'd - write to clear */
-#define STS_FRI (1 << 3) /* R/WC - Frame List Rollover */
-#define STS_PCI (1 << 2) /* R/WC - Port Change Detect */
-#define STS_UEI (1 << 1) /* R/WC - USB Error */
-#define STS_UI (1 << 0) /* R/WC - USB Transaction Complete */
-
+#define STS_NAKI (1 << 16) /* */
+#define STS_SLI (1 << 8) /* R/WC - suspend state entered */
+#define STS_SRI (1 << 7) /* R/WC - SOF recv'd */
+#define STS_URI (1 << 6) /* R/WC - RESET recv'd - write to clear */
+#define STS_FRI (1 << 3) /* R/WC - Frame List Rollover */
+#define STS_PCI (1 << 2) /* R/WC - Port Change Detect */
+#define STS_UEI (1 << 1) /* R/WC - USB Error */
+#define STS_UI (1 << 0) /* R/WC - USB Transaction Complete */
/* bits used in all the endpoint status registers */
#define EPT_TX(n) (1 << ((n) + 16))
#define EPT_RX(n) (1 << (n))
-
#define CTRL_TXE (1 << 23)
#define CTRL_TXR (1 << 22)
#define CTRL_TXI (1 << 21)
diff --git a/platform/msm_shared/i2c_qup.c b/platform/msm_shared/i2c_qup.c
index 583980c..7ec209e 100644
--- a/platform/msm_shared/i2c_qup.c
+++ b/platform/msm_shared/i2c_qup.c
@@ -48,98 +48,97 @@
#include <platform/timer.h>
#include <platform/interrupts.h>
-
static struct qup_i2c_dev *dev_addr = NULL;
/* QUP Registers */
enum {
- QUP_CONFIG = 0x0,
- QUP_STATE = 0x4,
- QUP_IO_MODE = 0x8,
- QUP_SW_RESET = 0xC,
- QUP_OPERATIONAL = 0x18,
- QUP_ERROR_FLAGS = 0x1C,
- QUP_ERROR_FLAGS_EN = 0x20,
- QUP_MX_READ_CNT = 0x208,
- QUP_MX_INPUT_CNT = 0x200,
- QUP_MX_WR_CNT = 0x100,
- QUP_OUT_DEBUG = 0x108,
- QUP_OUT_FIFO_CNT = 0x10C,
- QUP_OUT_FIFO_BASE = 0x110,
- QUP_IN_READ_CUR = 0x20C,
- QUP_IN_DEBUG = 0x210,
- QUP_IN_FIFO_CNT = 0x214,
- QUP_IN_FIFO_BASE = 0x218,
- QUP_I2C_CLK_CTL = 0x400,
- QUP_I2C_STATUS = 0x404,
+ QUP_CONFIG = 0x0,
+ QUP_STATE = 0x4,
+ QUP_IO_MODE = 0x8,
+ QUP_SW_RESET = 0xC,
+ QUP_OPERATIONAL = 0x18,
+ QUP_ERROR_FLAGS = 0x1C,
+ QUP_ERROR_FLAGS_EN = 0x20,
+ QUP_MX_READ_CNT = 0x208,
+ QUP_MX_INPUT_CNT = 0x200,
+ QUP_MX_WR_CNT = 0x100,
+ QUP_OUT_DEBUG = 0x108,
+ QUP_OUT_FIFO_CNT = 0x10C,
+ QUP_OUT_FIFO_BASE = 0x110,
+ QUP_IN_READ_CUR = 0x20C,
+ QUP_IN_DEBUG = 0x210,
+ QUP_IN_FIFO_CNT = 0x214,
+ QUP_IN_FIFO_BASE = 0x218,
+ QUP_I2C_CLK_CTL = 0x400,
+ QUP_I2C_STATUS = 0x404,
};
/* QUP States and reset values */
enum {
- QUP_RESET_STATE = 0,
- QUP_RUN_STATE = 1U,
- QUP_STATE_MASK = 3U,
- QUP_PAUSE_STATE = 3U,
- QUP_STATE_VALID = 1U << 2,
- QUP_I2C_MAST_GEN = 1U << 4,
- QUP_OPERATIONAL_RESET = 0xFF0,
- QUP_I2C_STATUS_RESET = 0xFFFFFC,
+ QUP_RESET_STATE = 0,
+ QUP_RUN_STATE = 1U,
+ QUP_STATE_MASK = 3U,
+ QUP_PAUSE_STATE = 3U,
+ QUP_STATE_VALID = 1U << 2,
+ QUP_I2C_MAST_GEN = 1U << 4,
+ QUP_OPERATIONAL_RESET = 0xFF0,
+ QUP_I2C_STATUS_RESET = 0xFFFFFC,
};
/* QUP OPERATIONAL FLAGS */
enum {
- QUP_OUT_SVC_FLAG = 1U << 8,
- QUP_IN_SVC_FLAG = 1U << 9,
- QUP_MX_INPUT_DONE = 1U << 11,
+ QUP_OUT_SVC_FLAG = 1U << 8,
+ QUP_IN_SVC_FLAG = 1U << 9,
+ QUP_MX_INPUT_DONE = 1U << 11,
};
/* I2C mini core related values */
enum {
- I2C_MINI_CORE = 2U << 8,
- I2C_N_VAL = 0xF,
+ I2C_MINI_CORE = 2U << 8,
+ I2C_N_VAL = 0xF,
};
/* Packing Unpacking words in FIFOs , and IO modes*/
enum {
- QUP_WR_BLK_MODE = 1U << 10,
- QUP_RD_BLK_MODE = 1U << 12,
- QUP_UNPACK_EN = 1U << 14,
- QUP_PACK_EN = 1U << 15,
+ QUP_WR_BLK_MODE = 1U << 10,
+ QUP_RD_BLK_MODE = 1U << 12,
+ QUP_UNPACK_EN = 1U << 14,
+ QUP_PACK_EN = 1U << 15,
};
/* QUP tags */
enum {
- QUP_OUT_NOP = 0,
- QUP_OUT_START = 1U << 8,
- QUP_OUT_DATA = 2U << 8,
- QUP_OUT_STOP = 3U << 8,
- QUP_OUT_REC = 4U << 8,
- QUP_IN_DATA = 5U << 8,
- QUP_IN_STOP = 6U << 8,
- QUP_IN_NACK = 7U << 8,
+ QUP_OUT_NOP = 0,
+ QUP_OUT_START = 1U << 8,
+ QUP_OUT_DATA = 2U << 8,
+ QUP_OUT_STOP = 3U << 8,
+ QUP_OUT_REC = 4U << 8,
+ QUP_IN_DATA = 5U << 8,
+ QUP_IN_STOP = 6U << 8,
+ QUP_IN_NACK = 7U << 8,
};
/* Status, Error flags */
enum {
- I2C_STATUS_WR_BUFFER_FULL = 1U << 0,
- I2C_STATUS_BUS_ACTIVE = 1U << 8,
- I2C_STATUS_ERROR_MASK = 0x38000FC,
- QUP_I2C_NACK_FLAG = 1U << 3,
- QUP_IN_NOT_EMPTY = 1U << 5,
- QUP_STATUS_ERROR_FLAGS = 0x7C,
+ I2C_STATUS_WR_BUFFER_FULL = 1U << 0,
+ I2C_STATUS_BUS_ACTIVE = 1U << 8,
+ I2C_STATUS_ERROR_MASK = 0x38000FC,
+ QUP_I2C_NACK_FLAG = 1U << 3,
+ QUP_IN_NOT_EMPTY = 1U << 5,
+ QUP_STATUS_ERROR_FLAGS = 0x7C,
};
#ifdef DEBUG_QUP
static void qup_print_status(struct qup_i2c_dev *dev)
{
- unsigned val;
- val = readl(dev->qup_base + QUP_CONFIG);
- dprintf(INFO, "Qup config is :0x%x\n", val);
- val = readl(dev->qup_base + QUP_STATE);
- dprintf(INFO, "Qup state is :0x%x\n", val);
- val = readl(dev->qup_base + QUP_IO_MODE);
- dprintf(INFO, "Qup mode is :0x%x\n", val);
+ unsigned val;
+ val = readl(dev->qup_base + QUP_CONFIG);
+ dprintf(INFO, "Qup config is :0x%x\n", val);
+ val = readl(dev->qup_base + QUP_STATE);
+ dprintf(INFO, "Qup state is :0x%x\n", val);
+ val = readl(dev->qup_base + QUP_IO_MODE);
+ dprintf(INFO, "Qup mode is :0x%x\n", val);
}
#else
static inline void qup_print_status(struct qup_i2c_dev *dev)
@@ -149,557 +148,589 @@
static irqreturn_t qup_i2c_interrupt(void)
{
- struct qup_i2c_dev *dev = dev_addr;
- if (!dev) {
- dprintf(CRITICAL,
- "dev_addr is NULL, that means i2c_qup_init failed...\n");
- return IRQ_FAIL;
- }
- unsigned status = readl(dev->qup_base + QUP_I2C_STATUS);
- unsigned status1 = readl(dev->qup_base + QUP_ERROR_FLAGS);
- unsigned op_flgs = readl(dev->qup_base + QUP_OPERATIONAL);
- int err = 0;
+ struct qup_i2c_dev *dev = dev_addr;
+ if (!dev) {
+ dprintf(CRITICAL,
+ "dev_addr is NULL, that means i2c_qup_init failed...\n");
+ return IRQ_FAIL;
+ }
+ unsigned status = readl(dev->qup_base + QUP_I2C_STATUS);
+ unsigned status1 = readl(dev->qup_base + QUP_ERROR_FLAGS);
+ unsigned op_flgs = readl(dev->qup_base + QUP_OPERATIONAL);
+ int err = 0;
- if (!dev->msg)
- return IRQ_HANDLED;
+ if (!dev->msg)
+ return IRQ_HANDLED;
- if (status & I2C_STATUS_ERROR_MASK) {
- dprintf(CRITICAL, "QUP: I2C status flags :0x%x \n", status);
- err = -status;
- /* Clear Error interrupt if it's a level triggered interrupt */
- if (dev->num_irqs == 1) {
- writel(QUP_RESET_STATE, dev->qup_base + QUP_STATE);
- }
- goto intr_done;
- }
+ if (status & I2C_STATUS_ERROR_MASK) {
+ dprintf(CRITICAL, "QUP: I2C status flags :0x%x \n", status);
+ err = -status;
+ /* Clear Error interrupt if it's a level triggered interrupt */
+ if (dev->num_irqs == 1) {
+ writel(QUP_RESET_STATE, dev->qup_base + QUP_STATE);
+ }
+ goto intr_done;
+ }
- if (status1 & 0x7F) {
- dprintf(CRITICAL, "QUP: QUP status flags :0x%x\n", status1);
- err = -status1;
- /* Clear Error interrupt if it's a level triggered interrupt */
- if (dev->num_irqs == 1)
- writel((status1 & QUP_STATUS_ERROR_FLAGS),
- dev->qup_base + QUP_ERROR_FLAGS);
- goto intr_done;
- }
+ if (status1 & 0x7F) {
+ dprintf(CRITICAL, "QUP: QUP status flags :0x%x\n", status1);
+ err = -status1;
+ /* Clear Error interrupt if it's a level triggered interrupt */
+ if (dev->num_irqs == 1)
+ writel((status1 & QUP_STATUS_ERROR_FLAGS),
+ dev->qup_base + QUP_ERROR_FLAGS);
+ goto intr_done;
+ }
- if (op_flgs & QUP_OUT_SVC_FLAG)
- writel(QUP_OUT_SVC_FLAG, dev->qup_base + QUP_OPERATIONAL);
- if (dev->msg->flags == I2C_M_RD) {
- if ((op_flgs & QUP_MX_INPUT_DONE) || (op_flgs & QUP_IN_SVC_FLAG))
- writel(QUP_IN_SVC_FLAG, dev->qup_base + QUP_OPERATIONAL);
- else
- return IRQ_HANDLED;
- }
+ if (op_flgs & QUP_OUT_SVC_FLAG)
+ writel(QUP_OUT_SVC_FLAG, dev->qup_base + QUP_OPERATIONAL);
+ if (dev->msg->flags == I2C_M_RD) {
+ if ((op_flgs & QUP_MX_INPUT_DONE)
+ || (op_flgs & QUP_IN_SVC_FLAG))
+ writel(QUP_IN_SVC_FLAG,
+ dev->qup_base + QUP_OPERATIONAL);
+ else
+ return IRQ_HANDLED;
+ }
-intr_done:
- dev->err = err;
- return IRQ_HANDLED;
+ intr_done:
+ dev->err = err;
+ return IRQ_HANDLED;
}
static int qup_i2c_poll_writeready(struct qup_i2c_dev *dev)
{
- unsigned retries = 0;
+ unsigned retries = 0;
- while (retries != 2000) {
- unsigned status = readl(dev->qup_base + QUP_I2C_STATUS);
+ while (retries != 2000) {
+ unsigned status = readl(dev->qup_base + QUP_I2C_STATUS);
- if (!(status & I2C_STATUS_WR_BUFFER_FULL)) {
- if (!(status & I2C_STATUS_BUS_ACTIVE))
- return 0;
- else /* 1-bit delay before we check for bus busy */
- udelay(dev->one_bit_t);
- }
- if (retries++ == 1000)
- udelay(100);
- }
- qup_print_status(dev);
- return -ETIMEDOUT;
+ if (!(status & I2C_STATUS_WR_BUFFER_FULL)) {
+ if (!(status & I2C_STATUS_BUS_ACTIVE))
+ return 0;
+ else /* 1-bit delay before we check for bus busy */
+ udelay(dev->one_bit_t);
+ }
+ if (retries++ == 1000)
+ udelay(100);
+ }
+ qup_print_status(dev);
+ return -ETIMEDOUT;
}
static int qup_i2c_poll_state(struct qup_i2c_dev *dev, unsigned state)
{
- unsigned retries = 0;
+ unsigned retries = 0;
- dprintf(INFO, "Polling Status for state:0x%x\n", state);
+ dprintf(INFO, "Polling Status for state:0x%x\n", state);
- while (retries != 2000) {
- unsigned status = readl(dev->qup_base + QUP_STATE);
+ while (retries != 2000) {
+ unsigned status = readl(dev->qup_base + QUP_STATE);
- if ((status & (QUP_STATE_VALID | state)) == (QUP_STATE_VALID | state))
- return 0;
- else if (retries++ == 1000)
- udelay(100);
- }
- return -ETIMEDOUT;
+ if ((status & (QUP_STATE_VALID | state)) ==
+ (QUP_STATE_VALID | state))
+ return 0;
+ else if (retries++ == 1000)
+ udelay(100);
+ }
+ return -ETIMEDOUT;
}
#ifdef DEBUG
-static void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val,
- unsigned addr, int rdwr)
+static void
+qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val, unsigned addr, int rdwr)
{
- if (rdwr)
- dprintf(INFO, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
- else
- dprintf(INFO, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
+ if (rdwr)
+ dprintf(INFO, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
+ else
+ dprintf(INFO, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
}
#else
-static inline void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val,
- unsigned addr, int rdwr)
+static inline void
+qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val, unsigned addr, int rdwr)
{
}
#endif
static void
qup_issue_read(struct qup_i2c_dev *dev, struct i2c_msg *msg, int *idx,
- unsigned carry_over)
+ unsigned carry_over)
{
- uint16_t addr = (msg->addr << 1) | 1;
- /* QUP limit 256 bytes per read. By HW design, 0 in the 8-bit field is
- treated as 256 byte read. */
- uint16_t rd_len = ((dev->cnt == 256) ? 0 : dev->cnt);
+ uint16_t addr = (msg->addr << 1) | 1;
+ /* QUP limit 256 bytes per read. By HW design, 0 in the 8-bit field is
+ treated as 256 byte read. */
+ uint16_t rd_len = ((dev->cnt == 256) ? 0 : dev->cnt);
- if (*idx % 4) {
- writel(carry_over | ((QUP_OUT_START | addr) << 16),
- dev->qup_base + QUP_OUT_FIFO_BASE);
+ if (*idx % 4) {
+ writel(carry_over | ((QUP_OUT_START | addr) << 16),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, carry_over |
- ((QUP_OUT_START | addr) << 16), (unsigned)dev->qup_base
- + QUP_OUT_FIFO_BASE + (*idx - 2), 1);
- writel((QUP_OUT_REC | rd_len), dev->qup_base + QUP_OUT_FIFO_BASE);
+ qup_verify_fifo(dev, carry_over |
+ ((QUP_OUT_START | addr) << 16),
+ (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE +
+ (*idx - 2), 1);
+ writel((QUP_OUT_REC | rd_len),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, (QUP_OUT_REC | rd_len),
- (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE + (*idx + 2),
- 1);
- } else {
- writel(((QUP_OUT_REC | rd_len) << 16) |
- QUP_OUT_START | addr, dev->qup_base + QUP_OUT_FIFO_BASE);
+ qup_verify_fifo(dev, (QUP_OUT_REC | rd_len),
+ (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE +
+ (*idx + 2), 1);
+ } else {
+ writel(((QUP_OUT_REC | rd_len) << 16) |
+ QUP_OUT_START | addr, dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, QUP_OUT_REC << 16 | rd_len << 16 |
- QUP_OUT_START | addr,
- (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE + (*idx), 1);
- }
- *idx += 4;
+ qup_verify_fifo(dev, QUP_OUT_REC << 16 | rd_len << 16 |
+ QUP_OUT_START | addr,
+ (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE +
+ (*idx), 1);
+ }
+ *idx += 4;
}
static void
qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem,
- int *idx, unsigned *carry_over)
+ int *idx, unsigned *carry_over)
{
- int entries = dev->cnt;
- int empty_sl = dev->wr_sz - ((*idx) >> 1);
- int i = 0;
- unsigned val = 0;
- unsigned last_entry = 0;
- uint16_t addr = msg->addr << 1;
+ int entries = dev->cnt;
+ int empty_sl = dev->wr_sz - ((*idx) >> 1);
+ int i = 0;
+ unsigned val = 0;
+ unsigned last_entry = 0;
+ uint16_t addr = msg->addr << 1;
- if (dev->pos == 0) {
- if (*idx % 4) {
- writel(*carry_over | ((QUP_OUT_START | addr) << 16),
- dev->qup_base + QUP_OUT_FIFO_BASE);
+ if (dev->pos == 0) {
+ if (*idx % 4) {
+ writel(*carry_over | ((QUP_OUT_START | addr) << 16),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 |
- addr << 16, (unsigned)dev->qup_base +
- QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
- } else
- val = QUP_OUT_START | addr;
- *idx += 2;
- i++;
- entries++;
- } else {
- /* Avoid setp time issue by adding 1 NOP when number of bytes are more
- than FIFO/BLOCK size. setup time issue can't appear otherwise since
- next byte to be written will always be ready */
- val = (QUP_OUT_NOP | 1);
- *idx += 2;
- i++;
- entries++;
- }
- if (entries > empty_sl)
- entries = empty_sl;
+ qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 |
+ addr << 16, (unsigned)dev->qup_base +
+ QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
+ } else
+ val = QUP_OUT_START | addr;
+ *idx += 2;
+ i++;
+ entries++;
+ } else {
+ /* Avoid setp time issue by adding 1 NOP when number of bytes are more
+ than FIFO/BLOCK size. setup time issue can't appear otherwise since
+ next byte to be written will always be ready */
+ val = (QUP_OUT_NOP | 1);
+ *idx += 2;
+ i++;
+ entries++;
+ }
+ if (entries > empty_sl)
+ entries = empty_sl;
- for (; i < (entries - 1); i++) {
- if (*idx % 4) {
- writel(val | ((QUP_OUT_DATA |
- msg->buf[dev->pos]) << 16),
- dev->qup_base + QUP_OUT_FIFO_BASE);
+ for (; i < (entries - 1); i++) {
+ if (*idx % 4) {
+ writel(val | ((QUP_OUT_DATA |
+ msg->buf[dev->pos]) << 16),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, val | QUP_OUT_DATA << 16 |
- msg->buf[dev->pos] << 16, (unsigned)dev->qup_base +
- QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
- } else
- val = QUP_OUT_DATA | msg->buf[dev->pos];
- (*idx) += 2;
- dev->pos++;
- }
- if (dev->pos < (msg->len - 1))
- last_entry = QUP_OUT_DATA;
- else if (rem > 1) /* not last array entry */
- last_entry = QUP_OUT_DATA;
- else
- last_entry = QUP_OUT_STOP;
- if ((*idx % 4) == 0) {
- /*
- * If read-start and read-command end up in different fifos, it
- * may result in extra-byte being read due to extra-read cycle.
- * Avoid that by inserting NOP as the last entry of fifo only
- * if write command(s) leave 1 space in fifo.
- */
- if (rem > 1) {
- struct i2c_msg *next = msg + 1;
- if (next->addr == msg->addr && (next->flags | I2C_M_RD)
- && *idx == ((dev->wr_sz * 2) - 4)) {
- writel(((last_entry | msg->buf[dev->pos]) |
- ((1 | QUP_OUT_NOP) << 16)),
- dev->qup_base + QUP_OUT_FIFO_BASE);
- *idx += 2;
- } else
- *carry_over = (last_entry | msg->buf[dev->pos]);
- } else {
- writel((last_entry | msg->buf[dev->pos]),
- dev->qup_base + QUP_OUT_FIFO_BASE);
+ qup_verify_fifo(dev, val | QUP_OUT_DATA << 16 |
+ msg->buf[dev->pos] << 16,
+ (unsigned)dev->qup_base +
+ QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
+ } else
+ val = QUP_OUT_DATA | msg->buf[dev->pos];
+ (*idx) += 2;
+ dev->pos++;
+ }
+ if (dev->pos < (msg->len - 1))
+ last_entry = QUP_OUT_DATA;
+ else if (rem > 1) /* not last array entry */
+ last_entry = QUP_OUT_DATA;
+ else
+ last_entry = QUP_OUT_STOP;
+ if ((*idx % 4) == 0) {
+ /*
+ * If read-start and read-command end up in different fifos, it
+ * may result in extra-byte being read due to extra-read cycle.
+ * Avoid that by inserting NOP as the last entry of fifo only
+ * if write command(s) leave 1 space in fifo.
+ */
+ if (rem > 1) {
+ struct i2c_msg *next = msg + 1;
+ if (next->addr == msg->addr && (next->flags | I2C_M_RD)
+ && *idx == ((dev->wr_sz * 2) - 4)) {
+ writel(((last_entry | msg->buf[dev->pos]) |
+ ((1 | QUP_OUT_NOP) << 16)),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
+ *idx += 2;
+ } else
+ *carry_over = (last_entry | msg->buf[dev->pos]);
+ } else {
+ writel((last_entry | msg->buf[dev->pos]),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, last_entry | msg->buf[dev->pos],
- (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE +
- (*idx), 0);
- }
- } else {
- writel(val | ((last_entry | msg->buf[dev->pos]) << 16),
- dev->qup_base + QUP_OUT_FIFO_BASE);
+ qup_verify_fifo(dev, last_entry | msg->buf[dev->pos],
+ (unsigned)dev->qup_base +
+ QUP_OUT_FIFO_BASE + (*idx), 0);
+ }
+ } else {
+ writel(val | ((last_entry | msg->buf[dev->pos]) << 16),
+ dev->qup_base + QUP_OUT_FIFO_BASE);
- qup_verify_fifo(dev, val | (last_entry << 16) |
- (msg->buf[dev->pos] << 16), (unsigned)dev->qup_base +
- QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
- }
+ qup_verify_fifo(dev, val | (last_entry << 16) |
+ (msg->buf[dev->pos] << 16),
+ (unsigned)dev->qup_base + QUP_OUT_FIFO_BASE +
+ (*idx) - 2, 0);
+ }
- *idx += 2;
- dev->pos++;
- dev->cnt = msg->len - dev->pos;
+ *idx += 2;
+ dev->pos++;
+ dev->cnt = msg->len - dev->pos;
}
static int qup_update_state(struct qup_i2c_dev *dev, unsigned state)
{
- if (qup_i2c_poll_state(dev, 0) != 0)
- return -EIO;
- writel(state, dev->qup_base + QUP_STATE);
- if (qup_i2c_poll_state(dev, state) != 0)
- return -EIO;
- return 0;
+ if (qup_i2c_poll_state(dev, 0) != 0)
+ return -EIO;
+ writel(state, dev->qup_base + QUP_STATE);
+ if (qup_i2c_poll_state(dev, state) != 0)
+ return -EIO;
+ return 0;
}
static int qup_set_read_mode(struct qup_i2c_dev *dev, int rd_len)
{
- unsigned wr_mode = (dev->wr_sz < dev->out_fifo_sz) ? QUP_WR_BLK_MODE : 0;
- if (rd_len > 256) {
- dprintf(INFO, "HW doesn't support READs > 256 bytes\n");
- return -EPROTONOSUPPORT;
- }
- if (rd_len <= dev->in_fifo_sz) {
- writel(wr_mode | QUP_PACK_EN | QUP_UNPACK_EN, dev->qup_base + QUP_IO_MODE);
- writel(rd_len, dev->qup_base + QUP_MX_READ_CNT);
- } else {
- writel(wr_mode | QUP_RD_BLK_MODE |
- QUP_PACK_EN | QUP_UNPACK_EN, dev->qup_base + QUP_IO_MODE);
- writel(rd_len, dev->qup_base + QUP_MX_INPUT_CNT);
- }
- return 0;
+ unsigned wr_mode =
+ (dev->wr_sz < dev->out_fifo_sz) ? QUP_WR_BLK_MODE : 0;
+ if (rd_len > 256) {
+ dprintf(INFO, "HW doesn't support READs > 256 bytes\n");
+ return -EPROTONOSUPPORT;
+ }
+ if (rd_len <= dev->in_fifo_sz) {
+ writel(wr_mode | QUP_PACK_EN | QUP_UNPACK_EN,
+ dev->qup_base + QUP_IO_MODE);
+ writel(rd_len, dev->qup_base + QUP_MX_READ_CNT);
+ } else {
+ writel(wr_mode | QUP_RD_BLK_MODE |
+ QUP_PACK_EN | QUP_UNPACK_EN,
+ dev->qup_base + QUP_IO_MODE);
+ writel(rd_len, dev->qup_base + QUP_MX_INPUT_CNT);
+ }
+ return 0;
}
static int qup_set_wr_mode(struct qup_i2c_dev *dev, int rem)
{
- int total_len = 0;
- int ret = 0;
- if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
- total_len = dev->msg->len + 1 + (dev->msg->len / (dev->out_blk_sz - 1));
- writel(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
- dev->qup_base + QUP_IO_MODE);
- dev->wr_sz = dev->out_blk_sz;
- } else
- writel(QUP_PACK_EN | QUP_UNPACK_EN, dev->qup_base + QUP_IO_MODE);
+ int total_len = 0;
+ int ret = 0;
+ if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
+ total_len =
+ dev->msg->len + 1 + (dev->msg->len / (dev->out_blk_sz - 1));
+ writel(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
+ dev->qup_base + QUP_IO_MODE);
+ dev->wr_sz = dev->out_blk_sz;
+ } else
+ writel(QUP_PACK_EN | QUP_UNPACK_EN,
+ dev->qup_base + QUP_IO_MODE);
- if (rem > 1) {
- struct i2c_msg *next = dev->msg + 1;
- if (next->addr == dev->msg->addr && next->flags == I2C_M_RD) {
- ret = qup_set_read_mode(dev, next->len);
- /* make sure read start & read command are in 1 blk */
- if ((total_len % dev->out_blk_sz) == (dev->out_blk_sz - 1))
- total_len += 3;
- else
- total_len += 2;
- }
- }
- /* WRITE COUNT register valid/used only in block mode */
- if (dev->wr_sz == dev->out_blk_sz)
- writel(total_len, dev->qup_base + QUP_MX_WR_CNT);
- return ret;
+ if (rem > 1) {
+ struct i2c_msg *next = dev->msg + 1;
+ if (next->addr == dev->msg->addr && next->flags == I2C_M_RD) {
+ ret = qup_set_read_mode(dev, next->len);
+ /* make sure read start & read command are in 1 blk */
+ if ((total_len % dev->out_blk_sz) ==
+ (dev->out_blk_sz - 1))
+ total_len += 3;
+ else
+ total_len += 2;
+ }
+ }
+ /* WRITE COUNT register valid/used only in block mode */
+ if (dev->wr_sz == dev->out_blk_sz)
+ writel(total_len, dev->qup_base + QUP_MX_WR_CNT);
+ return ret;
}
int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num)
{
- int ret;
- int rem = num;
- int err;
+ int ret;
+ int rem = num;
+ int err;
- if (dev->suspended) {
- return -EIO;
- }
+ if (dev->suspended) {
+ return -EIO;
+ }
- /* Set the GSBIn_QUP_APPS_CLK to 24MHz, then below figure out what speed to
- run I2C_MASTER_CORE at. */
- if (dev->clk_state == 0) {
- if (dev->clk_ctl == 0) {
- clock_config_i2c(dev->gsbi_number, dev->src_clk_freq);
- }
- }
- /* Initialize QUP registers during first transfer */
- if (dev->clk_ctl == 0) {
- int fs_div;
- int hs_div;
- unsigned fifo_reg;
- /* Configure the GSBI Protocol Code for i2c */
- writel((GSBI_PROTOCOL_CODE_I2C <<
- GSBI_CTRL_REG_PROTOCOL_CODE_S), GSBI_CTRL_REG(dev->gsbi_base));
+ /* Set the GSBIn_QUP_APPS_CLK to 24MHz, then below figure out what speed to
+ run I2C_MASTER_CORE at. */
+ if (dev->clk_state == 0) {
+ if (dev->clk_ctl == 0) {
+ clock_config_i2c(dev->gsbi_number, dev->src_clk_freq);
+ }
+ }
+ /* Initialize QUP registers during first transfer */
+ if (dev->clk_ctl == 0) {
+ int fs_div;
+ int hs_div;
+ unsigned fifo_reg;
+ /* Configure the GSBI Protocol Code for i2c */
+ writel((GSBI_PROTOCOL_CODE_I2C <<
+ GSBI_CTRL_REG_PROTOCOL_CODE_S),
+ GSBI_CTRL_REG(dev->gsbi_base));
- fs_div = ((dev->src_clk_freq / dev->clk_freq) / 2) - 3;
- hs_div = 3;
- dev->clk_ctl = ((hs_div & 0x7) << 8) | (fs_div & 0xff);
- fifo_reg = readl(dev->qup_base + QUP_IO_MODE);
- if (fifo_reg & 0x3)
- dev->out_blk_sz = (fifo_reg & 0x3) * 16;
- else
- dev->out_blk_sz = 16;
- if (fifo_reg & 0x60)
- dev->in_blk_sz = ((fifo_reg & 0x60) >> 5) * 16;
- else
- dev->in_blk_sz = 16;
- /*
- * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
- * associated with each byte written/received
- */
- dev->out_blk_sz /= 2;
- dev->in_blk_sz /= 2;
- dev->out_fifo_sz = dev->out_blk_sz * (2 << ((fifo_reg & 0x1C) >> 2));
- dev->in_fifo_sz = dev->in_blk_sz * (2 << ((fifo_reg & 0x380) >> 7));
- dprintf(INFO, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
- dev->in_blk_sz, dev->in_fifo_sz,
- dev->out_blk_sz, dev->out_fifo_sz);
- }
+ fs_div = ((dev->src_clk_freq / dev->clk_freq) / 2) - 3;
+ hs_div = 3;
+ dev->clk_ctl = ((hs_div & 0x7) << 8) | (fs_div & 0xff);
+ fifo_reg = readl(dev->qup_base + QUP_IO_MODE);
+ if (fifo_reg & 0x3)
+ dev->out_blk_sz = (fifo_reg & 0x3) * 16;
+ else
+ dev->out_blk_sz = 16;
+ if (fifo_reg & 0x60)
+ dev->in_blk_sz = ((fifo_reg & 0x60) >> 5) * 16;
+ else
+ dev->in_blk_sz = 16;
+ /*
+ * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
+ * associated with each byte written/received
+ */
+ dev->out_blk_sz /= 2;
+ dev->in_blk_sz /= 2;
+ dev->out_fifo_sz =
+ dev->out_blk_sz * (2 << ((fifo_reg & 0x1C) >> 2));
+ dev->in_fifo_sz =
+ dev->in_blk_sz * (2 << ((fifo_reg & 0x380) >> 7));
+ dprintf(INFO, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
+ dev->in_blk_sz, dev->in_fifo_sz, dev->out_blk_sz,
+ dev->out_fifo_sz);
+ }
- unmask_interrupt(dev->qup_irq);
- writel(1, dev->qup_base + QUP_SW_RESET);
- ret = qup_i2c_poll_state(dev, QUP_RESET_STATE);
- if (ret) {
- dprintf(INFO, "QUP Busy:Trying to recover\n");
- goto out_err;
- }
+ unmask_interrupt(dev->qup_irq);
+ writel(1, dev->qup_base + QUP_SW_RESET);
+ ret = qup_i2c_poll_state(dev, QUP_RESET_STATE);
+ if (ret) {
+ dprintf(INFO, "QUP Busy:Trying to recover\n");
+ goto out_err;
+ }
- /* Initialize QUP registers */
- writel(0, dev->qup_base + QUP_CONFIG);
- writel(QUP_OPERATIONAL_RESET, dev->qup_base + QUP_OPERATIONAL);
- writel(QUP_STATUS_ERROR_FLAGS, dev->qup_base + QUP_ERROR_FLAGS_EN);
+ /* Initialize QUP registers */
+ writel(0, dev->qup_base + QUP_CONFIG);
+ writel(QUP_OPERATIONAL_RESET, dev->qup_base + QUP_OPERATIONAL);
+ writel(QUP_STATUS_ERROR_FLAGS, dev->qup_base + QUP_ERROR_FLAGS_EN);
- writel(I2C_MINI_CORE | I2C_N_VAL, dev->qup_base + QUP_CONFIG);
+ writel(I2C_MINI_CORE | I2C_N_VAL, dev->qup_base + QUP_CONFIG);
- /* Initialize I2C mini core registers */
- writel(0, dev->qup_base + QUP_I2C_CLK_CTL);
- writel(QUP_I2C_STATUS_RESET, dev->qup_base + QUP_I2C_STATUS);
+ /* Initialize I2C mini core registers */
+ writel(0, dev->qup_base + QUP_I2C_CLK_CTL);
+ writel(QUP_I2C_STATUS_RESET, dev->qup_base + QUP_I2C_STATUS);
- dev->cnt = msgs->len;
- dev->pos = 0;
- dev->msg = msgs;
- while (rem) {
- int filled = FALSE;
+ dev->cnt = msgs->len;
+ dev->pos = 0;
+ dev->msg = msgs;
+ while (rem) {
+ int filled = FALSE;
- dev->wr_sz = dev->out_fifo_sz;
- dev->err = 0;
+ dev->wr_sz = dev->out_fifo_sz;
+ dev->err = 0;
- if (qup_i2c_poll_state(dev, QUP_I2C_MAST_GEN) != 0) {
- ret = -EIO;
- goto out_err;
- }
+ if (qup_i2c_poll_state(dev, QUP_I2C_MAST_GEN) != 0) {
+ ret = -EIO;
+ goto out_err;
+ }
- qup_print_status(dev);
- /* HW limits Read upto 256 bytes in 1 read without stop */
- if (dev->msg->flags & I2C_M_RD) {
- ret = qup_set_read_mode(dev, dev->cnt);
- if (ret != 0)
- goto out_err;
- } else {
- ret = qup_set_wr_mode(dev, rem);
- if (ret != 0)
- goto out_err;
- /* Don't fill block till we get interrupt */
- if (dev->wr_sz == dev->out_blk_sz)
- filled = TRUE;
- }
+ qup_print_status(dev);
+ /* HW limits Read upto 256 bytes in 1 read without stop */
+ if (dev->msg->flags & I2C_M_RD) {
+ ret = qup_set_read_mode(dev, dev->cnt);
+ if (ret != 0)
+ goto out_err;
+ } else {
+ ret = qup_set_wr_mode(dev, rem);
+ if (ret != 0)
+ goto out_err;
+ /* Don't fill block till we get interrupt */
+ if (dev->wr_sz == dev->out_blk_sz)
+ filled = TRUE;
+ }
- err = qup_update_state(dev, QUP_RUN_STATE);
- if (err < 0) {
- ret = err;
- goto out_err;
- }
+ err = qup_update_state(dev, QUP_RUN_STATE);
+ if (err < 0) {
+ ret = err;
+ goto out_err;
+ }
- qup_print_status(dev);
- writel(dev->clk_ctl, dev->qup_base + QUP_I2C_CLK_CTL);
+ qup_print_status(dev);
+ writel(dev->clk_ctl, dev->qup_base + QUP_I2C_CLK_CTL);
- do {
- int idx = 0;
- unsigned carry_over = 0;
+ do {
+ int idx = 0;
+ unsigned carry_over = 0;
- /* Transition to PAUSE state only possible from RUN */
- err = qup_update_state(dev, QUP_PAUSE_STATE);
- if (err < 0) {
- ret = err;
- goto out_err;
- }
+ /* Transition to PAUSE state only possible from RUN */
+ err = qup_update_state(dev, QUP_PAUSE_STATE);
+ if (err < 0) {
+ ret = err;
+ goto out_err;
+ }
- qup_print_status(dev);
- /* This operation is Write, check the next operation and decide
- mode */
- while (filled == FALSE) {
- if ((msgs->flags & I2C_M_RD) && (dev->cnt == msgs->len))
- qup_issue_read(dev, msgs, &idx, carry_over);
- else if (!(msgs->flags & I2C_M_RD))
- qup_issue_write(dev, msgs, rem, &idx, &carry_over);
- if (idx >= (dev->wr_sz << 1))
- filled = TRUE;
- /* Start new message */
- if (filled == FALSE) {
- if (msgs->flags & I2C_M_RD)
- filled = TRUE;
- else if (rem > 1) {
- /* Only combine operations with same address */
- struct i2c_msg *next = msgs + 1;
- if (next->addr != msgs->addr || next->flags == 0)
- filled = TRUE;
- else {
- rem--;
- msgs++;
- dev->msg = msgs;
- dev->pos = 0;
- dev->cnt = msgs->len;
- }
- } else
- filled = TRUE;
- }
- }
- err = qup_update_state(dev, QUP_RUN_STATE);
- if (err < 0) {
- ret = err;
- goto out_err;
- }
- dprintf(INFO, "idx:%d, rem:%d, num:%d, mode:%d\n",
- idx, rem, num, dev->mode);
+ qup_print_status(dev);
+ /* This operation is Write, check the next operation and decide
+ mode */
+ while (filled == FALSE) {
+ if ((msgs->flags & I2C_M_RD)
+ && (dev->cnt == msgs->len))
+ qup_issue_read(dev, msgs, &idx,
+ carry_over);
+ else if (!(msgs->flags & I2C_M_RD))
+ qup_issue_write(dev, msgs, rem, &idx,
+ &carry_over);
+ if (idx >= (dev->wr_sz << 1))
+ filled = TRUE;
+ /* Start new message */
+ if (filled == FALSE) {
+ if (msgs->flags & I2C_M_RD)
+ filled = TRUE;
+ else if (rem > 1) {
+ /* Only combine operations with same address */
+ struct i2c_msg *next = msgs + 1;
+ if (next->addr != msgs->addr
+ || next->flags == 0)
+ filled = TRUE;
+ else {
+ rem--;
+ msgs++;
+ dev->msg = msgs;
+ dev->pos = 0;
+ dev->cnt = msgs->len;
+ }
+ } else
+ filled = TRUE;
+ }
+ }
+ err = qup_update_state(dev, QUP_RUN_STATE);
+ if (err < 0) {
+ ret = err;
+ goto out_err;
+ }
+ dprintf(INFO, "idx:%d, rem:%d, num:%d, mode:%d\n",
+ idx, rem, num, dev->mode);
- qup_print_status(dev);
- if (dev->err) {
- if (dev->err & QUP_I2C_NACK_FLAG) {
- dprintf(CRITICAL,
- "I2C slave addr:0x%x not connected\n",
- dev->msg->addr);
- } else {
- dprintf(INFO, "QUP data xfer error %d\n", dev->err);
- }
- ret = dev->err;
- goto out_err;
- }
- if (dev->msg->flags & I2C_M_RD) {
- int i;
- unsigned dval = 0;
- for (i = 0; dev->pos < dev->msg->len; i++, dev->pos++) {
- unsigned rd_status = readl(dev->qup_base + QUP_OPERATIONAL);
- if (i % 2 == 0) {
- if ((rd_status & QUP_IN_NOT_EMPTY) == 0)
- break;
- dval = readl(dev->qup_base + QUP_IN_FIFO_BASE);
- dev->msg->buf[dev->pos] = dval & 0xFF;
- } else
- dev->msg->buf[dev->pos] = ((dval & 0xFF0000) >> 16);
- }
- dev->cnt -= i;
- } else
- filled = FALSE; /* refill output FIFO */
- } while (dev->cnt > 0);
- if (dev->cnt == 0) {
- rem--;
- msgs++;
- if (rem) {
- dev->pos = 0;
- dev->cnt = msgs->len;
- dev->msg = msgs;
- }
- }
- /* Wait for I2C bus to be idle */
- ret = qup_i2c_poll_writeready(dev);
- if (ret) {
- dprintf(INFO, "Error waiting for write ready\n");
- goto out_err;
- }
- }
+ qup_print_status(dev);
+ if (dev->err) {
+ if (dev->err & QUP_I2C_NACK_FLAG) {
+ dprintf(CRITICAL,
+ "I2C slave addr:0x%x not connected\n",
+ dev->msg->addr);
+ } else {
+ dprintf(INFO,
+ "QUP data xfer error %d\n",
+ dev->err);
+ }
+ ret = dev->err;
+ goto out_err;
+ }
+ if (dev->msg->flags & I2C_M_RD) {
+ int i;
+ unsigned dval = 0;
+ for (i = 0; dev->pos < dev->msg->len;
+ i++, dev->pos++) {
+ unsigned rd_status =
+ readl(dev->qup_base +
+ QUP_OPERATIONAL);
+ if (i % 2 == 0) {
+ if ((rd_status &
+ QUP_IN_NOT_EMPTY) == 0)
+ break;
+ dval =
+ readl(dev->qup_base +
+ QUP_IN_FIFO_BASE);
+ dev->msg->buf[dev->pos] =
+ dval & 0xFF;
+ } else
+ dev->msg->buf[dev->pos] =
+ ((dval & 0xFF0000) >> 16);
+ }
+ dev->cnt -= i;
+ } else
+ filled = FALSE; /* refill output FIFO */
+ }
+ while (dev->cnt > 0);
+ if (dev->cnt == 0) {
+ rem--;
+ msgs++;
+ if (rem) {
+ dev->pos = 0;
+ dev->cnt = msgs->len;
+ dev->msg = msgs;
+ }
+ }
+ /* Wait for I2C bus to be idle */
+ ret = qup_i2c_poll_writeready(dev);
+ if (ret) {
+ dprintf(INFO, "Error waiting for write ready\n");
+ goto out_err;
+ }
+ }
- ret = num;
-out_err:
- dev->msg = NULL;
- dev->pos = 0;
- dev->err = 0;
- dev->cnt = 0;
- mask_interrupt(dev->qup_irq);
- return ret;
+ ret = num;
+ out_err:
+ dev->msg = NULL;
+ dev->pos = 0;
+ dev->err = 0;
+ dev->cnt = 0;
+ mask_interrupt(dev->qup_irq);
+ return ret;
}
-struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id,
- unsigned clk_freq, unsigned src_clk_freq)
+struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id, unsigned clk_freq,
+ unsigned src_clk_freq)
{
- struct qup_i2c_dev *dev;
- if (dev_addr != NULL) {
- return dev_addr;
- }
+ struct qup_i2c_dev *dev;
+ if (dev_addr != NULL) {
+ return dev_addr;
+ }
- dev = malloc(sizeof(struct qup_i2c_dev));
- if (!dev) {
- return NULL;
- }
- dev = memset(dev, 0, sizeof(struct qup_i2c_dev));
+ dev = malloc(sizeof(struct qup_i2c_dev));
+ if (!dev) {
+ return NULL;
+ }
+ dev = memset(dev, 0, sizeof(struct qup_i2c_dev));
- /* Setup base addresses and irq based on gsbi_id */
- dev->qup_irq = GSBI_QUP_IRQ(gsbi_id);
- dev->qup_base = QUP_BASE(gsbi_id);
- dev->gsbi_base = GSBI_BASE(gsbi_id);
- dev->gsbi_number = gsbi_id;
+ /* Setup base addresses and irq based on gsbi_id */
+ dev->qup_irq = GSBI_QUP_IRQ(gsbi_id);
+ dev->qup_base = QUP_BASE(gsbi_id);
+ dev->gsbi_base = GSBI_BASE(gsbi_id);
+ dev->gsbi_number = gsbi_id;
- /* This must be done for qup_i2c_interrupt to work. */
- dev_addr = dev;
+ /* This must be done for qup_i2c_interrupt to work. */
+ dev_addr = dev;
- /* Initialize the GPIO for GSBIn as i2c */
- gpio_config_i2c(dev->gsbi_number);
+ /* Initialize the GPIO for GSBIn as i2c */
+ gpio_config_i2c(dev->gsbi_number);
- /* Configure the GSBI Protocol Code for i2c */
- writel((GSBI_PROTOCOL_CODE_I2C <<
- GSBI_CTRL_REG_PROTOCOL_CODE_S), GSBI_CTRL_REG(dev->gsbi_base));
+ /* Configure the GSBI Protocol Code for i2c */
+ writel((GSBI_PROTOCOL_CODE_I2C <<
+ GSBI_CTRL_REG_PROTOCOL_CODE_S), GSBI_CTRL_REG(dev->gsbi_base));
- /* Set clk_freq and src_clk_freq for i2c. */
- dev->clk_freq = clk_freq;
- dev->src_clk_freq = src_clk_freq;
+ /* Set clk_freq and src_clk_freq for i2c. */
+ dev->clk_freq = clk_freq;
+ dev->src_clk_freq = src_clk_freq;
- dev->num_irqs = 1;
+ dev->num_irqs = 1;
- dev->one_bit_t = USEC_PER_SEC / dev->clk_freq;
- dev->clk_ctl = 0;
+ dev->one_bit_t = USEC_PER_SEC / dev->clk_freq;
+ dev->clk_ctl = 0;
- /* Register the GSBIn QUP IRQ */
- register_int_handler(dev->qup_irq, (int_handler) qup_i2c_interrupt, 0);
+ /* Register the GSBIn QUP IRQ */
+ register_int_handler(dev->qup_irq, (int_handler) qup_i2c_interrupt, 0);
- /* Then disable it */
- mask_interrupt(dev->qup_irq);
+ /* Then disable it */
+ mask_interrupt(dev->qup_irq);
- return dev;
+ return dev;
}
int qup_i2c_deinit(struct qup_i2c_dev *dev)
{
- /* Disable the qup_irq */
- mask_interrupt(dev->qup_irq);
- /* Free the memory used for dev */
- free(dev);
- return 0;
+ /* Disable the qup_irq */
+ mask_interrupt(dev->qup_irq);
+ /* Free the memory used for dev */
+ free(dev);
+ return 0;
}
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index 0458c76..2b45d4c 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -32,8 +32,9 @@
/*
* Returns -1 if decryption failed otherwise size of plain_text in bytes
*/
-static int image_decrypt_signature(unsigned char * signature_ptr,
- unsigned char * plain_text){
+static int
+image_decrypt_signature(unsigned char *signature_ptr, unsigned char *plain_text)
+{
/*
* Extract Public Key and Decrypt Signature
*/
@@ -42,30 +43,29 @@
unsigned char *cert_ptr = certBuffer;
unsigned int cert_size = sizeof(certBuffer);
EVP_PKEY *pub_key = NULL;
- RSA* rsa_key = NULL;
+ RSA *rsa_key = NULL;
/*
* Get Pubkey and Convert the internal EVP_PKEY to RSA internal struct
*/
- if ((x509_certificate = d2i_X509(NULL, &cert_ptr, cert_size)) == NULL){
+ if ((x509_certificate = d2i_X509(NULL, &cert_ptr, cert_size)) == NULL) {
dprintf(CRITICAL,
"ERROR: Image Invalid, X509_Certificate is NULL!\n");
goto cleanup;
}
pub_key = X509_get_pubkey(x509_certificate);
rsa_key = EVP_PKEY_get1_RSA(pub_key);
- if (rsa_key == NULL){
- dprintf(CRITICAL,
- "ERROR: Boot Invalid, RSA_KEY is NULL!\n");
+ if (rsa_key == NULL) {
+ dprintf(CRITICAL, "ERROR: Boot Invalid, RSA_KEY is NULL!\n");
goto cleanup;
}
ret = RSA_public_decrypt(SIGNATURE_SIZE, signature_ptr, plain_text,
- rsa_key, RSA_PKCS1_PADDING);
- dprintf(SPEW,
- "DEBUG openssl: Return of RSA_public_decrypt = %d\n", ret);
+ rsa_key, RSA_PKCS1_PADDING);
+ dprintf(SPEW, "DEBUG openssl: Return of RSA_public_decrypt = %d\n",
+ ret);
-cleanup:
+ cleanup:
if (rsa_key != NULL)
RSA_free(rsa_key);
if (x509_certificate != NULL)
@@ -80,25 +80,26 @@
* Returns 0 when image is unauthorized.
* Expects a pointer to the start of image and pointer to start of sig
*/
-int image_verify(unsigned char * image_ptr,
- unsigned char * signature_ptr,
- unsigned int image_size,
- unsigned hash_type){
+int
+image_verify(unsigned char *image_ptr,
+ unsigned char *signature_ptr,
+ unsigned int image_size, unsigned hash_type)
+{
int ret = -1;
int auth = 0;
- unsigned char * plain_text = NULL;
+ unsigned char *plain_text = NULL;
unsigned int digest[8];
unsigned int hash_size;
- plain_text = (unsigned char*) calloc(sizeof(char), SIGNATURE_SIZE);
- if (plain_text == NULL){
+ plain_text = (unsigned char *)calloc(sizeof(char), SIGNATURE_SIZE);
+ if (plain_text == NULL) {
dprintf(CRITICAL, "ERROR: Calloc failed during verification\n");
goto cleanup;
}
ret = image_decrypt_signature(signature_ptr, plain_text);
- if (ret == -1){
+ if (ret == -1) {
dprintf(CRITICAL, "ERROR: Image Invalid! Decryption failed!\n");
goto cleanup;
}
@@ -106,25 +107,21 @@
/*
* Calculate hash of image for comparison
*/
- hash_size = (hash_type == CRYPTO_AUTH_ALG_SHA256) ?
- SHA256_SIZE : SHA1_SIZE;
- hash_find(image_ptr, image_size,
- (unsigned char*)&digest, hash_type);
- if(memcmp(plain_text, digest, hash_size) != 0)
- {
+ hash_size =
+ (hash_type == CRYPTO_AUTH_ALG_SHA256) ? SHA256_SIZE : SHA1_SIZE;
+ hash_find(image_ptr, image_size, (unsigned char *)&digest, hash_type);
+ if (memcmp(plain_text, digest, hash_size) != 0) {
dprintf(CRITICAL,
"ERROR: Image Invalid! Please use another image!\n");
ret = -1;
goto cleanup;
- }
- else
- {
+ } else {
/* Authorized image */
auth = 1;
}
/* Cleanup after complete usage of openssl - cached data and objects */
-cleanup:
+ cleanup:
if (plain_text != NULL)
free(plain_text);
EVP_cleanup();
diff --git a/platform/msm_shared/include/baseband.h b/platform/msm_shared/include/baseband.h
index d5b916d..128da30 100644
--- a/platform/msm_shared/include/baseband.h
+++ b/platform/msm_shared/include/baseband.h
@@ -29,16 +29,14 @@
#ifndef __BASEBAND_H__
#define __BASEBAND_H__
-enum baseband
-{
- BASEBAND_MSM = 0,
- BASEBAND_APQ = 1,
- BASEBAND_CSFB = 2,
- BASEBAND_SVLTE1 = 3,
- BASEBAND_SVLTE2A = 4,
- BASEBAND_MDM = 5,
- BASEBAND_32BITS = 0x7FFFFFFF
+enum baseband {
+ BASEBAND_MSM = 0,
+ BASEBAND_APQ = 1,
+ BASEBAND_CSFB = 2,
+ BASEBAND_SVLTE1 = 3,
+ BASEBAND_SVLTE2A = 4,
+ BASEBAND_MDM = 5,
+ BASEBAND_32BITS = 0x7FFFFFFF
};
#endif
-
diff --git a/platform/msm_shared/include/certificate.h b/platform/msm_shared/include/certificate.h
index 7dde655..7a35904 100644
--- a/platform/msm_shared/include/certificate.h
+++ b/platform/msm_shared/include/certificate.h
@@ -28,4 +28,4 @@
*/
#define CERTIFICATE_SIZE 724
-extern const char certBuffer [CERTIFICATE_SIZE];
+extern const char certBuffer[CERTIFICATE_SIZE];
diff --git a/platform/msm_shared/include/crypto4_eng.h b/platform/msm_shared/include/crypto4_eng.h
index 8046a67..c1597e4 100644
--- a/platform/msm_shared/include/crypto4_eng.h
+++ b/platform/msm_shared/include/crypto4_eng.h
@@ -53,7 +53,6 @@
#define CRYPTO_AUTH_BYTECNTn(n) (0x04A0 + 4*(n))
#define CRYPTO_AUTH_IVn(n) (0x0450 + 4*(n))
-
/* Register bit definitions */
#define SW_ERR BIT(0)
#define OPERATION_DONE BIT(1)
diff --git a/platform/msm_shared/include/crypto_hash.h b/platform/msm_shared/include/crypto_hash.h
index 2f9af3c..87f9ea9 100644
--- a/platform/msm_shared/include/crypto_hash.h
+++ b/platform/msm_shared/include/crypto_hash.h
@@ -46,74 +46,74 @@
#define CRYPTO_ERR_FAIL 0x02
typedef enum {
- CRYPTO_SHA_ERR_NONE,
- CRYPTO_SHA_ERR_BUSY,
- CRYPTO_SHA_ERR_FAIL,
- CRYPTO_SHA_ERR_INVALID_PARAM,
-}crypto_result_type;
+ CRYPTO_SHA_ERR_NONE,
+ CRYPTO_SHA_ERR_BUSY,
+ CRYPTO_SHA_ERR_FAIL,
+ CRYPTO_SHA_ERR_INVALID_PARAM,
+} crypto_result_type;
typedef enum {
- CRYPTO_AUTH_ALG_SHA1=1,
- CRYPTO_AUTH_ALG_SHA256
-}crypto_auth_alg_type;
+ CRYPTO_AUTH_ALG_SHA1 = 1,
+ CRYPTO_AUTH_ALG_SHA256
+} crypto_auth_alg_type;
typedef struct {
- unsigned int auth_bytecnt[2];
- unsigned char saved_buff[64];
- unsigned char saved_buff_indx;
- unsigned int auth_iv[5];
- unsigned char flags;
-}crypto_SHA1_ctx;
+ unsigned int auth_bytecnt[2];
+ unsigned char saved_buff[64];
+ unsigned char saved_buff_indx;
+ unsigned int auth_iv[5];
+ unsigned char flags;
+} crypto_SHA1_ctx;
typedef struct {
- unsigned int auth_bytecnt[2];
- unsigned char saved_buff[64];
- unsigned char saved_buff_indx;
- unsigned int auth_iv[8];
- unsigned char flags;
-}crypto_SHA256_ctx;
+ unsigned int auth_bytecnt[2];
+ unsigned char saved_buff[64];
+ unsigned char saved_buff_indx;
+ unsigned int auth_iv[8];
+ unsigned char flags;
+} crypto_SHA256_ctx;
extern void crypto_eng_reset(void);
extern void crypto_eng_init(void);
extern void crypto_set_sha_ctx(void *ctx_ptr,
- unsigned int bytes_to_write,
- crypto_auth_alg_type auth_alg,
- bool first, bool last);
+ unsigned int bytes_to_write,
+ crypto_auth_alg_type auth_alg,
+ bool first, bool last);
extern void crypto_send_data(void *ctx_ptr,
- unsigned char *data_ptr, unsigned int buff_size,
- unsigned int bytes_to_write,
- unsigned int *ret_status);
+ unsigned char *data_ptr, unsigned int buff_size,
+ unsigned int bytes_to_write,
+ unsigned int *ret_status);
extern void crypto_get_digest(unsigned char *digest_ptr,
- unsigned int *ret_status,
- crypto_auth_alg_type auth_alg,bool last);
+ unsigned int *ret_status,
+ crypto_auth_alg_type auth_alg, bool last);
extern void crypto_get_ctx(void *ctx_ptr);
static void crypto_init(void);
static crypto_result_type do_sha(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr,
- crypto_auth_alg_type auth_alg);
+ unsigned int buff_size,
+ unsigned char *digest_ptr,
+ crypto_auth_alg_type auth_alg);
static crypto_result_type do_sha_update(void *ctx_ptr,
- unsigned char *buff_ptr,
- unsigned int buff_size,
- crypto_auth_alg_type auth_alg,
- bool first, bool last);
+ unsigned char *buff_ptr,
+ unsigned int buff_size,
+ crypto_auth_alg_type auth_alg,
+ bool first, bool last);
static unsigned int calc_num_bytes_to_send(void *ctx_ptr,
- unsigned int buff_size, bool last);
+ unsigned int buff_size, bool last);
static crypto_result_type crypto_sha256(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr);
+ unsigned int buff_size,
+ unsigned char *digest_ptr);
static crypto_result_type crypto_sha1(unsigned char *buff_ptr,
- unsigned int buff_size,
- unsigned char *digest_ptr);
+ unsigned int buff_size,
+ unsigned char *digest_ptr);
#endif
diff --git a/platform/msm_shared/include/gsbi.h b/platform/msm_shared/include/gsbi.h
index 4a70265..8d504a7 100644
--- a/platform/msm_shared/include/gsbi.h
+++ b/platform/msm_shared/include/gsbi.h
@@ -58,4 +58,3 @@
};
#endif
-
diff --git a/platform/msm_shared/include/hdmi.h b/platform/msm_shared/include/hdmi.h
index c084258..489da12 100644
--- a/platform/msm_shared/include/hdmi.h
+++ b/platform/msm_shared/include/hdmi.h
@@ -60,31 +60,31 @@
extern int pm8058_ldo_set_voltage();
extern int pm8058_vreg_enable();
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable);
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable);
void dtv_on();
struct hdmi_disp_mode_timing_type {
- uint32_t height;
- uint32_t hsync_porch_fp;
- uint32_t hsync_width;
- uint32_t hsync_porch_bp;
- uint32_t width;
- uint32_t vsync_porch_fp;
- uint32_t vsync_width;
- uint32_t vsync_porch_bp;
- uint32_t refresh_rate;
+ uint32_t height;
+ uint32_t hsync_porch_fp;
+ uint32_t hsync_width;
+ uint32_t hsync_porch_bp;
+ uint32_t width;
+ uint32_t vsync_porch_fp;
+ uint32_t vsync_width;
+ uint32_t vsync_porch_bp;
+ uint32_t refresh_rate;
};
static struct fbcon_config fb_cfg = {
- .height = DTV_FB_HEIGHT,
- .width = DTV_FB_WIDTH,
- .stride = DTV_FB_WIDTH,
- .format = DTV_FORMAT_RGB565,
- .bpp = DTV_BPP,
- .update_start = NULL,
- .update_done = NULL,
+ .height = DTV_FB_HEIGHT,
+ .width = DTV_FB_WIDTH,
+ .stride = DTV_FB_WIDTH,
+ .format = DTV_FORMAT_RGB565,
+ .bpp = DTV_BPP,
+ .update_start = NULL,
+ .update_done = NULL,
};
-#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
+#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
diff --git a/platform/msm_shared/include/i2c_qup.h b/platform/msm_shared/include/i2c_qup.h
index b143768..9041cdf 100644
--- a/platform/msm_shared/include/i2c_qup.h
+++ b/platform/msm_shared/include/i2c_qup.h
@@ -66,54 +66,54 @@
* need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
*/
struct i2c_msg {
- unsigned short addr; /* slave address */
- unsigned short flags;
-#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
-#define I2C_M_WR 0x0000 /* write data, from master to slave */
-#define I2C_M_RD 0x0001 /* read data, from slave to master */
-#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
-#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
-#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
-#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
-#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
- unsigned short len; /* msg length */
- unsigned char *buf; /* pointer to msg data */
+ unsigned short addr; /* slave address */
+ unsigned short flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_WR 0x0000 /* write data, from master to slave */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ unsigned short len; /* msg length */
+ unsigned char *buf; /* pointer to msg data */
};
struct qup_i2c_dev {
- unsigned int gsbi_base;
- unsigned int qup_base;
- unsigned int gsbi_number;
- int qup_irq;
- int num_irqs;
- struct i2c_msg *msg;
- int pos;
- int cnt;
- int err;
- int mode;
- int clk_ctl;
- int clk_freq;
- int src_clk_freq;
- int one_bit_t;
- int out_fifo_sz;
- int in_fifo_sz;
- int out_blk_sz;
- int in_blk_sz;
- int wr_sz;
- int suspended;
- int clk_state;
+ unsigned int gsbi_base;
+ unsigned int qup_base;
+ unsigned int gsbi_number;
+ int qup_irq;
+ int num_irqs;
+ struct i2c_msg *msg;
+ int pos;
+ int cnt;
+ int err;
+ int mode;
+ int clk_ctl;
+ int clk_freq;
+ int src_clk_freq;
+ int one_bit_t;
+ int out_fifo_sz;
+ int in_fifo_sz;
+ int out_blk_sz;
+ int in_blk_sz;
+ int wr_sz;
+ int suspended;
+ int clk_state;
};
/* Function Definitions */
struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id,
- unsigned clk_freq, unsigned src_clk_freq);
+ unsigned clk_freq, unsigned src_clk_freq);
int qup_i2c_deinit(struct qup_i2c_dev *dev);
int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num);
struct device {
- struct device *parent;
- const char *init_name; /* initial name of the device */
- void (*release) (struct device * dev);
+ struct device *parent;
+ const char *init_name; /* initial name of the device */
+ void (*release) (struct device * dev);
};
/**
@@ -123,19 +123,19 @@
* @IRQ_WAKE_THREAD handler requests to wake the handler thread
*/
enum irqreturn {
- IRQ_NONE,
- IRQ_HANDLED,
- IRQ_WAKE_THREAD,
- IRQ_FAIL,
+ IRQ_NONE,
+ IRQ_HANDLED,
+ IRQ_WAKE_THREAD,
+ IRQ_FAIL,
};
typedef enum irqreturn irqreturn_t;
#define I2C_SMBUS_BLOCK_MAX 32
union i2c_smbus_data {
- unsigned char byte;
- unsigned short word;
- unsigned char block[I2C_SMBUS_BLOCK_MAX + 2];
+ unsigned char byte;
+ unsigned short word;
+ unsigned char block[I2C_SMBUS_BLOCK_MAX + 2];
};
/*
@@ -143,18 +143,18 @@
* with the access algorithms necessary to access it.
*/
struct i2c_adapter {
- struct module *owner;
- unsigned int id;
- unsigned int class; /* classes to allow probing for */
- const struct i2c_algorithm *algo; /* the algorithm to access the bus */
- void *algo_data;
- /* data fields that are valid for all devices */
- unsigned int level; /* nesting level for lockdep */
- int timeout; /* in jiffies */
- int retries;
- struct device dev; /* the adapter device */
- int nr;
- char name[48];
+ struct module *owner;
+ unsigned int id;
+ unsigned int class; /* classes to allow probing for */
+ const struct i2c_algorithm *algo; /* the algorithm to access the bus */
+ void *algo_data;
+ /* data fields that are valid for all devices */
+ unsigned int level; /* nesting level for lockdep */
+ int timeout; /* in jiffies */
+ int retries;
+ struct device dev; /* the adapter device */
+ int nr;
+ char name[48];
};
/*
@@ -164,20 +164,20 @@
* to name two of the most common.
*/
struct i2c_algorithm {
- /* If an adapter algorithm can't do I2C-level access, set master_xfer to
- NULL. If an adapter algorithm can do SMBus access, set smbus_xfer. If
- set to NULL, the SMBus protocol is simulated using common I2C messages */
- /* master_xfer should return the number of messages successfully processed,
- or a negative value on error */
- int (*master_xfer) (struct i2c_adapter * adap, struct i2c_msg * msgs,
- int num);
- int (*smbus_xfer) (struct i2c_adapter * adap, unsigned short addr,
- unsigned short flags, char read_write,
- unsigned char command, int size,
- union i2c_smbus_data * data);
+ /* If an adapter algorithm can't do I2C-level access, set master_xfer to
+ NULL. If an adapter algorithm can do SMBus access, set smbus_xfer. If
+ set to NULL, the SMBus protocol is simulated using common I2C messages */
+ /* master_xfer should return the number of messages successfully processed,
+ or a negative value on error */
+ int (*master_xfer) (struct i2c_adapter * adap, struct i2c_msg * msgs,
+ int num);
+ int (*smbus_xfer) (struct i2c_adapter * adap, unsigned short addr,
+ unsigned short flags, char read_write,
+ unsigned char command, int size,
+ union i2c_smbus_data * data);
- /* To determine what the adapter supports */
- unsigned int (*functionality) (struct i2c_adapter *);
+ /* To determine what the adapter supports */
+ unsigned int (*functionality) (struct i2c_adapter *);
};
#define EIO 5
@@ -206,9 +206,9 @@
#define I2C_FUNC_I2C 0x00000001
#define I2C_FUNC_10BIT_ADDR 0x00000002
-#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_NOSTART etc. */
+#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_NOSTART etc. */
#define I2C_FUNC_SMBUS_PEC 0x00000008
-#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
+#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
#define I2C_FUNC_SMBUS_QUICK 0x00010000
#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
@@ -219,8 +219,8 @@
#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
-#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
-#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
+#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
+#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
I2C_FUNC_SMBUS_WRITE_BYTE)
@@ -242,4 +242,4 @@
I2C_FUNC_SMBUS_I2C_BLOCK | \
I2C_FUNC_SMBUS_PEC)
-#endif /* __I2C_QUP__ */
+#endif /* __I2C_QUP__ */
diff --git a/platform/msm_shared/include/image_verify.h b/platform/msm_shared/include/image_verify.h
index 96ab127..fb9e1c5 100644
--- a/platform/msm_shared/include/image_verify.h
+++ b/platform/msm_shared/include/image_verify.h
@@ -32,10 +32,9 @@
/* For keys of length 2048 bits */
#define SIGNATURE_SIZE 256
-static int image_decrypt_signature(unsigned char * signature_ptr,
- unsigned char * plain_text);
-int image_verify(unsigned char * image_ptr,
- unsigned char * signature_ptr,
- unsigned int image_size,
- unsigned hash_type);
+static int image_decrypt_signature(unsigned char *signature_ptr,
+ unsigned char *plain_text);
+int image_verify(unsigned char *image_ptr,
+ unsigned char *signature_ptr,
+ unsigned int image_size, unsigned hash_type);
#endif
diff --git a/platform/msm_shared/include/jtag.h b/platform/msm_shared/include/jtag.h
index e6476d7..c14d71f 100644
--- a/platform/msm_shared/include/jtag.h
+++ b/platform/msm_shared/include/jtag.h
@@ -26,15 +26,12 @@
* SUCH DAMAGE.
*/
-
#ifndef _JTAG_H_
#define _JTAG_H_
void jtag_okay(const char *msg);
void jtag_fail(const char *msg);
void jtag_dputc(unsigned ch);
-void jtag_cmd_loop(void (*do_cmd)(const char *, unsigned, unsigned, unsigned));
-
+void jtag_cmd_loop(void (*do_cmd) (const char *, unsigned, unsigned, unsigned));
#endif /*__JTAG_H_ */
-
diff --git a/platform/msm_shared/include/mddi.h b/platform/msm_shared/include/mddi.h
index d1d3a77..6c5fee0 100644
--- a/platform/msm_shared/include/mddi.h
+++ b/platform/msm_shared/include/mddi.h
@@ -31,54 +31,53 @@
struct fbcon_config;
-struct __attribute__((packed)) mddi_client_caps
-{
- unsigned short length;
- unsigned short type;
- unsigned short client_id;
+struct __attribute__ ((packed)) mddi_client_caps {
+ unsigned short length;
+ unsigned short type;
+ unsigned short client_id;
- unsigned short protocol_ver;
- unsigned short min_protocol_ver;
- unsigned short data_rate_cap;
- unsigned char interface_type_cap;
- unsigned char num_alt_displays;
- unsigned short postcal_data_rate;
- unsigned short bitmap_width;
- unsigned short bitmap_height;
- unsigned short display_window_width;
- unsigned short display_window_height;
- unsigned cmap_size;
- unsigned short cmap_rgb_width;
- unsigned short rgb_cap;
- unsigned char mono_cap;
- unsigned char reserved1;
- unsigned short ycbcr_cap;
- unsigned short bayer_cap;
- unsigned short alpha_cursor_planes;
- unsigned client_feature_cap;
- unsigned char max_video_frame_rate_cap;
- unsigned char min_video_frame_rate_cap;
- unsigned short min_sub_frame_rate;
- unsigned short audio_buf_depth;
- unsigned short audio_channel_cap;
- unsigned short audio_sampe_rate_rap;
- unsigned char audio_sample_res;
- unsigned char mic_audio_sample_res;
- unsigned short mic_sample_rate_cap;
- unsigned char keyboard_data_fmt;
- unsigned char pointing_device_data_fmt;
- unsigned short content_protection_type;
- unsigned short manufacturer_name;
- unsigned short product_code;
- unsigned short reserved3;
- unsigned serial_no;
- unsigned char week_of_manufacture;
- unsigned char year_of_manufacture;
+ unsigned short protocol_ver;
+ unsigned short min_protocol_ver;
+ unsigned short data_rate_cap;
+ unsigned char interface_type_cap;
+ unsigned char num_alt_displays;
+ unsigned short postcal_data_rate;
+ unsigned short bitmap_width;
+ unsigned short bitmap_height;
+ unsigned short display_window_width;
+ unsigned short display_window_height;
+ unsigned cmap_size;
+ unsigned short cmap_rgb_width;
+ unsigned short rgb_cap;
+ unsigned char mono_cap;
+ unsigned char reserved1;
+ unsigned short ycbcr_cap;
+ unsigned short bayer_cap;
+ unsigned short alpha_cursor_planes;
+ unsigned client_feature_cap;
+ unsigned char max_video_frame_rate_cap;
+ unsigned char min_video_frame_rate_cap;
+ unsigned short min_sub_frame_rate;
+ unsigned short audio_buf_depth;
+ unsigned short audio_channel_cap;
+ unsigned short audio_sampe_rate_rap;
+ unsigned char audio_sample_res;
+ unsigned char mic_audio_sample_res;
+ unsigned short mic_sample_rate_cap;
+ unsigned char keyboard_data_fmt;
+ unsigned char pointing_device_data_fmt;
+ unsigned short content_protection_type;
+ unsigned short manufacturer_name;
+ unsigned short product_code;
+ unsigned short reserved3;
+ unsigned serial_no;
+ unsigned char week_of_manufacture;
+ unsigned char year_of_manufacture;
- unsigned short crc;
+ unsigned short crc;
};
void mddi_remote_write(unsigned val, unsigned reg);
struct fbcon_config *mddi_init(void);
-#endif /* __PLATFORM_MDDI_H */
+#endif /* __PLATFORM_MDDI_H */
diff --git a/platform/msm_shared/include/mdp3.h b/platform/msm_shared/include/mdp3.h
index 773f1a3..9d690c6 100644
--- a/platform/msm_shared/include/mdp3.h
+++ b/platform/msm_shared/include/mdp3.h
@@ -33,19 +33,19 @@
#define FAIL 1
int mdp_setup_dma_p_video_mode(unsigned short disp_width,
- unsigned short disp_height,
- unsigned short img_width,
- unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned short pack_pattern,
- unsigned char ystride);
+ unsigned short disp_height,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned short pack_pattern,
+ unsigned char ystride);
void mdp_disable(void);
void mdp_shutdown(void);
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index 703a20f..3ee82b3 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -66,26 +66,27 @@
#define MDP_INTR_STATUS REG_MDP(0x00054)
void mdp_setup_dma_p_video_config(unsigned short pack_pattern,
- unsigned short img_width,
- unsigned short img_height,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned char ystride);
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned char ystride);
int mdp_setup_dma_p_video_mode(unsigned short disp_width,
- unsigned short disp_height,
- unsigned short img_width,
- unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned short pack_pattern,
- unsigned char ystride);
-int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, unsigned short num_of_lanes);
+ unsigned short disp_height,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned short pack_pattern,
+ unsigned char ystride);
+int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
+ unsigned short num_of_lanes);
void mdp_shutdown(void);
void mdp_disable(void);
void mdp_start_dma(void);
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 39f0fa6..b8a55fd 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -71,1198 +71,1714 @@
#define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C)
#define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090)
-#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */
-#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */
+#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */
+#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */
-#define DTYPE_GEN_WRITE2 0x23 /* 4th Byte is 0x80 */
-#define DTYPE_GEN_LWRITE 0x29 /* 4th Byte is 0xc0 */
-#define DTYPE_DCS_WRITE1 0x15 /* 4th Byte is 0x80 */
+#define DTYPE_GEN_WRITE2 0x23 /* 4th Byte is 0x80 */
+#define DTYPE_GEN_LWRITE 0x29 /* 4th Byte is 0xc0 */
+#define DTYPE_DCS_WRITE1 0x15 /* 4th Byte is 0x80 */
//BEGINNING OF Tochiba Config- video mode
static const unsigned char toshiba_panel_mcap_off[8] = {
- 0x02, 0x00, 0x29, 0xc0,
- 0xb2, 0x00, 0xff, 0xff
+ 0x02, 0x00, 0x29, 0xc0,
+ 0xb2, 0x00, 0xff, 0xff
};
static const unsigned char toshiba_panel_ena_test_reg[8] = {
- 0x03, 0x00, 0x29, 0xc0,
- 0xEF, 0x01, 0x01, 0xff
+ 0x03, 0x00, 0x29, 0xc0,
+ 0xEF, 0x01, 0x01, 0xff
};
static const unsigned char toshiba_panel_ena_test_reg_wvga[8] = {
- 0x03, 0x00, 0x29, 0xc0,
- 0xEF, 0x01, 0x01, 0xff
+ 0x03, 0x00, 0x29, 0xc0,
+ 0xEF, 0x01, 0x01, 0xff
};
static const unsigned char toshiba_panel_num_of_2lane[8] = {
- 0x03, 0x00, 0x29, 0xc0, // 63:2lane
- 0xEF, 0x60, 0x63, 0xff
+ 0x03, 0x00, 0x29, 0xc0, // 63:2lane
+ 0xEF, 0x60, 0x63, 0xff
};
static const unsigned char toshiba_panel_num_of_1lane[8] = {
- 0x03, 0x00, 0x29, 0xc0, // 62:1lane
- 0xEF, 0x60, 0x62, 0xff
+ 0x03, 0x00, 0x29, 0xc0, // 62:1lane
+ 0xEF, 0x60, 0x62, 0xff
};
static const unsigned char toshiba_panel_non_burst_sync_pulse[8] = {
- 0x03, 0x00, 0x29, 0xc0,
- 0xef, 0x61, 0x09, 0xff
+ 0x03, 0x00, 0x29, 0xc0,
+ 0xef, 0x61, 0x09, 0xff
};
static const unsigned char toshiba_panel_set_DMODE_WQVGA[8] = {
- 0x02, 0x00, 0x29, 0xc0,
- 0xB3, 0x01, 0xFF, 0xff
+ 0x02, 0x00, 0x29, 0xc0,
+ 0xB3, 0x01, 0xFF, 0xff
};
static const unsigned char toshiba_panel_set_DMODE_WVGA[8] = {
- 0x02, 0x00, 0x29, 0xc0,
- 0xB3, 0x00, 0xFF, 0xff
+ 0x02, 0x00, 0x29, 0xc0,
+ 0xB3, 0x00, 0xFF, 0xff
};
static const unsigned char toshiba_panel_set_intern_WR_clk1_wvga[8]
= {
- 0x03, 0x00, 0x29, 0xC0, // 1 last packet
- 0xef, 0x2f, 0xcc, 0xff,
+ 0x03, 0x00, 0x29, 0xC0, // 1 last packet
+ 0xef, 0x2f, 0xcc, 0xff,
};
static const unsigned char toshiba_panel_set_intern_WR_clk2_wvga[8]
= {
- 0x03, 0x00, 0x29, 0xC0, // 1 last packet
- 0xef, 0x6e, 0xdd, 0xff,
+ 0x03, 0x00, 0x29, 0xC0, // 1 last packet
+ 0xef, 0x6e, 0xdd, 0xff,
};
static const unsigned char
- toshiba_panel_set_intern_WR_clk1_wqvga[8] = {
+ toshiba_panel_set_intern_WR_clk1_wqvga[8] = {
- 0x03, 0x00, 0x29, 0xC0, // 1 last packet
- 0xef, 0x2f, 0x22, 0xff,
+ 0x03, 0x00, 0x29, 0xC0, // 1 last packet
+ 0xef, 0x2f, 0x22, 0xff,
};
static const unsigned char
- toshiba_panel_set_intern_WR_clk2_wqvga[8] = {
+ toshiba_panel_set_intern_WR_clk2_wqvga[8] = {
- 0x03, 0x00, 0x29, 0xC0, // 1 last packet
- 0xef, 0x6e, 0x33, 0xff,
+ 0x03, 0x00, 0x29, 0xC0, // 1 last packet
+ 0xef, 0x6e, 0x33, 0xff,
};
static const unsigned char toshiba_panel_set_hor_addr_2A_wvga[12] = {
- 0x05, 0x00, 0x39, 0xC0, // 1 last packet
- // 0x2A, 0x00, 0x08, 0x00,//100 = 64h
- // 0x6b, 0xFF, 0xFF, 0xFF,
- 0x2A, 0x00, 0x00, 0x01, // 0X1DF = 480-1 0X13F = 320-1
- 0xdf, 0xFF, 0xFF, 0xFF,
+ 0x05, 0x00, 0x39, 0xC0, // 1 last packet
+ // 0x2A, 0x00, 0x08, 0x00,//100 = 64h
+ // 0x6b, 0xFF, 0xFF, 0xFF,
+ 0x2A, 0x00, 0x00, 0x01, // 0X1DF = 480-1 0X13F = 320-1
+ 0xdf, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2B_wvga[12] = {
- 0x05, 0x00, 0x39, 0xC0, // 1 last packet
- // 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1
- // 0x6b, 0xFF, 0xFF, 0xFF,
- 0x2B, 0x00, 0x00, 0x03, // 0X355 = 854-1; 0X1DF = 480-1
- 0x55, 0xFF, 0xFF, 0xFF,
+ 0x05, 0x00, 0x39, 0xC0, // 1 last packet
+ // 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1
+ // 0x6b, 0xFF, 0xFF, 0xFF,
+ 0x2B, 0x00, 0x00, 0x03, // 0X355 = 854-1; 0X1DF = 480-1
+ 0x55, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2A_wqvga[12]
= {
- 0x05, 0x00, 0x39, 0xC0, // 1 last packet
- 0x2A, 0x00, 0x00, 0x00, // 0XEF = 240-1
- 0xef, 0xFF, 0xFF, 0xFF,
+ 0x05, 0x00, 0x39, 0xC0, // 1 last packet
+ 0x2A, 0x00, 0x00, 0x00, // 0XEF = 240-1
+ 0xef, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2B_wqvga[12]
= {
- 0x05, 0x00, 0x39, 0xC0, // 1 last packet
- 0x2B, 0x00, 0x00, 0x01, // 0X1aa = 427-1;
- 0xaa, 0xFF, 0xFF, 0xFF,
+ 0x05, 0x00, 0x39, 0xC0, // 1 last packet
+ 0x2B, 0x00, 0x00, 0x01, // 0X1aa = 427-1;
+ 0xaa, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_IFSEL[8] = {
- 0x02, 0x00, 0x29, 0xc0,
- 0x53, 0x01, 0xff, 0xff
+ 0x02, 0x00, 0x29, 0xc0,
+ 0x53, 0x01, 0xff, 0xff
};
static const unsigned char toshiba_panel_IFSEL_cmd_mode[8] = {
- 0x02, 0x00, 0x29, 0xc0,
- 0x53, 0x00, 0xff, 0xff
+ 0x02, 0x00, 0x29, 0xc0,
+ 0x53, 0x00, 0xff, 0xff
};
static const unsigned char toshiba_panel_exit_sleep[4] = {
- 0x11, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
- // params
+ 0x11, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
+ // params
};
static const unsigned char toshiba_panel_display_on[4] = {
- // 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1
- // params
- 0x29, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
- // params
+ // 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1
+ // params
+ 0x29, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
+ // params
};
//color mode off
static const unsigned char dsi_display_config_color_mode_off[4] = {
- 0x00, 0x00, 0x02, 0x80,
+ 0x00, 0x00, 0x02, 0x80,
};
//color mode on
static const unsigned char dsi_display_config_color_mode_on[4] = {
- 0x00, 0x00, 0x12, 0x80,
+ 0x00, 0x00, 0x12, 0x80,
};
//the end OF Tochiba Config- video mode
/* NOVATEK BLUE panel */
-static char novatek_panel_sw_reset[4] = {0x01, 0x00, 0x05, 0x00}; /* DTYPE_DCS_WRITE */
-static char novatek_panel_enter_sleep[4] = {0x10, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
-static char novatek_panel_exit_sleep[4] = {0x11, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
-static char novatek_panel_display_off[4] = {0x28, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
-static char novatek_panel_display_on[4] = {0x29, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
-static char novatek_panel_max_packet[4] = {0x04, 0x00, 0x37, 0x80}; /* DTYPE_SET_MAX_PACKET */
+static char novatek_panel_sw_reset[4] = { 0x01, 0x00, 0x05, 0x00 }; /* DTYPE_DCS_WRITE */
+static char novatek_panel_enter_sleep[4] = { 0x10, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
+static char novatek_panel_exit_sleep[4] = { 0x11, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
+static char novatek_panel_display_off[4] = { 0x28, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
+static char novatek_panel_display_on[4] = { 0x29, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
+static char novatek_panel_max_packet[4] = { 0x04, 0x00, 0x37, 0x80 }; /* DTYPE_SET_MAX_PACKET */
-static char novatek_panel_set_onelane[4] = {0xae, 0x01, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
-static char novatek_panel_rgb_888[4] = {0x3A, 0x77, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
-static char novatek_panel_set_twolane[4] = {0xae, 0x03, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_set_onelane[4] = { 0xae, 0x01, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_rgb_888[4] = { 0x3A, 0x77, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_set_twolane[4] = { 0xae, 0x03, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
-static char novatek_panel_manufacture_id[4] = {0x04, 0x00, 0x06, 0xA0}; /* DTYPE_DCS_READ */
+static char novatek_panel_manufacture_id[4] = { 0x04, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
/* commands by Novatke */
-static char novatek_panel_f4[4] = {0xf4, 0x55, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
-static char novatek_panel_8c[20] = { /* DTYPE_DCS_LWRITE */
- 0x10, 0x00, 0x39, 0xC0, 0x8C, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x08, 0x08, 0x00, 0x30, 0xC0, 0xB7, 0x37};
-static char novatek_panel_ff[4] = {0xff, 0x55, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_f4[4] = { 0xf4, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
-static char novatek_panel_set_width[12] = { /* DTYPE_DCS_LWRITE */
- 0x05, 0x00, 0x39, 0xC0,//1 last packet
- 0x2A, 0x00, 0x00, 0x02,//clmn:0 - 0x21B=539
- 0x1B, 0xFF, 0xFF, 0xFF
-}; /* 540 - 1 */
-static char novatek_panel_set_height[12] = { /* DTYPE_DCS_LWRITE */
- 0x05, 0x00, 0x39, 0xC0,//1 last packet
- 0x2B, 0x00, 0x00, 0x03,//row:0 - 0x3BF=959
- 0xBF, 0xFF, 0xFF, 0xFF,
-}; /* 960 - 1 */
+static char novatek_panel_8c[20] = { /* DTYPE_DCS_LWRITE */
+ 0x10, 0x00, 0x39, 0xC0, 0x8C, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x08, 0x00, 0x30, 0xC0, 0xB7, 0x37
+};
+static char novatek_panel_ff[4] = { 0xff, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
+
+static char novatek_panel_set_width[12] = { /* DTYPE_DCS_LWRITE */
+ 0x05, 0x00, 0x39, 0xC0, //1 last packet
+ 0x2A, 0x00, 0x00, 0x02, //clmn:0 - 0x21B=539
+ 0x1B, 0xFF, 0xFF, 0xFF
+}; /* 540 - 1 */
+
+static char novatek_panel_set_height[12] = { /* DTYPE_DCS_LWRITE */
+ 0x05, 0x00, 0x39, 0xC0, //1 last packet
+ 0x2B, 0x00, 0x00, 0x03, //row:0 - 0x3BF=959
+ 0xBF, 0xFF, 0xFF, 0xFF,
+}; /* 960 - 1 */
/* Commands to control Backlight */
-static char novatek_panel_set_led_pwm1[8] = { /* DTYPE_DCS_LWRITE */
- 0x02, 0x00, 0x39, 0xC0,//1 last packet
- 0x51, 0xFA, 0xFF, 0xFF, // Brightness level set to 0xFA -> 250
+static char novatek_panel_set_led_pwm1[8] = { /* DTYPE_DCS_LWRITE */
+ 0x02, 0x00, 0x39, 0xC0, //1 last packet
+ 0x51, 0xFA, 0xFF, 0xFF, // Brightness level set to 0xFA -> 250
};
-static char novatek_panel_set_led_pwm2[8] = { /* DTYPE_DCS_LWRITE */
- 0x02, 0x00, 0x39, 0xC0,
- 0x53, 0x24, 0xFF, 0xFF,
+
+static char novatek_panel_set_led_pwm2[8] = { /* DTYPE_DCS_LWRITE */
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x24, 0xFF, 0xFF,
};
-static char novatek_panel_set_led_pwm3[8] = { /* DTYPE_DCS_LWRITE */
- 0x02, 0x00, 0x39, 0xC0,
- 0x55, 0x00, 0xFF, 0xFF,
+
+static char novatek_panel_set_led_pwm3[8] = { /* DTYPE_DCS_LWRITE */
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x55, 0x00, 0xFF, 0xFF,
};
/* End of Novatek Blue panel commands */
/* Toshiba mdt61 panel cmds */
static const unsigned char toshiba_mdt61_mcap_start[4] = {
- 0xB0, 0x04, DTYPE_GEN_WRITE2, 0x80,
+ 0xB0, 0x04, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_num_out_pixelform[8] = {
- 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xB3, 0x00, 0x87, 0xFF
+ 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xB3, 0x00, 0x87, 0xFF
};
static const unsigned char toshiba_mdt61_dsi_ctrl[8] = {
- 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xB6, 0x30, 0x83, 0xFF
+ 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xB6, 0x30, 0x83, 0xFF
};
static const unsigned char toshiba_mdt61_panel_driving[12] = {
- 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC0, 0x01, 0x00, 0x85,
- 0x00, 0x00, 0x00, 0xFF
+ 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC0, 0x01, 0x00, 0x85,
+ 0x00, 0x00, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_dispV_timing[12] = {
- 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC1, 0x00, 0x10, 0x00,
- 0x01, 0xFF, 0xFF, 0xFF
+ 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC1, 0x00, 0x10, 0x00,
+ 0x01, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_dispCtrl[8] = {
- 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC3, 0x00, 0x19, 0xFF
+ 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC3, 0x00, 0x19, 0xFF
};
static const unsigned char toshiba_mdt61_test_mode_c4[4] = {
- 0xC4, 0x03, DTYPE_GEN_WRITE2, 0x80,
+ 0xC4, 0x03, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_dispH_timing[20] = {
- 0x0F, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC5, 0x00, 0x01, 0x05,
- 0x04, 0x5E, 0x00, 0x00,
- 0x00, 0x00, 0x0B, 0x17,
- 0x05, 0x00, 0x00, 0xFF
+ 0x0F, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC5, 0x00, 0x01, 0x05,
+ 0x04, 0x5E, 0x00, 0x00,
+ 0x00, 0x00, 0x0B, 0x17,
+ 0x05, 0x00, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_test_mode_c6[4] = {
- 0xC6, 0x00, DTYPE_GEN_WRITE2, 0x80,
+ 0xC6, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_gamma_setA[20] = {
- 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC8, 0x0A, 0x15, 0x18,
- 0x1B, 0x1C, 0x0D, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC8, 0x0A, 0x15, 0x18,
+ 0x1B, 0x1C, 0x0D, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_gamma_setB[20] = {
- 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xC9, 0x0D, 0x1D, 0x1F,
- 0x1F, 0x1F, 0x10, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xC9, 0x0D, 0x1D, 0x1F,
+ 0x1F, 0x1F, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_gamma_setC[20] = {
- 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xCA, 0x1E, 0x1F, 0x1E,
- 0x1D, 0x1D, 0x10, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xCA, 0x1E, 0x1F, 0x1E,
+ 0x1D, 0x1D, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_powerSet_ChrgPmp[12] = {
- 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD0, 0x02, 0x00, 0xA3,
- 0xB8, 0xFF, 0xFF, 0xFF
+ 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD0, 0x02, 0x00, 0xA3,
+ 0xB8, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_d1[12] = {
- 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD1, 0x10, 0x14, 0x53,
- 0x64, 0x00, 0xFF, 0xFF
+ 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD1, 0x10, 0x14, 0x53,
+ 0x64, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_powerSet_SrcAmp[8] = {
- 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD2, 0xB3, 0x00, 0xFF
+ 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD2, 0xB3, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_powerInt_PS[8] = {
- 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD3, 0x33, 0x03, 0xFF
+ 0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD3, 0x33, 0x03, 0xFF
};
static const unsigned char toshiba_mdt61_vreg[4] = {
- 0xD5, 0x00, DTYPE_GEN_WRITE2, 0x80,
+ 0xD5, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_test_mode_d6[4] = {
- 0xD6, 0x01, DTYPE_GEN_WRITE2, 0x80,
+ 0xD6, 0x01, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_timingCtrl_d7[16] = {
- 0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD7, 0x09, 0x00, 0x84,
- 0x81, 0x61, 0xBC, 0xB5,
- 0x05, 0xFF, 0xFF, 0xFF
+ 0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD7, 0x09, 0x00, 0x84,
+ 0x81, 0x61, 0xBC, 0xB5,
+ 0x05, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_timingCtrl_d8[12] = {
- 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD8, 0x04, 0x25, 0x90,
- 0x4C, 0x92, 0x00, 0xFF
+ 0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD8, 0x04, 0x25, 0x90,
+ 0x4C, 0x92, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_timingCtrl_d9[8] = {
- 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xD9, 0x5B, 0x7F, 0x05
+ 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xD9, 0x5B, 0x7F, 0x05
};
static const unsigned char toshiba_mdt61_white_balance[12] = {
- 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xCB, 0x00, 0x00, 0x00,
- 0x1C, 0x00, 0xFF, 0xFF
+ 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xCB, 0x00, 0x00, 0x00,
+ 0x1C, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_vcs_settings[4] = {
- 0xDD, 0x53, DTYPE_GEN_WRITE2, 0x80,
+ 0xDD, 0x53, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_vcom_dc_settings[4] = {
- 0xDE, 0x43, DTYPE_GEN_WRITE2, 0x80,
+ 0xDE, 0x43, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_testMode_e3[12] = {
- 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xE3, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xE3, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_e4[12] = {
- 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xE4, 0x00, 0x00, 0x22,
- 0xAA, 0x00, 0xFF, 0xFF
+ 0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xE4, 0x00, 0x00, 0x22,
+ 0xAA, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_e5[4] = {
- 0xE5, 0x00, DTYPE_GEN_WRITE2, 0x80,
+ 0xE5, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_testMode_fa[8] = {
- 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xFA, 0x00, 0x00, 0x00
+ 0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xFA, 0x00, 0x00, 0x00
};
-
static const unsigned char toshiba_mdt61_testMode_fd[12] = {
- 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xFD, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xFD, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
-
static const unsigned char toshiba_mdt61_testMode_fe[12] = {
- 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
- 0xFE, 0x00, 0x00, 0x00,
- 0x00, 0xFF, 0xFF, 0xFF
+ 0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+ 0xFE, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_mcap_end[4] = {
- 0xB0, 0x03, DTYPE_GEN_WRITE2, 0x80,
+ 0xB0, 0x03, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_set_add_mode[4] = {
- 0x36, 0x00, DTYPE_DCS_WRITE1, 0x80,
+ 0x36, 0x00, DTYPE_DCS_WRITE1, 0x80,
};
static const unsigned char toshiba_mdt61_set_pixel_format[4] = {
- 0x3A, 0x70, DTYPE_DCS_WRITE1, 0x80,
+ 0x3A, 0x70, DTYPE_DCS_WRITE1, 0x80,
};
/* Done Toshiba MDT61 Panel Commands */
/* Toshiba MDT61 (R69320) End */
-static const unsigned char dsi_display_exit_sleep[4] =
-{
-0x11, 0x00, 0x15, 0x80,
+static const unsigned char dsi_display_exit_sleep[4] = {
+ 0x11, 0x00, 0x15, 0x80,
};
-static const unsigned char dsi_display_display_on[4] =
-{
-0x29, 0x00, 0x15, 0x80,
+static const unsigned char dsi_display_display_on[4] = {
+ 0x29, 0x00, 0x15, 0x80,
};
#define MIPI_VIDEO_MODE 1
#define MIPI_CMD_MODE 2
struct mipi_dsi_phy_ctrl {
- uint32_t regulator[5];
- uint32_t timing[12];
- uint32_t ctrl[4];
- uint32_t strength[4];
- uint32_t pll[21];
+ uint32_t regulator[5];
+ uint32_t timing[12];
+ uint32_t ctrl[4];
+ uint32_t strength[4];
+ uint32_t pll[21];
};
struct mipi_dsi_cmd {
- int size;
- char *payload;
+ int size;
+ char *payload;
};
struct mipi_dsi_panel_config {
- char mode;
- char num_of_lanes;
- struct mipi_dsi_phy_ctrl *dsi_phy_config;
- struct mipi_dsi_cmd *panel_cmds;
- int num_of_panel_cmds;
- int lane_swap;
+ char mode;
+ char num_of_lanes;
+ struct mipi_dsi_phy_ctrl *dsi_phy_config;
+ struct mipi_dsi_cmd *panel_cmds;
+ int num_of_panel_cmds;
+ int lane_swap;
};
static struct mipi_dsi_cmd toshiba_panel_video_mode_cmds[] = {
- {sizeof(toshiba_panel_mcap_off), (char *) toshiba_panel_mcap_off},
- {sizeof(toshiba_panel_ena_test_reg), (char *) toshiba_panel_ena_test_reg},
- {sizeof(toshiba_panel_num_of_1lane), (char *) toshiba_panel_num_of_1lane},
- {sizeof(toshiba_panel_non_burst_sync_pulse), (char *) toshiba_panel_non_burst_sync_pulse},
- {sizeof(toshiba_panel_set_DMODE_WVGA), (char *) toshiba_panel_set_DMODE_WVGA},
- {sizeof(toshiba_panel_set_intern_WR_clk1_wvga), (char *) toshiba_panel_set_intern_WR_clk1_wvga},
- {sizeof(toshiba_panel_set_intern_WR_clk2_wvga), (char *) toshiba_panel_set_intern_WR_clk2_wvga},
- {sizeof(toshiba_panel_set_hor_addr_2A_wvga), (char *) toshiba_panel_set_hor_addr_2A_wvga},
- {sizeof(toshiba_panel_set_hor_addr_2B_wvga), (char *) toshiba_panel_set_hor_addr_2B_wvga},
- {sizeof(toshiba_panel_IFSEL), (char *) toshiba_panel_IFSEL},
- {sizeof(toshiba_panel_exit_sleep), (char *) toshiba_panel_exit_sleep},
- {sizeof(toshiba_panel_display_on), (char *) toshiba_panel_display_on},
- {sizeof(dsi_display_config_color_mode_on), (char *) dsi_display_config_color_mode_on},
- {sizeof(dsi_display_config_color_mode_off), (char *) dsi_display_config_color_mode_off},
+ {sizeof(toshiba_panel_mcap_off), (char *)toshiba_panel_mcap_off},
+ {sizeof(toshiba_panel_ena_test_reg),
+ (char *)toshiba_panel_ena_test_reg},
+ {sizeof(toshiba_panel_num_of_1lane),
+ (char *)toshiba_panel_num_of_1lane},
+ {sizeof(toshiba_panel_non_burst_sync_pulse),
+ (char *)toshiba_panel_non_burst_sync_pulse},
+ {sizeof(toshiba_panel_set_DMODE_WVGA),
+ (char *)toshiba_panel_set_DMODE_WVGA},
+ {sizeof(toshiba_panel_set_intern_WR_clk1_wvga),
+ (char *)toshiba_panel_set_intern_WR_clk1_wvga},
+ {sizeof(toshiba_panel_set_intern_WR_clk2_wvga),
+ (char *)toshiba_panel_set_intern_WR_clk2_wvga},
+ {sizeof(toshiba_panel_set_hor_addr_2A_wvga),
+ (char *)toshiba_panel_set_hor_addr_2A_wvga},
+ {sizeof(toshiba_panel_set_hor_addr_2B_wvga),
+ (char *)toshiba_panel_set_hor_addr_2B_wvga},
+ {sizeof(toshiba_panel_IFSEL), (char *)toshiba_panel_IFSEL},
+ {sizeof(toshiba_panel_exit_sleep), (char *)toshiba_panel_exit_sleep},
+ {sizeof(toshiba_panel_display_on), (char *)toshiba_panel_display_on},
+ {sizeof(dsi_display_config_color_mode_on),
+ (char *)dsi_display_config_color_mode_on},
+ {sizeof(dsi_display_config_color_mode_off),
+ (char *)dsi_display_config_color_mode_off},
};
static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_panel_phy_ctrl = {
/* 480*854, RGB888, 1 Lane 60 fps video mode */
- {0x03, 0x01, 0x01, 0x00}, /* regulator */
- /* timing */
- {0x50, 0x0f, 0x14, 0x19, 0x23, 0x0e, 0x12, 0x16,
- 0x1b, 0x1c, 0x04},
- {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
- {0xee, 0x03, 0x86, 0x03}, /* strength */
- /* pll control */
+ {0x03, 0x01, 0x01, 0x00}, /* regulator */
+ /* timing */
+ {0x50, 0x0f, 0x14, 0x19, 0x23, 0x0e, 0x12, 0x16,
+ 0x1b, 0x1c, 0x04},
+ {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
+ {0xee, 0x03, 0x86, 0x03}, /* strength */
+ /* pll control */
#if defined(DSI_BIT_CLK_366MHZ)
- {0x41, 0xdb, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
- 0x31, 0x0f, 0x07,
- 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+ {0x41, 0xdb, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
+ 0x31, 0x0f, 0x07,
+ 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#elif defined(DSI_BIT_CLK_380MHZ)
- {0x41, 0xf7, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
- 0x31, 0x0f, 0x07,
- 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+ {0x41, 0xf7, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
+ 0x31, 0x0f, 0x07,
+ 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#elif defined(DSI_BIT_CLK_400MHZ)
- {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
- 0x31, 0x0f, 0x07,
- 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
-#else /* 200 mhz */
- {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
- 0x33, 0x1f, 0x1f /* for 1 lane ; 0x0f for 2 lanes*/,
- 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+ {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
+ 0x31, 0x0f, 0x07,
+ 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
+#else /* 200 mhz */
+ {0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
+ 0x33, 0x1f, 0x1f /* for 1 lane ; 0x0f for 2 lanes */ ,
+ 0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#endif
};
-
static struct mipi_dsi_cmd toshiba_mdt61_video_mode_cmds[] = {
- {sizeof(toshiba_mdt61_mcap_start), (char *) toshiba_mdt61_mcap_start},
- {sizeof(toshiba_mdt61_num_out_pixelform), (char *) toshiba_mdt61_num_out_pixelform},
- {sizeof(toshiba_mdt61_dsi_ctrl), (char *) toshiba_mdt61_dsi_ctrl},
- {sizeof(toshiba_mdt61_panel_driving), (char *) toshiba_mdt61_panel_driving},
- {sizeof(toshiba_mdt61_dispV_timing), (char *) toshiba_mdt61_dispV_timing},
- {sizeof(toshiba_mdt61_dispCtrl), (char *) toshiba_mdt61_dispCtrl},
- {sizeof(toshiba_mdt61_test_mode_c4), (char *) toshiba_mdt61_test_mode_c4},
- {sizeof(toshiba_mdt61_dispH_timing), (char *) toshiba_mdt61_dispH_timing},
- {sizeof(toshiba_mdt61_test_mode_c6), (char *) toshiba_mdt61_test_mode_c6},
- {sizeof(toshiba_mdt61_gamma_setA), (char *) toshiba_mdt61_gamma_setA},
- {sizeof(toshiba_mdt61_gamma_setB), (char *) toshiba_mdt61_gamma_setB},
- {sizeof(toshiba_mdt61_gamma_setC), (char *) toshiba_mdt61_gamma_setC},
- {sizeof(toshiba_mdt61_powerSet_ChrgPmp), (char *) toshiba_mdt61_powerSet_ChrgPmp},
- {sizeof(toshiba_mdt61_testMode_d1), (char *) toshiba_mdt61_testMode_d1},
- {sizeof(toshiba_mdt61_powerSet_SrcAmp), (char * )toshiba_mdt61_powerSet_SrcAmp},
- {sizeof(toshiba_mdt61_powerInt_PS), (char *) toshiba_mdt61_powerInt_PS},
- {sizeof(toshiba_mdt61_vreg), (char *) toshiba_mdt61_vreg},
- {sizeof(toshiba_mdt61_test_mode_d6), (char *) toshiba_mdt61_test_mode_d6},
- {sizeof(toshiba_mdt61_timingCtrl_d7), (char *) toshiba_mdt61_timingCtrl_d7},
- {sizeof(toshiba_mdt61_timingCtrl_d8), (char *) toshiba_mdt61_timingCtrl_d8},
- {sizeof(toshiba_mdt61_timingCtrl_d9), (char *) toshiba_mdt61_timingCtrl_d9},
- {sizeof(toshiba_mdt61_white_balance), (char *) toshiba_mdt61_white_balance},
- {sizeof(toshiba_mdt61_vcs_settings), (char *) toshiba_mdt61_vcs_settings},
- {sizeof(toshiba_mdt61_vcom_dc_settings), (char *) toshiba_mdt61_vcom_dc_settings},
- {sizeof(toshiba_mdt61_testMode_e3), (char *) toshiba_mdt61_testMode_e3},
- {sizeof(toshiba_mdt61_testMode_e4), (char *) toshiba_mdt61_testMode_e4},
- {sizeof(toshiba_mdt61_testMode_e5), (char *) toshiba_mdt61_testMode_e5},
- {sizeof(toshiba_mdt61_testMode_fa), (char *) toshiba_mdt61_testMode_fa},
- {sizeof(toshiba_mdt61_testMode_fd), (char *) toshiba_mdt61_testMode_fd},
- {sizeof(toshiba_mdt61_testMode_fe), (char *) toshiba_mdt61_testMode_fe},
- {sizeof(toshiba_mdt61_mcap_end), (char *) toshiba_mdt61_mcap_end},
- {sizeof(toshiba_mdt61_set_add_mode), (char *) toshiba_mdt61_set_add_mode},
- {sizeof(toshiba_mdt61_set_pixel_format), (char *) toshiba_mdt61_set_pixel_format},
- {sizeof(dsi_display_exit_sleep), (char *) dsi_display_exit_sleep},
- {sizeof(dsi_display_display_on), (char *) dsi_display_display_on},
+ {sizeof(toshiba_mdt61_mcap_start), (char *)toshiba_mdt61_mcap_start},
+ {sizeof(toshiba_mdt61_num_out_pixelform),
+ (char *)toshiba_mdt61_num_out_pixelform},
+ {sizeof(toshiba_mdt61_dsi_ctrl), (char *)toshiba_mdt61_dsi_ctrl},
+ {sizeof(toshiba_mdt61_panel_driving),
+ (char *)toshiba_mdt61_panel_driving},
+ {sizeof(toshiba_mdt61_dispV_timing),
+ (char *)toshiba_mdt61_dispV_timing},
+ {sizeof(toshiba_mdt61_dispCtrl), (char *)toshiba_mdt61_dispCtrl},
+ {sizeof(toshiba_mdt61_test_mode_c4),
+ (char *)toshiba_mdt61_test_mode_c4},
+ {sizeof(toshiba_mdt61_dispH_timing),
+ (char *)toshiba_mdt61_dispH_timing},
+ {sizeof(toshiba_mdt61_test_mode_c6),
+ (char *)toshiba_mdt61_test_mode_c6},
+ {sizeof(toshiba_mdt61_gamma_setA), (char *)toshiba_mdt61_gamma_setA},
+ {sizeof(toshiba_mdt61_gamma_setB), (char *)toshiba_mdt61_gamma_setB},
+ {sizeof(toshiba_mdt61_gamma_setC), (char *)toshiba_mdt61_gamma_setC},
+ {sizeof(toshiba_mdt61_powerSet_ChrgPmp),
+ (char *)toshiba_mdt61_powerSet_ChrgPmp},
+ {sizeof(toshiba_mdt61_testMode_d1), (char *)toshiba_mdt61_testMode_d1},
+ {sizeof(toshiba_mdt61_powerSet_SrcAmp),
+ (char *)toshiba_mdt61_powerSet_SrcAmp},
+ {sizeof(toshiba_mdt61_powerInt_PS), (char *)toshiba_mdt61_powerInt_PS},
+ {sizeof(toshiba_mdt61_vreg), (char *)toshiba_mdt61_vreg},
+ {sizeof(toshiba_mdt61_test_mode_d6),
+ (char *)toshiba_mdt61_test_mode_d6},
+ {sizeof(toshiba_mdt61_timingCtrl_d7),
+ (char *)toshiba_mdt61_timingCtrl_d7},
+ {sizeof(toshiba_mdt61_timingCtrl_d8),
+ (char *)toshiba_mdt61_timingCtrl_d8},
+ {sizeof(toshiba_mdt61_timingCtrl_d9),
+ (char *)toshiba_mdt61_timingCtrl_d9},
+ {sizeof(toshiba_mdt61_white_balance),
+ (char *)toshiba_mdt61_white_balance},
+ {sizeof(toshiba_mdt61_vcs_settings),
+ (char *)toshiba_mdt61_vcs_settings},
+ {sizeof(toshiba_mdt61_vcom_dc_settings),
+ (char *)toshiba_mdt61_vcom_dc_settings},
+ {sizeof(toshiba_mdt61_testMode_e3), (char *)toshiba_mdt61_testMode_e3},
+ {sizeof(toshiba_mdt61_testMode_e4), (char *)toshiba_mdt61_testMode_e4},
+ {sizeof(toshiba_mdt61_testMode_e5), (char *)toshiba_mdt61_testMode_e5},
+ {sizeof(toshiba_mdt61_testMode_fa), (char *)toshiba_mdt61_testMode_fa},
+ {sizeof(toshiba_mdt61_testMode_fd), (char *)toshiba_mdt61_testMode_fd},
+ {sizeof(toshiba_mdt61_testMode_fe), (char *)toshiba_mdt61_testMode_fe},
+ {sizeof(toshiba_mdt61_mcap_end), (char *)toshiba_mdt61_mcap_end},
+ {sizeof(toshiba_mdt61_set_add_mode),
+ (char *)toshiba_mdt61_set_add_mode},
+ {sizeof(toshiba_mdt61_set_pixel_format),
+ (char *)toshiba_mdt61_set_pixel_format},
+ {sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep},
+ {sizeof(dsi_display_display_on), (char *)dsi_display_display_on},
};
static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_mdt61_panel_phy_ctrl = {
/* 600*1024, RGB888, 3 Lane 55 fps video mode */
- {0x03, 0x0a, 0x04, 0x00, 0x20},
- /* timing */
- {0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
- 0x0c, 0x03, 0x04, 0xa0},
- {0x5f, 0x00, 0x00, 0x10}, /* phy ctrl */
- {0xff, 0x00, 0x06, 0x00}, /* strength */
+ {0x03, 0x0a, 0x04, 0x00, 0x20},
+ /* timing */
+ {0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
+ 0x0c, 0x03, 0x04, 0xa0},
+ {0x5f, 0x00, 0x00, 0x10}, /* phy ctrl */
+ {0xff, 0x00, 0x06, 0x00}, /* strength */
- /* pll control 1- 19 */
- {0x01, 0x7f, 0x31, 0xda, 0x00, 0x40, 0x03, 0x62,
- 0x41, 0x0f, 0x01,
- 0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01, 0x00 },
+ /* pll control 1- 19 */
+ {0x01, 0x7f, 0x31, 0xda, 0x00, 0x40, 0x03, 0x62,
+ 0x41, 0x0f, 0x01,
+ 0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01, 0x00},
};
static struct mipi_dsi_cmd novatek_panel_manufacture_id_cmd =
- {sizeof(novatek_panel_manufacture_id), novatek_panel_manufacture_id};
+ { sizeof(novatek_panel_manufacture_id), novatek_panel_manufacture_id };
static struct mipi_dsi_cmd novatek_panel_cmd_mode_cmds[] = {
- {sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset},
- {sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep},
- {sizeof(novatek_panel_display_on), novatek_panel_display_on},
- {sizeof(novatek_panel_max_packet), novatek_panel_max_packet},
- {sizeof(novatek_panel_f4), novatek_panel_f4},
- {sizeof(novatek_panel_8c), novatek_panel_8c},
- {sizeof(novatek_panel_ff), novatek_panel_ff},
- {sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane},
- {sizeof(novatek_panel_set_width), novatek_panel_set_width},
- {sizeof(novatek_panel_set_height), novatek_panel_set_height},
- {sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888},
- {sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1},
- {sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2},
- {sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3}
+ {sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset}
+ ,
+ {sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep}
+ ,
+ {sizeof(novatek_panel_display_on), novatek_panel_display_on}
+ ,
+ {sizeof(novatek_panel_max_packet), novatek_panel_max_packet}
+ ,
+ {sizeof(novatek_panel_f4), novatek_panel_f4}
+ ,
+ {sizeof(novatek_panel_8c), novatek_panel_8c}
+ ,
+ {sizeof(novatek_panel_ff), novatek_panel_ff}
+ ,
+ {sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane}
+ ,
+ {sizeof(novatek_panel_set_width), novatek_panel_set_width}
+ ,
+ {sizeof(novatek_panel_set_height), novatek_panel_set_height}
+ ,
+ {sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888}
+ ,
+ {sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1}
+ ,
+ {sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2}
+ ,
+ {sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3}
};
static struct mipi_dsi_phy_ctrl mipi_dsi_novatek_panel_phy_ctrl = {
- /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
- {0x03, 0x01, 0x01, 0x00}, /* regulator */
- /* timing */
- {0x96, 0x26, 0x23, 0x00, 0x50, 0x4B, 0x1e,
- 0x28, 0x28, 0x03, 0x04},
- {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
- {0xee, 0x02, 0x86, 0x00}, /* strength */
- /* pll control */
- {0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
- /* 0x30, 0x07, 0x07, --> One lane configuration */
- 0x30, 0x07, 0x03, /* --> Two lane configuration */
- 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
+ /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
+ {0x03, 0x01, 0x01, 0x00}, /* regulator */
+ /* timing */
+ {0x96, 0x26, 0x23, 0x00, 0x50, 0x4B, 0x1e,
+ 0x28, 0x28, 0x03, 0x04},
+ {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
+ {0xee, 0x02, 0x86, 0x00}, /* strength */
+ /* pll control */
+ {0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
+ /* 0x30, 0x07, 0x07, --> One lane configuration */
+ 0x30, 0x07, 0x03, /* --> Two lane configuration */
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
};
/* Renesas Tremelo-M panel: List of commands */
-static char config_sleep_out[4] = {0x11, 0x00, 0x05, 0x80};
-static char config_CMD_MODE[4] = {0x40, 0x01, 0x15, 0x80};
-static char config_WRTXHT[12] = {0x07, 0x00, 0x39, 0xC0, 0x92, 0x16, 0x08, 0x08, 0x00, 0x01, 0xe0, 0xff};
-static char config_WRTXVT[12] = {0x07, 0x00, 0x39, 0xC0, 0x8b, 0x02, 0x02, 0x02, 0x00, 0x03, 0x60, 0xff};
-static char config_PLL2NR[4] = {0xa0, 0x24, 0x15, 0x80};
-static char config_PLL2NF1[4] = {0xa2, 0xd0, 0x15, 0x80};
-static char config_PLL2NF2[4] = {0xa4, 0x00, 0x15, 0x80};
-static char config_PLL2BWADJ1[4] = {0xa6, 0xd0, 0x15, 0x80};
-static char config_PLL2BWADJ2[4] = {0xa8, 0x00, 0x15, 0x80};
-static char config_PLL2CTL[4] = {0xaa, 0x00, 0x15, 0x80};
-static char config_DBICBR[4] = {0x48, 0x03, 0x15, 0x80};
-static char config_DBICTYPE[4] = {0x49, 0x00, 0x15, 0x80};
-static char config_DBICSET1[4] = {0x4a, 0x1c, 0x15, 0x80};
-static char config_DBICADD[4] = {0x4b, 0x00, 0x15, 0x80};
-static char config_DBICCTL[4] = {0x4e, 0x01, 0x15, 0x80};
+static char config_sleep_out[4] = { 0x11, 0x00, 0x05, 0x80 };
+static char config_CMD_MODE[4] = { 0x40, 0x01, 0x15, 0x80 };
+static char config_WRTXHT[12] =
+ { 0x07, 0x00, 0x39, 0xC0, 0x92, 0x16, 0x08, 0x08, 0x00, 0x01, 0xe0, 0xff };
+static char config_WRTXVT[12] =
+ { 0x07, 0x00, 0x39, 0xC0, 0x8b, 0x02, 0x02, 0x02, 0x00, 0x03, 0x60, 0xff };
+static char config_PLL2NR[4] = { 0xa0, 0x24, 0x15, 0x80 };
+static char config_PLL2NF1[4] = { 0xa2, 0xd0, 0x15, 0x80 };
+static char config_PLL2NF2[4] = { 0xa4, 0x00, 0x15, 0x80 };
+static char config_PLL2BWADJ1[4] = { 0xa6, 0xd0, 0x15, 0x80 };
+static char config_PLL2BWADJ2[4] = { 0xa8, 0x00, 0x15, 0x80 };
+static char config_PLL2CTL[4] = { 0xaa, 0x00, 0x15, 0x80 };
+static char config_DBICBR[4] = { 0x48, 0x03, 0x15, 0x80 };
+static char config_DBICTYPE[4] = { 0x49, 0x00, 0x15, 0x80 };
+static char config_DBICSET1[4] = { 0x4a, 0x1c, 0x15, 0x80 };
+static char config_DBICADD[4] = { 0x4b, 0x00, 0x15, 0x80 };
+static char config_DBICCTL[4] = { 0x4e, 0x01, 0x15, 0x80 };
+
/* static char config_COLMOD_565[4] = {0x3a, 0x05, 0x15, 0x80}; */
/* static char config_COLMOD_666PACK[4] = {0x3a, 0x06, 0x15, 0x80}; */
-static char config_COLMOD_888[4] = {0x3a, 0x07, 0x15, 0x80};
-static char config_MADCTL[4] = {0x36, 0x00, 0x15, 0x80};
-static char config_DBIOC[4] = {0x82, 0x40, 0x15, 0x80};
-static char config_CASET[12] = {0x07, 0x00, 0x39, 0xC0, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf , 0xff};
-static char config_PASET[12] = {0x07, 0x00, 0x39, 0xC0, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x5f , 0xff};
-static char config_TXON[4] = {0x81, 0x00, 0x05, 0x80};
-static char config_BLSET_TM[4] = {0xff, 0x6c, 0x15, 0x80};
+static char config_COLMOD_888[4] = { 0x3a, 0x07, 0x15, 0x80 };
+static char config_MADCTL[4] = { 0x36, 0x00, 0x15, 0x80 };
+static char config_DBIOC[4] = { 0x82, 0x40, 0x15, 0x80 };
+static char config_CASET[12] =
+ { 0x07, 0x00, 0x39, 0xC0, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf, 0xff };
+static char config_PASET[12] =
+ { 0x07, 0x00, 0x39, 0xC0, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x5f, 0xff };
+static char config_TXON[4] = { 0x81, 0x00, 0x05, 0x80 };
+static char config_BLSET_TM[4] = { 0xff, 0x6c, 0x15, 0x80 };
-static char config_AGCPSCTL_TM[4] = {0x56, 0x08, 0x15, 0x80};
+static char config_AGCPSCTL_TM[4] = { 0x56, 0x08, 0x15, 0x80 };
-static char config_DBICADD70[4] = {0x4b, 0x70, 0x15, 0x80};
-static char config_DBICSET_15[4] = {0x4a, 0x15, 0x15, 0x80};
-static char config_DBICADD72[4] = {0x4b, 0x72, 0x15, 0x80};
+static char config_DBICADD70[4] = { 0x4b, 0x70, 0x15, 0x80 };
+static char config_DBICSET_15[4] = { 0x4a, 0x15, 0x15, 0x80 };
+static char config_DBICADD72[4] = { 0x4b, 0x72, 0x15, 0x80 };
-static char config_Power_Ctrl_2a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff};
-static char config_Auto_Sequencer_Setting_a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char Driver_Output_Ctrl_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff};
-static char Driver_Output_Ctrl_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff};
-static char config_LCD_drive_AC_Ctrl_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff};
-static char config_LCD_drive_AC_Ctrl_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff};
-static char config_Entry_Mode_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff};
-static char config_Entry_Mode_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_Display_Ctrl_1_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x07, 0xff};
-static char config_Display_Ctrl_1_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_Display_Ctrl_2_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x08, 0xff};
-static char config_Display_Ctrl_2_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x04, 0xff};
-static char config_Display_Ctrl_3_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x09, 0xff};
-static char config_Display_Ctrl_3_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff};
-static char config_Display_IF_Ctrl_1_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff};
-static char config_Display_IF_Ctrl_1_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff};
-static char config_Display_IF_Ctrl_2_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0e, 0xff};
-static char config_Display_IF_Ctrl_2_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
+static char config_Power_Ctrl_2a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
+static char config_Auto_Sequencer_Setting_a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char Driver_Output_Ctrl_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff };
+static char Driver_Output_Ctrl_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff };
+static char config_LCD_drive_AC_Ctrl_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
+static char config_LCD_drive_AC_Ctrl_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff };
+static char config_Entry_Mode_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff };
+static char config_Entry_Mode_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_Display_Ctrl_1_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x07, 0xff };
+static char config_Display_Ctrl_1_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_Display_Ctrl_2_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x08, 0xff };
+static char config_Display_Ctrl_2_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x04, 0xff };
+static char config_Display_Ctrl_3_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x09, 0xff };
+static char config_Display_Ctrl_3_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff };
+static char config_Display_IF_Ctrl_1_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff };
+static char config_Display_IF_Ctrl_1_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
+static char config_Display_IF_Ctrl_2_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0e, 0xff };
+static char config_Display_IF_Ctrl_2_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
-static char config_Panel_IF_Ctrl_1_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x20, 0xff};
-static char config_Panel_IF_Ctrl_1_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x3f, 0xff};
-static char config_Panel_IF_Ctrl_3_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x22, 0xff};
-static char config_Panel_IF_Ctrl_3_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x00, 0xff};
-static char config_Panel_IF_Ctrl_4_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x23, 0xff};
-static char config_Panel_IF_Ctrl_4_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x0a, 0xff};
-static char config_Panel_IF_Ctrl_5_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x24, 0xff};
-static char config_Panel_IF_Ctrl_5_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x2c, 0xff};
-static char config_Panel_IF_Ctrl_6_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x25, 0xff};
-static char config_Panel_IF_Ctrl_6_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x4e, 0xff};
-static char config_Panel_IF_Ctrl_8_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x27, 0xff};
-static char config_Panel_IF_Ctrl_8_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_Panel_IF_Ctrl_9_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x28, 0xff};
-static char config_Panel_IF_Ctrl_9_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x0c, 0xff};
+static char config_Panel_IF_Ctrl_1_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x20, 0xff };
+static char config_Panel_IF_Ctrl_1_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x3f, 0xff };
+static char config_Panel_IF_Ctrl_3_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x22, 0xff };
+static char config_Panel_IF_Ctrl_3_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x00, 0xff };
+static char config_Panel_IF_Ctrl_4_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x23, 0xff };
+static char config_Panel_IF_Ctrl_4_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x0a, 0xff };
+static char config_Panel_IF_Ctrl_5_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x24, 0xff };
+static char config_Panel_IF_Ctrl_5_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x2c, 0xff };
+static char config_Panel_IF_Ctrl_6_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x25, 0xff };
+static char config_Panel_IF_Ctrl_6_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x4e, 0xff };
+static char config_Panel_IF_Ctrl_8_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x27, 0xff };
+static char config_Panel_IF_Ctrl_8_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_Panel_IF_Ctrl_9_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x28, 0xff };
+static char config_Panel_IF_Ctrl_9_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x0c, 0xff };
-static char config_gam_adjust_00_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff};
-static char config_gam_adjust_00_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_gam_adjust_01_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x01, 0xff};
-static char config_gam_adjust_01_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x02, 0xff};
-static char config_gam_adjust_02_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x02, 0xff};
-static char config_gam_adjust_02_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x05, 0xff};
-static char config_gam_adjust_03_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x03, 0xff};
-static char config_gam_adjust_03_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_gam_adjust_04_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff};
-static char config_gam_adjust_04_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x00, 0xff};
-static char config_gam_adjust_05_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff};
-static char config_gam_adjust_05_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff};
-static char config_gam_adjust_06_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x06, 0xff};
-static char config_gam_adjust_06_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff};
-static char config_gam_adjust_07_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x07, 0xff};
-static char config_gam_adjust_07_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x02, 0xff};
-static char config_gam_adjust_08_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x08, 0xff};
-static char config_gam_adjust_08_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x04, 0xff};
-static char config_gam_adjust_09_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x09, 0xff};
-static char config_gam_adjust_09_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff};
-static char config_gam_adjust_0A_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0a, 0xff};
-static char config_gam_adjust_0A_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_gam_adjust_0B_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0b, 0xff};
-static char config_gam_adjust_0B_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff};
-static char config_gam_adjust_0C_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0c, 0xff};
-static char config_gam_adjust_0C_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff};
-static char config_gam_adjust_0D_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0d, 0xff};
-static char config_gam_adjust_0D_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff};
-static char config_gam_adjust_10_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff};
-static char config_gam_adjust_10_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x04, 0xff};
-static char config_gam_adjust_11_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x11, 0xff};
-static char config_gam_adjust_11_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x03, 0xff};
-static char config_gam_adjust_12_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x12, 0xff};
-static char config_gam_adjust_12_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff};
-static char config_gam_adjust_15_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x15, 0xff};
-static char config_gam_adjust_15_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff};
-static char config_gam_adjust_16_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x16, 0xff};
-static char config_gam_adjust_16_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff};
-static char config_gam_adjust_17_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x17, 0xff};
-static char config_gam_adjust_17_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x04, 0xff};
-static char config_gam_adjust_18_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x18, 0xff};
-static char config_gam_adjust_18_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x02, 0xff};
-static char config_gam_adjust_19_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x19, 0xff};
-static char config_gam_adjust_19_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff};
-static char config_gam_adjust_1C_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff};
-static char config_gam_adjust_1C_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff};
-static char config_gam_adjust_1D_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1D, 0xff};
-static char config_gam_adjust_1D_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x1f, 0xff};
-static char config_gam_adjust_20_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x20, 0xff};
-static char config_gam_adjust_20_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x07, 0xff};
-static char config_gam_adjust_21_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x21, 0xff};
-static char config_gam_adjust_21_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x06, 0x04, 0xff};
-static char config_gam_adjust_22_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x22, 0xff};
-static char config_gam_adjust_22_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x05, 0xff};
-static char config_gam_adjust_27_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x27, 0xff};
-static char config_gam_adjust_27_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x03, 0xff};
-static char config_gam_adjust_28_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x28, 0xff};
-static char config_gam_adjust_28_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff};
-static char config_gam_adjust_29_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x29, 0xff};
-static char config_gam_adjust_29_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff};
+static char config_gam_adjust_00_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff };
+static char config_gam_adjust_00_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_gam_adjust_01_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x01, 0xff };
+static char config_gam_adjust_01_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x02, 0xff };
+static char config_gam_adjust_02_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x02, 0xff };
+static char config_gam_adjust_02_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x05, 0xff };
+static char config_gam_adjust_03_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x03, 0xff };
+static char config_gam_adjust_03_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_gam_adjust_04_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
+static char config_gam_adjust_04_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x00, 0xff };
+static char config_gam_adjust_05_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff };
+static char config_gam_adjust_05_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
+static char config_gam_adjust_06_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x06, 0xff };
+static char config_gam_adjust_06_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff };
+static char config_gam_adjust_07_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x07, 0xff };
+static char config_gam_adjust_07_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x02, 0xff };
+static char config_gam_adjust_08_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x08, 0xff };
+static char config_gam_adjust_08_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x04, 0xff };
+static char config_gam_adjust_09_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x09, 0xff };
+static char config_gam_adjust_09_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
+static char config_gam_adjust_0A_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0a, 0xff };
+static char config_gam_adjust_0A_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_gam_adjust_0B_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0b, 0xff };
+static char config_gam_adjust_0B_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
+static char config_gam_adjust_0C_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0c, 0xff };
+static char config_gam_adjust_0C_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
+static char config_gam_adjust_0D_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0d, 0xff };
+static char config_gam_adjust_0D_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff };
+static char config_gam_adjust_10_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff };
+static char config_gam_adjust_10_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x04, 0xff };
+static char config_gam_adjust_11_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x11, 0xff };
+static char config_gam_adjust_11_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x03, 0xff };
+static char config_gam_adjust_12_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x12, 0xff };
+static char config_gam_adjust_12_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
+static char config_gam_adjust_15_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x15, 0xff };
+static char config_gam_adjust_15_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
+static char config_gam_adjust_16_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x16, 0xff };
+static char config_gam_adjust_16_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff };
+static char config_gam_adjust_17_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x17, 0xff };
+static char config_gam_adjust_17_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x04, 0xff };
+static char config_gam_adjust_18_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x18, 0xff };
+static char config_gam_adjust_18_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x02, 0xff };
+static char config_gam_adjust_19_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x19, 0xff };
+static char config_gam_adjust_19_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff };
+static char config_gam_adjust_1C_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff };
+static char config_gam_adjust_1C_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
+static char config_gam_adjust_1D_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1D, 0xff };
+static char config_gam_adjust_1D_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x1f, 0xff };
+static char config_gam_adjust_20_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x20, 0xff };
+static char config_gam_adjust_20_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x07, 0xff };
+static char config_gam_adjust_21_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x21, 0xff };
+static char config_gam_adjust_21_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x06, 0x04, 0xff };
+static char config_gam_adjust_22_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x22, 0xff };
+static char config_gam_adjust_22_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x05, 0xff };
+static char config_gam_adjust_27_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x27, 0xff };
+static char config_gam_adjust_27_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x03, 0xff };
+static char config_gam_adjust_28_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x28, 0xff };
+static char config_gam_adjust_28_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff };
+static char config_gam_adjust_29_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x29, 0xff };
+static char config_gam_adjust_29_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
-static char config_Power_Ctrl_1_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff};
-static char config_Power_Ctrl_1b_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x36, 0x3c, 0xff};
-static char config_Power_Ctrl_2_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x01, 0xff};
-static char config_Power_Ctrl_2b_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x03, 0xff};
-static char config_Power_Ctrl_3_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x02, 0xff};
-static char config_Power_Ctrl_3a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff};
-static char config_Power_Ctrl_4_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x03, 0xff};
-static char config_Power_Ctrl_4a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x3c, 0x58, 0xff};
-static char config_Power_Ctrl_6_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x0c, 0xff};
-static char config_Power_Ctrl_6a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x35, 0xff};
+static char config_Power_Ctrl_1_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff };
+static char config_Power_Ctrl_1b_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x36, 0x3c, 0xff };
+static char config_Power_Ctrl_2_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x01, 0xff };
+static char config_Power_Ctrl_2b_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x03, 0xff };
+static char config_Power_Ctrl_3_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x02, 0xff };
+static char config_Power_Ctrl_3a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff };
+static char config_Power_Ctrl_4_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x03, 0xff };
+static char config_Power_Ctrl_4a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x3c, 0x58, 0xff };
+static char config_Power_Ctrl_6_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x0c, 0xff };
+static char config_Power_Ctrl_6a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x35, 0xff };
-static char config_Auto_Sequencer_Setting_b_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff};
+static char config_Auto_Sequencer_Setting_b_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
-static char config_Panel_IF_Ctrl_10_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x29, 0xff};
-static char config_Panel_IF_Ctrl_10a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0xbf, 0xff};
-static char config_Auto_Sequencer_Setting_indx[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x06, 0xff};
-static char config_Auto_Sequencer_Setting_c_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff};
-static char config_Power_Ctrl_2c_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff};
+static char config_Panel_IF_Ctrl_10_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x29, 0xff };
+static char config_Panel_IF_Ctrl_10a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0xbf, 0xff };
+static char config_Auto_Sequencer_Setting_indx[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x06, 0xff };
+static char config_Auto_Sequencer_Setting_c_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff };
+static char config_Power_Ctrl_2c_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
-static char config_VIDEO[4] = {0x40, 0x00, 0x15, 0x80};
+static char config_VIDEO[4] = { 0x40, 0x00, 0x15, 0x80 };
-static char config_Panel_IF_Ctrl_10_indx_off[8] = {0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x29, 0xff};
+static char config_Panel_IF_Ctrl_10_indx_off[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x29, 0xff };
-static char config_Panel_IF_Ctrl_10b_cmd_off[8] = {0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x02, 0xff};
+static char config_Panel_IF_Ctrl_10b_cmd_off[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x02, 0xff };
-static char config_Power_Ctrl_1a_cmd[8] = {0x03, 0x00, 0x39, 0xC0, 0x4C, 0x30, 0x00, 0xff};
-
+static char config_Power_Ctrl_1a_cmd[8] =
+ { 0x03, 0x00, 0x39, 0xC0, 0x4C, 0x30, 0x00, 0xff };
static struct mipi_dsi_cmd renesas_panel_video_mode_cmds[] = {
- {sizeof(config_sleep_out), config_sleep_out},
- {sizeof(config_CMD_MODE), config_CMD_MODE},
- {sizeof(config_WRTXHT), config_WRTXHT},
- {sizeof(config_WRTXVT), config_WRTXVT},
- {sizeof(config_PLL2NR), config_PLL2NR },
- {sizeof(config_PLL2NF1), config_PLL2NF1 },
- {sizeof(config_PLL2NF2), config_PLL2NF2 },
- {sizeof(config_PLL2BWADJ1), config_PLL2BWADJ1},
- {sizeof(config_PLL2BWADJ2), config_PLL2BWADJ2},
- {sizeof(config_PLL2CTL), config_PLL2CTL},
- {sizeof(config_DBICBR), config_DBICBR},
- {sizeof(config_DBICTYPE), config_DBICTYPE},
- {sizeof(config_DBICSET1), config_DBICSET1},
- {sizeof(config_DBICADD), config_DBICADD},
- {sizeof(config_DBICCTL), config_DBICCTL},
- {sizeof(config_COLMOD_888), config_COLMOD_888},
+ {sizeof(config_sleep_out), config_sleep_out}
+ ,
+ {sizeof(config_CMD_MODE), config_CMD_MODE}
+ ,
+ {sizeof(config_WRTXHT), config_WRTXHT}
+ ,
+ {sizeof(config_WRTXVT), config_WRTXVT}
+ ,
+ {sizeof(config_PLL2NR), config_PLL2NR}
+ ,
+ {sizeof(config_PLL2NF1), config_PLL2NF1}
+ ,
+ {sizeof(config_PLL2NF2), config_PLL2NF2}
+ ,
+ {sizeof(config_PLL2BWADJ1), config_PLL2BWADJ1}
+ ,
+ {sizeof(config_PLL2BWADJ2), config_PLL2BWADJ2}
+ ,
+ {sizeof(config_PLL2CTL), config_PLL2CTL}
+ ,
+ {sizeof(config_DBICBR), config_DBICBR}
+ ,
+ {sizeof(config_DBICTYPE), config_DBICTYPE}
+ ,
+ {sizeof(config_DBICSET1), config_DBICSET1}
+ ,
+ {sizeof(config_DBICADD), config_DBICADD}
+ ,
+ {sizeof(config_DBICCTL), config_DBICCTL}
+ ,
+ {sizeof(config_COLMOD_888), config_COLMOD_888}
+ ,
/* Choose config_COLMOD_565 or config_COLMOD_666PACK for other modes */
- {sizeof(config_MADCTL), config_MADCTL},
- {sizeof(config_DBIOC), config_DBIOC},
- {sizeof(config_CASET), config_CASET},
- {sizeof(config_PASET), config_PASET},
- {sizeof(config_TXON), config_TXON},
- {sizeof(config_BLSET_TM), config_BLSET_TM},
- {sizeof(config_AGCPSCTL_TM), config_AGCPSCTL_TM},
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_1a_cmd), config_Power_Ctrl_1a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_2a_cmd), config_Power_Ctrl_2a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_MADCTL), config_MADCTL}
+ ,
+ {sizeof(config_DBIOC), config_DBIOC}
+ ,
+ {sizeof(config_CASET), config_CASET}
+ ,
+ {sizeof(config_PASET), config_PASET}
+ ,
+ {sizeof(config_TXON), config_TXON}
+ ,
+ {sizeof(config_BLSET_TM), config_BLSET_TM}
+ ,
+ {sizeof(config_AGCPSCTL_TM), config_AGCPSCTL_TM}
+ ,
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_1a_cmd), config_Power_Ctrl_1a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_2a_cmd), config_Power_Ctrl_2a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Auto_Sequencer_Setting_indx),
- config_Auto_Sequencer_Setting_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Auto_Sequencer_Setting_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Auto_Sequencer_Setting_a_cmd),
- config_Auto_Sequencer_Setting_a_cmd },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Auto_Sequencer_Setting_a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(Driver_Output_Ctrl_indx), Driver_Output_Ctrl_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(Driver_Output_Ctrl_indx), Driver_Output_Ctrl_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(Driver_Output_Ctrl_cmd),
- Driver_Output_Ctrl_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ Driver_Output_Ctrl_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_LCD_drive_AC_Ctrl_indx),
- config_LCD_drive_AC_Ctrl_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_LCD_drive_AC_Ctrl_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_LCD_drive_AC_Ctrl_cmd),
- config_LCD_drive_AC_Ctrl_cmd },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_LCD_drive_AC_Ctrl_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Entry_Mode_indx),
- config_Entry_Mode_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Entry_Mode_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Entry_Mode_cmd),
- config_Entry_Mode_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Entry_Mode_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Display_Ctrl_1_indx),
- config_Display_Ctrl_1_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Display_Ctrl_1_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Display_Ctrl_1_cmd),
- config_Display_Ctrl_1_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Display_Ctrl_1_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Display_Ctrl_2_indx),
- config_Display_Ctrl_2_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Display_Ctrl_2_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Display_Ctrl_2_cmd),
- config_Display_Ctrl_2_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Display_Ctrl_2_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Display_Ctrl_3_indx),
- config_Display_Ctrl_3_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Display_Ctrl_3_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Display_Ctrl_3_cmd),
- config_Display_Ctrl_3_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Display_Ctrl_3_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Display_IF_Ctrl_1_indx),
- config_Display_IF_Ctrl_1_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Display_IF_Ctrl_1_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Display_IF_Ctrl_1_cmd),
- config_Display_IF_Ctrl_1_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Display_IF_Ctrl_1_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Display_IF_Ctrl_2_indx),
- config_Display_IF_Ctrl_2_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Display_IF_Ctrl_2_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Display_IF_Ctrl_2_cmd),
- config_Display_IF_Ctrl_2_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Display_IF_Ctrl_2_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_1_indx),
- config_Panel_IF_Ctrl_1_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_1_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_1_cmd),
- config_Panel_IF_Ctrl_1_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_1_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_3_indx),
- config_Panel_IF_Ctrl_3_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_3_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_3_cmd),
- config_Panel_IF_Ctrl_3_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_3_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_4_indx),
- config_Panel_IF_Ctrl_4_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_4_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_4_cmd),
- config_Panel_IF_Ctrl_4_cmd },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_4_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_5_indx),
- config_Panel_IF_Ctrl_5_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_5_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_5_cmd),
- config_Panel_IF_Ctrl_5_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_5_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_6_indx),
- config_Panel_IF_Ctrl_6_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_6_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_6_cmd),
- config_Panel_IF_Ctrl_6_cmd },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_6_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_8_indx),
- config_Panel_IF_Ctrl_8_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_8_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_8_cmd),
- config_Panel_IF_Ctrl_8_cmd },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_8_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_9_indx),
- config_Panel_IF_Ctrl_9_indx },
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_9_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_9_cmd),
- config_Panel_IF_Ctrl_9_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_9_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_gam_adjust_00_indx),
- config_gam_adjust_00_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_gam_adjust_00_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_gam_adjust_00_cmd),
- config_gam_adjust_00_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_gam_adjust_00_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_gam_adjust_01_indx),
- config_gam_adjust_01_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_gam_adjust_01_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_gam_adjust_01_cmd),
- config_gam_adjust_01_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_gam_adjust_01_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_gam_adjust_02_indx),
- config_gam_adjust_02_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_gam_adjust_02_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_gam_adjust_02_cmd),
- config_gam_adjust_02_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_gam_adjust_02_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_gam_adjust_03_indx),
- config_gam_adjust_03_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_gam_adjust_03_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_gam_adjust_03_cmd),
- config_gam_adjust_03_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_gam_adjust_03_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_04_indx), config_gam_adjust_04_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_04_cmd), config_gam_adjust_04_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_04_indx), config_gam_adjust_04_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_04_cmd), config_gam_adjust_04_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_05_indx), config_gam_adjust_05_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_05_cmd), config_gam_adjust_05_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_05_indx), config_gam_adjust_05_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_05_cmd), config_gam_adjust_05_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_06_indx), config_gam_adjust_06_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_06_cmd), config_gam_adjust_06_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_06_indx), config_gam_adjust_06_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_06_cmd), config_gam_adjust_06_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_07_indx), config_gam_adjust_07_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_07_cmd), config_gam_adjust_07_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_07_indx), config_gam_adjust_07_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_07_cmd), config_gam_adjust_07_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_08_indx), config_gam_adjust_08_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_08_cmd), config_gam_adjust_08_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_08_indx), config_gam_adjust_08_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_08_cmd), config_gam_adjust_08_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_09_indx), config_gam_adjust_09_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_09_cmd), config_gam_adjust_09_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_09_indx), config_gam_adjust_09_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_09_cmd), config_gam_adjust_09_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_0A_indx), config_gam_adjust_0A_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_0A_cmd), config_gam_adjust_0A_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_0A_indx), config_gam_adjust_0A_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_0A_cmd), config_gam_adjust_0A_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_0B_indx), config_gam_adjust_0B_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_0B_cmd), config_gam_adjust_0B_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_0B_indx), config_gam_adjust_0B_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_0B_cmd), config_gam_adjust_0B_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_0C_indx), config_gam_adjust_0C_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_0C_cmd), config_gam_adjust_0C_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_0C_indx), config_gam_adjust_0C_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_0C_cmd), config_gam_adjust_0C_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_0D_indx), config_gam_adjust_0D_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_0D_cmd), config_gam_adjust_0D_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_0D_indx), config_gam_adjust_0D_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_0D_cmd), config_gam_adjust_0D_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_10_indx), config_gam_adjust_10_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_10_cmd), config_gam_adjust_10_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_10_indx), config_gam_adjust_10_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_10_cmd), config_gam_adjust_10_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_11_indx), config_gam_adjust_11_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_11_cmd), config_gam_adjust_11_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_11_indx), config_gam_adjust_11_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_11_cmd), config_gam_adjust_11_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_12_indx), config_gam_adjust_12_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_12_cmd), config_gam_adjust_12_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_12_indx), config_gam_adjust_12_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_12_cmd), config_gam_adjust_12_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_15_indx), config_gam_adjust_15_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_15_cmd), config_gam_adjust_15_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_15_indx), config_gam_adjust_15_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_15_cmd), config_gam_adjust_15_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_16_indx), config_gam_adjust_16_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_16_cmd), config_gam_adjust_16_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_16_indx), config_gam_adjust_16_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_16_cmd), config_gam_adjust_16_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_17_indx), config_gam_adjust_17_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_17_cmd), config_gam_adjust_17_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_17_indx), config_gam_adjust_17_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_17_cmd), config_gam_adjust_17_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_18_indx), config_gam_adjust_18_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_18_cmd), config_gam_adjust_18_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_18_indx), config_gam_adjust_18_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_18_cmd), config_gam_adjust_18_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_19_indx), config_gam_adjust_19_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_19_cmd), config_gam_adjust_19_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_19_indx), config_gam_adjust_19_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_19_cmd), config_gam_adjust_19_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_1C_indx), config_gam_adjust_1C_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_1C_cmd), config_gam_adjust_1C_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_1C_indx), config_gam_adjust_1C_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_1C_cmd), config_gam_adjust_1C_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_1D_indx), config_gam_adjust_1D_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_1D_cmd), config_gam_adjust_1D_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_1D_indx), config_gam_adjust_1D_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_1D_cmd), config_gam_adjust_1D_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_20_indx), config_gam_adjust_20_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_20_cmd), config_gam_adjust_20_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_20_indx), config_gam_adjust_20_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_20_cmd), config_gam_adjust_20_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_21_indx), config_gam_adjust_21_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_21_cmd), config_gam_adjust_21_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_21_indx), config_gam_adjust_21_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_21_cmd), config_gam_adjust_21_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_22_indx), config_gam_adjust_22_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_22_cmd), config_gam_adjust_22_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_27_indx), config_gam_adjust_27_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_27_cmd), config_gam_adjust_27_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_22_indx), config_gam_adjust_22_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_22_cmd), config_gam_adjust_22_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_28_indx), config_gam_adjust_28_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_28_cmd), config_gam_adjust_28_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_27_indx), config_gam_adjust_27_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_27_cmd), config_gam_adjust_27_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_gam_adjust_29_indx), config_gam_adjust_29_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_gam_adjust_29_cmd), config_gam_adjust_29_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_28_indx), config_gam_adjust_28_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_28_cmd), config_gam_adjust_28_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_1b_cmd), config_Power_Ctrl_1b_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_gam_adjust_29_indx), config_gam_adjust_29_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_gam_adjust_29_cmd), config_gam_adjust_29_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_2b_cmd), config_Power_Ctrl_2b_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_1b_cmd), config_Power_Ctrl_1b_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_3_indx), config_Power_Ctrl_3_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_3a_cmd), config_Power_Ctrl_3a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_2b_cmd), config_Power_Ctrl_2b_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_4_indx), config_Power_Ctrl_4_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_4a_cmd), config_Power_Ctrl_4a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_3_indx), config_Power_Ctrl_3_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_3a_cmd), config_Power_Ctrl_3a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
+ {sizeof(config_Power_Ctrl_6_indx), config_Power_Ctrl_6_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
+ {sizeof(config_Power_Ctrl_6a_cmd), config_Power_Ctrl_6a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_4_indx), config_Power_Ctrl_4_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_4a_cmd), config_Power_Ctrl_4a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
-
- {sizeof(config_DBICADD70), config_DBICADD70},
- {sizeof(config_Power_Ctrl_6_indx), config_Power_Ctrl_6_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
- {sizeof(config_Power_Ctrl_6a_cmd), config_Power_Ctrl_6a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
-
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Auto_Sequencer_Setting_indx),
- config_Auto_Sequencer_Setting_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Auto_Sequencer_Setting_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Auto_Sequencer_Setting_b_cmd),
- config_Auto_Sequencer_Setting_b_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Auto_Sequencer_Setting_b_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Panel_IF_Ctrl_10_indx),
- config_Panel_IF_Ctrl_10_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Panel_IF_Ctrl_10_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Panel_IF_Ctrl_10a_cmd),
- config_Panel_IF_Ctrl_10a_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Panel_IF_Ctrl_10a_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Auto_Sequencer_Setting_indx),
- config_Auto_Sequencer_Setting_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Auto_Sequencer_Setting_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Auto_Sequencer_Setting_c_cmd),
- config_Auto_Sequencer_Setting_c_cmd},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ config_Auto_Sequencer_Setting_c_cmd}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
- {sizeof(config_DBICADD70), config_DBICADD70},
+ {sizeof(config_DBICADD70), config_DBICADD70}
+ ,
{sizeof(config_Power_Ctrl_2_indx),
- config_Power_Ctrl_2_indx},
- {sizeof(config_DBICSET_15), config_DBICSET_15},
- {sizeof(config_DBICADD72), config_DBICADD72},
+ config_Power_Ctrl_2_indx}
+ ,
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
+ {sizeof(config_DBICADD72), config_DBICADD72}
+ ,
{sizeof(config_Power_Ctrl_2c_cmd),
- config_Power_Ctrl_2c_cmd},
+ config_Power_Ctrl_2c_cmd}
+ ,
- {sizeof(config_DBICSET_15), config_DBICSET_15},
+ {sizeof(config_DBICSET_15), config_DBICSET_15}
+ ,
{sizeof(config_VIDEO), config_VIDEO}
};
static struct mipi_dsi_phy_ctrl mipi_dsi_renesas_panel_phy_ctrl = {
- /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
- {0x03, 0x01, 0x01, 0x00}, /* regulator */
- /* timing */
- {0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
- 0x90, 0x18, 0x03, 0x04},
- {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
- {0xbb, 0x02, 0x06, 0x00}, /* strength */
- /* pll control */
- {0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
- 0x01, 0x0f, 0x07, /* --> Two lane configuration */
- 0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
+ /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
+ {0x03, 0x01, 0x01, 0x00}, /* regulator */
+ /* timing */
+ {0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
+ 0x90, 0x18, 0x03, 0x04},
+ {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
+ {0xbb, 0x02, 0x06, 0x00}, /* strength */
+ /* pll control */
+ {0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
+ 0x01, 0x0f, 0x07, /* --> Two lane configuration */
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
};
-
-
#endif
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 33dc336..a07d169 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -1,611 +1,598 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __MMC_H__
-#define __MMC_H__
-
-#ifndef MMC_SLOT
-#define MMC_SLOT 0
-#endif
-
-extern unsigned int mmc_boot_mci_base;
-
-#define MMC_BOOT_MCI_REG(offset) ((mmc_boot_mci_base) + offset)
-
-/*
- * Define Macros for SDCC Registers
- */
-#define MMC_BOOT_MCI_POWER MMC_BOOT_MCI_REG(0x000) /* 8 bit */
-
-/* MCICMD output control - 6th bit */
-#ifdef PLATFORM_MSM7X30
-#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
-#define MMC_BOOT_MCI_PWR_OFF 0x00
-#define MMC_BOOT_MCI_PWR_UP 0x01
-#define MMC_BOOT_MCI_PWR_ON 0x01
-#else
-#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
-#define MMC_BOOT_MCI_PWR_OFF 0x00
-#define MMC_BOOT_MCI_PWR_UP 0x02
-#define MMC_BOOT_MCI_PWR_ON 0x03
-#endif
-
-#define MMC_BOOT_MCI_CLK MMC_BOOT_MCI_REG(0x004) /* 16 bits */
-/* Enable MCI bus clock - 0: clock disabled 1: enabled */
-#define MMC_BOOT_MCI_CLK_ENABLE (1 << 8)
-/* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */
-#define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9)
-/* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */
-#define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10)
-#define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0
-#define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10)
-#define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10)
-/* Enable flow control- 0: disable 1: enable */
-#define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12)
-/* Set/clear to select rising/falling edge for data/cmd output */
-#define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13)
-/* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */
-#define MMC_BOOT_MCI_CLK_IN_FALLING 0x0
-#define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14)
-#define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14)
-#define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14)
-
-/* Bus Width */
-#define MMC_BOOT_BUS_WIDTH_1_BIT 0
-#define MMC_BOOT_BUS_WIDTH_4_BIT 2
-#define MMC_BOOT_BUS_WIDTH_8_BIT 3
-
-#define MMC_BOOT_MCI_ARGUMENT MMC_BOOT_MCI_REG(0x008) /* 32 bits */
-
-#define MMC_BOOT_MCI_CMD MMC_BOOT_MCI_REG(0x00C) /* 16 bits */
-/* Command Index: 0 -5 */
-/* Waits for response if set */
-#define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6)
-/* Receives a 136-bit long response if set */
-#define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7)
-/* If set, CPSM disables command timer and waits for interrupt */
-#define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8)
-/* If set waits for CmdPend before starting to send a command */
-#define MMC_BOOT_MCI_CMD_PENDING (1 << 9)
-/* CPSM is enabled if set */
-#define MMC_BOOT_MCI_CMD_ENABLE (1 << 10)
-/* If set PROG_DONE status bit asserted when busy is de-asserted */
-#define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11)
-/* To indicate that this is a Command with Data (for SDIO interrupts) */
-#define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12)
-/* Signals the next command to be an abort (stop) command. Always read 0 */
-#define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13)
-/* Waits for Command Completion Signal if set */
-#define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14)
-/* If set sends CCS disable sequence */
-#define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15)
-
-#define MMC_BOOT_MCI_RESP_CMD MMC_BOOT_MCI_REG(0x010)
-
-#define MMC_BOOT_MCI_RESP_0 MMC_BOOT_MCI_REG(0x014)
-#define MMC_BOOT_MCI_RESP_1 MMC_BOOT_MCI_REG(0x018)
-#define MMC_BOOT_MCI_RESP_2 MMC_BOOT_MCI_REG(0x01C)
-#define MMC_BOOT_MCI_RESP_3 MMC_BOOT_MCI_REG(0x020)
-
-#define MMC_BOOT_MCI_DATA_TIMER MMC_BOOT_MCI_REG(0x024)
-#define MMC_BOOT_MCI_DATA_LENGTH MMC_BOOT_MCI_REG(0x028)
-#define MMC_BOOT_MCI_DATA_CTL MMC_BOOT_MCI_REG(0x02C) /* 16 bits */
-/* Data transfer enabled */
-#define MMC_BOOT_MCI_DATA_ENABLE (1 << 0)
-/* Data transfer direction - 0: controller to card 1:card to controller */
-#define MMC_BOOT_MCI_DATA_DIR (1 << 1)
-/* Data transfer mode - 0: block data transfer 1: stream data transfer */
-#define MMC_BOOT_MCI_DATA_MODE (1 << 2)
-/* Enable DM interface - 0: DM disabled 1: DM enabled */
-#define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3)
-/* Data block length in bytes (1-4096) */
-#define MMC_BOOT_MCI_BLKSIZE_POS 4
-#define MMC_BOOT_MCI_DATA_COUNT MMC_BOOT_MCI_REG(0x030)
-#define MMC_BOOT_MCI_STATUS MMC_BOOT_MCI_REG(0x034)
-/* Command response received - CRC check failed */
-#define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0)
-/* Data block sent/received - CRC check failed */
-#define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1)
-/* Command resonse timeout */
-#define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2)
-/* Data timeout */
-#define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3)
-/* Transmit FIFO underrun error */
-#define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4)
-/* Receive FIFO overrun error */
-#define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5)
-/* Command response received - CRC check passed */
-#define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6)
-/* Command sent - no response required */
-#define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7)
-/* Data end - data counter zero */
-#define MMC_BOOT_MCI_STAT_DATA_END (1 << 8)
-/* Start bit not detected on all data signals in wide bus mode */
-#define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9)
-/* Data block sent/received - CRC check passed */
-#define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10)
-/* Command transfer in progress */
-#define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11)
-/* Data transmit in progress */
-#define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12)
-/* Data receive in progress */
-#define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13)
-/* Transmit FIFO half full */
-#define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14)
-/* Receive FIFO half full */
-#define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15)
-/* Transmit FIFO full */
-#define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16)
-/* Receive FIFO full */
-#define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17)
-/* Transmit FIFO empty */
-#define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18)
-/* Receive FIFO empty */
-#define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19)
-/* Data available in transmit FIFO */
-#define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20)
-/* Data available in receive FIFO */
-#define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21)
-/* SDIO interrupt indicator for wake-up */
-#define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22)
-/* Programming done */
-#define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23)
-/* CE-ATA command completion signal detected */
-#define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24)
-/* SDIO interrupt indicator for normal operation */
-#define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25)
-/* Commpand completion signal timeout */
-#define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26)
-
-#define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \
- MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \
- MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \
- MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \
- MMC_BOOT_MCI_STAT_TX_UNDRUN| \
- MMC_BOOT_MCI_STAT_RX_OVRRUN| \
- MMC_BOOT_MCI_STAT_CMD_RESP_END| \
- MMC_BOOT_MCI_STAT_CMD_SENT| \
- MMC_BOOT_MCI_STAT_DATA_END| \
- MMC_BOOT_MCI_STAT_START_BIT_ERR| \
- MMC_BOOT_MCI_STAT_DATA_BLK_END| \
- MMC_BOOT_MCI_SDIO_INTR_CLR| \
- MMC_BOOT_MCI_STAT_PROG_DONE| \
- MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\
- MMC_BOOT_MCI_STAT_CCS_TIMEOUT)
-
-#define MMC_BOOT_MCI_CLEAR MMC_BOOT_MCI_REG(0x038)
-#define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0)
-#define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1)
-#define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2)
-#define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3)
-#define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4)
-#define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5)
-#define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6)
-#define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7)
-#define MMC_BOOT_MCI_DATA_END_CLR (1 << 8)
-#define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9)
-#define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10)
-#define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22)
-#define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23)
-#define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24)
-#define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25)
-
-#define MMC_BOOT_MCI_INT_MASK0 MMC_BOOT_MCI_REG(0x03C)
-#define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0)
-#define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1)
-#define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2)
-#define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3)
-#define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4)
-#define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5)
-#define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6)
-#define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7)
-#define MMC_BOOT_MCI_DATA_END_MASK (1 << 8)
-#define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9)
-#define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10)
-#define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11)
-#define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12)
-#define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13)
-#define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14)
-#define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15)
-#define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16)
-#define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17)
-#define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18)
-#define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19)
-#define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20)
-#define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21)
-#define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22)
-#define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23)
-#define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24)
-#define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25)
-#define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26)
-
-#define MMC_BOOT_MCI_INT_MASK1 MMC_BOOT_MCI_REG(0x040)
-
-#define MMC_BOOT_MCI_FIFO_COUNT MMC_BOOT_MCI_REG(0x044)
-
-#define MMC_BOOT_MCI_CCS_TIMER MMC_BOOT_MCI_REG(0x0058)
-
-#define MMC_BOOT_MCI_FIFO MMC_BOOT_MCI_REG(0x080)
-
-/* Card status */
-#define MMC_BOOT_CARD_STATUS(x) ((x>>9) & 0x0F)
-#define MMC_BOOT_TRAN_STATE 4
-#define MMC_BOOT_PROG_STATE 7
-
-/* SD Memory Card bus commands */
-#define CMD0_GO_IDLE_STATE 0
-#define CMD1_SEND_OP_COND 1
-#define CMD2_ALL_SEND_CID 2
-#define CMD3_SEND_RELATIVE_ADDR 3
-#define CMD4_SET_DSR 4
-#define CMD6_SWITCH_FUNC 6
-#define ACMD6_SET_BUS_WIDTH 6 /* SD card */
-#define CMD7_SELECT_DESELECT_CARD 7
-#define CMD8_SEND_EXT_CSD 8
-#define CMD8_SEND_IF_COND 8 /* SD card */
-#define CMD9_SEND_CSD 9
-#define CMD10_SEND_CID 10
-#define CMD12_STOP_TRANSMISSION 12
-#define CMD13_SEND_STATUS 13
-#define CMD15_GO_INACTIVE_STATUS 15
-#define CMD16_SET_BLOCKLEN 16
-#define CMD17_READ_SINGLE_BLOCK 17
-#define CMD18_READ_MULTIPLE_BLOCK 18
-#define CMD23_SET_BLOCK_COUNT 23
-#define CMD24_WRITE_SINGLE_BLOCK 24
-#define CMD25_WRITE_MULTIPLE_BLOCK 25
-#define CMD28_SET_WRITE_PROTECT 28
-#define CMD29_CLEAR_WRITE_PROTECT 29
-#define CMD31_SEND_WRITE_PROT_TYPE 31
-#define CMD32_ERASE_WR_BLK_START 32
-#define CMD33_ERASE_WR_BLK_END 33
-#define CMD35_ERASE_GROUP_START 35
-#define CMD36_ERASE_GROUP_END 36
-#define CMD38_ERASE 38
-#define ACMD41_SEND_OP_COND 41 /* SD card */
-#define ACMD51_SEND_SCR 51 /* SD card */
-#define CMD55_APP_CMD 55 /* SD card */
-
-/* Switch Function Modes */
-#define MMC_BOOT_SWITCH_FUNC_CHECK 0
-#define MMC_BOOT_SWITCH_FUNC_SET 1
-
-/* OCR Register */
-#define MMC_BOOT_OCR_17_19 (1 << 7)
-#define MMC_BOOT_OCR_27_36 (0x1FF << 15)
-#define MMC_BOOT_OCR_SEC_MODE (2 << 29)
-#define MMC_BOOT_OCR_BUSY (1 << 31)
-
-/* Commands type */
-#define MMC_BOOT_CMD_BCAST (1 << 0)
-#define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1)
-#define MMC_BOOT_CMD_ADDRESS (1 << 2)
-#define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3)
-
-/* Response types */
-#define MMC_BOOT_RESP_NONE 0
-#define MMC_BOOT_RESP_R1 (1 << 0)
-#define MMC_BOOT_RESP_R1B (1 << 1)
-#define MMC_BOOT_RESP_R2 (1 << 2)
-#define MMC_BOOT_RESP_R3 (1 << 3)
-#define MMC_BOOT_RESP_R6 (1 << 6)
-#define MMC_BOOT_RESP_R7 (1 << 7)
-
-#define IS_RESP_136_BITS(x) (x & MMC_BOOT_RESP_R2)
-#define CHECK_FOR_BUSY_AT_RESP(x)
-
-/* Card Status bits (R1 register) */
-#define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3)
-#define MMC_BOOT_R1_APP_CMD (1 << 5)
-#define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6)
-#define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9)
-#define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9)
-#define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9)
-#define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9)
-#define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9)
-#define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9)
-#define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9)
-#define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9)
-#define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9)
-#define MMC_BOOT_R1_ERASE_RESET (1 << 13)
-#define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14)
-#define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15)
-#define MMC_BOOT_R1_ERROR (1 << 19)
-#define MMC_BOOT_R1_CC_ERROR (1 << 20)
-#define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21)
-#define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22)
-#define MMC_BOOT_R1_COM_CRC_ERR (1 << 23)
-#define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24)
-#define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25)
-#define MMC_BOOT_R1_WP_VIOLATION (1 << 26)
-#define MMC_BOOT_R1_ERASE_PARAM (1 << 27)
-#define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28)
-#define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29)
-#define MMC_BOOT_R1_ADDR_ERR (1 << 30)
-#define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31)
-
-/* Macros for Common Errors */
-#define MMC_BOOT_E_SUCCESS 0
-#define MMC_BOOT_E_FAILURE 1
-#define MMC_BOOT_E_TIMEOUT 2
-#define MMC_BOOT_E_INVAL 3
-#define MMC_BOOT_E_CRC_FAIL 4
-#define MMC_BOOT_E_INIT_FAIL 5
-#define MMC_BOOT_E_CMD_INDX_MISMATCH 6
-#define MMC_BOOT_E_RESP_VERIFY_FAIL 7
-#define MMC_BOOT_E_NOT_SUPPORTED 8
-#define MMC_BOOT_E_CARD_BUSY 9
-#define MMC_BOOT_E_MEM_ALLOC_FAIL 10
-#define MMC_BOOT_E_CLK_ENABLE_FAIL 11
-#define MMC_BOOT_E_CMMC_DECODE_FAIL 12
-#define MMC_BOOT_E_CID_DECODE_FAIL 13
-#define MMC_BOOT_E_BLOCKLEN_ERR 14
-#define MMC_BOOT_E_ADDRESS_ERR 15
-#define MMC_BOOT_E_DATA_CRC_FAIL 16
-#define MMC_BOOT_E_DATA_TIMEOUT 17
-#define MMC_BOOT_E_RX_OVRRUN 18
-#define MMC_BOOT_E_VREG_SET_FAILED 19
-#define MMC_BOOT_E_GPIO_CFG_FAIL 20
-#define MMC_BOOT_E_DATA_ADM_ERR 21
-
-/* EXT_CSD */
-#define MMC_BOOT_ACCESS_WRITE 0x3
-
-#define MMC_BOOT_EXT_USER_WP 171
-#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
-#define MMC_BOOT_EXT_ERASE_MEM_CONT 181
-#define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183
-#define MMC_BOOT_EXT_CMMC_HS_TIMING 185
-#define MMC_BOOT_EXT_HC_WP_GRP_SIZE 221
-#define MMC_BOOT_EXT_ERASE_TIMEOUT_MULT 223
-#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE 224
-
-#define IS_BIT_SET_EXT_CSD(val, bit) ((ext_csd_buf[val]) & (1<<(bit)))
-#define IS_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
-
-#define MMC_BOOT_US_PERM_WP_EN 2
-#define MMC_BOOT_US_PWR_WP_DIS 3
-
-#define MMC_BOOT_US_PERM_WP_DIS (1<<4)
-#define MMC_BOOT_US_PWR_WP_EN 1
-
-/* For SD */
-#define MMC_BOOT_SD_HC_VOLT_SUPPLIED 0x000001AA
-#define MMC_BOOT_SD_NEG_OCR 0x00FF8000
-#define MMC_BOOT_SD_HC_HCS 0x40000000
-#define MMC_BOOT_SD_DEV_READY 0x80000000
-#define MMC_BOOT_SD_SWITCH_HS 0x80FFFFF1
-
-/* Data structure definitions */
-struct mmc_boot_command
-{
- unsigned int cmd_index;
- unsigned int argument;
- unsigned int cmd_type;
-
- unsigned int resp[4];
- unsigned int resp_type;
- unsigned int prg_enabled;
- unsigned int xfer_mode;
-};
-
-#define MMC_BOOT_XFER_MODE_BLOCK 0
-#define MMC_BOOT_XFER_MODE_STREAM 1
-
-/* CSD Register.
- * Note: not all the fields have been defined here
- */
-struct mmc_boot_csd
-{
- unsigned int cmmc_structure;
- unsigned int spec_vers;
- unsigned int card_cmd_class;
- unsigned int write_blk_len;
- unsigned int read_blk_len;
- unsigned int r2w_factor;
- unsigned int sector_size;
- unsigned int c_size_mult;
- unsigned int c_size;
- unsigned int nsac_clk_cycle;
- unsigned int taac_ns;
- unsigned int tran_speed;
- unsigned int erase_grp_size;
- unsigned int erase_grp_mult;
- unsigned int wp_grp_size;
- unsigned int wp_grp_enable:1;
- unsigned int perm_wp:1;
- unsigned int temp_wp:1;
- unsigned int erase_blk_len:1;
- unsigned int read_blk_misalign:1;
- unsigned int write_blk_misalign:1;
- unsigned int read_blk_partial:1;
- unsigned int write_blk_partial:1;
-};
-
-/* CID Register */
-struct mmc_boot_cid
-{
- unsigned int mid; /* 8 bit manufacturer id*/
- unsigned int oid; /* 16 bits 2 character ASCII - OEM ID*/
- unsigned char pnm[7];/* 6 character ASCII - product name*/
- unsigned int prv; /* 8 bits - product revision */
- unsigned int psn; /* 32 bits - product serial number */
- unsigned int month; /* 4 bits manufacturing month */
- unsigned int year; /* 4 bits manufacturing year */
-};
-
-/* SCR Register */
-struct mmc_boot_scr
-{
- unsigned int scr_structure;
- unsigned int mmc_spec;
-#define MMC_BOOT_SCR_MMC_SPEC_V1_01 0
-#define MMC_BOOT_SCR_MMC_SPEC_V1_10 1
-#define MMC_BOOT_SCR_MMC_SPEC_V2_00 2
- unsigned int data_stat_after_erase;
- unsigned int mmc_security;
-#define MMC_BOOT_SCR_NO_SECURITY 0
-#define MMC_BOOT_SCR_SECURITY_UNUSED 1
-#define MMC_BOOT_SCR_SECURITY_V1_01 2
-#define MMC_BOOT_SCR_SECURITY_V2_00 3
- unsigned int mmc_bus_width;
-#define MMC_BOOT_SCR_BUS_WIDTH_1_BIT (1<<0)
-#define MMC_BOOT_SCR_BUS_WIDTH_4_BIT (1<<2)
-};
-
-struct mmc_boot_card
-{
- unsigned int rca;
- unsigned int ocr;
- unsigned long long capacity;
- unsigned int type;
-#define MMC_BOOT_TYPE_STD_SD 0
-#define MMC_BOOT_TYPE_SDHC 1
-#define MMC_BOOT_TYPE_SDIO 2
-#define MMC_BOOT_TYPE_MMCHC 3
-#define MMC_BOOT_TYPE_STD_MMC 4
- unsigned int status;
-#define MMC_BOOT_STATUS_INACTIVE 0
-#define MMC_BOOT_STATUS_ACTIVE 1
- unsigned int rd_timeout_ns;
- unsigned int wr_timeout_ns;
- unsigned int rd_block_len;
- unsigned int wr_block_len;
- //unsigned int data_xfer_len;
- struct mmc_boot_cid cid;
- struct mmc_boot_csd csd;
- struct mmc_boot_scr scr;
-};
-
-#define MMC_BOOT_XFER_MULTI_BLOCK 0
-#define MMC_BOOT_XFER_SINGLE_BLOCK 1
-
-struct mmc_boot_host
-{
- unsigned int mclk_rate;
- unsigned int ocr;
- unsigned int cmd_retry;
-};
-
-
-/* MACRO used to evoke regcomp */
-#define REGCOMP_CKRTN(regx, str, errhandle) \
- do { \
- if(regcomp(regx, str, REG_EXTENDED) != 0) { \
- printf("Error building regex: %s\n", str); \
- goto errhandle; \
- } \
- } while(0);
-
-
-#define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
- ((unsigned)*(x+1) << 8) | \
- ((unsigned)*(x+2) << 16) | \
- ((unsigned)*(x+3) << 24))
-
-#define PUT_LWORD_TO_BYTE(x, y) do{*(x) = y & 0xff; \
- *(x+1) = (y >> 8) & 0xff; \
- *(x+2) = (y >> 16) & 0xff; \
- *(x+3) = (y >> 24) & 0xff; }while(0)
-
-#define GET_PAR_NUM_FROM_POS(x) (((x & 0x0000FF00) >> 8) + (x & 0x000000FF))
-
-#define OFFSET_STATUS 0x00
-#define OFFSET_TYPE 0x04
-#define OFFSET_FIRST_SEC 0x08
-#define OFFSET_SIZE 0x0C
-#define COPYBUFF_SIZE (1024 * 16)
-#define BINARY_IN_TABLE_SIZE (16 * 512)
-#define MAX_FILE_ENTRIES 20
-
-#define MMC_RCA 2
-
-/* Can be used to unpack array of upto 32 bits data */
-#define UNPACK_BITS(array, start, len, size_of) \
- ({ \
- unsigned int indx = (start) / (size_of); \
- unsigned int offset = (start) % (size_of); \
- unsigned int mask = (((len)<(size_of))? 1<<(len):0) - 1; \
- unsigned int unpck = array[indx] >> offset; \
- unsigned int indx2 = ((start) + (len) - 1) / (size_of); \
- if(indx2 > indx) \
- unpck |= array[indx2] << ((size_of) - offset); \
- unpck & mask; \
- })
-
-#define MMC_BOOT_MAX_COMMAND_RETRY 1000
-#define MMC_BOOT_RD_BLOCK_LEN 512
-#define MMC_BOOT_WR_BLOCK_LEN 512
-
-/* We have 16 32-bits FIFO registers */
-#define MMC_BOOT_MCI_FIFO_DEPTH 16
-#define MMC_BOOT_MCI_HFIFO_COUNT ( MMC_BOOT_MCI_FIFO_DEPTH / 2 )
-#define MMC_BOOT_MCI_FIFO_SIZE ( MMC_BOOT_MCI_FIFO_DEPTH * 4 )
-
-#define MAX_PARTITIONS 64
-
-#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
-
-#define MMC_CLK_400KHZ 400000
-#define MMC_CLK_144KHZ 144000
-#define MMC_CLK_20MHZ 20000000
-#define MMC_CLK_25MHZ 25000000
-#define MMC_CLK_48MHZ 48000000
-#define MMC_CLK_50MHZ 49152000
-
-#define MMC_CLK_ENABLE 1
-#define MMC_CLK_DISABLE 0
-
-
-unsigned int mmc_boot_main (unsigned char slot, unsigned int base);
-unsigned int mmc_boot_read_from_card (struct mmc_boot_host* host,
- struct mmc_boot_card* card,
- unsigned long long data_addr,
- unsigned int data_len,
- unsigned int* out );
-unsigned int mmc_write (unsigned long long data_addr,
- unsigned int data_len, unsigned int* in);
-
-unsigned int mmc_read (unsigned long long data_addr, unsigned int* out,
- unsigned int data_len);
-unsigned mmc_get_psn(void);
-
-unsigned int mmc_boot_write_to_card (struct mmc_boot_host* host,
- struct mmc_boot_card* card,
- unsigned long long data_addr,
- unsigned int data_len,
- unsigned int *in );
-
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MMC_H__
+#define __MMC_H__
+
+#ifndef MMC_SLOT
+#define MMC_SLOT 0
+#endif
+
+extern unsigned int mmc_boot_mci_base;
+
+#define MMC_BOOT_MCI_REG(offset) ((mmc_boot_mci_base) + offset)
+
+/*
+ * Define Macros for SDCC Registers
+ */
+#define MMC_BOOT_MCI_POWER MMC_BOOT_MCI_REG(0x000) /* 8 bit */
+
+/* MCICMD output control - 6th bit */
+#ifdef PLATFORM_MSM7X30
+#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
+#define MMC_BOOT_MCI_PWR_OFF 0x00
+#define MMC_BOOT_MCI_PWR_UP 0x01
+#define MMC_BOOT_MCI_PWR_ON 0x01
+#else
+#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
+#define MMC_BOOT_MCI_PWR_OFF 0x00
+#define MMC_BOOT_MCI_PWR_UP 0x02
+#define MMC_BOOT_MCI_PWR_ON 0x03
+#endif
+
+#define MMC_BOOT_MCI_CLK MMC_BOOT_MCI_REG(0x004) /* 16 bits */
+/* Enable MCI bus clock - 0: clock disabled 1: enabled */
+#define MMC_BOOT_MCI_CLK_ENABLE (1 << 8)
+/* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */
+#define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9)
+/* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */
+#define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10)
+#define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0
+#define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10)
+#define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10)
+/* Enable flow control- 0: disable 1: enable */
+#define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12)
+/* Set/clear to select rising/falling edge for data/cmd output */
+#define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13)
+/* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */
+#define MMC_BOOT_MCI_CLK_IN_FALLING 0x0
+#define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14)
+#define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14)
+#define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14)
+
+/* Bus Width */
+#define MMC_BOOT_BUS_WIDTH_1_BIT 0
+#define MMC_BOOT_BUS_WIDTH_4_BIT 2
+#define MMC_BOOT_BUS_WIDTH_8_BIT 3
+
+#define MMC_BOOT_MCI_ARGUMENT MMC_BOOT_MCI_REG(0x008) /* 32 bits */
+
+#define MMC_BOOT_MCI_CMD MMC_BOOT_MCI_REG(0x00C) /* 16 bits */
+/* Command Index: 0 -5 */
+/* Waits for response if set */
+#define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6)
+/* Receives a 136-bit long response if set */
+#define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7)
+/* If set, CPSM disables command timer and waits for interrupt */
+#define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8)
+/* If set waits for CmdPend before starting to send a command */
+#define MMC_BOOT_MCI_CMD_PENDING (1 << 9)
+/* CPSM is enabled if set */
+#define MMC_BOOT_MCI_CMD_ENABLE (1 << 10)
+/* If set PROG_DONE status bit asserted when busy is de-asserted */
+#define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11)
+/* To indicate that this is a Command with Data (for SDIO interrupts) */
+#define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12)
+/* Signals the next command to be an abort (stop) command. Always read 0 */
+#define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13)
+/* Waits for Command Completion Signal if set */
+#define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14)
+/* If set sends CCS disable sequence */
+#define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15)
+
+#define MMC_BOOT_MCI_RESP_CMD MMC_BOOT_MCI_REG(0x010)
+
+#define MMC_BOOT_MCI_RESP_0 MMC_BOOT_MCI_REG(0x014)
+#define MMC_BOOT_MCI_RESP_1 MMC_BOOT_MCI_REG(0x018)
+#define MMC_BOOT_MCI_RESP_2 MMC_BOOT_MCI_REG(0x01C)
+#define MMC_BOOT_MCI_RESP_3 MMC_BOOT_MCI_REG(0x020)
+
+#define MMC_BOOT_MCI_DATA_TIMER MMC_BOOT_MCI_REG(0x024)
+#define MMC_BOOT_MCI_DATA_LENGTH MMC_BOOT_MCI_REG(0x028)
+#define MMC_BOOT_MCI_DATA_CTL MMC_BOOT_MCI_REG(0x02C) /* 16 bits */
+/* Data transfer enabled */
+#define MMC_BOOT_MCI_DATA_ENABLE (1 << 0)
+/* Data transfer direction - 0: controller to card 1:card to controller */
+#define MMC_BOOT_MCI_DATA_DIR (1 << 1)
+/* Data transfer mode - 0: block data transfer 1: stream data transfer */
+#define MMC_BOOT_MCI_DATA_MODE (1 << 2)
+/* Enable DM interface - 0: DM disabled 1: DM enabled */
+#define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3)
+/* Data block length in bytes (1-4096) */
+#define MMC_BOOT_MCI_BLKSIZE_POS 4
+#define MMC_BOOT_MCI_DATA_COUNT MMC_BOOT_MCI_REG(0x030)
+#define MMC_BOOT_MCI_STATUS MMC_BOOT_MCI_REG(0x034)
+/* Command response received - CRC check failed */
+#define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0)
+/* Data block sent/received - CRC check failed */
+#define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1)
+/* Command resonse timeout */
+#define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2)
+/* Data timeout */
+#define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3)
+/* Transmit FIFO underrun error */
+#define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4)
+/* Receive FIFO overrun error */
+#define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5)
+/* Command response received - CRC check passed */
+#define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6)
+/* Command sent - no response required */
+#define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7)
+/* Data end - data counter zero */
+#define MMC_BOOT_MCI_STAT_DATA_END (1 << 8)
+/* Start bit not detected on all data signals in wide bus mode */
+#define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9)
+/* Data block sent/received - CRC check passed */
+#define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10)
+/* Command transfer in progress */
+#define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11)
+/* Data transmit in progress */
+#define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12)
+/* Data receive in progress */
+#define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13)
+/* Transmit FIFO half full */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14)
+/* Receive FIFO half full */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15)
+/* Transmit FIFO full */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16)
+/* Receive FIFO full */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17)
+/* Transmit FIFO empty */
+#define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18)
+/* Receive FIFO empty */
+#define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19)
+/* Data available in transmit FIFO */
+#define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20)
+/* Data available in receive FIFO */
+#define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21)
+/* SDIO interrupt indicator for wake-up */
+#define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22)
+/* Programming done */
+#define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23)
+/* CE-ATA command completion signal detected */
+#define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24)
+/* SDIO interrupt indicator for normal operation */
+#define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25)
+/* Commpand completion signal timeout */
+#define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26)
+
+#define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \
+ MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \
+ MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \
+ MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \
+ MMC_BOOT_MCI_STAT_TX_UNDRUN| \
+ MMC_BOOT_MCI_STAT_RX_OVRRUN| \
+ MMC_BOOT_MCI_STAT_CMD_RESP_END| \
+ MMC_BOOT_MCI_STAT_CMD_SENT| \
+ MMC_BOOT_MCI_STAT_DATA_END| \
+ MMC_BOOT_MCI_STAT_START_BIT_ERR| \
+ MMC_BOOT_MCI_STAT_DATA_BLK_END| \
+ MMC_BOOT_MCI_SDIO_INTR_CLR| \
+ MMC_BOOT_MCI_STAT_PROG_DONE| \
+ MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\
+ MMC_BOOT_MCI_STAT_CCS_TIMEOUT)
+
+#define MMC_BOOT_MCI_CLEAR MMC_BOOT_MCI_REG(0x038)
+#define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0)
+#define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1)
+#define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2)
+#define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3)
+#define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4)
+#define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5)
+#define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6)
+#define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7)
+#define MMC_BOOT_MCI_DATA_END_CLR (1 << 8)
+#define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9)
+#define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10)
+#define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22)
+#define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23)
+#define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24)
+#define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25)
+
+#define MMC_BOOT_MCI_INT_MASK0 MMC_BOOT_MCI_REG(0x03C)
+#define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0)
+#define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1)
+#define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2)
+#define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3)
+#define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4)
+#define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5)
+#define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6)
+#define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7)
+#define MMC_BOOT_MCI_DATA_END_MASK (1 << 8)
+#define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9)
+#define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10)
+#define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11)
+#define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12)
+#define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13)
+#define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14)
+#define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15)
+#define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16)
+#define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17)
+#define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18)
+#define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19)
+#define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20)
+#define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21)
+#define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22)
+#define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23)
+#define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24)
+#define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25)
+#define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26)
+
+#define MMC_BOOT_MCI_INT_MASK1 MMC_BOOT_MCI_REG(0x040)
+
+#define MMC_BOOT_MCI_FIFO_COUNT MMC_BOOT_MCI_REG(0x044)
+
+#define MMC_BOOT_MCI_CCS_TIMER MMC_BOOT_MCI_REG(0x0058)
+
+#define MMC_BOOT_MCI_FIFO MMC_BOOT_MCI_REG(0x080)
+
+/* Card status */
+#define MMC_BOOT_CARD_STATUS(x) ((x>>9) & 0x0F)
+#define MMC_BOOT_TRAN_STATE 4
+#define MMC_BOOT_PROG_STATE 7
+
+/* SD Memory Card bus commands */
+#define CMD0_GO_IDLE_STATE 0
+#define CMD1_SEND_OP_COND 1
+#define CMD2_ALL_SEND_CID 2
+#define CMD3_SEND_RELATIVE_ADDR 3
+#define CMD4_SET_DSR 4
+#define CMD6_SWITCH_FUNC 6
+#define ACMD6_SET_BUS_WIDTH 6 /* SD card */
+#define CMD7_SELECT_DESELECT_CARD 7
+#define CMD8_SEND_EXT_CSD 8
+#define CMD8_SEND_IF_COND 8 /* SD card */
+#define CMD9_SEND_CSD 9
+#define CMD10_SEND_CID 10
+#define CMD12_STOP_TRANSMISSION 12
+#define CMD13_SEND_STATUS 13
+#define CMD15_GO_INACTIVE_STATUS 15
+#define CMD16_SET_BLOCKLEN 16
+#define CMD17_READ_SINGLE_BLOCK 17
+#define CMD18_READ_MULTIPLE_BLOCK 18
+#define CMD23_SET_BLOCK_COUNT 23
+#define CMD24_WRITE_SINGLE_BLOCK 24
+#define CMD25_WRITE_MULTIPLE_BLOCK 25
+#define CMD28_SET_WRITE_PROTECT 28
+#define CMD29_CLEAR_WRITE_PROTECT 29
+#define CMD31_SEND_WRITE_PROT_TYPE 31
+#define CMD32_ERASE_WR_BLK_START 32
+#define CMD33_ERASE_WR_BLK_END 33
+#define CMD35_ERASE_GROUP_START 35
+#define CMD36_ERASE_GROUP_END 36
+#define CMD38_ERASE 38
+#define ACMD41_SEND_OP_COND 41 /* SD card */
+#define ACMD51_SEND_SCR 51 /* SD card */
+#define CMD55_APP_CMD 55 /* SD card */
+
+/* Switch Function Modes */
+#define MMC_BOOT_SWITCH_FUNC_CHECK 0
+#define MMC_BOOT_SWITCH_FUNC_SET 1
+
+/* OCR Register */
+#define MMC_BOOT_OCR_17_19 (1 << 7)
+#define MMC_BOOT_OCR_27_36 (0x1FF << 15)
+#define MMC_BOOT_OCR_SEC_MODE (2 << 29)
+#define MMC_BOOT_OCR_BUSY (1 << 31)
+
+/* Commands type */
+#define MMC_BOOT_CMD_BCAST (1 << 0)
+#define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1)
+#define MMC_BOOT_CMD_ADDRESS (1 << 2)
+#define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3)
+
+/* Response types */
+#define MMC_BOOT_RESP_NONE 0
+#define MMC_BOOT_RESP_R1 (1 << 0)
+#define MMC_BOOT_RESP_R1B (1 << 1)
+#define MMC_BOOT_RESP_R2 (1 << 2)
+#define MMC_BOOT_RESP_R3 (1 << 3)
+#define MMC_BOOT_RESP_R6 (1 << 6)
+#define MMC_BOOT_RESP_R7 (1 << 7)
+
+#define IS_RESP_136_BITS(x) (x & MMC_BOOT_RESP_R2)
+#define CHECK_FOR_BUSY_AT_RESP(x)
+
+/* Card Status bits (R1 register) */
+#define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3)
+#define MMC_BOOT_R1_APP_CMD (1 << 5)
+#define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6)
+#define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9)
+#define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9)
+#define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9)
+#define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9)
+#define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9)
+#define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9)
+#define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9)
+#define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9)
+#define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9)
+#define MMC_BOOT_R1_ERASE_RESET (1 << 13)
+#define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14)
+#define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15)
+#define MMC_BOOT_R1_ERROR (1 << 19)
+#define MMC_BOOT_R1_CC_ERROR (1 << 20)
+#define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21)
+#define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22)
+#define MMC_BOOT_R1_COM_CRC_ERR (1 << 23)
+#define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24)
+#define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25)
+#define MMC_BOOT_R1_WP_VIOLATION (1 << 26)
+#define MMC_BOOT_R1_ERASE_PARAM (1 << 27)
+#define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28)
+#define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29)
+#define MMC_BOOT_R1_ADDR_ERR (1 << 30)
+#define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31)
+
+/* Macros for Common Errors */
+#define MMC_BOOT_E_SUCCESS 0
+#define MMC_BOOT_E_FAILURE 1
+#define MMC_BOOT_E_TIMEOUT 2
+#define MMC_BOOT_E_INVAL 3
+#define MMC_BOOT_E_CRC_FAIL 4
+#define MMC_BOOT_E_INIT_FAIL 5
+#define MMC_BOOT_E_CMD_INDX_MISMATCH 6
+#define MMC_BOOT_E_RESP_VERIFY_FAIL 7
+#define MMC_BOOT_E_NOT_SUPPORTED 8
+#define MMC_BOOT_E_CARD_BUSY 9
+#define MMC_BOOT_E_MEM_ALLOC_FAIL 10
+#define MMC_BOOT_E_CLK_ENABLE_FAIL 11
+#define MMC_BOOT_E_CMMC_DECODE_FAIL 12
+#define MMC_BOOT_E_CID_DECODE_FAIL 13
+#define MMC_BOOT_E_BLOCKLEN_ERR 14
+#define MMC_BOOT_E_ADDRESS_ERR 15
+#define MMC_BOOT_E_DATA_CRC_FAIL 16
+#define MMC_BOOT_E_DATA_TIMEOUT 17
+#define MMC_BOOT_E_RX_OVRRUN 18
+#define MMC_BOOT_E_VREG_SET_FAILED 19
+#define MMC_BOOT_E_GPIO_CFG_FAIL 20
+#define MMC_BOOT_E_DATA_ADM_ERR 21
+
+/* EXT_CSD */
+#define MMC_BOOT_ACCESS_WRITE 0x3
+
+#define MMC_BOOT_EXT_USER_WP 171
+#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
+#define MMC_BOOT_EXT_ERASE_MEM_CONT 181
+#define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183
+#define MMC_BOOT_EXT_CMMC_HS_TIMING 185
+#define MMC_BOOT_EXT_HC_WP_GRP_SIZE 221
+#define MMC_BOOT_EXT_ERASE_TIMEOUT_MULT 223
+#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE 224
+
+#define IS_BIT_SET_EXT_CSD(val, bit) ((ext_csd_buf[val]) & (1<<(bit)))
+#define IS_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
+
+#define MMC_BOOT_US_PERM_WP_EN 2
+#define MMC_BOOT_US_PWR_WP_DIS 3
+
+#define MMC_BOOT_US_PERM_WP_DIS (1<<4)
+#define MMC_BOOT_US_PWR_WP_EN 1
+
+/* For SD */
+#define MMC_BOOT_SD_HC_VOLT_SUPPLIED 0x000001AA
+#define MMC_BOOT_SD_NEG_OCR 0x00FF8000
+#define MMC_BOOT_SD_HC_HCS 0x40000000
+#define MMC_BOOT_SD_DEV_READY 0x80000000
+#define MMC_BOOT_SD_SWITCH_HS 0x80FFFFF1
+
+/* Data structure definitions */
+struct mmc_boot_command {
+ unsigned int cmd_index;
+ unsigned int argument;
+ unsigned int cmd_type;
+
+ unsigned int resp[4];
+ unsigned int resp_type;
+ unsigned int prg_enabled;
+ unsigned int xfer_mode;
+};
+
+#define MMC_BOOT_XFER_MODE_BLOCK 0
+#define MMC_BOOT_XFER_MODE_STREAM 1
+
+/* CSD Register.
+ * Note: not all the fields have been defined here
+ */
+struct mmc_boot_csd {
+ unsigned int cmmc_structure;
+ unsigned int spec_vers;
+ unsigned int card_cmd_class;
+ unsigned int write_blk_len;
+ unsigned int read_blk_len;
+ unsigned int r2w_factor;
+ unsigned int sector_size;
+ unsigned int c_size_mult;
+ unsigned int c_size;
+ unsigned int nsac_clk_cycle;
+ unsigned int taac_ns;
+ unsigned int tran_speed;
+ unsigned int erase_grp_size;
+ unsigned int erase_grp_mult;
+ unsigned int wp_grp_size;
+ unsigned int wp_grp_enable:1;
+ unsigned int perm_wp:1;
+ unsigned int temp_wp:1;
+ unsigned int erase_blk_len:1;
+ unsigned int read_blk_misalign:1;
+ unsigned int write_blk_misalign:1;
+ unsigned int read_blk_partial:1;
+ unsigned int write_blk_partial:1;
+};
+
+/* CID Register */
+struct mmc_boot_cid {
+ unsigned int mid; /* 8 bit manufacturer id */
+ unsigned int oid; /* 16 bits 2 character ASCII - OEM ID */
+ unsigned char pnm[7]; /* 6 character ASCII - product name */
+ unsigned int prv; /* 8 bits - product revision */
+ unsigned int psn; /* 32 bits - product serial number */
+ unsigned int month; /* 4 bits manufacturing month */
+ unsigned int year; /* 4 bits manufacturing year */
+};
+
+/* SCR Register */
+struct mmc_boot_scr {
+ unsigned int scr_structure;
+ unsigned int mmc_spec;
+#define MMC_BOOT_SCR_MMC_SPEC_V1_01 0
+#define MMC_BOOT_SCR_MMC_SPEC_V1_10 1
+#define MMC_BOOT_SCR_MMC_SPEC_V2_00 2
+ unsigned int data_stat_after_erase;
+ unsigned int mmc_security;
+#define MMC_BOOT_SCR_NO_SECURITY 0
+#define MMC_BOOT_SCR_SECURITY_UNUSED 1
+#define MMC_BOOT_SCR_SECURITY_V1_01 2
+#define MMC_BOOT_SCR_SECURITY_V2_00 3
+ unsigned int mmc_bus_width;
+#define MMC_BOOT_SCR_BUS_WIDTH_1_BIT (1<<0)
+#define MMC_BOOT_SCR_BUS_WIDTH_4_BIT (1<<2)
+};
+
+struct mmc_boot_card {
+ unsigned int rca;
+ unsigned int ocr;
+ unsigned long long capacity;
+ unsigned int type;
+#define MMC_BOOT_TYPE_STD_SD 0
+#define MMC_BOOT_TYPE_SDHC 1
+#define MMC_BOOT_TYPE_SDIO 2
+#define MMC_BOOT_TYPE_MMCHC 3
+#define MMC_BOOT_TYPE_STD_MMC 4
+ unsigned int status;
+#define MMC_BOOT_STATUS_INACTIVE 0
+#define MMC_BOOT_STATUS_ACTIVE 1
+ unsigned int rd_timeout_ns;
+ unsigned int wr_timeout_ns;
+ unsigned int rd_block_len;
+ unsigned int wr_block_len;
+ //unsigned int data_xfer_len;
+ struct mmc_boot_cid cid;
+ struct mmc_boot_csd csd;
+ struct mmc_boot_scr scr;
+};
+
+#define MMC_BOOT_XFER_MULTI_BLOCK 0
+#define MMC_BOOT_XFER_SINGLE_BLOCK 1
+
+struct mmc_boot_host {
+ unsigned int mclk_rate;
+ unsigned int ocr;
+ unsigned int cmd_retry;
+};
+
+/* MACRO used to evoke regcomp */
+#define REGCOMP_CKRTN(regx, str, errhandle) \
+ do { \
+ if(regcomp(regx, str, REG_EXTENDED) != 0) { \
+ printf("Error building regex: %s\n", str); \
+ goto errhandle; \
+ } \
+ } while(0);
+
+#define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
+ ((unsigned)*(x+1) << 8) | \
+ ((unsigned)*(x+2) << 16) | \
+ ((unsigned)*(x+3) << 24))
+
+#define PUT_LWORD_TO_BYTE(x, y) do{*(x) = y & 0xff; \
+ *(x+1) = (y >> 8) & 0xff; \
+ *(x+2) = (y >> 16) & 0xff; \
+ *(x+3) = (y >> 24) & 0xff; }while(0)
+
+#define GET_PAR_NUM_FROM_POS(x) (((x & 0x0000FF00) >> 8) + (x & 0x000000FF))
+
+#define OFFSET_STATUS 0x00
+#define OFFSET_TYPE 0x04
+#define OFFSET_FIRST_SEC 0x08
+#define OFFSET_SIZE 0x0C
+#define COPYBUFF_SIZE (1024 * 16)
+#define BINARY_IN_TABLE_SIZE (16 * 512)
+#define MAX_FILE_ENTRIES 20
+
+#define MMC_RCA 2
+
+/* Can be used to unpack array of upto 32 bits data */
+#define UNPACK_BITS(array, start, len, size_of) \
+ ({ \
+ unsigned int indx = (start) / (size_of); \
+ unsigned int offset = (start) % (size_of); \
+ unsigned int mask = (((len)<(size_of))? 1<<(len):0) - 1; \
+ unsigned int unpck = array[indx] >> offset; \
+ unsigned int indx2 = ((start) + (len) - 1) / (size_of); \
+ if(indx2 > indx) \
+ unpck |= array[indx2] << ((size_of) - offset); \
+ unpck & mask; \
+ })
+
+#define MMC_BOOT_MAX_COMMAND_RETRY 1000
+#define MMC_BOOT_RD_BLOCK_LEN 512
+#define MMC_BOOT_WR_BLOCK_LEN 512
+
+/* We have 16 32-bits FIFO registers */
+#define MMC_BOOT_MCI_FIFO_DEPTH 16
+#define MMC_BOOT_MCI_HFIFO_COUNT ( MMC_BOOT_MCI_FIFO_DEPTH / 2 )
+#define MMC_BOOT_MCI_FIFO_SIZE ( MMC_BOOT_MCI_FIFO_DEPTH * 4 )
+
+#define MAX_PARTITIONS 64
+
+#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
+
+#define MMC_CLK_400KHZ 400000
+#define MMC_CLK_144KHZ 144000
+#define MMC_CLK_20MHZ 20000000
+#define MMC_CLK_25MHZ 25000000
+#define MMC_CLK_48MHZ 48000000
+#define MMC_CLK_50MHZ 49152000
+
+#define MMC_CLK_ENABLE 1
+#define MMC_CLK_DISABLE 0
+
+unsigned int mmc_boot_main(unsigned char slot, unsigned int base);
+unsigned int mmc_boot_read_from_card(struct mmc_boot_host *host,
+ struct mmc_boot_card *card,
+ unsigned long long data_addr,
+ unsigned int data_len, unsigned int *out);
+unsigned int mmc_write(unsigned long long data_addr,
+ unsigned int data_len, unsigned int *in);
+
+unsigned int mmc_read(unsigned long long data_addr, unsigned int *out,
+ unsigned int data_len);
+unsigned mmc_get_psn(void);
+
+unsigned int mmc_boot_write_to_card(struct mmc_boot_host *host,
+ struct mmc_boot_card *card,
+ unsigned long long data_addr,
+ unsigned int data_len, unsigned int *in);
unsigned int mmc_erase_card(unsigned long long data_addr,
- unsigned long long data_len);
+ unsigned long long data_len);
-struct mmc_boot_host* get_mmc_host( void );
-struct mmc_boot_card* get_mmc_card( void );
-#endif
-
+struct mmc_boot_host *get_mmc_host(void);
+struct mmc_boot_card *get_mmc_card(void);
+#endif
diff --git a/platform/msm_shared/include/mmu.h b/platform/msm_shared/include/mmu.h
index dcf8a6f..9a946a8 100644
--- a/platform/msm_shared/include/mmu.h
+++ b/platform/msm_shared/include/mmu.h
@@ -31,13 +31,11 @@
#include <sys/types.h>
-typedef struct
-{
- addr_t paddress;
- addr_t vaddress;
+typedef struct {
+ addr_t paddress;
+ addr_t vaddress;
uint32_t num_of_sections;
uint32_t flags;
} mmu_section_t;
#endif
-
diff --git a/platform/msm_shared/include/nand.h b/platform/msm_shared/include/nand.h
index b3ae1a1..e8e3ccb 100644
--- a/platform/msm_shared/include/nand.h
+++ b/platform/msm_shared/include/nand.h
@@ -129,7 +129,6 @@
#define NAND_SFCMD_DATRD 0x6
#define NAND_SFCMD_DATWR 0x7
-
#define SFLASH_PREPCMD(numxfr, offval, delval, trnstp, mode, opcode) \
((numxfr<<20)|(offval<<12)|(delval<<6)|(trnstp<<5)|(mode<<4)|opcode)
@@ -173,7 +172,6 @@
#define ONENAND_ECC_ERRPOS_MAIN3 0xFF07
#define ONENAND_ECC_ERRPOS_SPARE3 0xFF08
-
/* Onenand commands */
#define ONENAND_CMDLOAD 0x0000
@@ -203,4 +201,4 @@
#define EBI2_NAND_ADM_MUX EBI2_REG(0x005C)
#define EBI2_CHIP_SELECT_CFG0 EBI2_REG(0x0000)
-#endif /* __PLATFORM_MSM_SHARED_NAND_H */
+#endif /* __PLATFORM_MSM_SHARED_NAND_H */
diff --git a/platform/msm_shared/include/partition_parser.h b/platform/msm_shared/include/partition_parser.h
index 6df3902..8e0f2ee 100644
--- a/platform/msm_shared/include/partition_parser.h
+++ b/platform/msm_shared/include/partition_parser.h
@@ -135,47 +135,47 @@
*((x)+7) = (((y) >> 56) & 0xff);
/* Unified mbr and gpt entry types */
-struct partition_entry
-{
- unsigned char type_guid[PARTITION_TYPE_GUID_SIZE];
- unsigned dtype;
- unsigned char unique_partition_guid[UNIQUE_PARTITION_GUID_SIZE];
- unsigned long long first_lba;
- unsigned long long last_lba;
- unsigned long long size;
- unsigned long long attribute_flag;
- unsigned char name[MAX_GPT_NAME_SIZE];
+struct partition_entry {
+ unsigned char type_guid[PARTITION_TYPE_GUID_SIZE];
+ unsigned dtype;
+ unsigned char unique_partition_guid[UNIQUE_PARTITION_GUID_SIZE];
+ unsigned long long first_lba;
+ unsigned long long last_lba;
+ unsigned long long size;
+ unsigned long long attribute_flag;
+ unsigned char name[MAX_GPT_NAME_SIZE];
};
-static void mbr_fill_name (struct partition_entry *partition_ent, unsigned int type);
-unsigned int mmc_boot_read_gpt( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card);
-unsigned int mmc_boot_read_mbr( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card);
-unsigned partition_get_index (const char * name);
-unsigned long long partition_get_size (int index);
-unsigned long long partition_get_offset (int index);
-unsigned int partition_verify_mbr_signature(unsigned size, unsigned char* buffer);
-unsigned int mbr_partition_get_type(unsigned size, unsigned char* partition,
- unsigned int *partition_type);
-unsigned int partition_get_type(unsigned size, unsigned char* partition,
- unsigned int *partition_type);
-unsigned int partition_read_table( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card);
-unsigned int partition_parse_gpt_header(unsigned char * buffer,
- unsigned long long * first_usable_lba,
- unsigned int * partition_entry_size,
- unsigned int * header_size,
- unsigned int * max_partition_count);
+static void mbr_fill_name(struct partition_entry *partition_ent,
+ unsigned int type);
+unsigned int mmc_boot_read_gpt(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card);
+unsigned int mmc_boot_read_mbr(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card);
+unsigned partition_get_index(const char *name);
+unsigned long long partition_get_size(int index);
+unsigned long long partition_get_offset(int index);
+unsigned int partition_verify_mbr_signature(unsigned size,
+ unsigned char *buffer);
+unsigned int mbr_partition_get_type(unsigned size, unsigned char *partition,
+ unsigned int *partition_type);
+unsigned int partition_get_type(unsigned size, unsigned char *partition,
+ unsigned int *partition_type);
+unsigned int partition_read_table(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card);
+unsigned int partition_parse_gpt_header(unsigned char *buffer,
+ unsigned long long *first_usable_lba,
+ unsigned int *partition_entry_size,
+ unsigned int *header_size,
+ unsigned int *max_partition_count);
unsigned int write_mbr(unsigned size, unsigned char *mbrImage,
- struct mmc_boot_host *mmc_host,
- struct mmc_boot_card *mmc_card);
+ struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card);
unsigned int write_gpt(unsigned size, unsigned char *gptImage,
- struct mmc_boot_host *mmc_host,
- struct mmc_boot_card *mmc_card);
-unsigned int write_partition(unsigned size, unsigned char* partition);
-
+ struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card);
+unsigned int write_partition(unsigned size, unsigned char *partition);
/* For Debugging */
void partition_dump(void);
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index 956cf89..8ef9108 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -57,8 +57,8 @@
#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
struct ihandler {
- int_handler func;
- void *arg;
+ int_handler func;
+ void *arg;
};
void qgic_init(void);
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 456cf46..3e78cf7 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -37,26 +37,23 @@
typedef unsigned int uint32;
-typedef struct
-{
- uint32 len;
- uint32 buf_offset;
- uint32 resp_hdr_offset;
- uint32 id;
+typedef struct {
+ uint32 len;
+ uint32 buf_offset;
+ uint32 resp_hdr_offset;
+ uint32 id;
} scm_command;
-typedef struct
-{
- uint32 len;
- uint32 buf_offset;
- uint32 is_complete;
+typedef struct {
+ uint32 len;
+ uint32 buf_offset;
+ uint32 is_complete;
} scm_response;
-typedef struct
-{
- scm_command common_req;
- uint32* img_ptr;
- uint32* img_len_ptr;
+typedef struct {
+ scm_command common_req;
+ uint32 *img_ptr;
+ uint32 *img_len_ptr;
} decrypt_img_req;
#define SYSCALL_CREATE_CMD_ID(s, f) \
@@ -65,11 +62,10 @@
#define SCM_SVC_SSD 7
#define SSD_DECRYPT_IMG_ID SYSCALL_CREATE_CMD_ID(SCM_SVC_SSD, 0x01)
-void setup_decrypt_cmd ( decrypt_img_req* dec_cmd,
- uint32** img_ptr,
- uint32* img_len_ptr);
+void setup_decrypt_cmd(decrypt_img_req * dec_cmd,
+ uint32 ** img_ptr, uint32 * img_len_ptr);
static uint32 smc(uint32 cmd_addr);
-int decrypt_img_scm(uint32** img_ptr, uint32* img_len_ptr);
+int decrypt_img_scm(uint32 ** img_ptr, uint32 * img_len_ptr);
#define SCM_SVC_FUSE 0x08
#define SCM_BLOW_SW_FUSE_ID 0x01
@@ -103,11 +99,11 @@
* to access the buffers in a safe manner.
*/
struct scm_command {
- uint32_t len;
- uint32_t buf_offset;
- uint32_t resp_hdr_offset;
- uint32_t id;
- uint32_t buf[0];
+ uint32_t len;
+ uint32_t buf_offset;
+ uint32_t resp_hdr_offset;
+ uint32_t id;
+ uint32_t buf[0];
};
/**
@@ -117,9 +113,9 @@
* @is_complete: indicates if the command has finished processing
*/
struct scm_response {
- uint32_t len;
- uint32_t buf_offset;
- uint32_t is_complete;
+ uint32_t len;
+ uint32_t buf_offset;
+ uint32_t is_complete;
};
#endif
diff --git a/platform/msm_shared/include/splash.h b/platform/msm_shared/include/splash.h
index 9026e65..2faa599 100644
--- a/platform/msm_shared/include/splash.h
+++ b/platform/msm_shared/include/splash.h
@@ -37,1757 +37,3508 @@
/* This image is (SPLASH_IMAGE_WIDTH x SPLASH_IMAGE_WIDTH) raw image */
static char imageBuffer[] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
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+ 0x01, 0x00, 0x41, 0x08,
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+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x78, 0xd5,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbd, 0xff, 0x86, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x41, 0x08,
+ 0xf8, 0xb5, 0xbd, 0xe7,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbf, 0xff,
+ 0x39, 0xef, 0xbd, 0xe7, 0xbd, 0xe7, 0xd3, 0x93, 0x41, 0x08, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x86, 0x29, 0xb4, 0xb5,
+ 0xf9, 0xce, 0xfd, 0xee, 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbd, 0xe7,
+ 0xfd, 0xee, 0xfc, 0xde, 0xfc, 0xde, 0xbd, 0xe7, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xbd, 0xe7, 0xbd, 0xe7, 0xfd, 0xee,
+ 0x39, 0xef, 0xfc, 0xde,
+ 0xfc, 0xde, 0xf9, 0xce, 0x7d, 0xe5, 0xf9, 0xce, 0xf9, 0xce, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x41, 0x08, 0x89, 0x4a,
+ 0xf4, 0xac, 0xf4, 0xac, 0xf9, 0xce, 0xfc, 0xde, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0x39, 0xef, 0xfc, 0xde, 0x39, 0xef, 0xbd, 0xe7, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xfd, 0xee, 0xf9, 0xce, 0xf9, 0xce,
+ 0xf8, 0xb5, 0x78, 0xd5,
+ 0xf8, 0xb5, 0xf8, 0xb5, 0xf8, 0xb5, 0xf8, 0xb5, 0xf9, 0xce, 0xfc, 0xde,
+ 0xc9, 0x72, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x02, 0x19,
+ 0xcd, 0x72, 0xf8, 0xb5, 0x78, 0xd5, 0xfc, 0xde, 0x39, 0xef, 0xbf, 0xff,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xe7, 0xbf, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xfd, 0xee, 0xfc, 0xde,
+ 0xf9, 0xce, 0xf9, 0xce, 0x78, 0xd5, 0xf9, 0xce, 0xb4, 0xb5, 0x78, 0xd5,
+ 0xf8, 0xb5, 0xff, 0xff,
+ 0x86, 0x29, 0x00, 0x00, 0x01, 0x00, 0x89, 0x4a, 0x86, 0x29, 0x41, 0x08,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x01, 0x00,
+ 0x02, 0x19, 0xf4, 0xac, 0xf9, 0xce, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbf, 0xff, 0xbd, 0xff, 0xbd, 0xe7, 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0x39, 0xef, 0xf9, 0xce, 0xf9, 0xce,
+ 0xf8, 0xb5, 0xf8, 0xb5,
+ 0xfc, 0xde, 0xff, 0xff, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x87, 0x49, 0x02, 0x19,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x86, 0x29, 0x00, 0x00,
+ 0x41, 0x08, 0xcd, 0x72, 0xf9, 0xce, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0x39, 0xef,
+ 0xf9, 0xce, 0xf8, 0xb5, 0x39, 0xef, 0xf9, 0xac, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x89, 0x4a, 0x87, 0x28, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x89, 0x4a, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0xf9, 0xce, 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbf, 0xff, 0xbf, 0xff,
+ 0xbd, 0xff, 0xfc, 0xde, 0x78, 0xd5, 0xf9, 0xce, 0xff, 0xff, 0x02, 0x19,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0x29, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x02, 0x19, 0x02, 0x19,
+ 0x00, 0x00, 0x00, 0x00, 0xcd, 0x73, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xde, 0xf9, 0xce, 0xf9, 0xce,
+ 0xf8, 0xb5, 0x00, 0x00,
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+ 0x00, 0x00, 0x01, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x01, 0x00, 0x41, 0x08,
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+ 0x01, 0x00, 0x00, 0x00,
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+ 0x01, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x89, 0x4a,
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+ 0xbd, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xbd, 0xe7,
+ 0x78, 0xd5, 0xbf, 0xff,
+ 0x41, 0x08, 0x01, 0x00, 0x02, 0x19, 0x86, 0x29, 0x02, 0x19, 0x87, 0x28,
+ 0x02, 0x19, 0x01, 0x00,
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+ 0x00, 0x00, 0x41, 0x08,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x01, 0x00, 0x41, 0x08,
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+ 0x41, 0x08, 0x02, 0x19,
+ 0x87, 0x28, 0x00, 0x00, 0x00, 0x00, 0xd3, 0x93, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x89, 0x4a, 0x00, 0x00, 0x86, 0x29, 0x89, 0x4a, 0x86, 0x29,
+ 0x41, 0x08, 0x87, 0x49,
+ 0x41, 0x08, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xfc, 0xde, 0x02, 0x19, 0x02, 0x19, 0x87, 0x49,
+ 0x02, 0x19, 0x41, 0x08,
+ 0x41, 0x08, 0x86, 0x29, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x41, 0x08,
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+ 0x01, 0x00, 0x00, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x00, 0x00, 0x41, 0x08,
+ 0x41, 0x08, 0x87, 0x28, 0x00, 0x00, 0x00, 0x00, 0xd3, 0x93, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xfc, 0xde, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x01, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x00, 0x00, 0x41, 0x08,
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+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x89, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xbd, 0xe7,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xbf, 0xff, 0xff, 0xff, 0x39, 0xef, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0x87, 0x28,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x29, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x86, 0x29, 0x00, 0x00, 0x00, 0x00, 0x89, 0x4a,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xfc, 0xde, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0x89, 0x4a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x86, 0x29,
+ 0x41, 0x08, 0x00, 0x00,
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+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
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+ 0x01, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x86, 0x29, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0xfc, 0xde, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xfc, 0xde, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbf, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xd3, 0x93,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x28,
+ 0x02, 0x19, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
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+ 0x00, 0x00, 0x01, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
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+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x89, 0x4a, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x19, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xfc, 0xde,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xb4, 0xb5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x02, 0x19,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x86, 0x29, 0x00, 0x00,
+ 0x41, 0x08, 0x89, 0x4a,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbd, 0xe7,
+ 0xfc, 0xde, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xf9, 0xce, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x87, 0x28,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x86, 0x29,
+ 0x41, 0x08, 0x00, 0x00,
+ 0xf8, 0xb5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0x39, 0xef,
+ 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x19, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x87, 0x49, 0x00, 0x00,
+ 0x00, 0x00, 0xfc, 0xde, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0x39, 0xef,
+ 0xfc, 0xde, 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x89, 0x4a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x89, 0x4a,
+ 0x00, 0x00, 0x41, 0x08, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xfc, 0xde, 0xfc, 0xde, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x89, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x02, 0x19,
+ 0x89, 0x4a, 0x00, 0x00, 0x00, 0x00, 0xbd, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x39, 0xef, 0xfc, 0xde, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x19, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x87, 0x49, 0xd3, 0x73, 0x00, 0x00, 0x02, 0x19, 0xff, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0xff, 0xfc, 0xde, 0xbd, 0xe7, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xe7,
+ 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x19, 0x41, 0x08, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x02, 0x19, 0xcd, 0x72, 0x41, 0x08, 0x02, 0x19, 0xbf, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xbf, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xfc, 0xde, 0xfc, 0xde, 0xbf, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x87, 0x49, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x86, 0x29, 0x00, 0x00, 0x86, 0x29,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xfc, 0xde, 0xbd, 0xe7,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xfc, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x02, 0x19,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x49,
+ 0x86, 0x29, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0xde,
+ 0x39, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0xb4, 0xb5, 0x00, 0x00, 0x41, 0x08, 0x86, 0x29, 0x86, 0x29,
+ 0x41, 0x08, 0x41, 0x08,
+ 0x87, 0x28, 0x86, 0x29, 0x02, 0x19, 0x02, 0x19, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x02, 0x19, 0xc2, 0x9b, 0xe3, 0xf5, 0xe0, 0xed, 0xc2, 0x9b, 0x00, 0x00,
+ 0x00, 0x00, 0x89, 0x4a,
+ 0xbd, 0xe7, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xfc, 0xde, 0xbd, 0xe7,
+ 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x89, 0x4a, 0x41, 0x08, 0x87, 0x28, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x86, 0x29, 0xcd, 0x72,
+ 0x02, 0x19, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x20, 0xbc, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0x61, 0xd5, 0x00, 0x00,
+ 0x00, 0x00, 0xc9, 0x72, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0x39, 0xef,
+ 0xfd, 0xee, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0x39, 0xef, 0x39, 0xef, 0xbd, 0xff, 0x86, 0x29, 0x02, 0x19, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x86, 0x29, 0x89, 0x4a,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0xc2, 0x9b, 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xa3, 0xcc, 0x00, 0x00, 0x01, 0x00, 0x89, 0x4a, 0xfd, 0xee, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xfc, 0xde, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xbd, 0xff,
+ 0x61, 0xd5, 0xe0, 0xf5, 0xe0, 0xed, 0xe0, 0xed, 0xe0, 0xed, 0x02, 0x19,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x87, 0x49,
+ 0x02, 0x19, 0x02, 0x19, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x02, 0x19, 0xa3, 0xcc, 0x61, 0xd5, 0x61, 0xed, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xa3, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x86, 0x29,
+ 0xfc, 0xde, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x39, 0xef, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0x39, 0xef, 0x61, 0xed, 0x62, 0xee, 0x62, 0xee, 0x22, 0xef, 0x62, 0xee,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x01, 0x00, 0x02, 0x19,
+ 0x02, 0x19, 0x01, 0x00, 0xc3, 0xbb, 0x62, 0xee, 0x02, 0x19, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0x82, 0x7b, 0x00, 0x00,
+ 0x00, 0x00, 0x02, 0x19,
+ 0xf9, 0xce, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xfc, 0xde, 0x39, 0xef, 0xbf, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0x39, 0xef, 0xe0, 0xd4, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xa3, 0xcc, 0x41, 0x08,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x81, 0x40, 0x62, 0xee, 0x22, 0xef, 0xe3, 0xf5,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x49,
+ 0x82, 0x7a, 0x82, 0x7a,
+ 0x82, 0x7a, 0x82, 0x7a, 0xc3, 0xbb, 0xe0, 0xd4, 0xa3, 0xcc, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0x81, 0x49, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x33, 0x95, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbf, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0x39, 0xef, 0xe0, 0xd4, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0x62, 0xee, 0x20, 0xbc,
+ 0x02, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0xe0, 0xd4, 0x62, 0xee, 0xe0, 0xed,
+ 0xe0, 0xed, 0x02, 0x19,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0xc3, 0xbb, 0xe0, 0xd4,
+ 0x61, 0xd5, 0x61, 0xd5,
+ 0xe0, 0xd4, 0xa3, 0xcc, 0xe0, 0xd4, 0xe0, 0xd4, 0x61, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x61, 0xd5,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x4a, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xbd, 0xff, 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xfd, 0xee, 0xf3, 0xd6, 0x61, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed,
+ 0x20, 0xbc, 0x81, 0x49, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0xc2, 0x9a, 0x62, 0xce, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0x02, 0x19, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x7a, 0xe0, 0xd4,
+ 0xa3, 0xcc, 0x61, 0xd5,
+ 0x61, 0xed, 0x61, 0xed, 0x61, 0xd5, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xc3, 0xbb, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x86, 0x29, 0xfc, 0xde,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xfc, 0xde, 0xf8, 0xb5, 0x73, 0xcd, 0xa3, 0xcc,
+ 0x61, 0xed, 0x61, 0xed,
+ 0x61, 0xd5, 0xe0, 0xd4, 0xc2, 0x9a, 0x41, 0x08, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0xc2, 0x9a, 0xe0, 0xd4, 0x61, 0xed,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0x02, 0x19, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc3, 0xbb,
+ 0x61, 0xd5, 0x61, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0xe3, 0xf5, 0xe3, 0xf5,
+ 0xe3, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x62, 0xee, 0x61, 0xd5, 0x81, 0x49, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0xf9, 0xce, 0xbf, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xf8, 0xb5, 0xf9, 0xce, 0x73, 0xcd,
+ 0x61, 0xd5, 0xe0, 0xed,
+ 0x61, 0xed, 0x61, 0xd5, 0xe0, 0xd4, 0x20, 0xbc, 0x20, 0xbc, 0x81, 0x49,
+ 0x81, 0x49, 0x02, 0x19,
+ 0x02, 0x19, 0x81, 0x49, 0xc2, 0x9a, 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xd5,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xf5, 0x02, 0x19, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xc3, 0xbb, 0xe0, 0xd4,
+ 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xed,
+ 0xe0, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0x62, 0xee, 0xe0, 0xf5, 0xa3, 0xcc, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xcd, 0x73, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0x78, 0xd5, 0xf8, 0xb5,
+ 0x73, 0xcd, 0xa3, 0xcc,
+ 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed, 0xa3, 0xcc, 0x20, 0xbc, 0xc3, 0xbb,
+ 0x20, 0xbc, 0xc3, 0xbb,
+ 0x20, 0xbc, 0x20, 0xbc, 0x20, 0xbc, 0x20, 0xbc, 0xa3, 0xcc, 0x61, 0xd5,
+ 0x61, 0xed, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xd4, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x20, 0xbc,
+ 0x61, 0xd5, 0x61, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe3, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0x62, 0xee, 0xe0, 0xed,
+ 0x82, 0x7a, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xd3, 0x93,
+ 0xbd, 0xe7, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xf8, 0xb5,
+ 0xf9, 0xce, 0xb4, 0xb5,
+ 0xe0, 0xd4, 0x61, 0xed, 0x61, 0xed, 0x61, 0xed, 0x61, 0xd5, 0xe0, 0xd4,
+ 0xe0, 0xd4, 0x20, 0xbc,
+ 0x20, 0xbc, 0xa3, 0xcc, 0x20, 0xbc, 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xd5,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe3, 0xf5, 0xa3, 0xcc,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xc2, 0x9b, 0xa3, 0xcc, 0x61, 0xd5, 0x61, 0xed, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0x62, 0xee, 0x61, 0xd5,
+ 0x02, 0x19, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xf9, 0xce,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xf9, 0xce, 0xf8, 0xb5,
+ 0x73, 0xcd, 0x20, 0xbc, 0xa3, 0xcc, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed,
+ 0x61, 0xed, 0xe0, 0xd4,
+ 0xa3, 0xcc, 0xe0, 0xd4, 0xe0, 0xd4, 0xa3, 0xcc, 0x61, 0xed, 0x61, 0xd5,
+ 0x61, 0xed, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x83, 0x71,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0xc3, 0xbb, 0xe0, 0xd4, 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x20, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xcd, 0x72, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xbd, 0xe7, 0xf9, 0xce,
+ 0x78, 0xd5, 0xb4, 0xb5, 0x20, 0xbc, 0x61, 0xd5, 0x61, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0x61, 0xd5,
+ 0x61, 0xed, 0x61, 0xed, 0xe0, 0xd4, 0xa3, 0xcc, 0x61, 0xed, 0x61, 0xd5,
+ 0x61, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0x61, 0xd5, 0x81, 0x49, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x81, 0x49, 0xc3, 0xe3, 0x61, 0xd5, 0x61, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x62, 0xee, 0x61, 0xd5, 0x81, 0x49, 0x00, 0x00, 0x01, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x89, 0x4a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xfc, 0xde, 0x78, 0xd5, 0xc5, 0x4a, 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xed,
+ 0xe0, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed, 0x61, 0xed,
+ 0x61, 0xed, 0x61, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0x82, 0x7a, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x02, 0x19, 0xe0, 0xd4, 0x61, 0xd5,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0x62, 0xee, 0xa3, 0xcc, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x33, 0x95, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xf9, 0xce, 0x89, 0x4a, 0x81, 0x49, 0x20, 0xbc, 0xa3, 0xcc,
+ 0x61, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xa3, 0xcc,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x81, 0x40, 0xe0, 0xd4,
+ 0xa3, 0xcc, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0x22, 0xef,
+ 0xc2, 0x9a, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xd3, 0x93, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbf, 0xff, 0x89, 0x4a, 0x00, 0x00, 0x82, 0x7a, 0x20, 0xbc,
+ 0xe0, 0xd4, 0x61, 0xd5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xc2, 0x9b, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19,
+ 0xe0, 0xd4, 0xe0, 0xd4,
+ 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xd5,
+ 0x82, 0x7b, 0xfc, 0xde, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0x86, 0x29, 0x00, 0x00, 0x00, 0x00, 0x82, 0x7a,
+ 0x20, 0xbc, 0xa3, 0xcc,
+ 0x61, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xd5, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x82, 0x7a, 0xa3, 0xcc,
+ 0xe0, 0xd4, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe0, 0xed, 0xa3, 0xcc, 0xb4, 0xb5, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff,
+ 0xbd, 0xe7, 0xbf, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbd, 0xe7, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x82, 0x7a, 0x20, 0xbc,
+ 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed, 0x61, 0xed, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x20, 0xbc,
+ 0x20, 0xbc, 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xd5, 0x61, 0xd5, 0xc2, 0x9b, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xbd, 0xff,
+ 0xff, 0xff, 0xd3, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x82, 0x7a,
+ 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x61, 0xd5, 0xa3, 0xcc, 0x81, 0x49, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xc3, 0xbb, 0xe0, 0xd4, 0x61, 0xd5, 0xe3, 0xf5, 0xe0, 0xed, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0x62, 0xee, 0x20, 0xbc, 0x82, 0x7a,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xbd, 0xff, 0xbd, 0xe7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff,
+ 0xff, 0xff, 0xbf, 0xff,
+ 0xf9, 0xce, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x82, 0x7a, 0xc2, 0x9b, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed, 0xe0, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xa3, 0xcc, 0x61, 0xed, 0xc2, 0x9b, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x82, 0x7a, 0x20, 0xbc, 0xe0, 0xd4, 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0x61, 0xd5, 0x61, 0xd5, 0xa3, 0xcc,
+ 0x82, 0x7b, 0x87, 0x49,
+ 0xbd, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xbd, 0xe7, 0xff, 0xff, 0xbd, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf9, 0xce,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x19, 0x82, 0x7a, 0x20, 0xbc, 0xe0, 0xd4, 0x61, 0xed, 0xe3, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x61, 0xed,
+ 0x61, 0xed, 0xa3, 0xcc, 0xe0, 0xd4, 0x81, 0x49, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x20, 0xbc, 0x20, 0xbc, 0x61, 0xd5, 0x61, 0xed, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0x61, 0xd5,
+ 0xe0, 0xd4, 0x20, 0xbc,
+ 0x81, 0x49, 0x00, 0x00, 0x89, 0x4a, 0xf9, 0xce, 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xe7, 0xff, 0xff,
+ 0xbd, 0xff, 0xff, 0xff, 0xbd, 0xff, 0xbf, 0xff, 0x39, 0xef, 0xf8, 0xb5,
+ 0xcd, 0x4a, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x81, 0x40, 0x82, 0x7a, 0x20, 0xbc, 0xa3, 0xcc, 0x61, 0xed,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0x61, 0xed,
+ 0xe0, 0xd4, 0xa3, 0xcc, 0xc2, 0x9a, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xa3, 0xcc, 0x20, 0xbc, 0x61, 0xed, 0x61, 0xed,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0xe0, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0x61, 0xed,
+ 0x61, 0xd5, 0xe0, 0xd4,
+ 0xc2, 0x9a, 0x82, 0x7a, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x86, 0x29,
+ 0x86, 0x29, 0x02, 0x19, 0x02, 0x19, 0x02, 0x19, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x81, 0x49, 0x82, 0x7a, 0x20, 0xbc, 0xe0, 0xd4,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe3, 0xf5, 0x61, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0x61, 0xed,
+ 0x61, 0xd5, 0xe0, 0xd4,
+ 0xc3, 0xbb, 0x82, 0x7a, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x20, 0xbc, 0xa3, 0xcc, 0xe0, 0xd4,
+ 0xa3, 0xcc, 0x61, 0xd5,
+ 0x61, 0xed, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0x61, 0xed,
+ 0x61, 0xed, 0xe3, 0xf5,
+ 0x61, 0xed, 0xe0, 0xf5, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed,
+ 0x61, 0xed, 0x61, 0xed,
+ 0x20, 0xbc, 0x20, 0xbc, 0x82, 0x7a, 0x81, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x81, 0x49, 0x82, 0x7a, 0x20, 0xbc,
+ 0xe0, 0xd4, 0x61, 0xed,
+ 0x61, 0xed, 0xe0, 0xed, 0xe0, 0xf5, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5,
+ 0xe0, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xf5, 0x61, 0xd5, 0x61, 0xed, 0x61, 0xd5,
+ 0xe0, 0xd4, 0x20, 0xbc,
+ 0x82, 0x7a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc2, 0x9b, 0x20, 0xbc,
+ 0x20, 0xbc, 0x20, 0xbc,
+ 0xc3, 0xe3, 0xe0, 0xd4, 0xa3, 0xcc, 0xe0, 0xd4, 0xa3, 0xcc, 0x61, 0xd5,
+ 0x61, 0xd5, 0x61, 0xed,
+ 0x61, 0xed, 0x61, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0x61, 0xed, 0xe0, 0xf5,
+ 0xe3, 0xf5, 0x61, 0xed,
+ 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0xe0, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed,
+ 0xe0, 0xd4, 0xa3, 0xcc, 0xc2, 0x9a, 0x82, 0x7a, 0x81, 0x49, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x81, 0x49, 0xc2, 0x9a,
+ 0x20, 0xbc, 0xa3, 0xcc,
+ 0xe0, 0xd4, 0xe3, 0xf5, 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xf5, 0xe3, 0xf5,
+ 0xe0, 0xed, 0x61, 0xed,
+ 0x61, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0x61, 0xd5, 0xa3, 0xcc, 0xe0, 0xd4,
+ 0xa3, 0xcc, 0xc2, 0x9a,
+ 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x41, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x41, 0x08, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x81, 0x40, 0xc2, 0x9a,
+ 0xc2, 0x9a, 0xc2, 0x9b, 0xc2, 0x9b, 0x20, 0xbc, 0x20, 0xbc, 0x20, 0xbc,
+ 0xe0, 0xd4, 0x20, 0xbc,
+ 0xa3, 0xcc, 0xe0, 0xd4, 0xe0, 0xd4, 0xa3, 0xcc, 0x61, 0xed, 0x61, 0xd5,
+ 0x61, 0xed, 0x61, 0xed,
+ 0xe0, 0xf5, 0xe0, 0xed, 0xe3, 0xf5, 0x61, 0xed, 0xe0, 0xed, 0x61, 0xed,
+ 0xe3, 0xf5, 0x61, 0xed,
+ 0x61, 0xd5, 0x20, 0xbc, 0xc2, 0x9b, 0xc2, 0x9a, 0x82, 0x7a, 0x81, 0x49,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x41, 0x08, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
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};
@@ -1796,2633 +3547,5260 @@
/* This image is 228x113 raw Image resembling QuIC logo*/
static char imageBuffer_rgb888[] = {
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+ 0x29, 0x00, 0x00, 0x00,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xef,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xe6, 0xce, 0xde, 0xce,
+ 0xce, 0xde, 0xce, 0x9c, 0xad, 0xce, 0xef, 0xf7, 0xe6, 0xa5, 0x9c, 0xad,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x29, 0x19, 0x08, 0x00,
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+ 0x4a, 0x00, 0x00, 0x00,
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+ 0xff, 0xf7, 0xff, 0xff,
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+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
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+ 0xef, 0xf7, 0xe6, 0xff,
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+ 0xf7, 0xff, 0xff, 0xff,
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+ 0xe6, 0xff, 0xf7, 0xff,
+ 0xef, 0xf7, 0xff, 0xef, 0xde, 0xef, 0xce, 0xe6, 0xad, 0xc5, 0xad, 0xd6,
+ 0xff, 0xff, 0xff, 0x10,
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+ 0x00, 0x00, 0x31, 0x31,
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+ 0x19, 0x08, 0x08, 0x10,
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+ 0xff, 0xff, 0xff, 0xef,
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+ 0xff, 0xff, 0xef, 0xf7,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xde, 0xef,
+ 0xce, 0xde, 0xce, 0xce,
+ 0xde, 0xce, 0xce, 0xad, 0xad, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x21, 0x00, 0x08, 0x08,
+ 0x10, 0x08, 0x08, 0x10, 0x4a, 0x52, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x4a, 0x52, 0x4a,
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+ 0xef, 0xf7, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xde, 0xef, 0xce, 0xde, 0xce, 0xef, 0xf7, 0xff, 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x3a, 0x10,
+ 0x21, 0x31, 0x31, 0x29, 0x31, 0x31, 0x29, 0x08, 0x08, 0x10, 0x10, 0x29,
+ 0x19, 0x00, 0x00, 0x00,
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+ 0x00, 0x10, 0x29, 0x19,
+ 0x3a, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x7b, 0x94,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xf7, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x4a,
+ 0x52, 0x4a, 0x00, 0x00,
+ 0x00, 0x10, 0x29, 0x19, 0x4a, 0x52, 0x4a, 0x31, 0x31, 0x29, 0x08, 0x08,
+ 0x10, 0x3a, 0x31, 0x4a,
+ 0x08, 0x08, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x08, 0x00, 0x00,
+ 0x4a, 0x52, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,
+ 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xce, 0xde,
+ 0xce, 0x3a, 0x10, 0x21, 0x10, 0x29, 0x19, 0x3a, 0x31, 0x4a, 0x3a, 0x10,
+ 0x21, 0x10, 0x21, 0x00,
+ 0x08, 0x08, 0x10, 0x31, 0x31, 0x29, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x3a, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x7b, 0x94, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xe6, 0xde, 0xde, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x4a, 0x52, 0x4a, 0x08, 0x08, 0x10,
+ 0x00, 0x00, 0x00, 0x08,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4a, 0x52, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xce, 0xe6, 0xef, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0x3a, 0x10, 0x21, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x31, 0x29,
+ 0x08, 0x08, 0x10, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x31, 0x31, 0x29, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4a,
+ 0x52, 0x4a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xe6, 0xde, 0xde,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4a, 0x52,
+ 0x4a, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x31,
+ 0x31, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x31, 0x29, 0x08, 0x08, 0x10,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xe6, 0xde, 0xde, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6,
+ 0xe6, 0xde, 0xde, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf7, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0x9c, 0x7b, 0x94,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x08,
+ 0x08, 0x10, 0x10, 0x29, 0x19, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x52, 0x4a,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x29, 0x19, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xce,
+ 0xe6, 0xef, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xa5, 0xb5, 0xb5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x08, 0x08, 0x10, 0x3a, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x31, 0x29, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x52, 0x4a, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf7, 0xff, 0xef,
+ 0xf7, 0xe6, 0xe6, 0xde, 0xde, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xce, 0xde, 0xce, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x10, 0x29, 0x19, 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x31,
+ 0x31, 0x29, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0xce, 0xad, 0xad, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xef, 0xde, 0xef, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x10, 0x29, 0x19, 0x08,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10,
+ 0x21, 0x00, 0x3a, 0x31, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xce,
+ 0xe6, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0xff, 0xce, 0xe6, 0xef, 0xe6, 0xde, 0xde, 0xef,
+ 0xf7, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x3a,
+ 0x31, 0x4a, 0x08, 0x08,
+ 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x08, 0x10, 0x4a, 0x52, 0x4a, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xe6, 0xde, 0xde, 0xe6,
+ 0xde, 0xde, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x4a, 0x52,
+ 0x4a, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a, 0x10, 0x21, 0x4a, 0x52, 0x4a, 0x00,
+ 0x00, 0x00, 0x08, 0x08,
+ 0x10, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xce,
+ 0xe6, 0xef, 0xe6, 0xde,
+ 0xde, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x10, 0x29, 0x19, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x3a, 0x31, 0x4a, 0x6b,
+ 0x7b, 0x73, 0x08, 0x00,
+ 0x00, 0x10, 0x29, 0x19, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xe6, 0xde,
+ 0xde, 0xef, 0xf7, 0xe6, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x10, 0x29, 0x19, 0x08, 0x08, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x10,
+ 0x29, 0x19, 0x6b, 0x5a,
+ 0x73, 0x08, 0x00, 0x00, 0x10, 0x29, 0x19, 0xff, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xe6, 0xde, 0xde, 0xe6, 0xde, 0xde, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x08, 0x10, 0x31, 0x31, 0x29, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x31, 0x31, 0x29, 0x08, 0x00, 0x00, 0x31, 0x31, 0x29, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7,
+ 0xff, 0xef, 0xf7, 0xff, 0xe6, 0xde, 0xde, 0xef, 0xf7, 0xe6, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xe6, 0xde, 0xde, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x10, 0x29, 0x19, 0x08, 0x08,
+ 0x10, 0x08, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a, 0x31, 0x4a, 0x31, 0x31,
+ 0x29, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0xde, 0xde, 0xce, 0xe6,
+ 0xef, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xef, 0xf7, 0xff, 0xff, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa5,
+ 0xb5, 0xb5, 0x00, 0x00,
+ 0x00, 0x10, 0x21, 0x00, 0x3a, 0x31, 0x4a, 0x10, 0x29, 0x19, 0x3a, 0x08,
+ 0x00, 0x08, 0x08, 0x10,
+ 0x08, 0x08, 0x10, 0x31, 0x31, 0x29, 0x31, 0x31, 0x29, 0x10, 0x29, 0x19,
+ 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x10,
+ 0x7b, 0x9c, 0x10, 0xc5,
+ 0xef, 0x10, 0xc5, 0xef, 0x10, 0x7b, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x4a, 0x52, 0x4a,
+ 0xef, 0xf7, 0xe6, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xf7,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0xde,
+ 0xde, 0xef, 0xf7, 0xe6,
+ 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x6b, 0x5a,
+ 0x4a, 0x08, 0x08, 0x10, 0x08, 0x08, 0x10, 0x08, 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x08, 0x08, 0x10,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00,
+ 0x3a, 0x10, 0x21, 0x6b,
+ 0x5a, 0x73, 0x10, 0x29, 0x19, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19,
+ 0x94, 0xce, 0x08, 0xad,
+ 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x08, 0xad,
+ 0xd6, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4a, 0x5a, 0x73, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xe6, 0xde, 0xde,
+ 0xef, 0xde, 0xef, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xce, 0xe6, 0xef, 0xce,
+ 0xe6, 0xef, 0xce, 0xe6,
+ 0xef, 0x08, 0x10, 0x42, 0x10, 0x29, 0x19, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x31, 0x31, 0x29, 0x4a, 0x52, 0x4a, 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19,
+ 0x7b, 0xbd, 0x00, 0x9c,
+ 0xd6, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd,
+ 0xf7, 0x19, 0xbd, 0xf7,
+ 0x00, 0x9c, 0xd6, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x4a, 0x52, 0x4a,
+ 0xef, 0xde, 0xef, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff,
+ 0xe6, 0xde, 0xde, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0x08, 0xad, 0xd6, 0x19,
+ 0xbd, 0xf7, 0x00, 0xbd,
+ 0xef, 0x10, 0xc5, 0xef, 0x10, 0xc5, 0xef, 0x08, 0x08, 0x10, 0x08, 0x08,
+ 0x10, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x08, 0x10, 0x31, 0x31, 0x29, 0x10, 0x29, 0x19, 0x3a,
+ 0x10, 0x21, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x84,
+ 0xbd, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x00, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0x7b, 0xbd, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x31,
+ 0x31, 0x29, 0xe6, 0xde, 0xde, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xce, 0xe6, 0xef, 0xef, 0xf7, 0xe6, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xce, 0xe6, 0xef, 0x08,
+ 0xad, 0xef, 0x00, 0xbd,
+ 0xf7, 0x10, 0xe6, 0xef, 0x10, 0xc5, 0xef, 0x10, 0xe6, 0xef, 0x08, 0x08,
+ 0x10, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x10, 0x29, 0x19, 0x10, 0x29, 0x19, 0x00,
+ 0x00, 0x00, 0x00, 0x84,
+ 0xbd, 0x10, 0xe6, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x19, 0x7b,
+ 0xbd, 0x00, 0x9c, 0xd6, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7,
+ 0x08, 0xad, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x10, 0xc5, 0xef,
+ 0x10, 0x5a, 0x9c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x29, 0x19, 0xce, 0xde, 0xce, 0xff,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0xde, 0xde, 0xef, 0xde, 0xef,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xce,
+ 0xe6, 0xef, 0x00, 0x9c,
+ 0xd6, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x08, 0xad,
+ 0xd6, 0x08, 0x08, 0x10,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x08, 0x10, 0x08, 0x00, 0x00, 0x08,
+ 0x08, 0x10, 0x08, 0x31,
+ 0x3a, 0x10, 0xc5, 0xef, 0x10, 0xc5, 0xef, 0x10, 0xc5, 0xef, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x84,
+ 0xbd, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x08, 0xad,
+ 0xef, 0x00, 0xbd, 0xef,
+ 0x19, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x00,
+ 0xbd, 0xef, 0x08, 0x31, 0x3a, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x9c, 0xa5,
+ 0x94, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xce, 0xe6,
+ 0xef, 0x08, 0xad, 0xd6, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd,
+ 0xef, 0x19, 0x94, 0xce,
+ 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x19, 0x94, 0xce, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xef, 0x10, 0xc5,
+ 0xef, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x84, 0xbd, 0x00,
+ 0x84, 0xbd, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x00, 0x84, 0xbd, 0x19,
+ 0x94, 0xce, 0x00, 0x84,
+ 0xbd, 0x08, 0xad, 0xd6, 0x00, 0x9c, 0xd6, 0x08, 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x19, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xd6, 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x4a, 0x52, 0x4a, 0xff, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xef, 0xde,
+ 0xef, 0x9c, 0xde, 0xd6, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x08, 0xad, 0xef,
+ 0x00, 0x84, 0xbd, 0x08, 0x31, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x08, 0x00,
+ 0x00, 0x10, 0x5a, 0x9c, 0x08, 0xad, 0xd6, 0x00, 0xbd, 0xef, 0x10, 0xc5,
+ 0xef, 0x10, 0xc5, 0xef,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x19,
+ 0x94, 0xce, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x08,
+ 0xad, 0xef, 0x08, 0xad,
+ 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x00,
+ 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19,
+ 0x7b, 0xbd, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x31,
+ 0x29, 0xce, 0xe6, 0xef,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xce, 0xe6,
+ 0xef, 0xce, 0xad, 0xad, 0x9c, 0xad, 0xce, 0x19, 0x94, 0xce, 0x08, 0xad,
+ 0xef, 0x00, 0xbd, 0xef,
+ 0x19, 0x94, 0xce, 0x00, 0x9c, 0xd6, 0x10, 0x5a, 0x9c, 0x08, 0x08, 0x10,
+ 0x00, 0x00, 0x00, 0x08,
+ 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00,
+ 0x00, 0x00, 0x08, 0x08,
+ 0x10, 0x10, 0x73, 0x7b, 0x00, 0x9c, 0xd6, 0x00, 0xbd, 0xef, 0x10, 0xc5,
+ 0xef, 0x08, 0xad, 0xef,
+ 0x00, 0xbd, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x84, 0xbd, 0x00, 0x9c, 0xd6, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x08,
+ 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x19, 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xef, 0x10, 0xce,
+ 0xce, 0x08, 0x31, 0x3a, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x08, 0x10, 0xce, 0xde, 0xce, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xc5, 0xad, 0xd6, 0xce, 0xde, 0xce, 0x9c, 0xad, 0xce, 0x08, 0xad,
+ 0xd6, 0x08, 0xad, 0xef,
+ 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x00, 0x9c, 0xd6, 0x19, 0x7b, 0xbd,
+ 0x10, 0x7b, 0x9c, 0x08,
+ 0x31, 0x5a, 0x08, 0x31, 0x3a, 0x08, 0x08, 0x10, 0x08, 0x31, 0x3a, 0x08,
+ 0x31, 0x3a, 0x10, 0x5a,
+ 0x9c, 0x00, 0x84, 0xbd, 0x00, 0x9c, 0xd6, 0x19, 0x94, 0xce, 0x00, 0xbd,
+ 0xef, 0x08, 0xad, 0xef,
+ 0x10, 0xc5, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x19, 0x7b, 0xbd, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x08,
+ 0xad, 0xef, 0x00, 0xbd,
+ 0xef, 0x19, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x10, 0xc5,
+ 0xef, 0x00, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x08, 0xad, 0xef, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xf7, 0x10, 0xc5,
+ 0xef, 0x00, 0xbd, 0xf7, 0x19, 0x94, 0xce, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x7b, 0x94,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xa5, 0xb5, 0xb5, 0xce, 0xde, 0xce, 0x9c, 0xad,
+ 0xce, 0x19, 0x94, 0xce,
+ 0x08, 0xad, 0xd6, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xd6, 0x00, 0x9c, 0xd6,
+ 0x00, 0x9c, 0xd6, 0x00,
+ 0x84, 0xbd, 0x00, 0x84, 0xbd, 0x00, 0x84, 0xbd, 0x00, 0x84, 0xbd, 0x19,
+ 0x7b, 0xbd, 0x00, 0x84,
+ 0xbd, 0x00, 0x84, 0xbd, 0x00, 0x84, 0xbd, 0x08, 0xad, 0xef, 0x08, 0xad,
+ 0xef, 0x10, 0xc5, 0xef,
+ 0x19, 0xbd, 0xf7, 0x08, 0xad, 0xef, 0x00, 0xbd, 0xef, 0x08, 0xad, 0xef,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0xbd, 0x08, 0xad, 0xd6, 0x08,
+ 0xad, 0xef, 0x10, 0xc5,
+ 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x08, 0xad, 0xef, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xef, 0x19,
+ 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x00,
+ 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xef, 0x10, 0x52,
+ 0x7b, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x6b,
+ 0x7b, 0x73, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xef, 0xf7,
+ 0xe6, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xce, 0xad, 0xad, 0xce, 0xde,
+ 0xce, 0xa5, 0xb5, 0xb5,
+ 0x00, 0x9c, 0xd6, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef,
+ 0x19, 0x94, 0xce, 0x00,
+ 0x9c, 0xd6, 0x19, 0x94, 0xce, 0x00, 0x84, 0xbd, 0x19, 0x94, 0xce, 0x00,
+ 0x84, 0xbd, 0x00, 0x84,
+ 0xbd, 0x00, 0x84, 0xbd, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x08, 0xad,
+ 0xef, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x10, 0xc5, 0xef,
+ 0x10, 0xc5, 0xef, 0x19,
+ 0x94, 0xce, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x7b, 0xbd, 0x19,
+ 0x94, 0xce, 0x08, 0xad,
+ 0xef, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef,
+ 0x00, 0xbd, 0xf7, 0x08,
+ 0xad, 0xef, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x10, 0xc5,
+ 0xef, 0x08, 0xad, 0xd6,
+ 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xce, 0xde, 0xce, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xff, 0xce, 0xde,
+ 0xce, 0xc5, 0xad, 0xd6,
+ 0xa5, 0xb5, 0xb5, 0x19, 0x94, 0xce, 0x00, 0x9c, 0xd6, 0x08, 0xad, 0xd6,
+ 0x08, 0xad, 0xef, 0x08,
+ 0xad, 0xef, 0x08, 0xad, 0xef, 0x00, 0x9c, 0xd6, 0x00, 0x9c, 0xd6, 0x00,
+ 0x9c, 0xd6, 0x00, 0x9c,
+ 0xd6, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x08, 0xad,
+ 0xef, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x08,
+ 0xad, 0xef, 0x08, 0xad, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x84, 0xbd, 0x00, 0x9c,
+ 0xd6, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x19, 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xef,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x19,
+ 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x10,
+ 0xc5, 0xef, 0x00, 0xbd,
+ 0xf7, 0x10, 0xc5, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x00, 0xbd,
+ 0xf7, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xef, 0x19, 0x7b, 0xbd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x5a, 0x73, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0xf7, 0xe6, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xce, 0xde, 0xce,
+ 0xa5, 0xb5, 0xb5, 0x9c, 0xad, 0xce, 0x00, 0x84, 0xbd, 0x00, 0x9c, 0xd6,
+ 0x08, 0xad, 0xef, 0x10,
+ 0xc5, 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x19,
+ 0x94, 0xce, 0x08, 0xad,
+ 0xef, 0x19, 0x94, 0xce, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x08, 0xad,
+ 0xef, 0x00, 0xbd, 0xef,
+ 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x08, 0xad, 0xef,
+ 0x19, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xf7, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x10, 0x7b, 0xe6, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x00, 0xbd,
+ 0xef, 0x00, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x08,
+ 0xad, 0xef, 0x10, 0xc5, 0xef, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x08,
+ 0xad, 0xef, 0x00, 0xbd,
+ 0xf7, 0x19, 0xbd, 0xf7, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x00, 0xbd,
+ 0xf7, 0x19, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x10, 0xe6, 0xef, 0x00, 0xbd, 0xef, 0x08, 0x31, 0x3a,
+ 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a,
+ 0x52, 0x4a, 0xff, 0xff,
+ 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0xf7, 0xe6, 0xff,
+ 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf7, 0xff,
+ 0xe6, 0xde, 0xde, 0xc5, 0xad, 0xd6, 0x29, 0x5a, 0x4a, 0x00, 0x84, 0xbd,
+ 0x19, 0x94, 0xce, 0x08,
+ 0xad, 0xd6, 0x08, 0xad, 0xef, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x00,
+ 0xbd, 0xef, 0x08, 0xad,
+ 0xef, 0x08, 0xad, 0xef, 0x08, 0xad, 0xd6, 0x08, 0xad, 0xef, 0x08, 0xad,
+ 0xef, 0x08, 0xad, 0xef,
+ 0x19, 0xbd, 0xf7, 0x08, 0xad, 0xef, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7,
+ 0x00, 0xbd, 0xf7, 0x00,
+ 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x19,
+ 0xbd, 0xf7, 0x00, 0xbd,
+ 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x19, 0x94, 0xce, 0x08, 0xad, 0xd6, 0x08, 0xad,
+ 0xef, 0x19, 0xbd, 0xf7,
+ 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xef, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x19,
+ 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x10,
+ 0xc5, 0xef, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd, 0xf7, 0x00, 0xbd, 0xf7, 0x19, 0xbd,
+ 0xf7, 0x00, 0xbd, 0xf7,
+ 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x00, 0xbd, 0xf7, 0x10, 0xc5, 0xef,
+ 0x08, 0xad, 0xd6, 0x08,
+ 0x08, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x9c, 0xa5,
+ 0x94, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7,
+ 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xef, 0xf7, 0xff, 0xff, 0xf7, 0xff, 0xef, 0xf7, 0xe6,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0xf7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xf7,
+ 0xe6, 0xff, 0xf7, 0xff,
+ 0xef, 0xf7, 0xff, 0xce, 0xde, 0xce, 0x4a, 0x52, 0x4a, 0x08, 0x31, 0x5a,
+ 0x00, 0x84, 0xbd, 0x00,
+ 0x9c, 0xd6, 0x08, 0xad, 0xef, 0x08, 0xad, 0xef, 0x19, 0xbd, 0xf7, 0x10,
+ 0xc5, 0xef, 0x08, 0xad,
+ 0xef, 0x10, 0xc5, 0xef, 0x08, 0xad, 0xef, 0x00, 0xbd, 0xef, 0x10, 0xc5,
+ 0xef, 0x08, 0xad, 0xef,
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+ 0x19, 0xbd, 0xf7, 0x00,
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
#endif
diff --git a/platform/msm_shared/include/uart_dm.h b/platform/msm_shared/include/uart_dm.h
index a3d0a72..c3c5718 100644
--- a/platform/msm_shared/include/uart_dm.h
+++ b/platform/msm_shared/include/uart_dm.h
@@ -1,232 +1,226 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UART_DM_H__
-#define __UART_DM_H__
-
-#include <platform/iomap.h>
-
-#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
- ((value << (32 - end_pos))\
- >> (32 - (end_pos - start_pos)))
-
-
-/* UART Parity Mode */
-enum MSM_BOOT_UART_DM_PARITY_MODE
-{
- MSM_BOOT_UART_DM_NO_PARITY,
- MSM_BOOT_UART_DM_ODD_PARITY,
- MSM_BOOT_UART_DM_EVEN_PARITY,
- MSM_BOOT_UART_DM_SPACE_PARITY
-};
-
-/* UART Stop Bit Length */
-enum MSM_BOOT_UART_DM_STOP_BIT_LEN
-{
- MSM_BOOT_UART_DM_SBL_9_16,
- MSM_BOOT_UART_DM_SBL_1,
- MSM_BOOT_UART_DM_SBL_1_9_16,
- MSM_BOOT_UART_DM_SBL_2
-};
-
-/* UART Bits per Char */
-enum MSM_BOOT_UART_DM_BITS_PER_CHAR
-{
- MSM_BOOT_UART_DM_5_BPS,
- MSM_BOOT_UART_DM_6_BPS,
- MSM_BOOT_UART_DM_7_BPS,
- MSM_BOOT_UART_DM_8_BPS
-};
-
-/* 8-N-1 Configuration */
-#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
- (MSM_BOOT_UART_DM_SBL_1 << 2) | \
- (MSM_BOOT_UART_DM_8_BPS << 4))
-
-/* UART_DM Registers */
-
-/* UART Operational Mode Register */
-#define MSM_BOOT_UART_DM_MR1(id) (GSBI_UART_DM_BASE(id) + 0x00)
-#define MSM_BOOT_UART_DM_MR2(id) (GSBI_UART_DM_BASE(id) + 0x04)
-#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
-#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
-
-/* UART Clock Selection Register */
-#define MSM_BOOT_UART_DM_CSR(id) (GSBI_UART_DM_BASE(id) + 0x08)
-
-/* UART DM TX FIFO Registers - 4 */
-#define MSM_BOOT_UART_DM_TF(id, x) (GSBI_UART_DM_BASE(id) + 0x70+(4*(x)))
-
-/* UART Command Register */
-#define MSM_BOOT_UART_DM_CR(id) (GSBI_UART_DM_BASE(id) + 0x10)
-#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
-#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
-#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
-#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
-
-/* UART Channel Command */
-#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
-#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
-#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
- MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
-#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
-#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
-#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
-#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
-#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
-#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
-#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
-#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
-#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
-#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
-#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
-#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
-#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
-#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
-#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
-#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
-#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
-#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
-
-/*UART General Command */
-#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
-
-#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
-#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
-#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
-#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
-#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
-#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
-#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
-
-/* UART Interrupt Mask Register */
-#define MSM_BOOT_UART_DM_IMR(id) (GSBI_UART_DM_BASE(id) + 0x14)
-#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
-#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
-#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
-#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
-#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
-#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
-#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
-#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
-#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
-#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
-#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
-#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
-#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
-
-#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
- MSM_BOOT_UART_DM_TXLEV | \
- MSM_BOOT_UART_DM_RXLEV | \
- MSM_BOOT_UART_DM_RXSTALE)
-
-/* UART Interrupt Programming Register */
-#define MSM_BOOT_UART_DM_IPR(id) (GSBI_UART_DM_BASE(id) + 0x18)
-#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
-#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
-
-/* UART Transmit/Receive FIFO Watermark Register */
-#define MSM_BOOT_UART_DM_TFWR(id) (GSBI_UART_DM_BASE(id) + 0x1C)
-/* Interrupt is generated when FIFO level is less than or equal to this value */
-#define MSM_BOOT_UART_DM_TFW_VALUE 0
-
-#define MSM_BOOT_UART_DM_RFWR(id) (GSBI_UART_DM_BASE(id) + 0x20)
-/*Interrupt generated when no of words in RX FIFO is greater than this value */
-#define MSM_BOOT_UART_DM_RFW_VALUE 0
-
-/* UART Hunt Character Register */
-#define MSM_BOOT_UART_DM_HCR(id) (GSBI_UART_DM_BASE(id) + 0x24)
-
-/* Used for RX transfer initialization */
-#define MSM_BOOT_UART_DM_DMRX(id) (GSBI_UART_DM_BASE(id) + 0x34)
-
-/* Default DMRX value - any value bigger than FIFO size would be fine */
-#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
-
-/* Register to enable IRDA function */
-#define MSM_BOOT_UART_DM_IRDA(id) (GSBI_UART_DM_BASE(id) + 0x38)
-
-/* UART Data Mover Enable Register */
-#define MSM_BOOT_UART_DM_DMEN(id) (GSBI_UART_DM_BASE(id) + 0x3C)
-
-/* Number of characters for Transmission */
-#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id) (GSBI_UART_DM_BASE(id) + 0x040)
-
-/* UART RX FIFO Base Address */
-#define MSM_BOOT_UART_DM_BADR(id) (GSBI_UART_DM_BASE(id) + 0x44)
-
-/* UART Status Register */
-#define MSM_BOOT_UART_DM_SR(id) (GSBI_UART_DM_BASE(id) + 0x008)
-#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
-#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
-#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
-#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
-#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
-#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
-#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
-#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
-#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
-
-/* UART Receive FIFO Registers - 4 in numbers */
-#define MSM_BOOT_UART_DM_RF(id, x) (GSBI_UART_DM_BASE(id) + 0x70 + (4*(x)))
-
-/* UART Masked Interrupt Status Register */
-#define MSM_BOOT_UART_DM_MISR(id) (GSBI_UART_DM_BASE(id) + 0x10)
-
-/* UART Interrupt Status Register */
-#define MSM_BOOT_UART_DM_ISR(id) (GSBI_UART_DM_BASE(id) + 0x14)
-
-/* Number of characters received since the end of last RX transfer */
-#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id) (GSBI_UART_DM_BASE(id) + 0x38)
-
-/* UART TX FIFO Status Register */
-#define MSM_BOOT_UART_DM_TXFS(id) (GSBI_UART_DM_BASE(id) + 0x4C)
-#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
-#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
-#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
-#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
-
-/* UART RX FIFO Status Register */
-#define MSM_BOOT_UART_DM_RXFS(id) (GSBI_UART_DM_BASE(id) + 0x50)
-#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
-#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
-#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
-#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
-
-
-
-/* Macros for Common Errors */
-#define MSM_BOOT_UART_DM_E_SUCCESS 0
-#define MSM_BOOT_UART_DM_E_FAILURE 1
-#define MSM_BOOT_UART_DM_E_TIMEOUT 2
-#define MSM_BOOT_UART_DM_E_INVAL 3
-#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
-#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
-
-void uart_init(uint8_t gsbi_id);
-#endif /* __UART_DM_H__*/
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __UART_DM_H__
+#define __UART_DM_H__
+
+#include <platform/iomap.h>
+
+#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
+ ((value << (32 - end_pos))\
+ >> (32 - (end_pos - start_pos)))
+
+/* UART Parity Mode */
+enum MSM_BOOT_UART_DM_PARITY_MODE {
+ MSM_BOOT_UART_DM_NO_PARITY,
+ MSM_BOOT_UART_DM_ODD_PARITY,
+ MSM_BOOT_UART_DM_EVEN_PARITY,
+ MSM_BOOT_UART_DM_SPACE_PARITY
+};
+
+/* UART Stop Bit Length */
+enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
+ MSM_BOOT_UART_DM_SBL_9_16,
+ MSM_BOOT_UART_DM_SBL_1,
+ MSM_BOOT_UART_DM_SBL_1_9_16,
+ MSM_BOOT_UART_DM_SBL_2
+};
+
+/* UART Bits per Char */
+enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
+ MSM_BOOT_UART_DM_5_BPS,
+ MSM_BOOT_UART_DM_6_BPS,
+ MSM_BOOT_UART_DM_7_BPS,
+ MSM_BOOT_UART_DM_8_BPS
+};
+
+/* 8-N-1 Configuration */
+#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
+ (MSM_BOOT_UART_DM_SBL_1 << 2) | \
+ (MSM_BOOT_UART_DM_8_BPS << 4))
+
+/* UART_DM Registers */
+
+/* UART Operational Mode Register */
+#define MSM_BOOT_UART_DM_MR1(id) (GSBI_UART_DM_BASE(id) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(id) (GSBI_UART_DM_BASE(id) + 0x04)
+#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
+#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
+
+/* UART Clock Selection Register */
+#define MSM_BOOT_UART_DM_CSR(id) (GSBI_UART_DM_BASE(id) + 0x08)
+
+/* UART DM TX FIFO Registers - 4 */
+#define MSM_BOOT_UART_DM_TF(id, x) (GSBI_UART_DM_BASE(id) + 0x70+(4*(x)))
+
+/* UART Command Register */
+#define MSM_BOOT_UART_DM_CR(id) (GSBI_UART_DM_BASE(id) + 0x10)
+#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
+#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
+#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
+#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
+
+/* UART Channel Command */
+#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
+#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
+ MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
+#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
+#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
+#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
+#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
+#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
+#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
+#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
+#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
+#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
+#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
+#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
+#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
+#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
+#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
+#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
+
+/*UART General Command */
+#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
+
+#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
+#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
+#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
+#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
+#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
+
+/* UART Interrupt Mask Register */
+#define MSM_BOOT_UART_DM_IMR(id) (GSBI_UART_DM_BASE(id) + 0x14)
+#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
+#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
+#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
+#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
+#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
+#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
+#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
+#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
+#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
+#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
+#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
+#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
+#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
+
+#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
+ MSM_BOOT_UART_DM_TXLEV | \
+ MSM_BOOT_UART_DM_RXLEV | \
+ MSM_BOOT_UART_DM_RXSTALE)
+
+/* UART Interrupt Programming Register */
+#define MSM_BOOT_UART_DM_IPR(id) (GSBI_UART_DM_BASE(id) + 0x18)
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
+
+/* UART Transmit/Receive FIFO Watermark Register */
+#define MSM_BOOT_UART_DM_TFWR(id) (GSBI_UART_DM_BASE(id) + 0x1C)
+/* Interrupt is generated when FIFO level is less than or equal to this value */
+#define MSM_BOOT_UART_DM_TFW_VALUE 0
+
+#define MSM_BOOT_UART_DM_RFWR(id) (GSBI_UART_DM_BASE(id) + 0x20)
+/*Interrupt generated when no of words in RX FIFO is greater than this value */
+#define MSM_BOOT_UART_DM_RFW_VALUE 0
+
+/* UART Hunt Character Register */
+#define MSM_BOOT_UART_DM_HCR(id) (GSBI_UART_DM_BASE(id) + 0x24)
+
+/* Used for RX transfer initialization */
+#define MSM_BOOT_UART_DM_DMRX(id) (GSBI_UART_DM_BASE(id) + 0x34)
+
+/* Default DMRX value - any value bigger than FIFO size would be fine */
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
+
+/* Register to enable IRDA function */
+#define MSM_BOOT_UART_DM_IRDA(id) (GSBI_UART_DM_BASE(id) + 0x38)
+
+/* UART Data Mover Enable Register */
+#define MSM_BOOT_UART_DM_DMEN(id) (GSBI_UART_DM_BASE(id) + 0x3C)
+
+/* Number of characters for Transmission */
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id) (GSBI_UART_DM_BASE(id) + 0x040)
+
+/* UART RX FIFO Base Address */
+#define MSM_BOOT_UART_DM_BADR(id) (GSBI_UART_DM_BASE(id) + 0x44)
+
+/* UART Status Register */
+#define MSM_BOOT_UART_DM_SR(id) (GSBI_UART_DM_BASE(id) + 0x008)
+#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
+#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
+#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
+#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
+#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
+#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
+#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
+#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
+#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
+
+/* UART Receive FIFO Registers - 4 in numbers */
+#define MSM_BOOT_UART_DM_RF(id, x) (GSBI_UART_DM_BASE(id) + 0x70 + (4*(x)))
+
+/* UART Masked Interrupt Status Register */
+#define MSM_BOOT_UART_DM_MISR(id) (GSBI_UART_DM_BASE(id) + 0x10)
+
+/* UART Interrupt Status Register */
+#define MSM_BOOT_UART_DM_ISR(id) (GSBI_UART_DM_BASE(id) + 0x14)
+
+/* Number of characters received since the end of last RX transfer */
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id) (GSBI_UART_DM_BASE(id) + 0x38)
+
+/* UART TX FIFO Status Register */
+#define MSM_BOOT_UART_DM_TXFS(id) (GSBI_UART_DM_BASE(id) + 0x4C)
+#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+/* UART RX FIFO Status Register */
+#define MSM_BOOT_UART_DM_RXFS(id) (GSBI_UART_DM_BASE(id) + 0x50)
+#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+/* Macros for Common Errors */
+#define MSM_BOOT_UART_DM_E_SUCCESS 0
+#define MSM_BOOT_UART_DM_E_FAILURE 1
+#define MSM_BOOT_UART_DM_E_TIMEOUT 2
+#define MSM_BOOT_UART_DM_E_INVAL 3
+#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
+#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
+
+void uart_init(uint8_t gsbi_id);
+#endif /* __UART_DM_H__ */
diff --git a/platform/msm_shared/jtag.c b/platform/msm_shared/jtag.c
index ca45404..0430eaf 100644
--- a/platform/msm_shared/jtag.c
+++ b/platform/msm_shared/jtag.c
@@ -42,50 +42,54 @@
volatile unsigned _jtag_arg1 = 0;
volatile unsigned _jtag_arg2 = 0;
-
void jtag_hook(void);
static void jtag_msg(unsigned status, const char *msg)
{
- unsigned char *out = _jtag_msg_buffer;
- while((*out++ = *msg++) != 0) ;
- _jtag_msg = status;
- do {
- jtag_hook();
- } while(_jtag_msg != 0);
+ unsigned char *out = _jtag_msg_buffer;
+ while ((*out++ = *msg++) != 0) ;
+ _jtag_msg = status;
+ do {
+ jtag_hook();
+ }
+ while (_jtag_msg != 0);
}
void jtag_okay(const char *msg)
{
- if(msg == 0) msg = "OKAY";
- jtag_msg(STATUS_OKAY, msg);
+ if (msg == 0)
+ msg = "OKAY";
+ jtag_msg(STATUS_OKAY, msg);
}
void jtag_fail(const char *msg)
{
- if(msg == 0) msg = "FAIL";
- jtag_msg(STATUS_FAIL, msg);
+ if (msg == 0)
+ msg = "FAIL";
+ jtag_msg(STATUS_FAIL, msg);
}
int jtag_cmd_pending()
{
- jtag_hook();
- return (int) _jtag_cmd;
+ jtag_hook();
+ return (int)_jtag_cmd;
}
-void jtag_cmd_loop(void (*do_cmd)(const char *, unsigned, unsigned, unsigned))
+void jtag_cmd_loop(void (*do_cmd) (const char *, unsigned, unsigned, unsigned))
{
- unsigned n;
- for(;;) {
- if(jtag_cmd_pending()){
- do_cmd((const char*) _jtag_cmd_buffer, _jtag_arg0, _jtag_arg1, _jtag_arg2);
- for(n = 0; n < 256; n++) _jtag_cmd_buffer[n] = 0;
- _jtag_arg0 = 0;
- _jtag_arg1 = 0;
- _jtag_arg2 = 0;
- _jtag_cmd = 0;
- }
- }
+ unsigned n;
+ for (;;) {
+ if (jtag_cmd_pending()) {
+ do_cmd((const char *)_jtag_cmd_buffer, _jtag_arg0,
+ _jtag_arg1, _jtag_arg2);
+ for (n = 0; n < 256; n++)
+ _jtag_cmd_buffer[n] = 0;
+ _jtag_arg0 = 0;
+ _jtag_arg1 = 0;
+ _jtag_arg2 = 0;
+ _jtag_cmd = 0;
+ }
+ }
}
static char jtag_putc_buffer[128];
@@ -93,23 +97,22 @@
static void jtag_push_buffer(void)
{
- jtag_putc_buffer[jtag_putc_count] = 0;
- jtag_putc_count = 0;
- jtag_msg(STATUS_PRINT, jtag_putc_buffer);
+ jtag_putc_buffer[jtag_putc_count] = 0;
+ jtag_putc_count = 0;
+ jtag_msg(STATUS_PRINT, jtag_putc_buffer);
}
void jtag_dputc(unsigned c)
{
- if((c < 32) || (c > 127)) {
- if(c == '\n') {
- jtag_push_buffer();
- }
- return;
- }
+ if ((c < 32) || (c > 127)) {
+ if (c == '\n') {
+ jtag_push_buffer();
+ }
+ return;
+ }
- jtag_putc_buffer[jtag_putc_count++] = c;
- if(jtag_putc_count == 127) {
- jtag_push_buffer();
- }
+ jtag_putc_buffer[jtag_putc_count++] = c;
+ if (jtag_putc_count == 127) {
+ jtag_push_buffer();
+ }
}
-
diff --git a/platform/msm_shared/lcdc.c b/platform/msm_shared/lcdc.c
index 7677b50..0ff9150 100644
--- a/platform/msm_shared/lcdc.c
+++ b/platform/msm_shared/lcdc.c
@@ -70,91 +70,107 @@
#define MDP_RGB_565_FORMAT (BIT(14) | (1<<9) | (0<<8) | (0<<6) | (1<<4) | (1<<2) | (2<<0))
static struct fbcon_config fb_cfg = {
- .height = LCDC_FB_HEIGHT,
- .width = LCDC_FB_WIDTH,
- .stride = LCDC_FB_WIDTH,
- .format = FB_FORMAT_RGB565,
- .bpp = LCDC_FB_BPP,
- .update_start = NULL,
- .update_done = NULL,
+ .height = LCDC_FB_HEIGHT,
+ .width = LCDC_FB_WIDTH,
+ .stride = LCDC_FB_WIDTH,
+ .format = FB_FORMAT_RGB565,
+ .bpp = LCDC_FB_BPP,
+ .update_start = NULL,
+ .update_done = NULL,
};
void lcdc_clock_init(unsigned rate);
-struct fbcon_config *lcdc_init_set( struct lcdc_timing_parameters *custom_timing_param )
+struct fbcon_config *lcdc_init_set(struct lcdc_timing_parameters
+ *custom_timing_param)
{
struct lcdc_timing_parameters timing_param;
unsigned mdp_rgb_size;
- if( custom_timing_param == DEFAULT_LCD_TIMING )
- {
- timing_param.lcdc_hsync_pulse_width_dclk = LCDC_HSYNC_PULSE_WIDTH_DCLK;
- timing_param.lcdc_hsync_back_porch_dclk = LCDC_HSYNC_BACK_PORCH_DCLK;
- timing_param.lcdc_hsync_front_porch_dclk = LCDC_HSYNC_FRONT_PORCH_DCLK;
- timing_param.lcdc_hsync_skew_dclk = LCDC_HSYNC_SKEW_DCLK;
+ if (custom_timing_param == DEFAULT_LCD_TIMING) {
+ timing_param.lcdc_hsync_pulse_width_dclk =
+ LCDC_HSYNC_PULSE_WIDTH_DCLK;
+ timing_param.lcdc_hsync_back_porch_dclk =
+ LCDC_HSYNC_BACK_PORCH_DCLK;
+ timing_param.lcdc_hsync_front_porch_dclk =
+ LCDC_HSYNC_FRONT_PORCH_DCLK;
+ timing_param.lcdc_hsync_skew_dclk = LCDC_HSYNC_SKEW_DCLK;
- timing_param.lcdc_vsync_pulse_width_lines = LCDC_VSYNC_PULSE_WIDTH_LINES;
- timing_param.lcdc_vsync_back_porch_lines = LCDC_VSYNC_BACK_PORCH_LINES;
- timing_param.lcdc_vsync_front_porch_lines = LCDC_VSYNC_FRONT_PORCH_LINES;
- }
- else
- {
- /*use custom timing parameters*/
- timing_param.lcdc_hsync_pulse_width_dclk = custom_timing_param->lcdc_hsync_pulse_width_dclk;
- timing_param.lcdc_hsync_back_porch_dclk = custom_timing_param->lcdc_hsync_back_porch_dclk;
- timing_param.lcdc_hsync_front_porch_dclk = custom_timing_param->lcdc_hsync_front_porch_dclk;
- timing_param.lcdc_hsync_skew_dclk = custom_timing_param->lcdc_hsync_skew_dclk;
+ timing_param.lcdc_vsync_pulse_width_lines =
+ LCDC_VSYNC_PULSE_WIDTH_LINES;
+ timing_param.lcdc_vsync_back_porch_lines =
+ LCDC_VSYNC_BACK_PORCH_LINES;
+ timing_param.lcdc_vsync_front_porch_lines =
+ LCDC_VSYNC_FRONT_PORCH_LINES;
+ } else {
+ /*use custom timing parameters */
+ timing_param.lcdc_hsync_pulse_width_dclk =
+ custom_timing_param->lcdc_hsync_pulse_width_dclk;
+ timing_param.lcdc_hsync_back_porch_dclk =
+ custom_timing_param->lcdc_hsync_back_porch_dclk;
+ timing_param.lcdc_hsync_front_porch_dclk =
+ custom_timing_param->lcdc_hsync_front_porch_dclk;
+ timing_param.lcdc_hsync_skew_dclk =
+ custom_timing_param->lcdc_hsync_skew_dclk;
- timing_param.lcdc_vsync_pulse_width_lines = custom_timing_param->lcdc_vsync_pulse_width_lines;
- timing_param.lcdc_vsync_back_porch_lines = custom_timing_param->lcdc_vsync_back_porch_lines;
- timing_param.lcdc_vsync_front_porch_lines = custom_timing_param->lcdc_vsync_front_porch_lines;
+ timing_param.lcdc_vsync_pulse_width_lines =
+ custom_timing_param->lcdc_vsync_pulse_width_lines;
+ timing_param.lcdc_vsync_back_porch_lines =
+ custom_timing_param->lcdc_vsync_back_porch_lines;
+ timing_param.lcdc_vsync_front_porch_lines =
+ custom_timing_param->lcdc_vsync_front_porch_lines;
/* only set when using custom timing since initialized with defaults */
fb_cfg.height = custom_timing_param->lcdc_fb_height;
- fb_cfg.width = custom_timing_param->lcdc_fb_width;
+ fb_cfg.width = custom_timing_param->lcdc_fb_width;
}
- mdp_rgb_size = (fb_cfg.height <<16) + fb_cfg.width;
+ mdp_rgb_size = (fb_cfg.height << 16) + fb_cfg.width;
- dprintf(INFO, "lcdc_init(): panel is %d x %d\n", fb_cfg.width, fb_cfg.height);
+ dprintf(INFO, "lcdc_init(): panel is %d x %d\n", fb_cfg.width,
+ fb_cfg.height);
#if PLATFORM_MSM8X60
fb_cfg.base = LCDC_FB_ADDR;
#else
fb_cfg.base =
- memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
+ memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
#endif
- writel((unsigned) fb_cfg.base, MSM_MDP_BASE1 + 0x90008);
+ writel((unsigned)fb_cfg.base, MSM_MDP_BASE1 + 0x90008);
writel((fb_cfg.height << 16) | fb_cfg.width, MSM_MDP_BASE1 + 0x90004);
writel(fb_cfg.width * fb_cfg.bpp / 8, MSM_MDP_BASE1 + 0x9000c);
writel(0, MSM_MDP_BASE1 + 0x90010);
- writel(DMA_PACK_ALIGN_LSB|DMA_PACK_PATTERN_RGB|DMA_DITHER_EN|DMA_OUT_SEL_LCDC|
- DMA_IBUF_FORMAT_RGB565|DMA_DSTC0G_8BITS|DMA_DSTC1B_8BITS|DMA_DSTC2R_8BITS,
- MSM_MDP_BASE1 + 0x90000);
+ writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | DMA_DITHER_EN |
+ DMA_OUT_SEL_LCDC | DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS |
+ DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, MSM_MDP_BASE1 + 0x90000);
- int hsync_period = timing_param.lcdc_hsync_pulse_width_dclk +
- timing_param.lcdc_hsync_back_porch_dclk +
- fb_cfg.width +
- timing_param.lcdc_hsync_front_porch_dclk;
- int vsync_period = ( timing_param.lcdc_vsync_pulse_width_lines +
- timing_param.lcdc_vsync_back_porch_lines +
- fb_cfg.height + timing_param.lcdc_vsync_front_porch_lines )
- * hsync_period;
- int hsync_start_x = timing_param.lcdc_hsync_pulse_width_dclk +
- timing_param.lcdc_hsync_back_porch_dclk;
- int hsync_end_x = hsync_period - timing_param.lcdc_hsync_front_porch_dclk - 1;
- int display_hctl = (hsync_end_x << 16) | hsync_start_x;
- int display_vstart= ( timing_param.lcdc_vsync_pulse_width_lines +
- timing_param.lcdc_vsync_back_porch_lines )
- * hsync_period + timing_param.lcdc_hsync_skew_dclk;
- int display_vend = vsync_period -
- ( timing_param.lcdc_vsync_front_porch_lines * hsync_period)
- + timing_param.lcdc_hsync_skew_dclk - 1;
+ int hsync_period = timing_param.lcdc_hsync_pulse_width_dclk +
+ timing_param.lcdc_hsync_back_porch_dclk +
+ fb_cfg.width + timing_param.lcdc_hsync_front_porch_dclk;
+ int vsync_period = (timing_param.lcdc_vsync_pulse_width_lines +
+ timing_param.lcdc_vsync_back_porch_lines +
+ fb_cfg.height +
+ timing_param.lcdc_vsync_front_porch_lines) *
+ hsync_period;
+ int hsync_start_x =
+ timing_param.lcdc_hsync_pulse_width_dclk +
+ timing_param.lcdc_hsync_back_porch_dclk;
+ int hsync_end_x =
+ hsync_period - timing_param.lcdc_hsync_front_porch_dclk - 1;
+ int display_hctl = (hsync_end_x << 16) | hsync_start_x;
+ int display_vstart = (timing_param.lcdc_vsync_pulse_width_lines +
+ timing_param.lcdc_vsync_back_porch_lines)
+ * hsync_period + timing_param.lcdc_hsync_skew_dclk;
+ int display_vend = vsync_period -
+ (timing_param.lcdc_vsync_front_porch_lines * hsync_period)
+ + timing_param.lcdc_hsync_skew_dclk - 1;
- writel((hsync_period << 16) | timing_param.lcdc_hsync_pulse_width_dclk, MSM_MDP_BASE1 + LCDC_BASE + 0x4);
+ writel((hsync_period << 16) | timing_param.lcdc_hsync_pulse_width_dclk,
+ MSM_MDP_BASE1 + LCDC_BASE + 0x4);
writel(vsync_period, MSM_MDP_BASE1 + LCDC_BASE + 0x8);
- writel(timing_param.lcdc_vsync_pulse_width_lines * hsync_period, MSM_MDP_BASE1 + LCDC_BASE + 0xc);
+ writel(timing_param.lcdc_vsync_pulse_width_lines * hsync_period,
+ MSM_MDP_BASE1 + LCDC_BASE + 0xc);
writel(display_hctl, MSM_MDP_BASE1 + LCDC_BASE + 0x10);
writel(display_vstart, MSM_MDP_BASE1 + LCDC_BASE + 0x14);
writel(display_vend, MSM_MDP_BASE1 + LCDC_BASE + 0x18);
@@ -162,7 +178,8 @@
#if MDP4
writel(0xf, MSM_MDP_BASE1 + LCDC_BASE + 0x28);
writel(0xff, MSM_MDP_BASE1 + LCDC_BASE + 0x2c);
- writel(timing_param.lcdc_hsync_skew_dclk, MSM_MDP_BASE1 + LCDC_BASE + 0x30);
+ writel(timing_param.lcdc_hsync_skew_dclk,
+ MSM_MDP_BASE1 + LCDC_BASE + 0x30);
writel(0x3, MSM_MDP_BASE1 + LCDC_BASE + 0x38);
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x1c);
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x20);
@@ -172,7 +189,7 @@
writel(0x100, MSM_MDP_BASE1 + 0x10100);
writel(mdp_rgb_size, MSM_MDP_BASE1 + 0x40000);
writel(mdp_rgb_size, MSM_MDP_BASE1 + 0x40008);
- writel((int) fb_cfg.base, MSM_MDP_BASE1 + 0x40010);
+ writel((int)fb_cfg.base, MSM_MDP_BASE1 + 0x40010);
writel(fb_cfg.width * fb_cfg.bpp / 8, MSM_MDP_BASE1 + 0x40040);
writel(0x00, MSM_MDP_BASE1 + 0x41008);
writel(MDP_RGB_565_FORMAT, MSM_MDP_BASE1 + 0x40050);
@@ -186,7 +203,8 @@
#else
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x28);
writel(0xff, MSM_MDP_BASE1 + LCDC_BASE + 0x2c);
- writel(timing_param.lcdc_hsync_skew_dclk, MSM_MDP_BASE1 + LCDC_BASE + 0x30);
+ writel(timing_param.lcdc_hsync_skew_dclk,
+ MSM_MDP_BASE1 + LCDC_BASE + 0x30);
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x38);
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x1c);
writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x20);
@@ -199,11 +217,10 @@
struct fbcon_config *lcdc_init(void)
{
- return lcdc_init_set( DEFAULT_LCD_TIMING );
+ return lcdc_init_set(DEFAULT_LCD_TIMING);
}
void lcdc_shutdown(void)
{
- writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x0);
+ writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x0);
}
-
diff --git a/platform/msm_shared/mddi.c b/platform/msm_shared/mddi.c
index b4f0d0d..cfa9527 100644
--- a/platform/msm_shared/mddi.c
+++ b/platform/msm_shared/mddi.c
@@ -55,10 +55,10 @@
static int mddi_update_done(void);
static struct fbcon_config fb_cfg = {
- .format = FB_FORMAT_RGB565,
- .bpp = 16,
- .update_start = mddi_start_update,
- .update_done = mddi_update_done,
+ .format = FB_FORMAT_RGB565,
+ .bpp = 16,
+ .update_start = mddi_start_update,
+ .update_done = mddi_update_done,
};
static void printcaps(struct mddi_client_caps *c)
@@ -71,8 +71,7 @@
dprintf(INFO, "mddi: bm: %d,%d win %d,%d rgb %x\n",
c->bitmap_width, c->bitmap_height,
- c->display_window_width, c->display_window_height,
- c->rgb_cap);
+ c->display_window_width, c->display_window_height, c->rgb_cap);
dprintf(INFO, "mddi: vend %x prod %x\n",
c->manufacturer_name, c->product_code);
}
@@ -80,14 +79,14 @@
/* TODO: add timeout */
static int mddi_wait_status(unsigned statmask)
{
- while ((readl(MDDI_STAT) & statmask) == 0);
+ while ((readl(MDDI_STAT) & statmask) == 0) ;
return 0;
}
/* TODO: add timeout */
static int mddi_wait_interrupt(unsigned intmask)
{
- while ((readl(MDDI_INT) & intmask) == 0);
+ while ((readl(MDDI_INT) & intmask) == 0) ;
return 0;
}
@@ -97,7 +96,7 @@
mddi_register_access *ra;
ll = mlist_remote_write;
-
+
ra = &(ll->u.r);
ra->length = 14 + 4;
ra->type = TYPE_REGISTER_ACCESS;
@@ -112,16 +111,17 @@
ll->header_count = 14;
ll->data_count = 4;
ll->data = &ra->reg_data[0];
- ll->next = (void *) 0;
+ ll->next = (void *)0;
ll->reserved = 0;
- writel((unsigned) ll, MDDI_PRI_PTR);
+ writel((unsigned)ll, MDDI_PRI_PTR);
mddi_wait_status(MDDI_STAT_PRI_LINK_LIST_DONE);
}
#ifdef MDDI_MULTI_WRITE
-void mddi_remote_multiwrite(unsigned *val_list, unsigned reg, unsigned val_count)
+void
+mddi_remote_multiwrite(unsigned *val_list, unsigned reg, unsigned val_count)
{
mddi_llentry *ll;
mddi_register_access *ra;
@@ -136,16 +136,16 @@
ra->crc = 0;
ra->reg_addr = reg;
- memcpy((void *)&ra->reg_data[0],val_list,val_count);
+ memcpy((void *)&ra->reg_data[0], val_list, val_count);
ll->flags = 1;
ll->header_count = 14;
ll->data_count = val_count * 4;
ll->data = &ra->reg_data;
- ll->next = (void *) 0;
+ ll->next = (void *)0;
ll->reserved = 0;
- writel((unsigned) ll, MDDI_PRI_PTR);
+ writel((unsigned)ll, MDDI_PRI_PTR);
mddi_wait_status(MDDI_STAT_PRI_LINK_LIST_DONE);
}
@@ -153,7 +153,7 @@
static void mddi_start_update(void)
{
- writel((unsigned) mlist, MDDI_PRI_PTR);
+ writel((unsigned)mlist, MDDI_PRI_PTR);
}
static int mddi_update_done(void)
@@ -170,8 +170,8 @@
static void mddi_init_rev_encap(void)
{
memset(rev_pkt_buf, 0xee, MDDI_REV_PKT_BUF_SIZE);
- writel((unsigned) rev_pkt_buf, MDDI_REV_PTR);
- writel((unsigned) rev_pkt_buf, MDDI_REV_PTR);
+ writel((unsigned)rev_pkt_buf, MDDI_REV_PTR);
+ writel((unsigned)rev_pkt_buf, MDDI_REV_PTR);
writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_SIZE);
writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_ENCAP_SZ);
mddi_do_cmd(CMD_FORCE_NEW_REV_PTR);
@@ -184,50 +184,50 @@
mddi_do_cmd(CMD_HIBERNATE | !!on);
}
-void mddi_set_caps(mddi_client_caps *c)
+void mddi_set_caps(mddi_client_caps * c)
{
- /* Hardcoding the capability values */
- c->length = 74;
- c->type = 66;
- c->client_id = 0;
- c->protocol_ver = 1;
- c->min_protocol_ver = 1;
- c->data_rate_cap = 400;
- c->interface_type_cap = 0;
- c->num_alt_displays = 1;
- c->postcal_data_rate = 400;
- c->bitmap_width = TARGET_XRES;
- c->bitmap_height = TARGET_YRES;
- c->display_window_width = TARGET_XRES;
- c->display_window_height = TARGET_YRES;
- c->cmap_size = 0;
- c->cmap_rgb_width = 0;
- c->rgb_cap = 34592;
- c->mono_cap = 0;
- c->reserved1 = 0;
- c->ycbcr_cap = 0;
- c->bayer_cap = 0;
- c->alpha_cursor_planes = 0;
- c->client_feature_cap = 4489216;
- c->max_video_frame_rate_cap = 60;
- c->min_video_frame_rate_cap = 0;
- c->min_sub_frame_rate = 0;
- c->audio_buf_depth = 0;
- c->audio_channel_cap = 0;
- c->audio_sampe_rate_rap = 0;
- c->audio_sample_res = 0;
- c->mic_audio_sample_res = 0;
- c->mic_sample_rate_cap = 0;
- c->keyboard_data_fmt = 0;
- c->pointing_device_data_fmt = 0;
- c->content_protection_type = 0;
- c->manufacturer_name = 53859;
- c->product_code = 34594;
- c->reserved3 = 0;
- c->serial_no = 1;
- c->week_of_manufacture = 0;
- c->year_of_manufacture = 0;
- c->crc = 53536;
+ /* Hardcoding the capability values */
+ c->length = 74;
+ c->type = 66;
+ c->client_id = 0;
+ c->protocol_ver = 1;
+ c->min_protocol_ver = 1;
+ c->data_rate_cap = 400;
+ c->interface_type_cap = 0;
+ c->num_alt_displays = 1;
+ c->postcal_data_rate = 400;
+ c->bitmap_width = TARGET_XRES;
+ c->bitmap_height = TARGET_YRES;
+ c->display_window_width = TARGET_XRES;
+ c->display_window_height = TARGET_YRES;
+ c->cmap_size = 0;
+ c->cmap_rgb_width = 0;
+ c->rgb_cap = 34592;
+ c->mono_cap = 0;
+ c->reserved1 = 0;
+ c->ycbcr_cap = 0;
+ c->bayer_cap = 0;
+ c->alpha_cursor_planes = 0;
+ c->client_feature_cap = 4489216;
+ c->max_video_frame_rate_cap = 60;
+ c->min_video_frame_rate_cap = 0;
+ c->min_sub_frame_rate = 0;
+ c->audio_buf_depth = 0;
+ c->audio_channel_cap = 0;
+ c->audio_sampe_rate_rap = 0;
+ c->audio_sample_res = 0;
+ c->mic_audio_sample_res = 0;
+ c->mic_sample_rate_cap = 0;
+ c->keyboard_data_fmt = 0;
+ c->pointing_device_data_fmt = 0;
+ c->content_protection_type = 0;
+ c->manufacturer_name = 53859;
+ c->product_code = 34594;
+ c->reserved3 = 0;
+ c->serial_no = 1;
+ c->week_of_manufacture = 0;
+ c->year_of_manufacture = 0;
+ c->crc = 53536;
}
static void mddi_get_caps(struct mddi_client_caps *caps)
@@ -240,20 +240,21 @@
/* sometimes this will fail -- do it three times for luck... */
mddi_do_cmd(CMD_RTD_MEASURE);
- thread_sleep(1);//mdelay(1);
+ thread_sleep(1); //mdelay(1);
mddi_do_cmd(CMD_RTD_MEASURE);
- thread_sleep(1);//mdelay(1);
+ thread_sleep(1); //mdelay(1);
mddi_do_cmd(CMD_RTD_MEASURE);
- thread_sleep(1);//mdelay(1);
+ thread_sleep(1); //mdelay(1);
mddi_do_cmd(CMD_GET_CLIENT_CAP);
do {
n = readl(MDDI_INT);
- } while (!(n & MDDI_INT_REV_DATA_AVAIL) && (--timeout));
-
+ }
+ while (!(n & MDDI_INT_REV_DATA_AVAIL) && (--timeout));
+
if (timeout == 0)
dprintf(INFO, "timeout\n");
@@ -310,7 +311,7 @@
//mddi_get_caps(&client_caps);
//if(!(client_caps.length == 0x4a && client_caps.type == 0x42))
{
- mddi_set_caps(&client_caps);
+ mddi_set_caps(&client_caps);
}
fb_cfg.width = client_caps.bitmap_width;
@@ -328,12 +329,12 @@
dprintf(INFO, "panel is %d x %d\n", fb_cfg.width, fb_cfg.height);
fb_cfg.base =
- memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
+ memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
mlist = memalign(32, sizeof(mddi_llentry) * (fb_cfg.height / 8));
- dprintf(INFO, "FB @ %p mlist @ %x\n", fb_cfg.base, (unsigned) mlist);
+ dprintf(INFO, "FB @ %p mlist @ %x\n", fb_cfg.base, (unsigned)mlist);
- for(n = 0; n < (fb_cfg.height / 8); n++) {
+ for (n = 0; n < (fb_cfg.height / 8); n++) {
unsigned y = n * 8;
unsigned pixels = fb_cfg.width * 8;
mddi_video_stream *vs = &(mlist[n].u.v);
@@ -341,7 +342,7 @@
vs->length = sizeof(mddi_video_stream) - 2 + (pixels * 2);
vs->type = TYPE_VIDEO_STREAM;
vs->client_id = 0;
- vs->format = 0x5565; // FORMAT_16BPP;
+ vs->format = 0x5565; // FORMAT_16BPP;
vs->pixattr = PIXATTR_BOTH_EYES | PIXATTR_TO_ALL;
vs->left = 0;
@@ -364,8 +365,8 @@
mlist[n].flags = 0;
}
- mlist[n-1].flags = 1;
- mlist[n-1].next = 0;
+ mlist[n - 1].flags = 1;
+ mlist[n - 1].next = 0;
mddi_set_auto_hibernate(1);
mddi_do_cmd(CMD_LINK_ACTIVE);
diff --git a/platform/msm_shared/mddi_hw.h b/platform/msm_shared/mddi_hw.h
index 22506cb..4c55275 100644
--- a/platform/msm_shared/mddi_hw.h
+++ b/platform/msm_shared/mddi_hw.h
@@ -49,10 +49,10 @@
#define MAX_CLIENT_REG 1
#endif
-enum { /* display configuration for MDP4 */
- PRIMARY_INTF_SEL,
- SECONDARY_INTF_SEL,
- EXTERNAL_INTF_SEL
+enum { /* display configuration for MDP4 */
+ PRIMARY_INTF_SEL,
+ SECONDARY_INTF_SEL,
+ EXTERNAL_INTF_SEL
};
#define outp32(port, val) (*((volatile unsigned *) (port)) = ((unsigned) (val)))
@@ -142,7 +142,6 @@
#define MDDI_PAD_IO_CTL MDDI_REG(0x00a0)
#define MDDI_PAD_CAL MDDI_REG(0x00a4)
-
#define CMD_POWER_DOWN 0x0100
#define CMD_POWER_UP 0x0200
#define CMD_HIBERNATE 0x0300
@@ -198,58 +197,56 @@
typedef struct mddi_llentry mddi_llentry;
-struct __attribute__((packed)) mddi_video_stream
-{
- unsigned short length; /* length in bytes excluding this field */
- unsigned short type; /* MDDI_TYPE_VIDEO_STREAM */
- unsigned short client_id; /* set to zero */
-
- unsigned short format;
- unsigned short pixattr;
+struct __attribute__ ((packed)) mddi_video_stream {
+ unsigned short length; /* length in bytes excluding this field */
+ unsigned short type; /* MDDI_TYPE_VIDEO_STREAM */
+ unsigned short client_id; /* set to zero */
- unsigned short left;
- unsigned short top;
- unsigned short right;
- unsigned short bottom;
+ unsigned short format;
+ unsigned short pixattr;
- unsigned short start_x;
- unsigned short start_y;
+ unsigned short left;
+ unsigned short top;
+ unsigned short right;
+ unsigned short bottom;
- unsigned short pixels;
+ unsigned short start_x;
+ unsigned short start_y;
- unsigned short crc;
- unsigned short reserved;
+ unsigned short pixels;
+
+ unsigned short crc;
+ unsigned short reserved;
};
-struct __attribute__((packed)) mddi_register_access
-{
- unsigned short length;
- unsigned short type;
- unsigned short client_id;
+struct __attribute__ ((packed)) mddi_register_access {
+ unsigned short length;
+ unsigned short type;
+ unsigned short client_id;
- unsigned short rw_info; /* flag below | count of reg_data */
+ unsigned short rw_info; /* flag below | count of reg_data */
#define MDDI_WRITE (0 << 14)
#define MDDI_READ (2 << 14)
#define MDDI_READ_RESP (3 << 14)
-
- unsigned reg_addr;
- unsigned short crc; /* 16 bit crc of the above */
- unsigned reg_data[MAX_CLIENT_REG]; /* "list" of 3byte data values */
+ unsigned reg_addr;
+ unsigned short crc; /* 16 bit crc of the above */
+
+ unsigned reg_data[MAX_CLIENT_REG]; /* "list" of 3byte data values */
};
-struct __attribute__((packed)) mddi_llentry {
- unsigned short flags;
- unsigned short header_count;
- unsigned short data_count;
- void *data;
- mddi_llentry *next;
- unsigned short reserved;
- union {
- mddi_video_stream v;
- mddi_register_access r;
- unsigned _[12];
- } u;
+struct __attribute__ ((packed)) mddi_llentry {
+ unsigned short flags;
+ unsigned short header_count;
+ unsigned short data_count;
+ void *data;
+ mddi_llentry *next;
+ unsigned short reserved;
+ union {
+ mddi_video_stream v;
+ mddi_register_access r;
+ unsigned _[12];
+ } u;
};
-#endif /* __PLATFORM_MSM7K_MDDI_HW_H */
+#endif /* __PLATFORM_MSM7K_MDDI_HW_H */
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index f9f3409..396ab6a 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -33,71 +33,69 @@
#include <platform/timer.h>
#include <platform/iomap.h>
-int mdp_setup_dma_p_video_mode(unsigned short disp_width,
- unsigned short disp_height,
- unsigned short img_width,
- unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned short pack_pattern,
- unsigned char ystride)
+int
+mdp_setup_dma_p_video_mode(unsigned short disp_width,
+ unsigned short disp_height,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned short pack_pattern, unsigned char ystride)
{
- // unsigned long mdp_intr_status;
- int status = FAIL;
- unsigned long hsync_period;
- unsigned long vsync_period;
- unsigned long vsync_period_intmd;
+ // unsigned long mdp_intr_status;
+ int status = FAIL;
+ unsigned long hsync_period;
+ unsigned long vsync_period;
+ unsigned long vsync_period_intmd;
- dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
+ dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
- hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
- vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
- vsync_period = vsync_period_intmd * hsync_period;
+ hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
+ vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
+ vsync_period = vsync_period_intmd * hsync_period;
+ // ------------- programming MDP_DMA_P_CONFIG ---------------------
+ writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
- // ------------- programming MDP_DMA_P_CONFIG ---------------------
- writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
+ writel(0x00000000, MDP_DMA_P_OUT_XY);
+ writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
+ writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
+ writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
+ writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
+ MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel((img_height + vsync_porch0_bp) * hsync_period,
+ MDP_DSI_VIDEO_DISPLAY_V_END);
+ writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
+ writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
+ writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
+ // end of cmd mdp
- writel(0x00000000, MDP_DMA_P_OUT_XY);
- writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
- writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
- writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
- writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
- MDP_DSI_VIDEO_DISPLAY_HCTL);
- writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
- writel((img_height + vsync_porch0_bp) * hsync_period,
- MDP_DSI_VIDEO_DISPLAY_V_END);
- writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
- writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
- writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
- // end of cmd mdp
+ writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
- writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
-
- status = PASS;
- return status;
+ status = PASS;
+ return status;
}
+
void mdp_disable(void)
{
- writel(0x00000000, MDP_DSI_VIDEO_EN);
+ writel(0x00000000, MDP_DSI_VIDEO_EN);
}
void mdp_shutdown(void)
{
- mdp_disable();
- mdelay(60);
- writel(0x00000000, MDP_INTR_ENABLE);
- writel(0x01ffffff, MDP_INTR_CLEAR);
+ mdp_disable();
+ mdelay(60);
+ writel(0x00000000, MDP_INTR_ENABLE);
+ writel(0x01ffffff, MDP_INTR_CLEAR);
}
-
-
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 3fbf2fc..21fad3d 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -33,155 +33,158 @@
#include <platform/timer.h>
#include <platform/iomap.h>
-void mdp_setup_dma_p_video_config(unsigned short pack_pattern,
- unsigned short img_width,
- unsigned short img_height,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned char ystride){
- dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
+void
+mdp_setup_dma_p_video_config(unsigned short pack_pattern,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned char ystride)
+{
+ dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
- // ----- programming MDP_AXI_RDMASTER_CONFIG --------
- /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
- the only port connected */
- //TODO: Seems to still work without this
- writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ // ----- programming MDP_AXI_RDMASTER_CONFIG --------
+ /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
+ the only port connected */
+ //TODO: Seems to still work without this
+ writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
- writel(0x00000049, MDP_DISP_INTF_SEL);
+ /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
+ writel(0x00000049, MDP_DISP_INTF_SEL);
- /* DMA P */
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ /* DMA P */
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- /* RGB 888 */
- writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
+ /* RGB 888 */
+ writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
- writel(0x0, MDP_DMA_P_OUT_XY);
+ writel(0x0, MDP_DMA_P_OUT_XY);
- writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
+ writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
}
-int mdp_setup_dma_p_video_mode(unsigned short disp_width,
- unsigned short disp_height,
- unsigned short img_width,
- unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned short pack_pattern,
- unsigned char ystride)
+int
+mdp_setup_dma_p_video_mode(unsigned short disp_width,
+ unsigned short disp_height,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned short pack_pattern, unsigned char ystride)
{
- // unsigned long mdp_intr_status;
- int status = FAIL;
- unsigned long hsync_period;
- unsigned long vsync_period;
- unsigned long vsync_period_intmd;
+ // unsigned long mdp_intr_status;
+ int status = FAIL;
+ unsigned long hsync_period;
+ unsigned long vsync_period;
+ unsigned long vsync_period_intmd;
- dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
+ dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
- hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
- vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
- vsync_period = vsync_period_intmd * hsync_period;
+ hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
+ vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
+ vsync_period = vsync_period_intmd * hsync_period;
- // ----- programming MDP_AXI_RDMASTER_CONFIG --------
- /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
- the only port connected */
- writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL*/
- writel(0x00000049, MDP_DISP_INTF_SEL);
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ // ----- programming MDP_AXI_RDMASTER_CONFIG --------
+ /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
+ the only port connected */
+ writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */
+ writel(0x00000049, MDP_DISP_INTF_SEL);
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- // ------------- programming MDP_DMA_P_CONFIG ---------------------
- writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
+ // ------------- programming MDP_DMA_P_CONFIG ---------------------
+ writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
- writel(0x00000000, MDP_DMA_P_OUT_XY);
- writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
- writel(0x00ff0000, MDP_DMA_P_OP_MODE);
- writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
- writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
- writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
- MDP_DSI_VIDEO_DISPLAY_HCTL);
- writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
- writel((img_height + vsync_porch0_bp) * hsync_period,
- MDP_DSI_VIDEO_DISPLAY_V_END);
- writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
- writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
- writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
- // end of cmd mdp
+ writel(0x00000000, MDP_DMA_P_OUT_XY);
+ writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(0x00ff0000, MDP_DMA_P_OP_MODE);
+ writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
+ writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
+ writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
+ writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
+ MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel((img_height + vsync_porch0_bp) * hsync_period,
+ MDP_DSI_VIDEO_DISPLAY_V_END);
+ writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
+ writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
+ writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
+ // end of cmd mdp
- writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
+ writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
- status = PASS;
- return status;
+ status = PASS;
+ return status;
}
-
-int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, unsigned short num_of_lanes)
+int
+mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
+ unsigned short num_of_lanes)
{
- int status = 0;
- unsigned long input_img_addr = MIPI_FB_ADDR;
- unsigned short image_wd = mipi_fb_cfg.width;
- unsigned short image_ht = mipi_fb_cfg.height;
- unsigned short pack_pattern = 0x12;
- unsigned char ystride = 3;
+ int status = 0;
+ unsigned long input_img_addr = MIPI_FB_ADDR;
+ unsigned short image_wd = mipi_fb_cfg.width;
+ unsigned short image_ht = mipi_fb_cfg.height;
+ unsigned short pack_pattern = 0x12;
+ unsigned char ystride = 3;
- writel(0x03ffffff, MDP_INTR_ENABLE);
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ writel(0x03ffffff, MDP_INTR_ENABLE);
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- // ------------- programming MDP_DMA_P_CONFIG ---------------------
- writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
+ // ------------- programming MDP_DMA_P_CONFIG ---------------------
+ writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
- writel(0x00000000, MDP_DMA_P_OUT_XY);
- writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(0x00000000, MDP_DMA_P_OUT_XY);
+ writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
- writel(0x00000000, MDP_DMA_P_OP_MODE);
+ writel(0x00000000, MDP_DMA_P_OP_MODE);
- writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
- writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
+ writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
+ writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
- writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- writel(0x8a, MDP_DISP_INTF_SEL);
+ writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ writel(0x8a, MDP_DISP_INTF_SEL);
- return status;
+ return status;
}
void mdp_disable(void)
{
- writel(0x00000000, MDP_DSI_VIDEO_EN);
+ writel(0x00000000, MDP_DSI_VIDEO_EN);
}
void mdp_shutdown(void)
{
- mdp_disable();
- mdelay(60);
- writel(0x00000000, MDP_INTR_ENABLE);
- writel(0x00000003, MDP_OVERLAYPROC0_CFG);
+ mdp_disable();
+ mdelay(60);
+ writel(0x00000000, MDP_INTR_ENABLE);
+ writel(0x00000003, MDP_OVERLAYPROC0_CFG);
}
void mdp_start_dma(void)
{
- writel(0x00000001, MDP_DMA_P_START);
+ writel(0x00000001, MDP_DMA_P_START);
}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 5d6fc94..795dca7 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -40,89 +40,94 @@
#include <platform/timer.h>
extern void mdp_disable(void);
-extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, unsigned short num_of_lanes);
+extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
+ unsigned short num_of_lanes);
extern void mdp_shutdown(void);
extern void mdp_start_dma(void);
extern void dsb(void);
#if DISPLAY_MIPI_PANEL_TOSHIBA
static struct fbcon_config mipi_fb_cfg = {
- .height = TSH_MIPI_FB_HEIGHT,
- .width = TSH_MIPI_FB_WIDTH,
- .stride = TSH_MIPI_FB_WIDTH,
- .format = FB_FORMAT_RGB888,
- .bpp = 24,
- .update_start = NULL,
- .update_done = NULL,
+ .height = TSH_MIPI_FB_HEIGHT,
+ .width = TSH_MIPI_FB_WIDTH,
+ .stride = TSH_MIPI_FB_WIDTH,
+ .format = FB_FORMAT_RGB888,
+ .bpp = 24,
+ .update_start = NULL,
+ .update_done = NULL,
};
+
struct mipi_dsi_panel_config toshiba_panel_info = {
- .mode = MIPI_VIDEO_MODE,
- .num_of_lanes = 1,
- .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl,
- .panel_cmds = toshiba_panel_video_mode_cmds,
- .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds),
+ .mode = MIPI_VIDEO_MODE,
+ .num_of_lanes = 1,
+ .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl,
+ .panel_cmds = toshiba_panel_video_mode_cmds,
+ .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds),
};
#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
static struct fbcon_config mipi_fb_cfg = {
- .height = NOV_MIPI_FB_HEIGHT,
- .width = NOV_MIPI_FB_WIDTH,
- .stride = NOV_MIPI_FB_WIDTH,
- .format = FB_FORMAT_RGB888,
- .bpp = 24,
- .update_start = NULL,
- .update_done = NULL,
+ .height = NOV_MIPI_FB_HEIGHT,
+ .width = NOV_MIPI_FB_WIDTH,
+ .stride = NOV_MIPI_FB_WIDTH,
+ .format = FB_FORMAT_RGB888,
+ .bpp = 24,
+ .update_start = NULL,
+ .update_done = NULL,
};
+
struct mipi_dsi_panel_config novatek_panel_info = {
- .mode = MIPI_CMD_MODE,
- .num_of_lanes = 2,
- .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl,
- .panel_cmds = novatek_panel_cmd_mode_cmds,
- .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds),
+ .mode = MIPI_CMD_MODE,
+ .num_of_lanes = 2,
+ .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl,
+ .panel_cmds = novatek_panel_cmd_mode_cmds,
+ .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds),
};
#elif DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
static struct fbcon_config mipi_fb_cfg = {
- .height = TSH_MDT61_MIPI_FB_HEIGHT,
- .width = TSH_MDT61_MIPI_FB_WIDTH,
- .stride = TSH_MDT61_MIPI_FB_WIDTH,
- .format = FB_FORMAT_RGB888,
- .bpp = 24,
- .update_start = NULL,
- .update_done = NULL,
+ .height = TSH_MDT61_MIPI_FB_HEIGHT,
+ .width = TSH_MDT61_MIPI_FB_WIDTH,
+ .stride = TSH_MDT61_MIPI_FB_WIDTH,
+ .format = FB_FORMAT_RGB888,
+ .bpp = 24,
+ .update_start = NULL,
+ .update_done = NULL,
};
+
struct mipi_dsi_panel_config toshiba_mdt61_panel_info = {
- .mode = MIPI_VIDEO_MODE,
- .num_of_lanes = 3,
- .dsi_phy_config = &mipi_dsi_toshiba_mdt61_panel_phy_ctrl,
- .panel_cmds = toshiba_mdt61_video_mode_cmds,
- .num_of_panel_cmds = ARRAY_SIZE(toshiba_mdt61_video_mode_cmds),
+ .mode = MIPI_VIDEO_MODE,
+ .num_of_lanes = 3,
+ .dsi_phy_config = &mipi_dsi_toshiba_mdt61_panel_phy_ctrl,
+ .panel_cmds = toshiba_mdt61_video_mode_cmds,
+ .num_of_panel_cmds = ARRAY_SIZE(toshiba_mdt61_video_mode_cmds),
};
#elif DISPLAY_MIPI_PANEL_RENESAS
static struct fbcon_config mipi_fb_cfg = {
- .height = REN_MIPI_FB_HEIGHT,
- .width = REN_MIPI_FB_WIDTH,
- .stride = REN_MIPI_FB_WIDTH,
- .format = FB_FORMAT_RGB888,
- .bpp = 24,
- .update_start = NULL,
- .update_done = NULL,
+ .height = REN_MIPI_FB_HEIGHT,
+ .width = REN_MIPI_FB_WIDTH,
+ .stride = REN_MIPI_FB_WIDTH,
+ .format = FB_FORMAT_RGB888,
+ .bpp = 24,
+ .update_start = NULL,
+ .update_done = NULL,
};
+
struct mipi_dsi_panel_config renesas_panel_info = {
- .mode = MIPI_VIDEO_MODE,
- .num_of_lanes = 2,
- .dsi_phy_config = &mipi_dsi_renesas_panel_phy_ctrl,
- .panel_cmds = renesas_panel_video_mode_cmds,
- .num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds),
- .lane_swap = 1,
+ .mode = MIPI_VIDEO_MODE,
+ .num_of_lanes = 2,
+ .dsi_phy_config = &mipi_dsi_renesas_panel_phy_ctrl,
+ .panel_cmds = renesas_panel_video_mode_cmds,
+ .num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds),
+ .lane_swap = 1,
};
#else
static struct fbcon_config mipi_fb_cfg = {
- .height = 0,
- .width = 0,
- .stride = 0,
- .format = 0,
- .bpp = 0,
- .update_start = NULL,
- .update_done = NULL,
+ .height = 0,
+ .width = 0,
+ .stride = 0,
+ .format = 0,
+ .bpp = 0,
+ .update_start = NULL,
+ .update_done = NULL,
};
#endif
@@ -132,134 +137,133 @@
int mipi_dsi_phy_ctrl_config(struct mipi_dsi_panel_config *pinfo)
{
- unsigned i;
- unsigned off = 0;
- struct mipi_dsi_phy_ctrl *pd;
+ unsigned i;
+ unsigned off = 0;
+ struct mipi_dsi_phy_ctrl *pd;
- writel(0x00000001, DSIPHY_SW_RESET);
- writel(0x00000000, DSIPHY_SW_RESET);
+ writel(0x00000001, DSIPHY_SW_RESET);
+ writel(0x00000000, DSIPHY_SW_RESET);
- pd = (pinfo->dsi_phy_config);
+ pd = (pinfo->dsi_phy_config);
- off = 0x02cc; /* regulator ctrl 0 */
- for (i = 0; i < 4; i++) {
- writel(pd->regulator[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x02cc; /* regulator ctrl 0 */
+ for (i = 0; i < 4; i++) {
+ writel(pd->regulator[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- off = 0x0260; /* phy timig ctrl 0 */
- for (i = 0; i < 11; i++) {
- writel(pd->timing[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0260; /* phy timig ctrl 0 */
+ for (i = 0; i < 11; i++) {
+ writel(pd->timing[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- // T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing length should >
- // data lane HS timing length
- writel(0xa1e, DSI_CLKOUT_TIMING_CTRL);
+ // T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing length should >
+ // data lane HS timing length
+ writel(0xa1e, DSI_CLKOUT_TIMING_CTRL);
- off = 0x0290; /* ctrl 0 */
- for (i = 0; i < 4; i++) {
- writel(pd->ctrl[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0290; /* ctrl 0 */
+ for (i = 0; i < 4; i++) {
+ writel(pd->ctrl[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- off = 0x02a0; /* strength 0 */
- for (i = 0; i < 4; i++) {
- writel(pd->strength[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x02a0; /* strength 0 */
+ for (i = 0; i < 4; i++) {
+ writel(pd->strength[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
#if DISPLAY_MIPI_PANEL_RENESAS
- if(machine_is_7x25a()) {
- pd->pll[10] |=0x8;
- }
+ if (machine_is_7x25a()) {
+ pd->pll[10] |= 0x8;
+ }
#endif
- off = 0x0204; /* pll ctrl 1, skip 0 */
- for (i = 1; i < 21; i++) {
- writel(pd->pll[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0204; /* pll ctrl 1, skip 0 */
+ for (i = 1; i < 21; i++) {
+ writel(pd->pll[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- /* pll ctrl 0 */
- writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
- writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
- /* lane swp ctrol */
- if (pinfo->lane_swap)
- writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac);
- return (0);
+ /* pll ctrl 0 */
+ writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
+ writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
+ /* lane swp ctrol */
+ if (pinfo->lane_swap)
+ writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac);
+ return (0);
}
struct mipi_dsi_panel_config *get_panel_info(void)
{
#if DISPLAY_MIPI_PANEL_TOSHIBA
- return &toshiba_panel_info;
+ return &toshiba_panel_info;
#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
- return &novatek_panel_info;
+ return &novatek_panel_info;
#elif DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
- return &toshiba_mdt61_panel_info;
+ return &toshiba_mdt61_panel_info;
#elif DISPLAY_MIPI_PANEL_RENESAS
- if(machine_is_7x25a()) {
- renesas_panel_info.num_of_lanes = 1;
- mipi_fb_cfg.height = REN_MIPI_FB_HEIGHT_HVGA;
- }
- return &renesas_panel_info;
+ if (machine_is_7x25a()) {
+ renesas_panel_info.num_of_lanes = 1;
+ mipi_fb_cfg.height = REN_MIPI_FB_HEIGHT_HVGA;
+ }
+ return &renesas_panel_info;
#endif
- return NULL;
+ return NULL;
}
int dsi_cmd_dma_trigger_for_panel()
{
- unsigned long ReadValue;
- unsigned long count = 0;
- int status = 0;
+ unsigned long ReadValue;
+ unsigned long count = 0;
+ int status = 0;
- writel(0x03030303, DSI_INT_CTRL);
- writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
- dsb();
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- while (ReadValue != 0x00000001) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- count++;
- if (count > 0xffff) {
- status = FAIL;
- dprintf(CRITICAL, "Panel CMD: command mode dma test failed\n");
- return status;
- }
- }
+ writel(0x03030303, DSI_INT_CTRL);
+ writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
+ dsb();
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ while (ReadValue != 0x00000001) {
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ count++;
+ if (count > 0xffff) {
+ status = FAIL;
+ dprintf(CRITICAL,
+ "Panel CMD: command mode dma test failed\n");
+ return status;
+ }
+ }
- writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
- dprintf
- (SPEW, "Panel CMD: command mode dma tested successfully\n");
- return status;
+ writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
+ dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
+ return status;
}
-
int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
{
- int ret = 0;
- struct mipi_dsi_cmd *cm;
- int i = 0;
- char pload[256];
- uint32_t off;
+ int ret = 0;
+ struct mipi_dsi_cmd *cm;
+ int i = 0;
+ char pload[256];
+ uint32_t off;
- /* Align pload at 8 byte boundry */
- off = pload;
- off &= 0x07;
- if (off)
- off = 8 - off;
- off += pload;
+ /* Align pload at 8 byte boundry */
+ off = pload;
+ off &= 0x07;
+ if (off)
+ off = 8 - off;
+ off += pload;
- cm = cmds;
- for (i = 0; i < count; i++) {
- memcpy((void *) off, (cm->payload), cm->size);
- writel(off, DSI_DMA_CMD_OFFSET);
- writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
- dsb();
- ret += dsi_cmd_dma_trigger_for_panel();
- udelay(80);
- cm++;
- }
- return ret;
+ cm = cmds;
+ for (i = 0; i < count; i++) {
+ memcpy((void *)off, (cm->payload), cm->size);
+ writel(off, DSI_DMA_CMD_OFFSET);
+ writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
+ dsb();
+ ret += dsi_cmd_dma_trigger_for_panel();
+ udelay(80);
+ cm++;
+ }
+ return ret;
}
/*
@@ -272,458 +276,460 @@
*/
int mipi_dsi_cmds_rx(char **rp, int len)
{
- uint32_t *lp, data;
- char * dp;
- int i, off, cnt;
- int rlen, res;
+ uint32_t *lp, data;
+ char *dp;
+ int i, off, cnt;
+ int rlen, res;
- if(len <= 2)
- rlen = 4; /* short read */
- else
- rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
+ if (len <= 2)
+ rlen = 4; /* short read */
+ else
+ rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
- if (rlen > MIPI_DSI_REG_LEN) {
- return 0;
- }
+ if (rlen > MIPI_DSI_REG_LEN) {
+ return 0;
+ }
- res = rlen & 0x03;
+ res = rlen & 0x03;
- rlen += res; /* 4 byte align */
- lp = (uint32_t *)(*rp);
+ rlen += res; /* 4 byte align */
+ lp = (uint32_t *) (*rp);
- cnt = rlen;
- cnt += 3;
- cnt >>=2;
+ cnt = rlen;
+ cnt += 3;
+ cnt >>= 2;
- if (cnt > 4)
- cnt = 4; /* 4 x 32 bits registers only */
+ if (cnt > 4)
+ cnt = 4; /* 4 x 32 bits registers only */
- off = 0x068; /* DSI_RDBK_DATA0 */
- off += ((cnt - 1) * 4);
+ off = 0x068; /* DSI_RDBK_DATA0 */
+ off += ((cnt - 1) * 4);
- for (i = 0; i < cnt; i++) {
- data = (uint32_t)readl(MIPI_DSI_BASE + off);
- *lp++ = ntohl(data); /* to network byte order */
- off -= 4;
- }
+ for (i = 0; i < cnt; i++) {
+ data = (uint32_t) readl(MIPI_DSI_BASE + off);
+ *lp++ = ntohl(data); /* to network byte order */
+ off -= 4;
+ }
- if(len > 2)
- {
- /*First 4 bytes + paded bytes will be header next len bytes would be payload*/
- for(i = 0; i < len; i++)
- {
- dp = *rp;
- dp[i] = dp[4 + res + i];
- }
- }
+ if (len > 2) {
+ /*First 4 bytes + paded bytes will be header next len bytes would be payload */
+ for (i = 0; i < len; i++) {
+ dp = *rp;
+ dp[i] = dp[4 + res + i];
+ }
+ }
- return len;
+ return len;
}
static int mipi_dsi_cmd_bta_sw_trigger(void)
{
- uint32_t data;
- int cnt = 0;
- int err = 0;
+ uint32_t data;
+ int cnt = 0;
+ int err = 0;
- writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
- while (cnt < 10000) {
- data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS*/
- if ((data & 0x0010) == 0)
- break;
- cnt++;
- }
- if(cnt == 10000)
- err = 1;
- return err;
+ writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
+ while (cnt < 10000) {
+ data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */
+ if ((data & 0x0010) == 0)
+ break;
+ cnt++;
+ }
+ if (cnt == 10000)
+ err = 1;
+ return err;
}
static uint32_t mipi_novatek_manufacture_id(void)
{
- char rec_buf[24];
- char *rp = rec_buf;
- uint32_t *lp, data;
+ char rec_buf[24];
+ char *rp = rec_buf;
+ uint32_t *lp, data;
- mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1);
- mipi_dsi_cmds_rx(&rp, 3);
+ mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1);
+ mipi_dsi_cmds_rx(&rp, 3);
- lp = (uint32_t *)rp;
- data = (uint32_t)*lp;
- data = ntohl(data);
- data = data >> 8;
- return data;
+ lp = (uint32_t *) rp;
+ data = (uint32_t) * lp;
+ data = ntohl(data);
+ data = data >> 8;
+ return data;
}
int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
{
- unsigned char DMA_STREAM1 = 0; // for mdp display processor path
- unsigned char EMBED_MODE1 = 1; // from frame buffer
- unsigned char POWER_MODE2 = 1; // from frame buffer
- unsigned char PACK_TYPE1 = 1; // long packet
- unsigned char VC1 = 0;
- unsigned char DT1 = 0; // non embedded mode
- unsigned short WC1 = 0; // for non embedded mode only
- int status = 0;
- unsigned char DLNx_EN;
+ unsigned char DMA_STREAM1 = 0; // for mdp display processor path
+ unsigned char EMBED_MODE1 = 1; // from frame buffer
+ unsigned char POWER_MODE2 = 1; // from frame buffer
+ unsigned char PACK_TYPE1 = 1; // long packet
+ unsigned char VC1 = 0;
+ unsigned char DT1 = 0; // non embedded mode
+ unsigned short WC1 = 0; // for non embedded mode only
+ int status = 0;
+ unsigned char DLNx_EN;
- switch (pinfo->num_of_lanes) {
- default:
- case 1:
- DLNx_EN = 1; // 1 lane
- break;
- case 2:
- DLNx_EN = 3; // 2 lane
- break;
- case 3:
- DLNx_EN = 7; // 3 lane
- break;
- }
+ switch (pinfo->num_of_lanes) {
+ default:
+ case 1:
+ DLNx_EN = 1; // 1 lane
+ break;
+ case 2:
+ DLNx_EN = 3; // 2 lane
+ break;
+ case 3:
+ DLNx_EN = 7; // 3 lane
+ break;
+ }
- writel(0x0001, DSI_SOFT_RESET);
- writel(0x0000, DSI_SOFT_RESET);
+ writel(0x0001, DSI_SOFT_RESET);
+ writel(0x0000, DSI_SOFT_RESET);
- writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
+ writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
+ writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
+ // trigger 0x4; dma stream1
- writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
- // build
- writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
- | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- DSI_COMMAND_MODE_DMA_CTRL);
+ writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
+ // build
+ writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
+ | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
+ DSI_COMMAND_MODE_DMA_CTRL);
- status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds);
+ status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds);
- return status;
+ return status;
}
//TODO: Clean up arguments being passed in not being used
-int config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height,
- unsigned short img_width, unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width, unsigned short dst_format,
- unsigned short traffic_mode,
- unsigned short datalane_num)
+int
+config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height,
+ unsigned short img_width, unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width, unsigned short dst_format,
+ unsigned short traffic_mode, unsigned short datalane_num)
{
- unsigned char DST_FORMAT;
- unsigned char TRAFIC_MODE;
- unsigned char DLNx_EN;
- // video mode data ctrl
- int status = 0;
- unsigned long low_pwr_stop_mode = 0;
- unsigned char eof_bllp_pwr = 0x9;
- unsigned char interleav = 0;
+ unsigned char DST_FORMAT;
+ unsigned char TRAFIC_MODE;
+ unsigned char DLNx_EN;
+ // video mode data ctrl
+ int status = 0;
+ unsigned long low_pwr_stop_mode = 0;
+ unsigned char eof_bllp_pwr = 0x9;
+ unsigned char interleav = 0;
- // disable mdp first
- mdp_disable();
+ // disable mdp first
+ mdp_disable();
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000002, DSI_CLK_CTRL);
- writel(0x00000006, DSI_CLK_CTRL);
- writel(0x0000000e, DSI_CLK_CTRL);
- writel(0x0000001e, DSI_CLK_CTRL);
- writel(0x0000003e, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000002, DSI_CLK_CTRL);
+ writel(0x00000006, DSI_CLK_CTRL);
+ writel(0x0000000e, DSI_CLK_CTRL);
+ writel(0x0000001e, DSI_CLK_CTRL);
+ writel(0x0000003e, DSI_CLK_CTRL);
- writel(0, DSI_CTRL);
+ writel(0, DSI_CTRL);
- writel(0, DSI_ERR_INT_MASK0);
+ writel(0, DSI_ERR_INT_MASK0);
- DST_FORMAT = 0; // RGB565
- dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n");
+ DST_FORMAT = 0; // RGB565
+ dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n");
- DLNx_EN = 1; // 1 lane with clk programming
- dprintf(SPEW, "Data Lane: 1 lane\n");
+ DLNx_EN = 1; // 1 lane with clk programming
+ dprintf(SPEW, "Data Lane: 1 lane\n");
- TRAFIC_MODE = 0; // non burst mode with sync pulses
- dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
+ TRAFIC_MODE = 0; // non burst mode with sync pulses
+ dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
- writel(0x02020202, DSI_INT_CTRL);
+ writel(0x02020202, DSI_INT_CTRL);
- writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
- DSI_VIDEO_MODE_ACTIVE_H);
+ writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
+ DSI_VIDEO_MODE_ACTIVE_H);
- writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
- DSI_VIDEO_MODE_ACTIVE_V);
+ writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
+ DSI_VIDEO_MODE_ACTIVE_V);
- writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16)
- | img_width + hsync_porch0_fp + hsync_porch0_bp,
- DSI_VIDEO_MODE_TOTAL);
+ writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16)
+ | img_width + hsync_porch0_fp + hsync_porch0_bp,
+ DSI_VIDEO_MODE_TOTAL);
- writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
+ writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
- writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
+ writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
- writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
+ writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
- writel(1, DSI_EOT_PACKET_CTRL);
+ writel(1, DSI_EOT_PACKET_CTRL);
- writel(0x00000100, DSI_MISR_VIDEO_CTRL);
+ writel(0x00000100, DSI_MISR_VIDEO_CTRL);
- writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8
- | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
+ writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8
+ | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
- writel(0x67, DSI_CAL_STRENGTH_CTRL);
+ writel(0x67, DSI_CAL_STRENGTH_CTRL);
- writel(0x80006711, DSI_CAL_CTRL);
+ writel(0x80006711, DSI_CAL_CTRL);
- writel(0x00010100, DSI_MISR_VIDEO_CTRL);
+ writel(0x00010100, DSI_MISR_VIDEO_CTRL);
- writel(0x00010100, DSI_INT_CTRL);
- writel(0x02010202, DSI_INT_CTRL);
+ writel(0x00010100, DSI_INT_CTRL);
+ writel(0x02010202, DSI_INT_CTRL);
- writel(0x02030303, DSI_INT_CTRL);
+ writel(0x02030303, DSI_INT_CTRL);
- writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4
- | 0x103, DSI_CTRL);
- mdelay(10);
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4
+ | 0x103, DSI_CTRL);
+ mdelay(10);
- return status;
+ return status;
}
-int config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height,
- unsigned short img_width, unsigned short img_height,
- unsigned short dst_format,
- unsigned short traffic_mode,
- unsigned short datalane_num)
+int
+config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height,
+ unsigned short img_width, unsigned short img_height,
+ unsigned short dst_format,
+ unsigned short traffic_mode, unsigned short datalane_num)
{
- unsigned char DST_FORMAT;
- unsigned char TRAFIC_MODE;
- unsigned char DLNx_EN;
- // video mode data ctrl
- int status = 0;
+ unsigned char DST_FORMAT;
+ unsigned char TRAFIC_MODE;
+ unsigned char DLNx_EN;
+ // video mode data ctrl
+ int status = 0;
unsigned char interleav = 0;
unsigned char ystride = 0x03;
- // disable mdp first
+ // disable mdp first
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000002, DSI_CLK_CTRL);
- writel(0x00000006, DSI_CLK_CTRL);
- writel(0x0000000e, DSI_CLK_CTRL);
- writel(0x0000001e, DSI_CLK_CTRL);
- writel(0x0000003e, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000002, DSI_CLK_CTRL);
+ writel(0x00000006, DSI_CLK_CTRL);
+ writel(0x0000000e, DSI_CLK_CTRL);
+ writel(0x0000001e, DSI_CLK_CTRL);
+ writel(0x0000003e, DSI_CLK_CTRL);
- writel(0x10000000, DSI_ERR_INT_MASK0);
+ writel(0x10000000, DSI_ERR_INT_MASK0);
- // writel(0, DSI_CTRL);
+ // writel(0, DSI_CTRL);
- // writel(0, DSI_ERR_INT_MASK0);
+ // writel(0, DSI_ERR_INT_MASK0);
- DST_FORMAT = 8; // RGB888
- dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
+ DST_FORMAT = 8; // RGB888
+ dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
- DLNx_EN = 3; // 2 lane with clk programming
- dprintf(SPEW, "Data Lane: 2 lane\n");
+ DLNx_EN = 3; // 2 lane with clk programming
+ dprintf(SPEW, "Data Lane: 2 lane\n");
- TRAFIC_MODE = 0; // non burst mode with sync pulses
- dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
+ TRAFIC_MODE = 0; // non burst mode with sync pulses
+ dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
- writel(0x02020202, DSI_INT_CTRL);
+ writel(0x02020202, DSI_INT_CTRL);
- writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
- writel((img_width * ystride + 1) << 16 | 0x0039,
- DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
- writel((img_width * ystride + 1) << 16 | 0x0039,
- DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
- writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
- writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
- writel(0xEE, DSI_CAL_STRENGTH_CTRL);
- writel(0x80000000, DSI_CAL_CTRL);
- writel(0x40, DSI_TRIG_CTRL);
- writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
- writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
- DSI_CTRL);
- mdelay(10);
- writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
- writel(0x10000000, DSI_MISR_CMD_CTRL);
- writel(0x00000040, DSI_ERR_INT_MASK0);
- writel(0x1, DSI_EOT_PACKET_CTRL);
- // writel(0x0, MDP_OVERLAYPROC0_START);
- mdp_start_dma();
- mdelay(10);
- writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
+ writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
+ writel((img_width * ystride + 1) << 16 | 0x0039,
+ DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
+ writel((img_width * ystride + 1) << 16 | 0x0039,
+ DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
+ writel(img_height << 16 | img_width,
+ DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
+ writel(img_height << 16 | img_width,
+ DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
+ writel(0xEE, DSI_CAL_STRENGTH_CTRL);
+ writel(0x80000000, DSI_CAL_CTRL);
+ writel(0x40, DSI_TRIG_CTRL);
+ writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
+ DSI_CTRL);
+ mdelay(10);
+ writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
+ writel(0x10000000, DSI_MISR_CMD_CTRL);
+ writel(0x00000040, DSI_ERR_INT_MASK0);
+ writel(0x1, DSI_EOT_PACKET_CTRL);
+ // writel(0x0, MDP_OVERLAYPROC0_START);
+ mdp_start_dma();
+ mdelay(10);
+ writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
- status = 1;
- return status;
+ status = 1;
+ return status;
}
int mipi_dsi_video_config(unsigned short num_of_lanes)
{
- int status = 0;
- unsigned long ReadValue;
- unsigned long count = 0;
- unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from
- // bit16, high spd mode 0x0
- unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or
- // let cmd mode eng send packets in hs
- // or lp mode
- unsigned short image_wd = mipi_fb_cfg.width;
- unsigned short image_ht = mipi_fb_cfg.height;
+ int status = 0;
+ unsigned long ReadValue;
+ unsigned long count = 0;
+ unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from
+ // bit16, high spd mode 0x0
+ unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or
+ // let cmd mode eng send packets in hs
+ // or lp mode
+ unsigned short image_wd = mipi_fb_cfg.width;
+ unsigned short image_ht = mipi_fb_cfg.height;
#if !DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
- unsigned short display_wd = mipi_fb_cfg.width;
- unsigned short display_ht = mipi_fb_cfg.height;
- unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
- unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
- unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
- unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
- unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
- unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
- unsigned short dst_format = 0;
- unsigned short traffic_mode = 0;
+ unsigned short display_wd = mipi_fb_cfg.width;
+ unsigned short display_ht = mipi_fb_cfg.height;
+ unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
+ unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
+ unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
+ unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
+ unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
+ unsigned short dst_format = 0;
+ unsigned short traffic_mode = 0;
#endif
- unsigned short pack_pattern = 0x12; //BGR
- unsigned char ystride = 3;
+ unsigned short pack_pattern = 0x12; //BGR
+ unsigned char ystride = 3;
- low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA,
- // bit24:HFP, bit28:PULSE MODE, need enough
- // time for swithc from LP to HS
- eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send
- // packets in hs or lp mode
+ low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA,
+ // bit24:HFP, bit28:PULSE MODE, need enough
+ // time for swithc from LP to HS
+ eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send
+ // packets in hs or lp mode
#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
- pack_pattern = 0x21; //RGB
- config_mdt61_dsi_video_mode();
+ pack_pattern = 0x21; //RGB
+ config_mdt61_dsi_video_mode();
- /* Two functions make up mdp_setup_dma_p_video_mode with mdt61 panel functions*/
- mdp_setup_dma_p_video_config(pack_pattern, image_wd, image_ht, MIPI_FB_ADDR, image_wd, ystride);
- mdp_setup_mdt61_video_dsi_config();
+ /* Two functions make up mdp_setup_dma_p_video_mode with mdt61 panel functions */
+ mdp_setup_dma_p_video_config(pack_pattern, image_wd, image_ht,
+ MIPI_FB_ADDR, image_wd, ystride);
+ mdp_setup_mdt61_video_dsi_config();
#elif DISPLAY_MIPI_PANEL_RENESAS
- if(machine_is_7x25a()) {
- display_wd = REN_MIPI_FB_WIDTH_HVGA;
- display_ht = REN_MIPI_FB_HEIGHT_HVGA;
- image_wd = REN_MIPI_FB_WIDTH_HVGA;
- image_ht = REN_MIPI_FB_HEIGHT_HVGA;
- hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA;
- hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA;
- vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA;
- vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES_HVGA;
- hsync_width = MIPI_HSYNC_PULSE_WIDTH_HVGA;
- vsync_width = MIPI_VSYNC_PULSE_WIDTH_HVGA;
- }
+ if (machine_is_7x25a()) {
+ display_wd = REN_MIPI_FB_WIDTH_HVGA;
+ display_ht = REN_MIPI_FB_HEIGHT_HVGA;
+ image_wd = REN_MIPI_FB_WIDTH_HVGA;
+ image_ht = REN_MIPI_FB_HEIGHT_HVGA;
+ hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA;
+ hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA;
+ vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA;
+ vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES_HVGA;
+ hsync_width = MIPI_HSYNC_PULSE_WIDTH_HVGA;
+ vsync_width = MIPI_VSYNC_PULSE_WIDTH_HVGA;
+ }
- pack_pattern = 0x21; //RGB
- config_renesas_dsi_video_mode();
+ pack_pattern = 0x21; //RGB
+ config_renesas_dsi_video_mode();
- status +=
- mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, image_ht,
- hsync_porch_fp, hsync_porch_bp,
- vsync_porch_fp, vsync_porch_bp, hsync_width,
- vsync_width, MIPI_FB_ADDR, image_wd,
- pack_pattern, ystride);
+ status +=
+ mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd,
+ image_ht, hsync_porch_fp, hsync_porch_bp,
+ vsync_porch_fp, vsync_porch_bp,
+ hsync_width, vsync_width, MIPI_FB_ADDR,
+ image_wd, pack_pattern, ystride);
#else
- status += config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht,
- hsync_porch_fp, hsync_porch_bp,
- vsync_porch_fp, vsync_porch_bp, hsync_width,
- vsync_width, dst_format, traffic_mode,
- num_of_lanes);
+ status +=
+ config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht,
+ hsync_porch_fp, hsync_porch_bp,
+ vsync_porch_fp, vsync_porch_bp, hsync_width,
+ vsync_width, dst_format, traffic_mode,
+ num_of_lanes);
- status +=
- mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, image_ht,
- hsync_porch_fp, hsync_porch_bp,
- vsync_porch_fp, vsync_porch_bp, hsync_width,
- vsync_width, MIPI_FB_ADDR, image_wd,
- pack_pattern, ystride);
+ status +=
+ mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd,
+ image_ht, hsync_porch_fp, hsync_porch_bp,
+ vsync_porch_fp, vsync_porch_bp,
+ hsync_width, vsync_width, MIPI_FB_ADDR,
+ image_wd, pack_pattern, ystride);
#endif
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
- while (ReadValue != 0x00010000) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
- count++;
- if (count > 0xffff) {
- status = FAIL;
- dprintf(CRITICAL, "Video lane test failed\n");
- return status;
- }
- }
+ ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
+ while (ReadValue != 0x00010000) {
+ ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
+ count++;
+ if (count > 0xffff) {
+ status = FAIL;
+ dprintf(CRITICAL, "Video lane test failed\n");
+ return status;
+ }
+ }
- dprintf(SPEW, "Video lane tested successfully\n");
- return status;
+ dprintf(SPEW, "Video lane tested successfully\n");
+ return status;
}
int is_cmd_mode_enabled(void)
{
- return cmd_mode_status;
+ return cmd_mode_status;
}
#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
void mipi_dsi_cmd_mode_trigger(void)
{
- int status = 0;
- unsigned short display_wd = mipi_fb_cfg.width;
- unsigned short display_ht = mipi_fb_cfg.height;
- unsigned short image_wd = mipi_fb_cfg.width;
- unsigned short image_ht = mipi_fb_cfg.height;
- unsigned short dst_format = 0;
- unsigned short traffic_mode = 0;
- struct mipi_dsi_panel_config *panel_info = &novatek_panel_info;
- status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes);
- mdelay(50);
- config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht,
- dst_format, traffic_mode,
- panel_info->num_of_lanes /* num_of_lanes */ );
+ int status = 0;
+ unsigned short display_wd = mipi_fb_cfg.width;
+ unsigned short display_ht = mipi_fb_cfg.height;
+ unsigned short image_wd = mipi_fb_cfg.width;
+ unsigned short image_ht = mipi_fb_cfg.height;
+ unsigned short dst_format = 0;
+ unsigned short traffic_mode = 0;
+ struct mipi_dsi_panel_config *panel_info = &novatek_panel_info;
+ status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes);
+ mdelay(50);
+ config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht,
+ dst_format, traffic_mode,
+ panel_info->num_of_lanes /* num_of_lanes */ );
}
#endif
void mipi_dsi_shutdown(void)
{
- mdp_shutdown();
- writel(0x01010101, DSI_INT_CTRL);
- writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
+ mdp_shutdown();
+ writel(0x01010101, DSI_INT_CTRL);
+ writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
- /* Disable branch clocks */
- writel(0x0, BYTE_CC_REG);
- writel(0x0, PIXEL_CC_REG);
- writel(0x0, ESC_CC_REG);
- /* Disable root clock */
- writel(0x0, DSI_CC_REG);
+ /* Disable branch clocks */
+ writel(0x0, BYTE_CC_REG);
+ writel(0x0, PIXEL_CC_REG);
+ writel(0x0, ESC_CC_REG);
+ /* Disable root clock */
+ writel(0x0, DSI_CC_REG);
#elif (!DISPLAY_MIPI_PANEL_RENESAS)
- secure_writel(0x0, DSI_CC_REG);
- secure_writel(0x0, PIXEL_CC_REG);
+ secure_writel(0x0, DSI_CC_REG);
+ secure_writel(0x0, PIXEL_CC_REG);
#endif
- writel(0, DSI_CLK_CTRL);
- writel(0, DSI_CTRL);
- writel(0, DSIPHY_PLL_CTRL(0));
+ writel(0, DSI_CLK_CTRL);
+ writel(0, DSI_CTRL);
+ writel(0, DSIPHY_PLL_CTRL(0));
}
struct fbcon_config *mipi_init(void)
{
- int status = 0;
- struct mipi_dsi_panel_config *panel_info = get_panel_info();
- /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
+ int status = 0;
+ struct mipi_dsi_panel_config *panel_info = get_panel_info();
+ /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
#if (!DISPLAY_MIPI_PANEL_RENESAS)
- writel(0x00001800, MMSS_SFPB_GPREG);
+ writel(0x00001800, MMSS_SFPB_GPREG);
#endif
#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
- mipi_dsi_phy_init(panel_info);
+ mipi_dsi_phy_init(panel_info);
#else
- mipi_dsi_phy_ctrl_config(panel_info);
+ mipi_dsi_phy_ctrl_config(panel_info);
#endif
- status += mipi_dsi_panel_initialize(panel_info);
+ status += mipi_dsi_panel_initialize(panel_info);
#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
- mipi_dsi_cmd_bta_sw_trigger();
- mipi_novatek_manufacture_id();
+ mipi_dsi_cmd_bta_sw_trigger();
+ mipi_novatek_manufacture_id();
#endif
- mipi_fb_cfg.base = MIPI_FB_ADDR;
+ mipi_fb_cfg.base = MIPI_FB_ADDR;
- if (panel_info->mode == MIPI_VIDEO_MODE)
- status += mipi_dsi_video_config(panel_info->num_of_lanes);
+ if (panel_info->mode == MIPI_VIDEO_MODE)
+ status += mipi_dsi_video_config(panel_info->num_of_lanes);
- if (panel_info->mode == MIPI_CMD_MODE)
- cmd_mode_status = 1;
+ if (panel_info->mode == MIPI_CMD_MODE)
+ cmd_mode_status = 1;
- return &mipi_fb_cfg;
+ return &mipi_fb_cfg;
}
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 3e10002..b1fc977 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -1,2957 +1,2832 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <string.h>
-#include <stdlib.h>
-#include <debug.h>
-#include <reg.h>
-#include "mmc.h"
-#include <partition_parser.h>
-#include <platform/iomap.h>
-#include <platform/timer.h>
-
-#if MMC_BOOT_ADM
-#include "adm.h"
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define MMC_BOOT_DATA_READ 0
-#define MMC_BOOT_DATA_WRITE 1
-
-
-static unsigned int mmc_boot_fifo_data_transfer(unsigned int* data_ptr,
- unsigned int data_len,
- unsigned char direction);
-
-static unsigned int mmc_boot_fifo_read(unsigned int* data_ptr,
- unsigned int data_len);
-
-static unsigned int mmc_boot_fifo_write(unsigned int* data_ptr,
- unsigned int data_len);
-
-#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
-
-/* data access time unit in ns */
-static const unsigned int taac_unit[] =
-{ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 };
-/* data access time value x 10 */
-static const unsigned int taac_value[] =
-{ 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
-
-/* data transfer rate in kbit/s */
-static const unsigned int xfer_rate_unit[] =
-{ 100, 1000, 10000, 100000, 0, 0, 0, 0 };
-/* data transfer rate value x 10*/
-static const unsigned int xfer_rate_value[] =
-{ 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 };
-
-
-unsigned char mmc_slot = 0;
-unsigned int mmc_boot_mci_base = 0;
-
-static unsigned char ext_csd_buf[512];
-static unsigned char wp_status_buf[8];
-
-int mmc_clock_enable_disable(unsigned id, unsigned enable);
-int mmc_clock_get_rate(unsigned id);
-int mmc_clock_set_rate(unsigned id, unsigned rate);
-
-struct mmc_boot_host mmc_host;
-struct mmc_boot_card mmc_card;
-
-static unsigned int mmc_wp(unsigned int addr, unsigned int size,
- unsigned char set_clear_wp);
-static unsigned int mmc_boot_send_ext_cmd (struct mmc_boot_card* card,
- unsigned char* buf);
-static unsigned int mmc_boot_read_reg(struct mmc_boot_card *card,
- unsigned int data_len,
- unsigned int command, unsigned int addr,
- unsigned int *out);
-
-unsigned int SWAP_ENDIAN(unsigned int val)
-{
- return ((val & 0xFF) << 24) |
- (((val >> 8) & 0xFF) << 16) |
- (((val >> 16) & 0xFF) << 8) |
- (val >> 24);
-}
-
-
-/* Sets a timeout for read operation.
- */
-static unsigned int mmc_boot_set_read_timeout( struct mmc_boot_host* host,
- struct mmc_boot_card* card )
-{
- unsigned int timeout_ns = 0;
-
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- if( (card->type == MMC_BOOT_TYPE_MMCHC) || (card->type == MMC_BOOT_TYPE_SDHC) )
- {
- card->rd_timeout_ns = 100000000;
- }
- else if( (card->type == MMC_BOOT_TYPE_STD_SD) || (card->type == MMC_BOOT_TYPE_STD_MMC) )
- {
- timeout_ns = 10 * ( (card->csd.taac_ns ) +
- ( card->csd.nsac_clk_cycle / (host->mclk_rate/1000000000)));
- card->rd_timeout_ns = timeout_ns;
- }
- else
- {
- return MMC_BOOT_E_NOT_SUPPORTED;
- }
-
- dprintf(SPEW, " Read timeout set: %d ns\n", card->rd_timeout_ns );
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/* Sets a timeout for write operation.
- */
-static unsigned int mmc_boot_set_write_timeout( struct mmc_boot_host* host,
- struct mmc_boot_card* card )
-{
- unsigned int timeout_ns = 0;
-
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- if( (card->type == MMC_BOOT_TYPE_MMCHC) || (card->type == MMC_BOOT_TYPE_SDHC) )
- {
- card->wr_timeout_ns = 100000000;
- }
- else if( card->type == MMC_BOOT_TYPE_STD_SD || (card->type == MMC_BOOT_TYPE_STD_MMC) )
- {
- timeout_ns = 10 * ( ( card->csd.taac_ns ) +
- ( card->csd.nsac_clk_cycle / ( host->mclk_rate/1000000000 ) ) );
- timeout_ns = timeout_ns << card->csd.r2w_factor;
- card->wr_timeout_ns = timeout_ns;
- }
- else
- {
- return MMC_BOOT_E_NOT_SUPPORTED;
- }
-
- dprintf(SPEW, " Write timeout set: %d ns\n", card->wr_timeout_ns );
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-
-/*
- * Decodes CSD response received from the card. Note that we have defined only
- * few of the CSD elements in csd structure. We'll only decode those values.
- */
-static unsigned int mmc_boot_decode_and_save_csd( struct mmc_boot_card* card,
- unsigned int* raw_csd )
-{
- unsigned int mmc_sizeof = 0;
- unsigned int mmc_unit = 0;
- unsigned int mmc_value = 0;
- unsigned int mmc_temp = 0;
-
- struct mmc_boot_csd mmc_csd;
-
- if( ( card == NULL ) || ( raw_csd == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- mmc_sizeof = sizeof(unsigned int) * 8;
-
- mmc_csd.cmmc_structure = UNPACK_BITS( raw_csd, 126, 2, mmc_sizeof );
-
- if( (card->type == MMC_BOOT_TYPE_SDHC) || (card->type == MMC_BOOT_TYPE_STD_SD))
- {
- /* Parse CSD according to SD card spec. */
-
- /* CSD register is little bit differnet for CSD version 2.0 High Capacity
- * and CSD version 1.0/2.0 Standard memory cards. In Version 2.0 some of
- * the fields have fixed values and it's not necessary for host to refer
- * these fields in CSD sent by card */
-
- if( mmc_csd.cmmc_structure == 1)
- {
- /* CSD Version 2.0 */
- mmc_csd.card_cmd_class = UNPACK_BITS( raw_csd, 84, 12, mmc_sizeof );
- mmc_csd.write_blk_len = 512; /* Fixed value is 9 = 2^9 = 512 */
- mmc_csd.read_blk_len = 512; /* Fixed value is 9 = 512 */
- mmc_csd.r2w_factor = 0x2; /* Fixed value: 010b */
- mmc_csd.c_size_mult = 0; /* not there in version 2.0 */
- mmc_csd.c_size = UNPACK_BITS( raw_csd, 48, 22, mmc_sizeof );
- mmc_csd.nsac_clk_cycle = UNPACK_BITS( raw_csd, 104, 8, mmc_sizeof) * 100;
-
-//TODO: Investigate the nsac and taac. Spec suggests not using this for timeouts.
-
- mmc_unit = UNPACK_BITS( raw_csd, 112, 3, mmc_sizeof );
- mmc_value = UNPACK_BITS( raw_csd, 115, 4, mmc_sizeof );
- mmc_csd.taac_ns = ( taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
-
- mmc_csd.erase_blk_len = 1;
- mmc_csd.read_blk_misalign = 0;
- mmc_csd.write_blk_misalign = 0;
- mmc_csd.read_blk_partial = 0;
- mmc_csd.write_blk_partial = 0;
-
- mmc_unit = UNPACK_BITS( raw_csd, 96, 3, mmc_sizeof );
- mmc_value = UNPACK_BITS( raw_csd, 99, 4, mmc_sizeof );
- mmc_csd.tran_speed = ( xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10;
-
- mmc_csd.wp_grp_size = 0x0;
- mmc_csd.wp_grp_enable = 0x0;
- mmc_csd.perm_wp = UNPACK_BITS( raw_csd, 13, 1, mmc_sizeof );
- mmc_csd.temp_wp = UNPACK_BITS( raw_csd, 12, 1, mmc_sizeof );
-
- /* Calculate the card capcity */
- card->capacity = ( 1 + mmc_csd.c_size ) * 512 * 1024;
- }
- else
- {
- /* CSD Version 1.0 */
- mmc_csd.card_cmd_class = UNPACK_BITS( raw_csd, 84, 12, mmc_sizeof );
-
- mmc_temp = UNPACK_BITS( raw_csd, 22, 4, mmc_sizeof );
- mmc_csd.write_blk_len = ( mmc_temp > 8 && mmc_temp < 12 )? ( 1 << mmc_temp ) : 512;
-
- mmc_temp = UNPACK_BITS( raw_csd, 80, 4, mmc_sizeof );
- mmc_csd.read_blk_len = ( mmc_temp > 8 && mmc_temp < 12 )? ( 1 << mmc_temp ) : 512;
-
- mmc_unit = UNPACK_BITS( raw_csd, 112, 3, mmc_sizeof );
- mmc_value = UNPACK_BITS( raw_csd, 115, 4, mmc_sizeof );
- mmc_csd.taac_ns = ( taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
-
- mmc_unit = UNPACK_BITS( raw_csd, 96, 3, mmc_sizeof );
- mmc_value = UNPACK_BITS( raw_csd, 99, 4, mmc_sizeof );
- mmc_csd.tran_speed = ( xfer_rate_value[mmc_value] * xfer_rate_unit[mmc_unit]) / 10;
-
- mmc_csd.nsac_clk_cycle = UNPACK_BITS( raw_csd, 104, 8, mmc_sizeof ) * 100;
-
- mmc_csd.r2w_factor = UNPACK_BITS( raw_csd, 26, 3, mmc_sizeof );
- mmc_csd.sector_size = UNPACK_BITS( raw_csd, 39, 7, mmc_sizeof ) + 1;
-
- mmc_csd.erase_blk_len = UNPACK_BITS( raw_csd, 46, 1, mmc_sizeof );
- mmc_csd.read_blk_misalign = UNPACK_BITS( raw_csd, 77, 1, mmc_sizeof );
- mmc_csd.write_blk_misalign = UNPACK_BITS( raw_csd, 78, 1, mmc_sizeof );
- mmc_csd.read_blk_partial = UNPACK_BITS( raw_csd, 79, 1, mmc_sizeof );
- mmc_csd.write_blk_partial = UNPACK_BITS( raw_csd, 21, 1, mmc_sizeof );
-
- mmc_csd.c_size_mult = UNPACK_BITS( raw_csd, 47, 3, mmc_sizeof );
- mmc_csd.c_size = UNPACK_BITS( raw_csd, 62, 12, mmc_sizeof );
- mmc_csd.wp_grp_size = UNPACK_BITS( raw_csd, 32, 7, mmc_sizeof );
- mmc_csd.wp_grp_enable = UNPACK_BITS( raw_csd, 31, 1, mmc_sizeof );
- mmc_csd.perm_wp = UNPACK_BITS( raw_csd, 13, 1, mmc_sizeof );
- mmc_csd.temp_wp = UNPACK_BITS( raw_csd, 12, 1, mmc_sizeof );
-
- /* Calculate the card capacity */
- mmc_temp = ( 1 << ( mmc_csd.c_size_mult + 2 ) ) * ( mmc_csd.c_size + 1 );
- card->capacity = mmc_temp * mmc_csd.read_blk_len;
- }
- }
- else
- {
- /* Parse CSD according to MMC card spec. */
- mmc_csd.spec_vers = UNPACK_BITS( raw_csd, 122, 4, mmc_sizeof );
- mmc_csd.card_cmd_class = UNPACK_BITS( raw_csd, 84, 12, mmc_sizeof );
- mmc_csd.write_blk_len = 1 << UNPACK_BITS( raw_csd, 22, 4, mmc_sizeof );
- mmc_csd.read_blk_len = 1 << UNPACK_BITS( raw_csd, 80, 4, mmc_sizeof );
- mmc_csd.r2w_factor = UNPACK_BITS( raw_csd, 26, 3, mmc_sizeof );
- mmc_csd.c_size_mult = UNPACK_BITS( raw_csd, 47, 3, mmc_sizeof );
- mmc_csd.c_size = UNPACK_BITS( raw_csd, 62, 12, mmc_sizeof );
- mmc_csd.nsac_clk_cycle = UNPACK_BITS( raw_csd, 104, 8, mmc_sizeof) * 100;
-
- mmc_unit = UNPACK_BITS( raw_csd, 112, 3, mmc_sizeof );
- mmc_value = UNPACK_BITS( raw_csd, 115, 4, mmc_sizeof );
- mmc_csd.taac_ns = ( taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
-
- mmc_csd.read_blk_misalign = UNPACK_BITS( raw_csd, 77, 1, mmc_sizeof );
- mmc_csd.write_blk_misalign = UNPACK_BITS( raw_csd, 78, 1, mmc_sizeof );
- mmc_csd.read_blk_partial = UNPACK_BITS( raw_csd, 79, 1, mmc_sizeof );
- mmc_csd.write_blk_partial = UNPACK_BITS( raw_csd, 21, 1, mmc_sizeof );
- mmc_csd.tran_speed = 0x00; /* Ignore -- no use of this value. */
-
- mmc_csd.erase_grp_size = UNPACK_BITS( raw_csd, 42, 5, mmc_sizeof );
- mmc_csd.erase_grp_mult = UNPACK_BITS( raw_csd, 37, 5, mmc_sizeof );
- mmc_csd.wp_grp_size = UNPACK_BITS( raw_csd, 32, 5, mmc_sizeof );
- mmc_csd.wp_grp_enable = UNPACK_BITS( raw_csd, 31, 1, mmc_sizeof );
- mmc_csd.perm_wp = UNPACK_BITS( raw_csd, 13, 1, mmc_sizeof );
- mmc_csd.temp_wp = UNPACK_BITS( raw_csd, 12, 1, mmc_sizeof );
-
- /* Calculate the card capcity */
- if(mmc_csd.c_size != 0xFFF)
- {
- /* For cards less than or equal to 2GB */
- mmc_temp = ( 1 << ( mmc_csd.c_size_mult + 2 ) ) * ( mmc_csd.c_size + 1 );
- card->capacity = mmc_temp * mmc_csd.read_blk_len;
- }
- else
- {
- /* For cards greater than 2GB, Ext CSD register's SEC_COUNT
- * is used to calculate the size.
- */
- unsigned long long sec_count;
-
- sec_count = (ext_csd_buf[215] << 24) |
- (ext_csd_buf[214] << 16) |
- (ext_csd_buf[213] << 8) |
- ext_csd_buf[212];
-
- card->capacity = sec_count * 512;
- }
- }
-
-
- /* save the information in card structure */
- memcpy( (struct mmc_boot_csd *)&card->csd, (struct mmc_boot_csd *)&mmc_csd,
- sizeof(struct mmc_boot_csd) );
-
- dprintf(SPEW, "Decoded CSD fields:\n" );
- dprintf(SPEW, "cmmc_structure: %d\n", mmc_csd.cmmc_structure );
- dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class );
- dprintf(SPEW, "write_blk_len: %d\n", mmc_csd.write_blk_len );
- dprintf(SPEW, "read_blk_len: %d\n", mmc_csd.read_blk_len );
- dprintf(SPEW, "r2w_factor: %d\n", mmc_csd.r2w_factor );
- dprintf(SPEW, "sector_size: %d\n", mmc_csd.sector_size );
- dprintf(SPEW, "c_size_mult:%d\n", mmc_csd.c_size_mult );
- dprintf(SPEW, "c_size: %d\n", mmc_csd.c_size );
- dprintf(SPEW, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle );
- dprintf(SPEW, "taac_ns: %d\n", mmc_csd.taac_ns );
- dprintf(SPEW, "tran_speed: %d kbps\n", mmc_csd.tran_speed );
- dprintf(SPEW, "erase_blk_len: %d\n", mmc_csd.erase_blk_len );
- dprintf(SPEW, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign );
- dprintf(SPEW, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign );
- dprintf(SPEW, "read_blk_partial: %d\n", mmc_csd.read_blk_partial );
- dprintf(SPEW, "write_blk_partial: %d\n", mmc_csd.write_blk_partial );
- dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity );
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Decode CID sent by the card.
- */
-static unsigned int mmc_boot_decode_and_save_cid( struct mmc_boot_card* card,
- unsigned int* raw_cid )
-{
- struct mmc_boot_cid mmc_cid;
- unsigned int mmc_sizeof = 0;
- int i = 0;
-
- if( ( card == NULL ) || ( raw_cid == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- mmc_sizeof = sizeof( unsigned int ) * 8;
-
- if( (card->type == MMC_BOOT_TYPE_SDHC) || (card->type == MMC_BOOT_TYPE_STD_SD))
- {
- mmc_cid.mid = UNPACK_BITS( raw_cid, 120, 8, mmc_sizeof );
- mmc_cid.oid = UNPACK_BITS( raw_cid, 104, 16, mmc_sizeof );
-
- for( i = 0; i < 5; i++ )
- {
- mmc_cid.pnm[i] = (unsigned char) UNPACK_BITS(raw_cid, \
- (104 - 8 * (i+1)), 8, mmc_sizeof );
- }
- mmc_cid.pnm[5] = 0;
- mmc_cid.pnm[6] = 0;
-
- mmc_cid.prv = UNPACK_BITS( raw_cid, 56, 8, mmc_sizeof );
- mmc_cid.psn = UNPACK_BITS( raw_cid, 24, 32, mmc_sizeof );
- mmc_cid.month = UNPACK_BITS( raw_cid, 8, 4, mmc_sizeof );
- mmc_cid.year = UNPACK_BITS( raw_cid, 12, 8, mmc_sizeof );
- mmc_cid.year += 2000;
- }
- else
- {
- mmc_cid.mid = UNPACK_BITS( raw_cid, 120, 8, mmc_sizeof );
- mmc_cid.oid = UNPACK_BITS( raw_cid, 104, 16, mmc_sizeof );
-
- for( i = 0; i < 6; i++ )
- {
- mmc_cid.pnm[i] = (unsigned char) UNPACK_BITS(raw_cid, \
- (104 - 8 * (i+1)), 8, mmc_sizeof );
- }
- mmc_cid.pnm[6] = 0;
-
- mmc_cid.prv = UNPACK_BITS( raw_cid, 48, 8, mmc_sizeof );
- mmc_cid.psn = UNPACK_BITS( raw_cid, 16, 32, mmc_sizeof );
- mmc_cid.month = UNPACK_BITS( raw_cid, 8, 4, mmc_sizeof );
- mmc_cid.year = UNPACK_BITS( raw_cid, 12, 4, mmc_sizeof );
- mmc_cid.year += 1997;
- }
-
- /* save it in card database */
- memcpy( ( struct mmc_boot_cid * )&card->cid, \
- ( struct mmc_boot_cid * )&mmc_cid, \
- sizeof( struct mmc_boot_cid ) );
-
- dprintf(SPEW, "Decoded CID fields:\n" );
- dprintf(SPEW, "Manufacturer ID: %x\n", mmc_cid.mid );
- dprintf(SPEW, "OEM ID: 0x%x\n", mmc_cid.oid );
- dprintf(SPEW, "Product Name: %s\n", mmc_cid.pnm );
- dprintf(SPEW, "Product revision: %d.%d\n", (mmc_cid.prv >> 4), (mmc_cid.prv & 0xF) );
- dprintf(SPEW, "Product serial number: %X\n", mmc_cid.psn );
- dprintf(SPEW, "Manufacturing date: %d %d\n", mmc_cid.month, mmc_cid.year );
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Sends specified command to a card and waits for a response.
- */
-static unsigned int mmc_boot_send_command( struct mmc_boot_command* cmd )
-{
- unsigned int mmc_cmd = 0;
- unsigned int mmc_status = 0;
- unsigned int mmc_resp = 0;
- unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
- unsigned int cmd_index = 0;
- int i = 0;
-
- /* basic check */
- if( cmd == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */
- writel( cmd->argument, MMC_BOOT_MCI_ARGUMENT );
-
- /* Writes to MCI port are not effective for 3 ticks of PCLK.
- * The min pclk is 144KHz which gives 6.94 us/tick.
- * Thus 21us == 3 ticks.
- */
- udelay(21);
-
- /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */
- /* 2a. Write command index in CMD_INDEX field */
- cmd_index = cmd->cmd_index;
- mmc_cmd |= cmd->cmd_index;
- /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 */
- if( cmd_index != CMD0_GO_IDLE_STATE )
- {
- mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE;
- }
-
- /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */
- if( IS_RESP_136_BITS(cmd->resp_type) )
- {
- mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP;
- }
-
- /* 2d. Set INTERRUPT bit to 1 to disable command timeout */
-
- /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream
- mode data transfer*/
- if( cmd->xfer_mode == MMC_BOOT_XFER_MODE_STREAM )
- {
- mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING;
- }
-
- /* 2f. Set ENABLE bit to 1 */
- mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE;
-
- /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of
- write data transfer */
- if( ( cmd_index == CMD12_STOP_TRANSMISSION ||
- cmd_index == CMD13_SEND_STATUS ) && cmd->prg_enabled )
- {
- mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA;
- }
-
- /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */
- /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal
- of CE-ATA device is enabled */
-
- /* 2j. clear all static status bits */
- writel( MMC_BOOT_MCI_STATIC_STATUS, MMC_BOOT_MCI_CLEAR );
-
- /* 2k. Write to MMC_BOOT_MCI_CMD register */
- writel( mmc_cmd, MMC_BOOT_MCI_CMD );
-
- dprintf(SPEW, "Command sent: CMD%d MCI_CMD_REG:%x MCI_ARG:%x\n",
- cmd_index, mmc_cmd, cmd->argument );
-
- /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS
- register */
- do{
- /* 3a. Read MCI_STATUS register */
- while(readl( MMC_BOOT_MCI_STATUS ) \
- & MMC_BOOT_MCI_STAT_CMD_ACTIVE);
-
- mmc_status = readl( MMC_BOOT_MCI_STATUS );
-
- /* 3b. CMD_SENT bit supposed to be set to 1 only after CMD0 is sent -
- no response required. */
- if( ( cmd->resp_type == MMC_BOOT_RESP_NONE ) &&
- (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT ) )
- {
- break;
- }
-
- /* 3c. If CMD_TIMEOUT bit is set then no response was received */
- else if( mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT )
- {
- mmc_return = MMC_BOOT_E_TIMEOUT;
- break;
- }
- /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's response was
- received and CRC check passed
- Spcial case for ACMD41: it seems to always fail CRC even if
- the response is valid
- */
- else if (( mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END ) || (cmd_index == CMD1_SEND_OP_COND)
- || (cmd_index == CMD8_SEND_IF_COND))
- {
- /* 3i. Read MCI_RESP_CMD register to verify that response index is
- equal to command index */
- mmc_resp = readl( MMC_BOOT_MCI_RESP_CMD ) & 0x3F;
-
- /* However, long response does not contain the command index field.
- * In that case, response index field must be set to 111111b (0x3F) */
- if( ( mmc_resp == cmd_index ) ||
- ( cmd->resp_type == MMC_BOOT_RESP_R2 ||
- cmd->resp_type == MMC_BOOT_RESP_R3 ||
- cmd->resp_type == MMC_BOOT_RESP_R6 ||
- cmd->resp_type == MMC_BOOT_RESP_R7 ) )
- {
- /* 3j. If resp index is equal to cmd index, read command resp
- from MCI_RESPn registers
- - MCI_RESP0/1/2/3 for CMD2/9/10
- - MCI_RESP0 for all other registers */
- if( IS_RESP_136_BITS( cmd->resp_type ) )
- {
- for( i = 0; i < 4; i++ )
- {
- cmd->resp[3-i] = readl( MMC_BOOT_MCI_RESP_0 + ( i * 4 ) );
-
- }
- }
- else
- {
- cmd->resp[0] = readl( MMC_BOOT_MCI_RESP_0 );
- }
- }
- else
- {
- /* command index mis-match */
- mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH;
- }
-
- dprintf(SPEW, "Command response received: %X\n", cmd->resp[0] );
- break;
- }
-
- /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response was recvd,
- but CRC check failed. */
- else if( ( mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL ) )
- {
- if(cmd_index == ACMD41_SEND_OP_COND)
- {
- cmd->resp[0] = readl( MMC_BOOT_MCI_RESP_0);
- }
- else
- mmc_return = MMC_BOOT_E_CRC_FAIL;
- break;
- }
-
- }while(1);
-
- return mmc_return;
-}
-
-/*
- * Reset all the cards to idle condition (CMD 0)
- */
-static unsigned int mmc_boot_reset_cards( void )
-{
- struct mmc_boot_command cmd;
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- cmd.cmd_index = CMD0_GO_IDLE_STATE;
- cmd.argument = 0; // stuff bits - ignored
- cmd.cmd_type = MMC_BOOT_CMD_BCAST;
- cmd.resp_type = MMC_BOOT_RESP_NONE;
-
- /* send command */
- return mmc_boot_send_command( &cmd );
-}
-
-/*
- * Send CMD1 to know whether the card supports host VDD profile or not.
- */
-static unsigned int mmc_boot_send_op_cond( struct mmc_boot_host* host,
- struct mmc_boot_card* card )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_resp = 0;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD1 format:
- * [31] Busy bit
- * [30:29] Access mode
- * [28:24] reserved
- * [23:15] 2.7-3.6
- * [14:8] 2.0-2.6
- * [7] 1.7-1.95
- * [6:0] reserved
- */
-
- cmd.cmd_index = CMD1_SEND_OP_COND;
- cmd.argument = host->ocr;
- cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
- cmd.resp_type = MMC_BOOT_RESP_R3;
-
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Now it's time to examine response */
- mmc_resp = cmd.resp[0];
-
- /* Response contains card's ocr. Update card's information */
- card->ocr = mmc_resp;
-
- /* Check the response for busy status */
- if( !( mmc_resp & MMC_BOOT_OCR_BUSY ) )
- {
- return MMC_BOOT_E_CARD_BUSY;
- }
-
- if(mmc_resp & MMC_BOOT_OCR_SEC_MODE)
- {
- card->type = MMC_BOOT_TYPE_MMCHC;
- }
- else
- {
- card->type = MMC_BOOT_TYPE_STD_MMC;
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Request any card to send its uniquie card identification (CID) number (CMD2).
- */
-static unsigned int mmc_boot_all_send_cid( struct mmc_boot_card* card )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD2 Format:
- * [31:0] stuff bits
- */
- cmd.cmd_index = CMD2_ALL_SEND_CID;
- cmd.argument = 0;
- cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
- cmd.resp_type = MMC_BOOT_RESP_R2;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Response contains card's 128 bits CID register */
- mmc_ret = mmc_boot_decode_and_save_cid( card, cmd.resp );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Ask any card to send it's relative card address (RCA).This RCA number is
- * shorter than CID and is used by the host to address the card in future (CMD3)
- */
-static unsigned int mmc_boot_send_relative_address( struct mmc_boot_card* card )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD3 Format:
- * [31:0] stuff bits
- */
- if(card->type == MMC_BOOT_TYPE_SDHC || card->type == MMC_BOOT_TYPE_STD_SD)
- {
- cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
- cmd.argument = 0;
- cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
- cmd.resp_type = MMC_BOOT_RESP_R6;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- /* For sD, card will send RCA. Store it */
- card->rca = (cmd.resp[0] >> 16);
- }
- else
- {
- cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
- cmd.argument = (MMC_RCA << 16);
- card->rca = (cmd.argument >> 16);
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Requests card to send it's CSD register's contents. (CMD9)
- */
-static unsigned int mmc_boot_send_csd( struct mmc_boot_card* card,
- unsigned int* raw_csd )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_arg = 0;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD9 Format:
- * [31:16] RCA
- * [15:0] stuff bits
- */
- mmc_arg |= card->rca << 16;
-
- cmd.cmd_index = CMD9_SEND_CSD;
- cmd.argument = mmc_arg;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R2;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* response contains the card csd */
- memcpy(raw_csd, cmd.resp, sizeof(cmd.resp));
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Selects a card by sending CMD7 to the card with its RCA.
- * If RCA field is set as 0 ( or any other address ),
- * the card will be de-selected. (CMD7)
- */
-static unsigned int mmc_boot_select_card( struct mmc_boot_card* card,
- unsigned int rca )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_arg = 0;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD7 Format:
- * [31:16] RCA
- * [15:0] stuff bits
- */
- mmc_arg |= rca << 16;
-
- cmd.cmd_index = CMD7_SELECT_DESELECT_CARD;
- cmd.argument = mmc_arg;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- /* If we are deselecting card, we do not get response */
- if( rca == card->rca && rca)
- {
- if(card->type == MMC_BOOT_TYPE_SDHC || card->type == MMC_BOOT_TYPE_STD_SD)
- cmd.resp_type = MMC_BOOT_RESP_R1B;
- else
- cmd.resp_type = MMC_BOOT_RESP_R1;
- }
- else
- {
- cmd.resp_type = MMC_BOOT_RESP_NONE;
- }
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* As of now no need to look into a response. If it's required
- * we'll explore later on */
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Send command to set block length.
- */
-static unsigned int mmc_boot_set_block_len( struct mmc_boot_card* card,
- unsigned int block_len )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD16 Format:
- * [31:0] block length
- */
-
- cmd.cmd_index = CMD16_SET_BLOCKLEN;
- cmd.argument = block_len;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* If blocklength is larger than 512 bytes,
- * the card sets BLOCK_LEN_ERROR bit. */
- if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Requests the card to stop transmission of data.
- */
-static unsigned int mmc_boot_send_stop_transmission( struct mmc_boot_card* card,
- unsigned int prg_enabled )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD12 Format:
- * [31:0] stuff bits
- */
-
- cmd.cmd_index = CMD12_STOP_TRANSMISSION;
- cmd.argument = 0;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1B;
- cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
- cmd.prg_enabled = prg_enabled;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Get the card's current status
- */
-static unsigned int mmc_boot_get_card_status( struct mmc_boot_card* card,
- unsigned int prg_enabled, unsigned int* status )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD13 Format:
- * [31:16] RCA
- * [15:0] stuff bits
- */
- cmd.cmd_index = CMD13_SEND_STATUS;
- cmd.argument = card->rca << 16;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
- cmd.prg_enabled = prg_enabled;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */
- if(IS_ADDR_OUT_OF_RANGE(cmd.resp[0]))
- {
- return MMC_BOOT_E_FAILURE;
- }
-
- *status = cmd.resp[0];
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Decode type of error caused during read and write
- */
-static unsigned int mmc_boot_status_error(unsigned mmc_status)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
- card/device during the data transfer */
- if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
- {
- mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
- }
- /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
- the data timeout period without completing the transfer */
- else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
- {
- mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
- }
- /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
- the card before empty storage for new received data was available.
- Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
- else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
- {
- /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
- for now */
- mmc_ret = MMC_BOOT_E_RX_OVRRUN;
- }
- /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to
- the card before new data for sending was available. Verify that bit
- FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
- else if( mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN )
- {
- /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now*/
- mmc_ret = MMC_BOOT_E_RX_OVRRUN;
- }
- return mmc_ret;
-}
-
-/*
- * Send ext csd command.
- */
-static unsigned int mmc_boot_send_ext_cmd (struct mmc_boot_card* card, unsigned char* buf)
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_reg = 0;
- unsigned int* mmc_ptr = (unsigned int *)buf;
-
- memset(buf,0, 512);
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* set block len */
- if( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
- {
- mmc_ret = mmc_boot_set_block_len( card, 512);
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
- mmc_ret, (char *)(card->rca) );
- return mmc_ret;
- }
- }
-
- /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
- mmc_reg = readl( MMC_BOOT_MCI_CLK );
- mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
- writel( mmc_reg, MMC_BOOT_MCI_CLK );
-
- /* Write data timeout period to MCI_DATA_TIMER register. */
- /* Data timeout period should be in card bus clock periods */
- mmc_reg =0xFFFFFFFF;
- writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
- writel( 512, MMC_BOOT_MCI_DATA_LENGTH );
-
- /* Set appropriate fields and write the MCI_DATA_CTL register. */
- /* Set ENABLE bit to 1 to enable the data transfer. */
- mmc_reg = MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (512 << MMC_BOOT_MCI_BLKSIZE_POS);
-
-#if MMC_BOOT_ADM
- mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
-#endif
-
- writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
- /* CMD8 */
- cmd.cmd_index = CMD8_SEND_EXT_CSD;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
- cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Read the transfer data from SDCC FIFO. */
- mmc_ret = mmc_boot_fifo_data_transfer(mmc_ptr, 512, MMC_BOOT_DATA_READ);
-
- return mmc_ret;
-}
-
-/*
- * Switch command
- */
-static unsigned int mmc_boot_switch_cmd (struct mmc_boot_card* card,
- unsigned access,
- unsigned index,
- unsigned value)
-{
-
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD6 Format:
- * [31:26] set to 0
- * [25:24] access
- * [23:16] index
- * [15:8] value
- * [7:3] set to 0
- * [2:0] cmd set
- */
- cmd.cmd_index = CMD6_SWITCH_FUNC;
- cmd.argument |= (access << 24);
- cmd.argument |= (index << 16);
- cmd.argument |= (value << 8);
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1B;
-
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * A command to set the data bus width for card. Set width to either
- */
-static unsigned int mmc_boot_set_bus_width( struct mmc_boot_card* card,
- unsigned int width )
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_reg = 0;
- unsigned int mmc_width = 0;
- unsigned int status;
- unsigned int wait_count = 100;
-
-
- if( width != MMC_BOOT_BUS_WIDTH_1_BIT)
- {
- mmc_width = width-1;
- }
-
-
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
- MMC_BOOT_EXT_CMMC_BUS_WIDTH, mmc_width);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Wait for the card to complete the switch command processing */
- do
- {
- mmc_ret = mmc_boot_get_card_status(card, 0, &status);
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- wait_count--;
- if(wait_count == 0)
- {
- return MMC_BOOT_E_FAILURE;
- }
- }while( MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE );
-
-
- /* set MCI_CLK accordingly */
- mmc_reg = readl( MMC_BOOT_MCI_CLK );
- mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE;
- if ( width == MMC_BOOT_BUS_WIDTH_1_BIT )
- {
- mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT;
- }
- else if (width == MMC_BOOT_BUS_WIDTH_4_BIT )
- {
- mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT;
- }
- else if (width == MMC_BOOT_BUS_WIDTH_8_BIT )
- {
- mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT;
- }
- writel( mmc_reg, MMC_BOOT_MCI_CLK );
-
- mdelay(10); // Giving some time to card to stabilize.
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-
-/*
- * A command to start data read from card. Either a single block or
- * multiple blocks can be read. Multiple blocks read will continuously
- * transfer data from card to host unless requested to stop by issuing
- * CMD12 - STOP_TRANSMISSION.
- */
-static unsigned int mmc_boot_send_read_command( struct mmc_boot_card* card,
- unsigned int xfer_type,
- unsigned int data_addr )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD17/18 Format:
- * [31:0] Data Address
- */
- if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
- {
- cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK;
- }
- else
- {
- cmd.cmd_index = CMD17_READ_SINGLE_BLOCK;
- }
-
- cmd.argument = data_addr;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Response contains 32 bit Card status. Here we'll check
- BLOCK_LEN_ERROR and ADDRESS_ERROR */
- if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
- /* Misaligned address not matching block length */
- if( cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR )
- {
- return MMC_BOOT_E_ADDRESS_ERR;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * A command to start data write to card. Either a single block or
- * multiple blocks can be written. Multiple block write will continuously
- * transfer data from host to card unless requested to stop by issuing
- * CMD12 - STOP_TRANSMISSION.
- */
-static unsigned int mmc_boot_send_write_command( struct mmc_boot_card* card,
- unsigned int xfer_type,
- unsigned int data_addr )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD24/25 Format:
- * [31:0] Data Address
- */
- if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
- {
- cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK;
- }
- else
- {
- cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK;
- }
-
- cmd.argument = data_addr;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Response contains 32 bit Card status. Here we'll check
- BLOCK_LEN_ERROR and ADDRESS_ERROR */
- if( cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR )
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
- /* Misaligned address not matching block length */
- if( cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR )
- {
- return MMC_BOOT_E_ADDRESS_ERR;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-
-/*
- * Write data_len data to address specified by data_addr. data_len is
- * multiple of blocks for block data transfer.
- */
-unsigned int mmc_boot_write_to_card( struct mmc_boot_host* host,
- struct mmc_boot_card* card,
- unsigned long long data_addr,
- unsigned int data_len,
- unsigned int* in )
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_status = 0;
- unsigned int mmc_reg = 0;
- unsigned int addr;
- unsigned int xfer_type;
- unsigned int status;
-
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block
- length. So no need to send CMD16. */
- if( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
- {
- mmc_ret = mmc_boot_set_block_len( card, card->wr_block_len );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card\
- (RCA:%s)\n", mmc_ret, (char *)(card->rca) );
- return mmc_ret;
- }
- }
-
- /* use multi-block mode to transfer for data larger than a block */
- xfer_type = (data_len > card->rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
- MMC_BOOT_XFER_SINGLE_BLOCK;
-
- /* For MMCHC/SDHC data address is specified in unit of 512B */
- addr = ( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
- ? (unsigned int) data_addr : (unsigned int) (data_addr / 512);
-
- /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
- mmc_reg = readl( MMC_BOOT_MCI_CLK );
- mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
- writel( mmc_reg, MMC_BOOT_MCI_CLK );
-
- /* Write data timeout period to MCI_DATA_TIMER register */
- /* Data timeout period should be in card bus clock periods */
- /*TODO: Fix timeout value*/
- mmc_reg = 0xFFFFFFFF;
- writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
-
- /* Write the total size of the transfer data to MCI_DATA_LENGTH register */
- writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
-
- /* Send command to the card/device in order to start the write data xfer.
- The possible commands are CMD24/25/53/60/61 */
- mmc_ret = mmc_boot_send_write_command( card, xfer_type, addr );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure sending write command to the\
- Card(RCA:%x)\n", mmc_ret, card->rca );
- return mmc_ret;
- }
-
- /* Set appropriate fields and write the MCI_DATA_CTL register */
- /* Set ENABLE bit to 1 to enable the data transfer. */
- mmc_reg = 0;
- mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
- /* Clear DIRECTION bit to 0 to enable transfer from host to card */
- /* Clear MODE bit to 0 to enable block oriented data transfer. For
- MMC cards only, if stream data transfer mode is desired, set
- MODE bit to 1. */
-
- /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */
-
-#if MMC_BOOT_ADM
- mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
-#endif
-
- /* Write size of block to be used during the data transfer to
- BLOCKSIZE field */
- mmc_reg |= card->wr_block_len << MMC_BOOT_MCI_BLKSIZE_POS;
- writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
-
- /* write data to FIFO */
- mmc_ret = mmc_boot_fifo_data_transfer(in, data_len, MMC_BOOT_DATA_WRITE);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
- Card(RCA:%x)\n", mmc_ret, card->rca );
- /* In case of any failure happening for multi block transfer */
- if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
- mmc_boot_send_stop_transmission( card, 1 );
- return mmc_ret;
- }
-
- /* Send command to the card/device in order to poll the de-assertion of
- card/device BUSY condition. It is important to set PROG_ENA bit in
- MCI_CLK register before sending the command. Possible commands are
- CMD12/13. */
- if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
- {
- mmc_ret = mmc_boot_send_stop_transmission( card, 1 );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
- command to the Card(RCA:%x)\n", mmc_ret, card->rca );
- return mmc_ret;
- }
- }
- else
- {
- mmc_ret = mmc_boot_get_card_status( card, 1, &status );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure getting card status of Card(RCA:%x)\n",
- mmc_ret, card->rca );
- return mmc_ret;
- }
- }
-
- /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. If
- PROG_DONE bit is set to 1 it means that the card finished it programming
- and stopped driving DAT0 line to 0 */
- do
- {
- mmc_status = readl( MMC_BOOT_MCI_STATUS );
- if( mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE )
- {
- break;
- }
- } while(1);
-
- return MMC_BOOT_E_SUCCESS;
-}
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
-
-/*
- * Adjust the interface speed to optimal speed
- */
-static unsigned int mmc_boot_adjust_interface_speed( struct mmc_boot_host* host,
- struct mmc_boot_card* card )
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int status;
- unsigned int wait_count = 100;
-
- /* Setting HS_TIMING in EXT_CSD (CMD6) */
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
- MMC_BOOT_EXT_CMMC_HS_TIMING, 1);
-
- if(mmc_ret!= MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- /* Wait for the card to complete the switch command processing */
- do
- {
- mmc_ret = mmc_boot_get_card_status(card, 0, &status);
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- wait_count--;
- if(wait_count == 0)
- {
- return MMC_BOOT_E_FAILURE;
- }
- }while( MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE );
-
-
- clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
-
- host->mclk_rate = MMC_CLK_50MHZ;
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-static unsigned int mmc_boot_set_block_count( struct mmc_boot_card* card,
- unsigned int block_count )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( card == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* CMD23 Format:
- * [15:0] number of blocks
- */
-
- cmd.cmd_index = CMD23_SET_BLOCK_COUNT;
- cmd.argument = block_count;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- if( cmd.resp[0] & MMC_BOOT_R1_OUT_OF_RANGE)
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Reads a data of data_len from the address specified. data_len
- * should be multiple of block size for block data transfer.
- */
-unsigned int mmc_boot_read_from_card( struct mmc_boot_host* host,
- struct mmc_boot_card* card,
- unsigned long long data_addr,
- unsigned int data_len,
- unsigned int* out )
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_reg = 0;
- unsigned int xfer_type;
- unsigned int addr = 0;
- unsigned char open_ended_read = 1;
-
- if ( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block
- length. So no need to send CMD16. */
- if ( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
- {
- mmc_ret = mmc_boot_set_block_len( card, card->rd_block_len );
- if ( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
- mmc_ret, (char *)(card->rca) );
- return mmc_ret;
- }
- }
-
- /* use multi-block mode to transfer for data larger than a block */
- xfer_type = (data_len > card->rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
- MMC_BOOT_XFER_SINGLE_BLOCK;
-
- if(xfer_type == MMC_BOOT_XFER_MULTI_BLOCK)
- {
- if( (card->type == MMC_BOOT_TYPE_MMCHC) || (card->type == MMC_BOOT_TYPE_STD_MMC) )
- {
- /* Virtio model does not support open-ended multi-block reads.
- * So, block count must be set before sending read command.
- * All SD cards do not support this command. Restrict this to MMC.
- */
- mmc_ret = mmc_boot_set_block_count( card, data_len/(card->rd_block_len));
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting read block count for Card (RCA:%s)\n",
- mmc_ret, (char *)(card->rca) );
- return mmc_ret;
- }
-
- open_ended_read = 0;
- }
- }
-
- /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
- /* Note: It's already enabled */
-
- /* If Data Mover is used for data transfer then prepare Command
- List Entry and enable the Data mover to work with SDCC2 */
-
- /* Write data timeout period to MCI_DATA_TIMER register. */
- /* Data timeout period should be in card bus clock periods */
- mmc_reg = (unsigned long)(card->rd_timeout_ns / 1000000) *
- (host->mclk_rate / 1000);
- mmc_reg += 1000; // add some extra clock cycles to be safe
- mmc_reg = mmc_reg/2;
- writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
-
- /* Write the total size of the transfer data to MCI_DATA_LENGTH
- register. For block xfer it must be multiple of the block
- size. */
- writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
-
- /* For MMCHC/SDHC data address is specified in unit of 512B */
- addr = ( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
- ? (unsigned int) data_addr :(unsigned int) (data_addr / 512);
-
- /* Set appropriate fields and write the MCI_DATA_CTL register. */
- /* Set ENABLE bit to 1 to enable the data transfer. */
- mmc_reg = 0;
- mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
- /* Clear DIRECTION bit to 1 to enable transfer from card to host */
- mmc_reg |= MMC_BOOT_MCI_DATA_DIR;
- /* Clear MODE bit to 0 to enable block oriented data transfer. For
- MMC cards only, if stream data transfer mode is desired, set
- MODE bit to 1. */
-
- /* If DMA is to be used, Set DM_ENABLE bit to 1 */
-
-#if MMC_BOOT_ADM
- mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
-#endif
-
- /* Write size of block to be used during the data transfer to
- BLOCKSIZE field */
- mmc_reg |= (card->rd_block_len << MMC_BOOT_MCI_BLKSIZE_POS);
- writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
-
- /* Send command to the card/device in order to start the read data
- transfer. Possible commands: CMD17/18/53/60/61. */
- mmc_ret = mmc_boot_send_read_command( card, xfer_type, addr );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure sending read command to the Card(RCA:%x)\n",
- mmc_ret, card->rca );
- return mmc_ret;
- }
-
- /* Read the transfer data from SDCC FIFO. */
- mmc_ret = mmc_boot_fifo_data_transfer(out, data_len, MMC_BOOT_DATA_READ);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
- Card(RCA:%x)\n", mmc_ret, card->rca );
- return mmc_ret;
- }
-
- /* In case a multiple block transfer was performed, send CMD12 to the
- card/device in order to indicate the end of read data transfer */
- if( (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) && open_ended_read )
- {
- mmc_ret = mmc_boot_send_stop_transmission( card, 0 );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
- command to the Card(RCA:%x)\n", mmc_ret, card->rca );
- return mmc_ret;
- }
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Initialize host structure, set and enable clock-rate and power mode.
- */
-unsigned int mmc_boot_init( struct mmc_boot_host* host )
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_pwr = 0;
-
-
- host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE;
- host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY;
-
- /* Initialize any clocks needed for SDC controller */
- clock_init_mmc(mmc_slot);
-
- /* Setup initial freq to 400KHz */
- clock_config_mmc(mmc_slot, MMC_CLK_400KHZ);
-
- host->mclk_rate = MMC_CLK_400KHZ;
-
- /* set power mode*/
- /* give some time to reach minimum voltate */
- mdelay(2);
- mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP;
- mmc_pwr |= MMC_BOOT_MCI_PWR_ON;
- mmc_pwr |= MMC_BOOT_MCI_PWR_UP;
- writel( mmc_pwr, MMC_BOOT_MCI_POWER );
- /* some more time to stabilize voltage */
- mdelay(2);
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Performs card identification process:
- * - get card's unique identification number (CID)
- * - get(for sd)/set (for mmc) relative card address (RCA)
- * - get CSD
- * - select the card, thus transitioning it to Transfer State
- * - get Extended CSD (for mmc)
- */
-static unsigned int mmc_boot_identify_card( struct mmc_boot_host* host,
- struct mmc_boot_card* card)
-{
- unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
- unsigned int raw_csd[4];
-
- /* basic check */
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* Ask card to send its unique card identification (CID) number (CMD2) */
- mmc_return = mmc_boot_all_send_cid( card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No. %d: Failure getting card's CID number!\n",
- mmc_return );
- return mmc_return;
- }
-
- /* Ask card to send a relative card address (RCA) (CMD3) */
- mmc_return = mmc_boot_send_relative_address( card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No. %d: Failure getting card's RCA!\n",
- mmc_return );
- return mmc_return;
- }
-
- /* Get card's CSD register (CMD9) */
- mmc_return = mmc_boot_send_csd( card, raw_csd );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure getting card's CSD information!\n",
- mmc_return );
- return mmc_return;
- }
-
- /* Select the card (CMD7) */
- mmc_return = mmc_boot_select_card( card, card->rca );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure selecting the Card with RCA: %x\n",
- mmc_return, card->rca );
- return mmc_return;
- }
-
- /* Set the card status as active */
- card->status = MMC_BOOT_STATUS_ACTIVE;
-
- if( (card->type == MMC_BOOT_TYPE_STD_MMC) || (card->type == MMC_BOOT_TYPE_MMCHC))
- {
- /* For MMC cards, also get the extended csd */
- mmc_return = mmc_boot_send_ext_cmd( card, ext_csd_buf);
-
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure getting card's ExtCSD information!\n",
- mmc_return );
-
- return mmc_return;
- }
-
- }
-
- /* Decode and save the CSD register */
- mmc_return = mmc_boot_decode_and_save_csd( card, raw_csd );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure decoding card's CSD information!\n",
- mmc_return );
- return mmc_return;
- }
-
- /* Once CSD is received, set read and write timeout value now itself */
- mmc_return = mmc_boot_set_read_timeout( host, card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting Read Timeout value!\n",
- mmc_return );
- return mmc_return;
- }
-
- mmc_return = mmc_boot_set_write_timeout( host, card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure setting Write Timeout value!\n",
- mmc_return );
- return mmc_return;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-static unsigned int mmc_boot_send_app_cmd(unsigned int rca)
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- cmd.cmd_index = CMD55_APP_CMD;
- cmd.argument = (rca << 16);
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- mmc_ret = mmc_boot_send_command(&cmd);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-static unsigned int mmc_boot_sd_init_card(struct mmc_boot_card* card)
-{
- unsigned int i,mmc_ret;
- unsigned int ocr_cmd_arg;
- struct mmc_boot_command cmd;
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* Send CMD8 to set interface condition */
- for(i=0;i<3;i++)
- {
- cmd.cmd_index = CMD8_SEND_IF_COND;
- cmd.argument = MMC_BOOT_SD_HC_VOLT_SUPPLIED;
- cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
- cmd.resp_type = MMC_BOOT_RESP_R7;
-
- mmc_ret = mmc_boot_send_command(&cmd);
- if( mmc_ret == MMC_BOOT_E_SUCCESS )
- {
- if(cmd.resp[0] != MMC_BOOT_SD_HC_VOLT_SUPPLIED)
- return MMC_BOOT_E_FAILURE;
- /* Set argument for ACMD41 */
- ocr_cmd_arg = MMC_BOOT_SD_NEG_OCR | MMC_BOOT_SD_HC_HCS;
- break;
- }
- mdelay(1);
- }
-
- /* Send ACMD41 to set operating condition */
- /* Try for a max of 1 sec as per spec */
- for(i=0;i<20;i++)
- {
- mmc_ret = mmc_boot_send_app_cmd(0);
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- cmd.cmd_index = ACMD41_SEND_OP_COND;
- cmd.argument = ocr_cmd_arg;
- cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
- cmd.resp_type = MMC_BOOT_RESP_R3;
-
- mmc_ret = mmc_boot_send_command(&cmd);
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- else if (cmd.resp[0] & MMC_BOOT_SD_DEV_READY)
- {
- /* Check for HC */
- if(cmd.resp[0] & (1 << 30))
- {
- card->type = MMC_BOOT_TYPE_SDHC;
- }
- else
- {
- card->type = MMC_BOOT_TYPE_STD_SD;
- }
- break;
- }
- mdelay(50);
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Routine to initialize MMC card. It resets a card to idle state, verify operating
- * voltage and set the card inready state.
- */
-static unsigned int mmc_boot_init_card( struct mmc_boot_host* host,
- struct mmc_boot_card* card )
-{
- unsigned int mmc_retry = 0;
- unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
-
- /* basic check */
- if( ( host == NULL ) || ( card == NULL ) )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* 1. Card Reset - CMD0 */
- mmc_return = mmc_boot_reset_cards();
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.:%d: Failure resetting MMC cards!\n", mmc_return);
- return mmc_return;
- }
-
- /* 2. Card Initialization process */
-
- /* Send CMD1 to identify and reject cards that do not match host's VDD range
- profile. Cards sends its OCR register in response.
- */
- mmc_retry = 0;
- do
- {
- mmc_return = mmc_boot_send_op_cond( host, card );
- /* Card returns busy status. We'll retry again! */
- if( mmc_return == MMC_BOOT_E_CARD_BUSY )
- {
- mmc_retry++;
- mdelay(1);
- continue;
- }
- else if( mmc_return == MMC_BOOT_E_SUCCESS )
- {
- break;
- }
- else
- {
- dprintf(CRITICAL, "Error No. %d: Failure Initializing MMC Card!\n",
- mmc_return );
-
- /* Check for sD card */
- mmc_return = mmc_boot_sd_init_card(card);
- return mmc_return;
- }
- }while( mmc_retry < host->cmd_retry );
-
- /* If card still returned busy status we are out of luck.
- * Card cannot be initialized */
- if( mmc_return == MMC_BOOT_E_CARD_BUSY )
- {
- dprintf(CRITICAL, "Error No. %d: Card has busy status set. \
- Initialization not completed\n", mmc_return );
- return MMC_BOOT_E_CARD_BUSY;
- }
- return MMC_BOOT_E_SUCCESS;
-}
-
-
-static unsigned int mmc_boot_set_sd_bus_width(struct mmc_boot_card* card, unsigned int width)
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int sd_reg;
-
- mmc_ret = mmc_boot_send_app_cmd(card->rca);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* Send ACMD6 to set bus width */
- cmd.cmd_index = ACMD6_SET_BUS_WIDTH;
- /* 10 => 4 bit wide */
- if ( width == MMC_BOOT_BUS_WIDTH_1_BIT )
- {
- cmd.argument = 0;
- }
- else if (width == MMC_BOOT_BUS_WIDTH_4_BIT )
- {
- cmd.argument = (1<<1);
- }
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- mmc_ret = mmc_boot_send_command(&cmd);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* set MCI_CLK accordingly */
- sd_reg = readl( MMC_BOOT_MCI_CLK );
- sd_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE;
- if ( width == MMC_BOOT_BUS_WIDTH_1_BIT )
- {
- sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT;
- }
- else if (width == MMC_BOOT_BUS_WIDTH_4_BIT )
- {
- sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT;
- }
- else if (width == MMC_BOOT_BUS_WIDTH_8_BIT )
- {
- sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT;
- }
- writel( sd_reg, MMC_BOOT_MCI_CLK );
-
- mdelay(10); // Giving some time to card to stabilize.
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-static unsigned int mmc_boot_set_sd_hs(struct mmc_boot_host* host, struct mmc_boot_card* card)
-{
- unsigned char sw_buf[64];
- unsigned int mmc_ret;
-
- /* CMD6 is a data transfer command. sD card returns 512 bits of data*/
- /* Refer 4.3.10 of sD card specification 3.0 */
- mmc_ret = mmc_boot_read_reg(card,64,CMD6_SWITCH_FUNC,MMC_BOOT_SD_SWITCH_HS,
- (unsigned int *)&sw_buf);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- mdelay(1);
-
- clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
-
- host->mclk_rate = MMC_CLK_50MHZ;
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Performs initialization and identification of all the MMC cards connected
- * to the host.
- */
-
-static unsigned int mmc_boot_init_and_identify_cards( struct mmc_boot_host* host, struct mmc_boot_card* card )
-{
- unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
- unsigned int status;
-
- /* Basic check */
- if( host == NULL )
- {
- return MMC_BOOT_E_INVAL;
- }
-
- /* Initialize MMC card structure */
- card->status = MMC_BOOT_STATUS_INACTIVE;
- card->rd_block_len = MMC_BOOT_RD_BLOCK_LEN;
- card->wr_block_len = MMC_BOOT_WR_BLOCK_LEN;
-
- /* Start initialization process (CMD0 & CMD1) */
- mmc_return = mmc_boot_init_card( host, card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- return mmc_return;
- }
-
- /* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */
- mmc_return = mmc_boot_identify_card( host, card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- return mmc_return;
- }
-
- if(card->type == MMC_BOOT_TYPE_SDHC || card->type == MMC_BOOT_TYPE_STD_SD)
- {
- /* Setting sD card to high speed without checking card's capability.
- Cards that do not support high speed may fail to boot */
- mmc_return = mmc_boot_set_sd_hs(host, card);
- if(mmc_return != MMC_BOOT_E_SUCCESS)
- {
- return mmc_return;
- }
-
- mmc_return = mmc_boot_set_sd_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT);
- if(mmc_return != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL,"Couldn't set 4bit mode for sD card\n");
- mmc_return = mmc_boot_set_sd_bus_width(card, MMC_BOOT_BUS_WIDTH_1_BIT);
- if(mmc_return != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL, "Error No.%d: Failed in setting bus width!\n",
- mmc_return);
- return mmc_return;
- }
- }
- }
- else
- {
- /* set interface speed */
- mmc_return = mmc_boot_adjust_interface_speed( host, card );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Error adjusting interface speed!\n",
- mmc_return );
- return mmc_return;
- }
-
- /* enable wide bus */
- mmc_return = mmc_boot_set_bus_width( card, MMC_BOOT_BUS_WIDTH_4_BIT );
- if( mmc_return != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n",
- mmc_return, card->rca );
- return mmc_return;
- }
- }
-
- /* Just checking whether we're in TRAN state after changing speed and bus width */
- mmc_return = mmc_boot_get_card_status(card, 0, &status);
- if(mmc_return != MMC_BOOT_E_SUCCESS)
- {
- return mmc_return;
- }
-
- if(MMC_BOOT_CARD_STATUS(status) != MMC_BOOT_TRAN_STATE)
- return MMC_BOOT_E_FAILURE;
-
- return MMC_BOOT_E_SUCCESS;
-}
-
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
-void mmc_display_ext_csd(void)
-{
- dprintf(SPEW, "part_config: %x\n", ext_csd_buf[179] );
- dprintf(SPEW, "erase_group_def: %x\n", ext_csd_buf[175] );
- dprintf(SPEW, "user_wp: %x\n", ext_csd_buf[171] );
-}
+#include <string.h>
+#include <stdlib.h>
+#include <debug.h>
+#include <reg.h>
+#include "mmc.h"
+#include <partition_parser.h>
+#include <platform/iomap.h>
+#include <platform/timer.h>
+#if MMC_BOOT_ADM
+#include "adm.h"
+#endif
+#ifndef NULL
+#define NULL 0
+#endif
-void mmc_display_csd(void)
-{
- dprintf(SPEW, "erase_grpsize: %d\n", mmc_card.csd.erase_grp_size );
- dprintf(SPEW, "erase_grpmult: %d\n", mmc_card.csd.erase_grp_mult );
- dprintf(SPEW, "wp_grpsize: %d\n", mmc_card.csd.wp_grp_size );
- dprintf(SPEW, "wp_grpen: %d\n", mmc_card.csd.wp_grp_enable );
- dprintf(SPEW, "perm_wp: %d\n", mmc_card.csd.perm_wp );
- dprintf(SPEW, "temp_wp: %d\n", mmc_card.csd.temp_wp );
-}
+#define MMC_BOOT_DATA_READ 0
+#define MMC_BOOT_DATA_WRITE 1
+static unsigned int mmc_boot_fifo_data_transfer(unsigned int *data_ptr,
+ unsigned int data_len,
+ unsigned char direction);
+static unsigned int mmc_boot_fifo_read(unsigned int *data_ptr,
+ unsigned int data_len);
-/*
- * Entry point to MMC boot process
- */
-unsigned int mmc_boot_main(unsigned char slot, unsigned int base)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- memset( (struct mmc_boot_host*)&mmc_host, 0, sizeof( struct mmc_boot_host ) );
- memset( (struct mmc_boot_card*)&mmc_card, 0, sizeof(struct mmc_boot_card) );
-
- mmc_slot = slot;
- mmc_boot_mci_base = base;
-
- /* Initialize necessary data structure and enable/set clock and power */
- dprintf(SPEW," Initializing MMC host data structure and clock!\n" );
- mmc_ret = mmc_boot_init( &mmc_host );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "MMC Boot: Error Initializing MMC Card!!!\n" );
- return MMC_BOOT_E_FAILURE;
- }
-
- /* Initialize and identify cards connected to host */
- mmc_ret = mmc_boot_init_and_identify_cards( &mmc_host, &mmc_card );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "MMC Boot: Failed detecting MMC/SDC @ slot%d\n",slot);
- return MMC_BOOT_E_FAILURE;
- }
-
- mmc_display_csd();
- mmc_display_ext_csd();
-
- mmc_ret = partition_read_table(&mmc_host, &mmc_card);
- return mmc_ret;
-}
-
-/*
- * MMC write function
- */
-unsigned int mmc_write (unsigned long long data_addr, unsigned int data_len, unsigned int* in)
-{
- int val = 0;
- unsigned int write_size = ((unsigned)(0xFFFFFF/512))*512;
- unsigned offset = 0;
- unsigned int *sptr = in;
+static unsigned int mmc_boot_fifo_write(unsigned int *data_ptr,
+ unsigned int data_len);
- if(data_len % 512)
- data_len = ROUND_TO_PAGE(data_len, 511);
+#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
- while(data_len > write_size)
- {
- val = mmc_boot_write_to_card( &mmc_host, &mmc_card, \
- data_addr + offset, \
- write_size, sptr);
- if(val)
- {
- return val;
- }
-
- sptr += (write_size/sizeof(unsigned));
- offset += write_size;
- data_len -= write_size;
- }
- if (data_len)
- {
- val = mmc_boot_write_to_card( &mmc_host, &mmc_card, \
- data_addr + offset, \
- data_len, sptr);
- }
- return val;
-}
+/* data access time unit in ns */
+static const unsigned int taac_unit[] =
+ { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 };
+/* data access time value x 10 */
+static const unsigned int taac_value[] =
+ { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
-/*
- * MMC read function
- */
-
-unsigned int mmc_read (unsigned long long data_addr, unsigned int* out, unsigned int data_len)
-{
- int val = 0;
- val = mmc_boot_read_from_card( &mmc_host, &mmc_card, data_addr, data_len, out);
- return val;
-}
-
-/*
- * Function to read registers from MMC or SD card
- */
-static unsigned int mmc_boot_read_reg(struct mmc_boot_card *card,
- unsigned int data_len,
- unsigned int command, unsigned int addr,
- unsigned int *out)
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_reg = 0;
-
- /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
- mmc_reg = readl( MMC_BOOT_MCI_CLK );
- mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
- writel( mmc_reg, MMC_BOOT_MCI_CLK );
-
- /* Write data timeout period to MCI_DATA_TIMER register. */
- /* Data timeout period should be in card bus clock periods */
- mmc_reg =0xFFFFFFFF;
- writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
- writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
-
- /* Set appropriate fields and write the MCI_DATA_CTL register. */
- /* Set ENABLE bit to 1 to enable the data transfer. */
- mmc_reg = MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (data_len << MMC_BOOT_MCI_BLKSIZE_POS);
-
-#if MMC_BOOT_ADM
- mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
-#endif
-
- writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- cmd.cmd_index = command;
- cmd.argument = addr;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- /* send command */
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Read the transfer data from SDCC FIFO. */
- mmc_ret = mmc_boot_fifo_data_transfer(out, data_len, MMC_BOOT_DATA_READ);
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
- Card(RCA:%x)\n", mmc_ret, card->rca );
- return mmc_ret;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Function to set/clear power-on write protection for the user area partitions
- */
-static unsigned int mmc_boot_set_clr_power_on_wp_user(struct mmc_boot_card* card,
- unsigned int addr,
- unsigned int size,
- unsigned char set_clear_wp)
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int wp_group_size, loop_count;
- unsigned int status;
-
- memset( (struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command) );
-
- /* Disabling PERM_WP for USER AREA (CMD6) */
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
- MMC_BOOT_EXT_USER_WP,
- MMC_BOOT_US_PERM_WP_DIS);
-
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- /* Sending CMD13 to check card status */
- do
- {
- mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
- if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
- break;
- } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
- (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- mmc_ret = mmc_boot_send_ext_cmd (card,ext_csd_buf);
-
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- /* Make sure power-on write protection for user area is not disabled
- and permanent write protection for user area is not enabled */
-
- if((IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PERM_WP_EN)) ||
- (IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PWR_WP_DIS)))
- {
- return MMC_BOOT_E_FAILURE;
- }
-
- if(ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF])
- {
- /* wp_group_size = 512KB * HC_WP_GRP_SIZE * HC_ERASE_GRP_SIZE.
- Getting write protect group size in sectors here. */
-
- wp_group_size = (512*1024) * ext_csd_buf[MMC_BOOT_EXT_HC_WP_GRP_SIZE] *
- ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] /
- MMC_BOOT_WR_BLOCK_LEN;
- }
- else
- {
- /* wp_group_size = (WP_GRP_SIZE + 1) * (ERASE_GRP_SIZE + 1)
- * (ERASE_GRP_MULT + 1).
- This is defined as the number of write blocks directly */
-
- wp_group_size = (card->csd.erase_grp_size + 1) *
- (card->csd.erase_grp_mult + 1) *
- (card->csd.wp_grp_size + 1);
- }
-
- if(wp_group_size == 0)
- {
- return MMC_BOOT_E_FAILURE;
- }
-
- /* Setting POWER_ON_WP for USER AREA (CMD6) */
-
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
- MMC_BOOT_EXT_USER_WP,
- MMC_BOOT_US_PWR_WP_EN);
-
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- /* Sending CMD13 to check card status */
- do
- {
- mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
- if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
- break;
- } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
- (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Calculating the loop count for sending SET_WRITE_PROTECT (CMD28)
- or CLEAR_WRITE_PROTECT (CMD29).
- We are write protecting the partitions in blocks of write protect
- group sizes only */
-
- if(size % wp_group_size)
- {
- loop_count = (size / wp_group_size) + 1;
- }
- else
- {
- loop_count = (size / wp_group_size);
- }
-
- if(set_clear_wp)
- cmd.cmd_index = CMD28_SET_WRITE_PROTECT;
- else
- cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT;
-
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1B;
-
- for (unsigned int i = 0; i < loop_count; i++)
- {
- /* Sending CMD28 for each WP group size
- address is in sectors already */
- cmd.argument = (addr + (i * wp_group_size));
-
- mmc_ret = mmc_boot_send_command( &cmd );
-
- if(mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- return mmc_ret;
- }
-
- /* Checking ADDR_OUT_OF_RANGE error in CMD28 response */
- if(IS_ADDR_OUT_OF_RANGE(cmd.resp[0]))
- {
- return MMC_BOOT_E_FAILURE;
- }
-
- /* Sending CMD13 to check card status */
- do
- {
- mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
- if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
- break;
- } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
- (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Function to get Write Protect status of the given sector
- */
-static unsigned int mmc_boot_get_wp_status (struct mmc_boot_card* card,
- unsigned int sector)
-{
- unsigned int rc = MMC_BOOT_E_SUCCESS;
- memset(wp_status_buf, 0, 8);
-
- rc = mmc_boot_read_reg(card, 8, CMD31_SEND_WRITE_PROT_TYPE, sector,
- (unsigned int *) wp_status_buf);
- return rc;
-}
-
-/*
- * Test Function for setting Write protect for given sector
- */
-static unsigned int mmc_wp(unsigned int sector, unsigned int size,
- unsigned char set_clear_wp)
-{
- unsigned int rc = MMC_BOOT_E_SUCCESS;
-
- /* Checking whether group write protection feature is available */
- if(mmc_card.csd.wp_grp_enable)
- {
- rc = mmc_boot_get_wp_status(&mmc_card,sector);
- rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card,sector,size,set_clear_wp);
- rc = mmc_boot_get_wp_status(&mmc_card,sector);
- return rc;
- }
- else
- return MMC_BOOT_E_FAILURE;
-}
-
-void mmc_wp_test(void)
-{
- unsigned int mmc_ret=0;
- mmc_ret = mmc_wp(0xE06000,0x5000,1);
-}
-
-
-unsigned mmc_get_psn(void)
-{
- return mmc_card.cid.psn;
+/* data transfer rate in kbit/s */
+static const unsigned int xfer_rate_unit[] =
+ { 100, 1000, 10000, 100000, 0, 0, 0, 0 };
+/* data transfer rate value x 10*/
+static const unsigned int xfer_rate_value[] =
+ { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 };
+
+unsigned char mmc_slot = 0;
+unsigned int mmc_boot_mci_base = 0;
+
+static unsigned char ext_csd_buf[512];
+static unsigned char wp_status_buf[8];
+
+int mmc_clock_enable_disable(unsigned id, unsigned enable);
+int mmc_clock_get_rate(unsigned id);
+int mmc_clock_set_rate(unsigned id, unsigned rate);
+
+struct mmc_boot_host mmc_host;
+struct mmc_boot_card mmc_card;
+
+static unsigned int mmc_wp(unsigned int addr, unsigned int size,
+ unsigned char set_clear_wp);
+static unsigned int mmc_boot_send_ext_cmd(struct mmc_boot_card *card,
+ unsigned char *buf);
+static unsigned int mmc_boot_read_reg(struct mmc_boot_card *card,
+ unsigned int data_len,
+ unsigned int command,
+ unsigned int addr, unsigned int *out);
+
+unsigned int SWAP_ENDIAN(unsigned int val)
+{
+ return ((val & 0xFF) << 24) |
+ (((val >> 8) & 0xFF) << 16) | (((val >> 16) & 0xFF) << 8) | (val >>
+ 24);
}
-/*
- * Read/write data from/to SDC FIFO.
- */
-static unsigned int mmc_boot_fifo_data_transfer(unsigned int* data_ptr,
- unsigned int data_len,
- unsigned char direction)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
-#if MMC_BOOT_ADM
- adm_result_t ret;
- adm_dir_t adm_dir;
-
- if(direction == MMC_BOOT_DATA_READ)
- {
- adm_dir = ADM_MMC_READ;
- }
- else
- {
- adm_dir = ADM_MMC_WRITE;
- }
-
- ret = adm_transfer_mmc_data(mmc_slot,
- (unsigned char*) data_ptr,
- data_len,
- adm_dir);
-
- if(ret != ADM_RESULT_SUCCESS)
- {
- dprintf(CRITICAL, "MMC ADM transfer error: %d\n", ret);
- mmc_ret = MMC_BOOT_E_FAILURE;
- }
-#else
-
- if(direction == MMC_BOOT_DATA_READ)
- {
- mmc_ret = mmc_boot_fifo_read(data_ptr, data_len);
- }
- else
- {
- mmc_ret = mmc_boot_fifo_write(data_ptr, data_len);
- }
-#endif
- return mmc_ret;
-}
-
-/*
- * Read data to SDC FIFO.
- */
-static unsigned int mmc_boot_fifo_read(unsigned int* mmc_ptr,
- unsigned int data_len)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_status = 0;
- unsigned int mmc_count = 0;
- unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
- MMC_BOOT_MCI_STAT_DATA_TIMEOUT | \
- MMC_BOOT_MCI_STAT_RX_OVRRUN;
-
-
- /* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL
- bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
- DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
- Continue the reads until the whole transfer data is received */
-
- do
- {
- mmc_ret = MMC_BOOT_E_SUCCESS;
- mmc_status = readl( MMC_BOOT_MCI_STATUS );
-
- if( mmc_status & read_error )
- {
- mmc_ret = mmc_boot_status_error(mmc_status);
- break;
- }
-
- if( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL )
- {
- unsigned read_count = 1;
- if ( mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL)
- {
- read_count = MMC_BOOT_MCI_HFIFO_COUNT;
- }
-
- for (unsigned int i=0; i<read_count; i++)
- {
- /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
- *mmc_ptr = readl( MMC_BOOT_MCI_FIFO +
- ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
- mmc_ptr++;
- /* increase mmc_count by word size */
- mmc_count += sizeof( unsigned int );
- }
- /* quit if we have read enough of data */
- if (mmc_count == data_len)
- break;
- }
- else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_END )
- {
- break;
- }
- }while(1);
-
- return mmc_ret;
-}
-
-/*
- * Write data to SDC FIFO.
- */
-static unsigned int mmc_boot_fifo_write(unsigned int* mmc_ptr,
- unsigned int data_len)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int mmc_status = 0;
- unsigned int mmc_count = 0;
- unsigned int write_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
- MMC_BOOT_MCI_STAT_DATA_TIMEOUT | \
- MMC_BOOT_MCI_STAT_TX_UNDRUN;
-
-
- /* Write the transfer data to SDCC3 FIFO */
- do
- {
- mmc_ret = MMC_BOOT_E_SUCCESS;
- mmc_status = readl( MMC_BOOT_MCI_STATUS );
-
- if( mmc_status & write_error )
- {
- mmc_ret = mmc_boot_status_error(mmc_status);
- break;
- }
-
- /* Write the data in MCI_FIFO register as long as TXFIFO_FULL bit of
- MCI_STATUS register is 0. Continue the writes until the whole
- transfer data is written. */
- if (((data_len-mmc_count) >= MMC_BOOT_MCI_FIFO_SIZE/2) &&
- ( mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_HFULL ))
- {
- for (int i=0; i < MMC_BOOT_MCI_HFIFO_COUNT; i++ )
- {
- /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
- writel( *mmc_ptr, MMC_BOOT_MCI_FIFO +
- ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
- mmc_ptr++;
- /* increase mmc_count by word size */
- mmc_count += sizeof( unsigned int );
- }
-
- }
- else if( !( mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_FULL ) && (mmc_count != data_len))
- {
- /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
- writel( *mmc_ptr, MMC_BOOT_MCI_FIFO +
- ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
- mmc_ptr++;
- /* increase mmc_count by word size */
- mmc_count += sizeof( unsigned int );
- }
- else if((mmc_status & MMC_BOOT_MCI_STAT_DATA_END))
- {
- break; //success
- }
-
- } while(1);
- return mmc_ret;
-}
+/* Sets a timeout for read operation.
+ */
+static unsigned int
+mmc_boot_set_read_timeout(struct mmc_boot_host *host,
+ struct mmc_boot_card *card)
+{
+ unsigned int timeout_ns = 0;
-
-/*
- * CMD35_ERASE_GROUP_START
- */
-
-static unsigned int mmc_boot_send_erase_group_start(struct mmc_boot_card* card,
- unsigned long long data_addr )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- if( card == NULL)
- return MMC_BOOT_E_INVAL;
-
- memset((struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command));
-
- cmd.cmd_index = CMD35_ERASE_GROUP_START;
- cmd.argument = data_addr;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Checking for address error */
- if( IS_ADDR_OUT_OF_RANGE(cmd.resp[0]) )
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
-
- return MMC_BOOT_E_SUCCESS;
-
-}
-
-/*
- * CMD36 ERASE GROUP END
- */
-static unsigned int mmc_boot_send_erase_group_end(struct mmc_boot_card* card,
- unsigned long long data_addr )
-{
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
- if( card == NULL)
- return MMC_BOOT_E_INVAL;
-
- memset((struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command));
-
- cmd.cmd_index = CMD36_ERASE_GROUP_END;
- cmd.argument = data_addr;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1;
-
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Checking for address error */
- if(IS_ADDR_OUT_OF_RANGE(cmd.resp[0]))
- {
- return MMC_BOOT_E_BLOCKLEN_ERR;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * CMD38 ERASE
- */
-static unsigned int mmc_boot_send_erase(struct mmc_boot_card* card )
-{
-
- struct mmc_boot_command cmd;
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned int status;
-
- if( card == NULL)
- return MMC_BOOT_E_INVAL;
-
- memset((struct mmc_boot_command *)&cmd, 0,
- sizeof(struct mmc_boot_command));
-
- cmd.cmd_index = CMD38_ERASE;
- cmd.argument = 0x00000000;
- cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
- cmd.resp_type = MMC_BOOT_RESP_R1B;
-
- /* Checking if the card is in the transfer state */
- do
- {
- mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
- if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
- break;
- } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
- (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
- mmc_ret = mmc_boot_send_command( &cmd );
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- /* Checking for write protect */
- if( cmd.resp[0] & MMC_BOOT_R1_WP_ERASE_SKIP )
- {
- dprintf(CRITICAL , "Write protect enabled for sector \n");
- return;
- }
-
- /* Checking if the erase operation for the card is compelete */
- do
- {
- mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
- if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
- break;
- } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
- (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
-
- if( mmc_ret != MMC_BOOT_E_SUCCESS )
- {
- return mmc_ret;
- }
-
- return MMC_BOOT_E_SUCCESS;
-}
-
-/*
- * Function to erase data on the eMMC card
- */
-unsigned int mmc_erase_card ( unsigned long long data_addr, unsigned long long size)
-{
- unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
- unsigned long long erase_grp_size;
- unsigned long long data_end = 0x00000000;
- unsigned long long loop_count;
- unsigned int out[512] = {0};
-
- /* Converting size to sectors */
- size =size /512;
-
-
- if(ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF])
- {
- erase_grp_size = (512 * ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE]* 1024);
- erase_grp_size = erase_grp_size/512;
- }
- else
- {
- erase_grp_size = (mmc_card.csd.erase_grp_size + 1) *
- (mmc_card.csd.erase_grp_mult + 1);
- }
-
- if( erase_grp_size == 0 )
- {
- return MMC_BOOT_E_FAILURE;
- }
-
- if(size % erase_grp_size)
- {
- dprintf(CRITICAL, "Overflow beyond ERASE_GROUP_SIZE:%llu\n",
- (size % erase_grp_size));
-
- }
- loop_count = (size / erase_grp_size);
- /*
- *In case the partition size is less than the erase_grp_size
- 0 is written to the first block of the partition.
- */
- if( loop_count < 1 )
- {
- mmc_ret = mmc_write(data_addr, 512 ,(unsigned int *)out);
- if (mmc_ret != MMC_BOOT_E_SUCCESS)
- return mmc_ret;
- else
- return MMC_BOOT_E_SUCCESS;
- }
- else
- {
- data_addr = ( (mmc_card.type != MMC_BOOT_TYPE_MMCHC) &&
- (mmc_card.type != MMC_BOOT_TYPE_SDHC) )
- ? (unsigned int) data_addr :(unsigned int) (data_addr / 512);
- data_end = data_addr + erase_grp_size * (loop_count-1);
- }
-
- /* Sending CMD35 */
- mmc_ret = mmc_boot_send_erase_group_start (&mmc_card , data_addr);
- if( mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL, "Error %d: Failure sending erase group start "
- "command to the card (RCA:%x)\n", mmc_ret, mmc_card.rca);
- return mmc_ret;
- }
-
- /* Sending CMD36 */
- mmc_ret = mmc_boot_send_erase_group_end (&mmc_card , data_end - 1);
- if( mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL, "Error %d: Failure sending erase group end "
- "command to the card (RCA:%x)\n", mmc_ret, mmc_card.rca);
- return mmc_ret;
- }
-
- for( unsigned long long i = 0; i < loop_count ;i++ )
- {
- /* Sending CMD38 */
- mmc_ret = mmc_boot_send_erase (&mmc_card );
- if( mmc_ret != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL, "Error %d: Failure sending erase command "
- "to the card (RCA:%x)\n", mmc_ret, mmc_card.rca );
- return mmc_ret;
-
- }
- }
- dprintf(CRITICAL, "ERASE SUCCESSFULLY COMPLETED\n");
- return MMC_BOOT_E_SUCCESS;
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ if ((card->type == MMC_BOOT_TYPE_MMCHC)
+ || (card->type == MMC_BOOT_TYPE_SDHC)) {
+ card->rd_timeout_ns = 100000000;
+ } else if ((card->type == MMC_BOOT_TYPE_STD_SD)
+ || (card->type == MMC_BOOT_TYPE_STD_MMC)) {
+ timeout_ns = 10 * ((card->csd.taac_ns) +
+ (card->csd.nsac_clk_cycle /
+ (host->mclk_rate / 1000000000)));
+ card->rd_timeout_ns = timeout_ns;
+ } else {
+ return MMC_BOOT_E_NOT_SUPPORTED;
+ }
+
+ dprintf(SPEW, " Read timeout set: %d ns\n", card->rd_timeout_ns);
+
+ return MMC_BOOT_E_SUCCESS;
}
-struct mmc_boot_host* get_mmc_host ( void )
-{
- return &mmc_host;
-}
-
-struct mmc_boot_card* get_mmc_card( void )
-{
- return &mmc_card;
-}
-
+/* Sets a timeout for write operation.
+ */
+static unsigned int
+mmc_boot_set_write_timeout(struct mmc_boot_host *host,
+ struct mmc_boot_card *card)
+{
+ unsigned int timeout_ns = 0;
+
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ if ((card->type == MMC_BOOT_TYPE_MMCHC)
+ || (card->type == MMC_BOOT_TYPE_SDHC)) {
+ card->wr_timeout_ns = 100000000;
+ } else if (card->type == MMC_BOOT_TYPE_STD_SD
+ || (card->type == MMC_BOOT_TYPE_STD_MMC)) {
+ timeout_ns = 10 * ((card->csd.taac_ns) +
+ (card->csd.nsac_clk_cycle /
+ (host->mclk_rate / 1000000000)));
+ timeout_ns = timeout_ns << card->csd.r2w_factor;
+ card->wr_timeout_ns = timeout_ns;
+ } else {
+ return MMC_BOOT_E_NOT_SUPPORTED;
+ }
+
+ dprintf(SPEW, " Write timeout set: %d ns\n", card->wr_timeout_ns);
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Decodes CSD response received from the card. Note that we have defined only
+ * few of the CSD elements in csd structure. We'll only decode those values.
+ */
+static unsigned int
+mmc_boot_decode_and_save_csd(struct mmc_boot_card *card, unsigned int *raw_csd)
+{
+ unsigned int mmc_sizeof = 0;
+ unsigned int mmc_unit = 0;
+ unsigned int mmc_value = 0;
+ unsigned int mmc_temp = 0;
+
+ struct mmc_boot_csd mmc_csd;
+
+ if ((card == NULL) || (raw_csd == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ mmc_sizeof = sizeof(unsigned int) * 8;
+
+ mmc_csd.cmmc_structure = UNPACK_BITS(raw_csd, 126, 2, mmc_sizeof);
+
+ if ((card->type == MMC_BOOT_TYPE_SDHC)
+ || (card->type == MMC_BOOT_TYPE_STD_SD)) {
+ /* Parse CSD according to SD card spec. */
+
+ /* CSD register is little bit differnet for CSD version 2.0 High Capacity
+ * and CSD version 1.0/2.0 Standard memory cards. In Version 2.0 some of
+ * the fields have fixed values and it's not necessary for host to refer
+ * these fields in CSD sent by card */
+
+ if (mmc_csd.cmmc_structure == 1) {
+ /* CSD Version 2.0 */
+ mmc_csd.card_cmd_class =
+ UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof);
+ mmc_csd.write_blk_len = 512; /* Fixed value is 9 = 2^9 = 512 */
+ mmc_csd.read_blk_len = 512; /* Fixed value is 9 = 512 */
+ mmc_csd.r2w_factor = 0x2; /* Fixed value: 010b */
+ mmc_csd.c_size_mult = 0; /* not there in version 2.0 */
+ mmc_csd.c_size =
+ UNPACK_BITS(raw_csd, 48, 22, mmc_sizeof);
+ mmc_csd.nsac_clk_cycle =
+ UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100;
+
+//TODO: Investigate the nsac and taac. Spec suggests not using this for timeouts.
+
+ mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof);
+ mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof);
+ mmc_csd.taac_ns =
+ (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
+
+ mmc_csd.erase_blk_len = 1;
+ mmc_csd.read_blk_misalign = 0;
+ mmc_csd.write_blk_misalign = 0;
+ mmc_csd.read_blk_partial = 0;
+ mmc_csd.write_blk_partial = 0;
+
+ mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof);
+ mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof);
+ mmc_csd.tran_speed =
+ (xfer_rate_value[mmc_value] *
+ xfer_rate_unit[mmc_unit]) / 10;
+
+ mmc_csd.wp_grp_size = 0x0;
+ mmc_csd.wp_grp_enable = 0x0;
+ mmc_csd.perm_wp =
+ UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof);
+ mmc_csd.temp_wp =
+ UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof);
+
+ /* Calculate the card capcity */
+ card->capacity = (1 + mmc_csd.c_size) * 512 * 1024;
+ } else {
+ /* CSD Version 1.0 */
+ mmc_csd.card_cmd_class =
+ UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof);
+
+ mmc_temp = UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof);
+ mmc_csd.write_blk_len = (mmc_temp > 8
+ && mmc_temp <
+ 12) ? (1 << mmc_temp) : 512;
+
+ mmc_temp = UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof);
+ mmc_csd.read_blk_len = (mmc_temp > 8
+ && mmc_temp <
+ 12) ? (1 << mmc_temp) : 512;
+
+ mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof);
+ mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof);
+ mmc_csd.taac_ns =
+ (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
+
+ mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof);
+ mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof);
+ mmc_csd.tran_speed =
+ (xfer_rate_value[mmc_value] *
+ xfer_rate_unit[mmc_unit]) / 10;
+
+ mmc_csd.nsac_clk_cycle =
+ UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100;
+
+ mmc_csd.r2w_factor =
+ UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof);
+ mmc_csd.sector_size =
+ UNPACK_BITS(raw_csd, 39, 7, mmc_sizeof) + 1;
+
+ mmc_csd.erase_blk_len =
+ UNPACK_BITS(raw_csd, 46, 1, mmc_sizeof);
+ mmc_csd.read_blk_misalign =
+ UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof);
+ mmc_csd.write_blk_misalign =
+ UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof);
+ mmc_csd.read_blk_partial =
+ UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof);
+ mmc_csd.write_blk_partial =
+ UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof);
+
+ mmc_csd.c_size_mult =
+ UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof);
+ mmc_csd.c_size =
+ UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof);
+ mmc_csd.wp_grp_size =
+ UNPACK_BITS(raw_csd, 32, 7, mmc_sizeof);
+ mmc_csd.wp_grp_enable =
+ UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof);
+ mmc_csd.perm_wp =
+ UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof);
+ mmc_csd.temp_wp =
+ UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof);
+
+ /* Calculate the card capacity */
+ mmc_temp =
+ (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size +
+ 1);
+ card->capacity = mmc_temp * mmc_csd.read_blk_len;
+ }
+ } else {
+ /* Parse CSD according to MMC card spec. */
+ mmc_csd.spec_vers = UNPACK_BITS(raw_csd, 122, 4, mmc_sizeof);
+ mmc_csd.card_cmd_class =
+ UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof);
+ mmc_csd.write_blk_len =
+ 1 << UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof);
+ mmc_csd.read_blk_len =
+ 1 << UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof);
+ mmc_csd.r2w_factor = UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof);
+ mmc_csd.c_size_mult = UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof);
+ mmc_csd.c_size = UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof);
+ mmc_csd.nsac_clk_cycle =
+ UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100;
+
+ mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof);
+ mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof);
+ mmc_csd.taac_ns =
+ (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10;
+
+ mmc_csd.read_blk_misalign =
+ UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof);
+ mmc_csd.write_blk_misalign =
+ UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof);
+ mmc_csd.read_blk_partial =
+ UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof);
+ mmc_csd.write_blk_partial =
+ UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof);
+ mmc_csd.tran_speed = 0x00; /* Ignore -- no use of this value. */
+
+ mmc_csd.erase_grp_size =
+ UNPACK_BITS(raw_csd, 42, 5, mmc_sizeof);
+ mmc_csd.erase_grp_mult =
+ UNPACK_BITS(raw_csd, 37, 5, mmc_sizeof);
+ mmc_csd.wp_grp_size = UNPACK_BITS(raw_csd, 32, 5, mmc_sizeof);
+ mmc_csd.wp_grp_enable = UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof);
+ mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof);
+ mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof);
+
+ /* Calculate the card capcity */
+ if (mmc_csd.c_size != 0xFFF) {
+ /* For cards less than or equal to 2GB */
+ mmc_temp =
+ (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size +
+ 1);
+ card->capacity = mmc_temp * mmc_csd.read_blk_len;
+ } else {
+ /* For cards greater than 2GB, Ext CSD register's SEC_COUNT
+ * is used to calculate the size.
+ */
+ unsigned long long sec_count;
+
+ sec_count = (ext_csd_buf[215] << 24) |
+ (ext_csd_buf[214] << 16) |
+ (ext_csd_buf[213] << 8) | ext_csd_buf[212];
+
+ card->capacity = sec_count * 512;
+ }
+ }
+
+ /* save the information in card structure */
+ memcpy((struct mmc_boot_csd *)&card->csd,
+ (struct mmc_boot_csd *)&mmc_csd, sizeof(struct mmc_boot_csd));
+
+ dprintf(SPEW, "Decoded CSD fields:\n");
+ dprintf(SPEW, "cmmc_structure: %d\n", mmc_csd.cmmc_structure);
+ dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class);
+ dprintf(SPEW, "write_blk_len: %d\n", mmc_csd.write_blk_len);
+ dprintf(SPEW, "read_blk_len: %d\n", mmc_csd.read_blk_len);
+ dprintf(SPEW, "r2w_factor: %d\n", mmc_csd.r2w_factor);
+ dprintf(SPEW, "sector_size: %d\n", mmc_csd.sector_size);
+ dprintf(SPEW, "c_size_mult:%d\n", mmc_csd.c_size_mult);
+ dprintf(SPEW, "c_size: %d\n", mmc_csd.c_size);
+ dprintf(SPEW, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle);
+ dprintf(SPEW, "taac_ns: %d\n", mmc_csd.taac_ns);
+ dprintf(SPEW, "tran_speed: %d kbps\n", mmc_csd.tran_speed);
+ dprintf(SPEW, "erase_blk_len: %d\n", mmc_csd.erase_blk_len);
+ dprintf(SPEW, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign);
+ dprintf(SPEW, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign);
+ dprintf(SPEW, "read_blk_partial: %d\n", mmc_csd.read_blk_partial);
+ dprintf(SPEW, "write_blk_partial: %d\n", mmc_csd.write_blk_partial);
+ dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity);
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Decode CID sent by the card.
+ */
+static unsigned int
+mmc_boot_decode_and_save_cid(struct mmc_boot_card *card, unsigned int *raw_cid)
+{
+ struct mmc_boot_cid mmc_cid;
+ unsigned int mmc_sizeof = 0;
+ int i = 0;
+
+ if ((card == NULL) || (raw_cid == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ mmc_sizeof = sizeof(unsigned int) * 8;
+
+ if ((card->type == MMC_BOOT_TYPE_SDHC)
+ || (card->type == MMC_BOOT_TYPE_STD_SD)) {
+ mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof);
+ mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof);
+
+ for (i = 0; i < 5; i++) {
+ mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid,
+ (104 -
+ 8 * (i +
+ 1)),
+ 8,
+ mmc_sizeof);
+ }
+ mmc_cid.pnm[5] = 0;
+ mmc_cid.pnm[6] = 0;
+
+ mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof);
+ mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
+ mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof);
+ mmc_cid.year += 2000;
+ } else {
+ mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof);
+ mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof);
+
+ for (i = 0; i < 6; i++) {
+ mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid,
+ (104 -
+ 8 * (i +
+ 1)),
+ 8,
+ mmc_sizeof);
+ }
+ mmc_cid.pnm[6] = 0;
+
+ mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof);
+ mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
+ mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof);
+ mmc_cid.year += 1997;
+ }
+
+ /* save it in card database */
+ memcpy((struct mmc_boot_cid *)&card->cid,
+ (struct mmc_boot_cid *)&mmc_cid, sizeof(struct mmc_boot_cid));
+
+ dprintf(SPEW, "Decoded CID fields:\n");
+ dprintf(SPEW, "Manufacturer ID: %x\n", mmc_cid.mid);
+ dprintf(SPEW, "OEM ID: 0x%x\n", mmc_cid.oid);
+ dprintf(SPEW, "Product Name: %s\n", mmc_cid.pnm);
+ dprintf(SPEW, "Product revision: %d.%d\n", (mmc_cid.prv >> 4),
+ (mmc_cid.prv & 0xF));
+ dprintf(SPEW, "Product serial number: %X\n", mmc_cid.psn);
+ dprintf(SPEW, "Manufacturing date: %d %d\n", mmc_cid.month,
+ mmc_cid.year);
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Sends specified command to a card and waits for a response.
+ */
+static unsigned int mmc_boot_send_command(struct mmc_boot_command *cmd)
+{
+ unsigned int mmc_cmd = 0;
+ unsigned int mmc_status = 0;
+ unsigned int mmc_resp = 0;
+ unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
+ unsigned int cmd_index = 0;
+ int i = 0;
+
+ /* basic check */
+ if (cmd == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */
+ writel(cmd->argument, MMC_BOOT_MCI_ARGUMENT);
+
+ /* Writes to MCI port are not effective for 3 ticks of PCLK.
+ * The min pclk is 144KHz which gives 6.94 us/tick.
+ * Thus 21us == 3 ticks.
+ */
+ udelay(21);
+
+ /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */
+ /* 2a. Write command index in CMD_INDEX field */
+ cmd_index = cmd->cmd_index;
+ mmc_cmd |= cmd->cmd_index;
+ /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 */
+ if (cmd_index != CMD0_GO_IDLE_STATE) {
+ mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE;
+ }
+
+ /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */
+ if (IS_RESP_136_BITS(cmd->resp_type)) {
+ mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP;
+ }
+
+ /* 2d. Set INTERRUPT bit to 1 to disable command timeout */
+
+ /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream
+ mode data transfer */
+ if (cmd->xfer_mode == MMC_BOOT_XFER_MODE_STREAM) {
+ mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING;
+ }
+
+ /* 2f. Set ENABLE bit to 1 */
+ mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE;
+
+ /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of
+ write data transfer */
+ if ((cmd_index == CMD12_STOP_TRANSMISSION ||
+ cmd_index == CMD13_SEND_STATUS) && cmd->prg_enabled) {
+ mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA;
+ }
+
+ /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */
+ /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal
+ of CE-ATA device is enabled */
+
+ /* 2j. clear all static status bits */
+ writel(MMC_BOOT_MCI_STATIC_STATUS, MMC_BOOT_MCI_CLEAR);
+
+ /* 2k. Write to MMC_BOOT_MCI_CMD register */
+ writel(mmc_cmd, MMC_BOOT_MCI_CMD);
+
+ dprintf(SPEW, "Command sent: CMD%d MCI_CMD_REG:%x MCI_ARG:%x\n",
+ cmd_index, mmc_cmd, cmd->argument);
+
+ /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS
+ register */
+ do {
+ /* 3a. Read MCI_STATUS register */
+ while (readl(MMC_BOOT_MCI_STATUS) &
+ MMC_BOOT_MCI_STAT_CMD_ACTIVE) ;
+
+ mmc_status = readl(MMC_BOOT_MCI_STATUS);
+
+ /* 3b. CMD_SENT bit supposed to be set to 1 only after CMD0 is sent -
+ no response required. */
+ if ((cmd->resp_type == MMC_BOOT_RESP_NONE) &&
+ (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT)) {
+ break;
+ }
+
+ /* 3c. If CMD_TIMEOUT bit is set then no response was received */
+ else if (mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT) {
+ mmc_return = MMC_BOOT_E_TIMEOUT;
+ break;
+ }
+ /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's response was
+ received and CRC check passed
+ Spcial case for ACMD41: it seems to always fail CRC even if
+ the response is valid
+ */
+ else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END)
+ || (cmd_index == CMD1_SEND_OP_COND)
+ || (cmd_index == CMD8_SEND_IF_COND)) {
+ /* 3i. Read MCI_RESP_CMD register to verify that response index is
+ equal to command index */
+ mmc_resp = readl(MMC_BOOT_MCI_RESP_CMD) & 0x3F;
+
+ /* However, long response does not contain the command index field.
+ * In that case, response index field must be set to 111111b (0x3F) */
+ if ((mmc_resp == cmd_index) ||
+ (cmd->resp_type == MMC_BOOT_RESP_R2 ||
+ cmd->resp_type == MMC_BOOT_RESP_R3 ||
+ cmd->resp_type == MMC_BOOT_RESP_R6 ||
+ cmd->resp_type == MMC_BOOT_RESP_R7)) {
+ /* 3j. If resp index is equal to cmd index, read command resp
+ from MCI_RESPn registers
+ - MCI_RESP0/1/2/3 for CMD2/9/10
+ - MCI_RESP0 for all other registers */
+ if (IS_RESP_136_BITS(cmd->resp_type)) {
+ for (i = 0; i < 4; i++) {
+ cmd->resp[3 - i] =
+ readl(MMC_BOOT_MCI_RESP_0 +
+ (i * 4));
+
+ }
+ } else {
+ cmd->resp[0] =
+ readl(MMC_BOOT_MCI_RESP_0);
+ }
+ } else {
+ /* command index mis-match */
+ mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH;
+ }
+
+ dprintf(SPEW, "Command response received: %X\n",
+ cmd->resp[0]);
+ break;
+ }
+
+ /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response was recvd,
+ but CRC check failed. */
+ else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL)) {
+ if (cmd_index == ACMD41_SEND_OP_COND) {
+ cmd->resp[0] = readl(MMC_BOOT_MCI_RESP_0);
+ } else
+ mmc_return = MMC_BOOT_E_CRC_FAIL;
+ break;
+ }
+
+ }
+ while (1);
+
+ return mmc_return;
+}
+
+/*
+ * Reset all the cards to idle condition (CMD 0)
+ */
+static unsigned int mmc_boot_reset_cards(void)
+{
+ struct mmc_boot_command cmd;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = CMD0_GO_IDLE_STATE;
+ cmd.argument = 0; // stuff bits - ignored
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST;
+ cmd.resp_type = MMC_BOOT_RESP_NONE;
+
+ /* send command */
+ return mmc_boot_send_command(&cmd);
+}
+
+/*
+ * Send CMD1 to know whether the card supports host VDD profile or not.
+ */
+static unsigned int
+mmc_boot_send_op_cond(struct mmc_boot_host *host, struct mmc_boot_card *card)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_resp = 0;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD1 format:
+ * [31] Busy bit
+ * [30:29] Access mode
+ * [28:24] reserved
+ * [23:15] 2.7-3.6
+ * [14:8] 2.0-2.6
+ * [7] 1.7-1.95
+ * [6:0] reserved
+ */
+
+ cmd.cmd_index = CMD1_SEND_OP_COND;
+ cmd.argument = host->ocr;
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
+ cmd.resp_type = MMC_BOOT_RESP_R3;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Now it's time to examine response */
+ mmc_resp = cmd.resp[0];
+
+ /* Response contains card's ocr. Update card's information */
+ card->ocr = mmc_resp;
+
+ /* Check the response for busy status */
+ if (!(mmc_resp & MMC_BOOT_OCR_BUSY)) {
+ return MMC_BOOT_E_CARD_BUSY;
+ }
+
+ if (mmc_resp & MMC_BOOT_OCR_SEC_MODE) {
+ card->type = MMC_BOOT_TYPE_MMCHC;
+ } else {
+ card->type = MMC_BOOT_TYPE_STD_MMC;
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Request any card to send its uniquie card identification (CID) number (CMD2).
+ */
+static unsigned int mmc_boot_all_send_cid(struct mmc_boot_card *card)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD2 Format:
+ * [31:0] stuff bits
+ */
+ cmd.cmd_index = CMD2_ALL_SEND_CID;
+ cmd.argument = 0;
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
+ cmd.resp_type = MMC_BOOT_RESP_R2;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Response contains card's 128 bits CID register */
+ mmc_ret = mmc_boot_decode_and_save_cid(card, cmd.resp);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Ask any card to send it's relative card address (RCA).This RCA number is
+ * shorter than CID and is used by the host to address the card in future (CMD3)
+ */
+static unsigned int mmc_boot_send_relative_address(struct mmc_boot_card *card)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD3 Format:
+ * [31:0] stuff bits
+ */
+ if (card->type == MMC_BOOT_TYPE_SDHC
+ || card->type == MMC_BOOT_TYPE_STD_SD) {
+ cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
+ cmd.argument = 0;
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
+ cmd.resp_type = MMC_BOOT_RESP_R6;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ /* For sD, card will send RCA. Store it */
+ card->rca = (cmd.resp[0] >> 16);
+ } else {
+ cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR;
+ cmd.argument = (MMC_RCA << 16);
+ card->rca = (cmd.argument >> 16);
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Requests card to send it's CSD register's contents. (CMD9)
+ */
+static unsigned int
+mmc_boot_send_csd(struct mmc_boot_card *card, unsigned int *raw_csd)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_arg = 0;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD9 Format:
+ * [31:16] RCA
+ * [15:0] stuff bits
+ */
+ mmc_arg |= card->rca << 16;
+
+ cmd.cmd_index = CMD9_SEND_CSD;
+ cmd.argument = mmc_arg;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R2;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* response contains the card csd */
+ memcpy(raw_csd, cmd.resp, sizeof(cmd.resp));
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Selects a card by sending CMD7 to the card with its RCA.
+ * If RCA field is set as 0 ( or any other address ),
+ * the card will be de-selected. (CMD7)
+ */
+static unsigned int
+mmc_boot_select_card(struct mmc_boot_card *card, unsigned int rca)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_arg = 0;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD7 Format:
+ * [31:16] RCA
+ * [15:0] stuff bits
+ */
+ mmc_arg |= rca << 16;
+
+ cmd.cmd_index = CMD7_SELECT_DESELECT_CARD;
+ cmd.argument = mmc_arg;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ /* If we are deselecting card, we do not get response */
+ if (rca == card->rca && rca) {
+ if (card->type == MMC_BOOT_TYPE_SDHC
+ || card->type == MMC_BOOT_TYPE_STD_SD)
+ cmd.resp_type = MMC_BOOT_RESP_R1B;
+ else
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+ } else {
+ cmd.resp_type = MMC_BOOT_RESP_NONE;
+ }
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* As of now no need to look into a response. If it's required
+ * we'll explore later on */
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Send command to set block length.
+ */
+static unsigned int
+mmc_boot_set_block_len(struct mmc_boot_card *card, unsigned int block_len)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD16 Format:
+ * [31:0] block length
+ */
+
+ cmd.cmd_index = CMD16_SET_BLOCKLEN;
+ cmd.argument = block_len;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* If blocklength is larger than 512 bytes,
+ * the card sets BLOCK_LEN_ERROR bit. */
+ if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Requests the card to stop transmission of data.
+ */
+static unsigned int
+mmc_boot_send_stop_transmission(struct mmc_boot_card *card,
+ unsigned int prg_enabled)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD12 Format:
+ * [31:0] stuff bits
+ */
+
+ cmd.cmd_index = CMD12_STOP_TRANSMISSION;
+ cmd.argument = 0;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1B;
+ cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
+ cmd.prg_enabled = prg_enabled;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Get the card's current status
+ */
+static unsigned int
+mmc_boot_get_card_status(struct mmc_boot_card *card,
+ unsigned int prg_enabled, unsigned int *status)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD13 Format:
+ * [31:16] RCA
+ * [15:0] stuff bits
+ */
+ cmd.cmd_index = CMD13_SEND_STATUS;
+ cmd.argument = card->rca << 16;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+ cmd.prg_enabled = prg_enabled;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */
+ if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) {
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ *status = cmd.resp[0];
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Decode type of error caused during read and write
+ */
+static unsigned int mmc_boot_status_error(unsigned mmc_status)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
+ card/device during the data transfer */
+ if (mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL) {
+ mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
+ }
+ /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
+ the data timeout period without completing the transfer */
+ else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT) {
+ mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
+ }
+ /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
+ the card before empty storage for new received data was available.
+ Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */
+ else if (mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN) {
+ /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
+ for now */
+ mmc_ret = MMC_BOOT_E_RX_OVRRUN;
+ }
+ /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to
+ the card before new data for sending was available. Verify that bit
+ FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */
+ else if (mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN) {
+ /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now */
+ mmc_ret = MMC_BOOT_E_RX_OVRRUN;
+ }
+ return mmc_ret;
+}
+
+/*
+ * Send ext csd command.
+ */
+static unsigned int
+mmc_boot_send_ext_cmd(struct mmc_boot_card *card, unsigned char *buf)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_reg = 0;
+ unsigned int *mmc_ptr = (unsigned int *)buf;
+
+ memset(buf, 0, 512);
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* set block len */
+ if ((card->type != MMC_BOOT_TYPE_MMCHC)
+ && (card->type != MMC_BOOT_TYPE_SDHC)) {
+ mmc_ret = mmc_boot_set_block_len(card, 512);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
+ mmc_ret, (char *)(card->rca));
+ return mmc_ret;
+ }
+ }
+
+ /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
+ mmc_reg = readl(MMC_BOOT_MCI_CLK);
+ mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ writel(mmc_reg, MMC_BOOT_MCI_CLK);
+
+ /* Write data timeout period to MCI_DATA_TIMER register. */
+ /* Data timeout period should be in card bus clock periods */
+ mmc_reg = 0xFFFFFFFF;
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER);
+ writel(512, MMC_BOOT_MCI_DATA_LENGTH);
+
+ /* Set appropriate fields and write the MCI_DATA_CTL register. */
+ /* Set ENABLE bit to 1 to enable the data transfer. */
+ mmc_reg =
+ MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (512 <<
+ MMC_BOOT_MCI_BLKSIZE_POS);
+
+#if MMC_BOOT_ADM
+ mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
+#endif
+
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL);
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+ /* CMD8 */
+ cmd.cmd_index = CMD8_SEND_EXT_CSD;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+ cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Read the transfer data from SDCC FIFO. */
+ mmc_ret = mmc_boot_fifo_data_transfer(mmc_ptr, 512, MMC_BOOT_DATA_READ);
+
+ return mmc_ret;
+}
+
+/*
+ * Switch command
+ */
+static unsigned int
+mmc_boot_switch_cmd(struct mmc_boot_card *card,
+ unsigned access, unsigned index, unsigned value)
+{
+
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD6 Format:
+ * [31:26] set to 0
+ * [25:24] access
+ * [23:16] index
+ * [15:8] value
+ * [7:3] set to 0
+ * [2:0] cmd set
+ */
+ cmd.cmd_index = CMD6_SWITCH_FUNC;
+ cmd.argument |= (access << 24);
+ cmd.argument |= (index << 16);
+ cmd.argument |= (value << 8);
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1B;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * A command to set the data bus width for card. Set width to either
+ */
+static unsigned int
+mmc_boot_set_bus_width(struct mmc_boot_card *card, unsigned int width)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_reg = 0;
+ unsigned int mmc_width = 0;
+ unsigned int status;
+ unsigned int wait_count = 100;
+
+ if (width != MMC_BOOT_BUS_WIDTH_1_BIT) {
+ mmc_width = width - 1;
+ }
+
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ MMC_BOOT_EXT_CMMC_BUS_WIDTH, mmc_width);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Wait for the card to complete the switch command processing */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ wait_count--;
+ if (wait_count == 0) {
+ return MMC_BOOT_E_FAILURE;
+ }
+ }
+ while (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE);
+
+ /* set MCI_CLK accordingly */
+ mmc_reg = readl(MMC_BOOT_MCI_CLK);
+ mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE;
+ if (width == MMC_BOOT_BUS_WIDTH_1_BIT) {
+ mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT;
+ } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) {
+ mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT;
+ } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) {
+ mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT;
+ }
+ writel(mmc_reg, MMC_BOOT_MCI_CLK);
+
+ mdelay(10); // Giving some time to card to stabilize.
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * A command to start data read from card. Either a single block or
+ * multiple blocks can be read. Multiple blocks read will continuously
+ * transfer data from card to host unless requested to stop by issuing
+ * CMD12 - STOP_TRANSMISSION.
+ */
+static unsigned int
+mmc_boot_send_read_command(struct mmc_boot_card *card,
+ unsigned int xfer_type, unsigned int data_addr)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD17/18 Format:
+ * [31:0] Data Address
+ */
+ if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) {
+ cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK;
+ } else {
+ cmd.cmd_index = CMD17_READ_SINGLE_BLOCK;
+ }
+
+ cmd.argument = data_addr;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Response contains 32 bit Card status. Here we'll check
+ BLOCK_LEN_ERROR and ADDRESS_ERROR */
+ if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+ /* Misaligned address not matching block length */
+ if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) {
+ return MMC_BOOT_E_ADDRESS_ERR;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * A command to start data write to card. Either a single block or
+ * multiple blocks can be written. Multiple block write will continuously
+ * transfer data from host to card unless requested to stop by issuing
+ * CMD12 - STOP_TRANSMISSION.
+ */
+static unsigned int
+mmc_boot_send_write_command(struct mmc_boot_card *card,
+ unsigned int xfer_type, unsigned int data_addr)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD24/25 Format:
+ * [31:0] Data Address
+ */
+ if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) {
+ cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK;
+ } else {
+ cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK;
+ }
+
+ cmd.argument = data_addr;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Response contains 32 bit Card status. Here we'll check
+ BLOCK_LEN_ERROR and ADDRESS_ERROR */
+ if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+ /* Misaligned address not matching block length */
+ if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) {
+ return MMC_BOOT_E_ADDRESS_ERR;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Write data_len data to address specified by data_addr. data_len is
+ * multiple of blocks for block data transfer.
+ */
+unsigned int
+mmc_boot_write_to_card(struct mmc_boot_host *host,
+ struct mmc_boot_card *card,
+ unsigned long long data_addr,
+ unsigned int data_len, unsigned int *in)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_status = 0;
+ unsigned int mmc_reg = 0;
+ unsigned int addr;
+ unsigned int xfer_type;
+ unsigned int status;
+
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block
+ length. So no need to send CMD16. */
+ if ((card->type != MMC_BOOT_TYPE_MMCHC)
+ && (card->type != MMC_BOOT_TYPE_SDHC)) {
+ mmc_ret = mmc_boot_set_block_len(card, card->wr_block_len);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card\
+ (RCA:%s)\n", mmc_ret,
+ (char *)(card->rca));
+ return mmc_ret;
+ }
+ }
+
+ /* use multi-block mode to transfer for data larger than a block */
+ xfer_type =
+ (data_len >
+ card->
+ rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
+ MMC_BOOT_XFER_SINGLE_BLOCK;
+
+ /* For MMCHC/SDHC data address is specified in unit of 512B */
+ addr = ((card->type != MMC_BOOT_TYPE_MMCHC)
+ && (card->type !=
+ MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned
+ int)
+ (data_addr / 512);
+
+ /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
+ mmc_reg = readl(MMC_BOOT_MCI_CLK);
+ mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ writel(mmc_reg, MMC_BOOT_MCI_CLK);
+
+ /* Write data timeout period to MCI_DATA_TIMER register */
+ /* Data timeout period should be in card bus clock periods */
+ /*TODO: Fix timeout value */
+ mmc_reg = 0xFFFFFFFF;
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER);
+
+ /* Write the total size of the transfer data to MCI_DATA_LENGTH register */
+ writel(data_len, MMC_BOOT_MCI_DATA_LENGTH);
+
+ /* Send command to the card/device in order to start the write data xfer.
+ The possible commands are CMD24/25/53/60/61 */
+ mmc_ret = mmc_boot_send_write_command(card, xfer_type, addr);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure sending write command to the\
+ Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ return mmc_ret;
+ }
+
+ /* Set appropriate fields and write the MCI_DATA_CTL register */
+ /* Set ENABLE bit to 1 to enable the data transfer. */
+ mmc_reg = 0;
+ mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
+ /* Clear DIRECTION bit to 0 to enable transfer from host to card */
+ /* Clear MODE bit to 0 to enable block oriented data transfer. For
+ MMC cards only, if stream data transfer mode is desired, set
+ MODE bit to 1. */
+
+ /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */
+
+#if MMC_BOOT_ADM
+ mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
+#endif
+
+ /* Write size of block to be used during the data transfer to
+ BLOCKSIZE field */
+ mmc_reg |= card->wr_block_len << MMC_BOOT_MCI_BLKSIZE_POS;
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL);
+
+ /* write data to FIFO */
+ mmc_ret =
+ mmc_boot_fifo_data_transfer(in, data_len, MMC_BOOT_DATA_WRITE);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
+ Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ /* In case of any failure happening for multi block transfer */
+ if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK)
+ mmc_boot_send_stop_transmission(card, 1);
+ return mmc_ret;
+ }
+
+ /* Send command to the card/device in order to poll the de-assertion of
+ card/device BUSY condition. It is important to set PROG_ENA bit in
+ MCI_CLK register before sending the command. Possible commands are
+ CMD12/13. */
+ if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) {
+ mmc_ret = mmc_boot_send_stop_transmission(card, 1);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
+ command to the Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ return mmc_ret;
+ }
+ } else {
+ mmc_ret = mmc_boot_get_card_status(card, 1, &status);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure getting card status of Card(RCA:%x)\n",
+ mmc_ret, card->rca);
+ return mmc_ret;
+ }
+ }
+
+ /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. If
+ PROG_DONE bit is set to 1 it means that the card finished it programming
+ and stopped driving DAT0 line to 0 */
+ do {
+ mmc_status = readl(MMC_BOOT_MCI_STATUS);
+ if (mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE) {
+ break;
+ }
+ }
+ while (1);
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Adjust the interface speed to optimal speed
+ */
+static unsigned int
+mmc_boot_adjust_interface_speed(struct mmc_boot_host *host,
+ struct mmc_boot_card *card)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int status;
+ unsigned int wait_count = 100;
+
+ /* Setting HS_TIMING in EXT_CSD (CMD6) */
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ MMC_BOOT_EXT_CMMC_HS_TIMING, 1);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Wait for the card to complete the switch command processing */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ wait_count--;
+ if (wait_count == 0) {
+ return MMC_BOOT_E_FAILURE;
+ }
+ }
+ while (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE);
+
+ clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
+
+ host->mclk_rate = MMC_CLK_50MHZ;
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+static unsigned int
+mmc_boot_set_block_count(struct mmc_boot_card *card, unsigned int block_count)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if (card == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* CMD23 Format:
+ * [15:0] number of blocks
+ */
+
+ cmd.cmd_index = CMD23_SET_BLOCK_COUNT;
+ cmd.argument = block_count;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ if (cmd.resp[0] & MMC_BOOT_R1_OUT_OF_RANGE) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Reads a data of data_len from the address specified. data_len
+ * should be multiple of block size for block data transfer.
+ */
+unsigned int
+mmc_boot_read_from_card(struct mmc_boot_host *host,
+ struct mmc_boot_card *card,
+ unsigned long long data_addr,
+ unsigned int data_len, unsigned int *out)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_reg = 0;
+ unsigned int xfer_type;
+ unsigned int addr = 0;
+ unsigned char open_ended_read = 1;
+
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block
+ length. So no need to send CMD16. */
+ if ((card->type != MMC_BOOT_TYPE_MMCHC)
+ && (card->type != MMC_BOOT_TYPE_SDHC)) {
+ mmc_ret = mmc_boot_set_block_len(card, card->rd_block_len);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
+ mmc_ret, (char *)(card->rca));
+ return mmc_ret;
+ }
+ }
+
+ /* use multi-block mode to transfer for data larger than a block */
+ xfer_type =
+ (data_len >
+ card->
+ rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK :
+ MMC_BOOT_XFER_SINGLE_BLOCK;
+
+ if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) {
+ if ((card->type == MMC_BOOT_TYPE_MMCHC)
+ || (card->type == MMC_BOOT_TYPE_STD_MMC)) {
+ /* Virtio model does not support open-ended multi-block reads.
+ * So, block count must be set before sending read command.
+ * All SD cards do not support this command. Restrict this to MMC.
+ */
+ mmc_ret =
+ mmc_boot_set_block_count(card,
+ data_len /
+ (card->rd_block_len));
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure setting read block count for Card (RCA:%s)\n",
+ mmc_ret, (char *)(card->rca));
+ return mmc_ret;
+ }
+
+ open_ended_read = 0;
+ }
+ }
+
+ /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
+ /* Note: It's already enabled */
+
+ /* If Data Mover is used for data transfer then prepare Command
+ List Entry and enable the Data mover to work with SDCC2 */
+
+ /* Write data timeout period to MCI_DATA_TIMER register. */
+ /* Data timeout period should be in card bus clock periods */
+ mmc_reg = (unsigned long)(card->rd_timeout_ns / 1000000) *
+ (host->mclk_rate / 1000);
+ mmc_reg += 1000; // add some extra clock cycles to be safe
+ mmc_reg = mmc_reg / 2;
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER);
+
+ /* Write the total size of the transfer data to MCI_DATA_LENGTH
+ register. For block xfer it must be multiple of the block
+ size. */
+ writel(data_len, MMC_BOOT_MCI_DATA_LENGTH);
+
+ /* For MMCHC/SDHC data address is specified in unit of 512B */
+ addr = ((card->type != MMC_BOOT_TYPE_MMCHC)
+ && (card->type !=
+ MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned
+ int)
+ (data_addr / 512);
+
+ /* Set appropriate fields and write the MCI_DATA_CTL register. */
+ /* Set ENABLE bit to 1 to enable the data transfer. */
+ mmc_reg = 0;
+ mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE;
+ /* Clear DIRECTION bit to 1 to enable transfer from card to host */
+ mmc_reg |= MMC_BOOT_MCI_DATA_DIR;
+ /* Clear MODE bit to 0 to enable block oriented data transfer. For
+ MMC cards only, if stream data transfer mode is desired, set
+ MODE bit to 1. */
+
+ /* If DMA is to be used, Set DM_ENABLE bit to 1 */
+
+#if MMC_BOOT_ADM
+ mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
+#endif
+
+ /* Write size of block to be used during the data transfer to
+ BLOCKSIZE field */
+ mmc_reg |= (card->rd_block_len << MMC_BOOT_MCI_BLKSIZE_POS);
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL);
+
+ /* Send command to the card/device in order to start the read data
+ transfer. Possible commands: CMD17/18/53/60/61. */
+ mmc_ret = mmc_boot_send_read_command(card, xfer_type, addr);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure sending read command to the Card(RCA:%x)\n",
+ mmc_ret, card->rca);
+ return mmc_ret;
+ }
+
+ /* Read the transfer data from SDCC FIFO. */
+ mmc_ret =
+ mmc_boot_fifo_data_transfer(out, data_len, MMC_BOOT_DATA_READ);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
+ Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ return mmc_ret;
+ }
+
+ /* In case a multiple block transfer was performed, send CMD12 to the
+ card/device in order to indicate the end of read data transfer */
+ if ((xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) && open_ended_read) {
+ mmc_ret = mmc_boot_send_stop_transmission(card, 0);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \
+ command to the Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ return mmc_ret;
+ }
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Initialize host structure, set and enable clock-rate and power mode.
+ */
+unsigned int mmc_boot_init(struct mmc_boot_host *host)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_pwr = 0;
+
+ host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE;
+ host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY;
+
+ /* Initialize any clocks needed for SDC controller */
+ clock_init_mmc(mmc_slot);
+
+ /* Setup initial freq to 400KHz */
+ clock_config_mmc(mmc_slot, MMC_CLK_400KHZ);
+
+ host->mclk_rate = MMC_CLK_400KHZ;
+
+ /* set power mode */
+ /* give some time to reach minimum voltate */
+ mdelay(2);
+ mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP;
+ mmc_pwr |= MMC_BOOT_MCI_PWR_ON;
+ mmc_pwr |= MMC_BOOT_MCI_PWR_UP;
+ writel(mmc_pwr, MMC_BOOT_MCI_POWER);
+ /* some more time to stabilize voltage */
+ mdelay(2);
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Performs card identification process:
+ * - get card's unique identification number (CID)
+ * - get(for sd)/set (for mmc) relative card address (RCA)
+ * - get CSD
+ * - select the card, thus transitioning it to Transfer State
+ * - get Extended CSD (for mmc)
+ */
+static unsigned int
+mmc_boot_identify_card(struct mmc_boot_host *host, struct mmc_boot_card *card)
+{
+ unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
+ unsigned int raw_csd[4];
+
+ /* basic check */
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* Ask card to send its unique card identification (CID) number (CMD2) */
+ mmc_return = mmc_boot_all_send_cid(card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No. %d: Failure getting card's CID number!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* Ask card to send a relative card address (RCA) (CMD3) */
+ mmc_return = mmc_boot_send_relative_address(card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No. %d: Failure getting card's RCA!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* Get card's CSD register (CMD9) */
+ mmc_return = mmc_boot_send_csd(card, raw_csd);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure getting card's CSD information!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* Select the card (CMD7) */
+ mmc_return = mmc_boot_select_card(card, card->rca);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure selecting the Card with RCA: %x\n",
+ mmc_return, card->rca);
+ return mmc_return;
+ }
+
+ /* Set the card status as active */
+ card->status = MMC_BOOT_STATUS_ACTIVE;
+
+ if ((card->type == MMC_BOOT_TYPE_STD_MMC)
+ || (card->type == MMC_BOOT_TYPE_MMCHC)) {
+ /* For MMC cards, also get the extended csd */
+ mmc_return = mmc_boot_send_ext_cmd(card, ext_csd_buf);
+
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure getting card's ExtCSD information!\n",
+ mmc_return);
+
+ return mmc_return;
+ }
+
+ }
+
+ /* Decode and save the CSD register */
+ mmc_return = mmc_boot_decode_and_save_csd(card, raw_csd);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure decoding card's CSD information!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* Once CSD is received, set read and write timeout value now itself */
+ mmc_return = mmc_boot_set_read_timeout(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure setting Read Timeout value!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ mmc_return = mmc_boot_set_write_timeout(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure setting Write Timeout value!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+static unsigned int mmc_boot_send_app_cmd(unsigned int rca)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = CMD55_APP_CMD;
+ cmd.argument = (rca << 16);
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+static unsigned int mmc_boot_sd_init_card(struct mmc_boot_card *card)
+{
+ unsigned int i, mmc_ret;
+ unsigned int ocr_cmd_arg;
+ struct mmc_boot_command cmd;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* Send CMD8 to set interface condition */
+ for (i = 0; i < 3; i++) {
+ cmd.cmd_index = CMD8_SEND_IF_COND;
+ cmd.argument = MMC_BOOT_SD_HC_VOLT_SUPPLIED;
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
+ cmd.resp_type = MMC_BOOT_RESP_R7;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret == MMC_BOOT_E_SUCCESS) {
+ if (cmd.resp[0] != MMC_BOOT_SD_HC_VOLT_SUPPLIED)
+ return MMC_BOOT_E_FAILURE;
+ /* Set argument for ACMD41 */
+ ocr_cmd_arg = MMC_BOOT_SD_NEG_OCR | MMC_BOOT_SD_HC_HCS;
+ break;
+ }
+ mdelay(1);
+ }
+
+ /* Send ACMD41 to set operating condition */
+ /* Try for a max of 1 sec as per spec */
+ for (i = 0; i < 20; i++) {
+ mmc_ret = mmc_boot_send_app_cmd(0);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ cmd.cmd_index = ACMD41_SEND_OP_COND;
+ cmd.argument = ocr_cmd_arg;
+ cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP;
+ cmd.resp_type = MMC_BOOT_RESP_R3;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ } else if (cmd.resp[0] & MMC_BOOT_SD_DEV_READY) {
+ /* Check for HC */
+ if (cmd.resp[0] & (1 << 30)) {
+ card->type = MMC_BOOT_TYPE_SDHC;
+ } else {
+ card->type = MMC_BOOT_TYPE_STD_SD;
+ }
+ break;
+ }
+ mdelay(50);
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Routine to initialize MMC card. It resets a card to idle state, verify operating
+ * voltage and set the card inready state.
+ */
+static unsigned int
+mmc_boot_init_card(struct mmc_boot_host *host, struct mmc_boot_card *card)
+{
+ unsigned int mmc_retry = 0;
+ unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
+
+ /* basic check */
+ if ((host == NULL) || (card == NULL)) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* 1. Card Reset - CMD0 */
+ mmc_return = mmc_boot_reset_cards();
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.:%d: Failure resetting MMC cards!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* 2. Card Initialization process */
+
+ /* Send CMD1 to identify and reject cards that do not match host's VDD range
+ profile. Cards sends its OCR register in response.
+ */
+ mmc_retry = 0;
+ do {
+ mmc_return = mmc_boot_send_op_cond(host, card);
+ /* Card returns busy status. We'll retry again! */
+ if (mmc_return == MMC_BOOT_E_CARD_BUSY) {
+ mmc_retry++;
+ mdelay(1);
+ continue;
+ } else if (mmc_return == MMC_BOOT_E_SUCCESS) {
+ break;
+ } else {
+ dprintf(CRITICAL,
+ "Error No. %d: Failure Initializing MMC Card!\n",
+ mmc_return);
+
+ /* Check for sD card */
+ mmc_return = mmc_boot_sd_init_card(card);
+ return mmc_return;
+ }
+ }
+ while (mmc_retry < host->cmd_retry);
+
+ /* If card still returned busy status we are out of luck.
+ * Card cannot be initialized */
+ if (mmc_return == MMC_BOOT_E_CARD_BUSY) {
+ dprintf(CRITICAL, "Error No. %d: Card has busy status set. \
+ Initialization not completed\n", mmc_return);
+ return MMC_BOOT_E_CARD_BUSY;
+ }
+ return MMC_BOOT_E_SUCCESS;
+}
+
+static unsigned int
+mmc_boot_set_sd_bus_width(struct mmc_boot_card *card, unsigned int width)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int sd_reg;
+
+ mmc_ret = mmc_boot_send_app_cmd(card->rca);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* Send ACMD6 to set bus width */
+ cmd.cmd_index = ACMD6_SET_BUS_WIDTH;
+ /* 10 => 4 bit wide */
+ if (width == MMC_BOOT_BUS_WIDTH_1_BIT) {
+ cmd.argument = 0;
+ } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) {
+ cmd.argument = (1 << 1);
+ }
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* set MCI_CLK accordingly */
+ sd_reg = readl(MMC_BOOT_MCI_CLK);
+ sd_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE;
+ if (width == MMC_BOOT_BUS_WIDTH_1_BIT) {
+ sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT;
+ } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) {
+ sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT;
+ } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) {
+ sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT;
+ }
+ writel(sd_reg, MMC_BOOT_MCI_CLK);
+
+ mdelay(10); // Giving some time to card to stabilize.
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+static unsigned int
+mmc_boot_set_sd_hs(struct mmc_boot_host *host, struct mmc_boot_card *card)
+{
+ unsigned char sw_buf[64];
+ unsigned int mmc_ret;
+
+ /* CMD6 is a data transfer command. sD card returns 512 bits of data */
+ /* Refer 4.3.10 of sD card specification 3.0 */
+ mmc_ret =
+ mmc_boot_read_reg(card, 64, CMD6_SWITCH_FUNC, MMC_BOOT_SD_SWITCH_HS,
+ (unsigned int *)&sw_buf);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ mdelay(1);
+
+ clock_config_mmc(mmc_slot, MMC_CLK_50MHZ);
+
+ host->mclk_rate = MMC_CLK_50MHZ;
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Performs initialization and identification of all the MMC cards connected
+ * to the host.
+ */
+
+static unsigned int
+mmc_boot_init_and_identify_cards(struct mmc_boot_host *host,
+ struct mmc_boot_card *card)
+{
+ unsigned int mmc_return = MMC_BOOT_E_SUCCESS;
+ unsigned int status;
+
+ /* Basic check */
+ if (host == NULL) {
+ return MMC_BOOT_E_INVAL;
+ }
+
+ /* Initialize MMC card structure */
+ card->status = MMC_BOOT_STATUS_INACTIVE;
+ card->rd_block_len = MMC_BOOT_RD_BLOCK_LEN;
+ card->wr_block_len = MMC_BOOT_WR_BLOCK_LEN;
+
+ /* Start initialization process (CMD0 & CMD1) */
+ mmc_return = mmc_boot_init_card(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ return mmc_return;
+ }
+
+ /* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */
+ mmc_return = mmc_boot_identify_card(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ return mmc_return;
+ }
+
+ if (card->type == MMC_BOOT_TYPE_SDHC
+ || card->type == MMC_BOOT_TYPE_STD_SD) {
+ /* Setting sD card to high speed without checking card's capability.
+ Cards that do not support high speed may fail to boot */
+ mmc_return = mmc_boot_set_sd_hs(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ return mmc_return;
+ }
+
+ mmc_return =
+ mmc_boot_set_sd_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Couldn't set 4bit mode for sD card\n");
+ mmc_return =
+ mmc_boot_set_sd_bus_width(card,
+ MMC_BOOT_BUS_WIDTH_1_BIT);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failed in setting bus width!\n",
+ mmc_return);
+ return mmc_return;
+ }
+ }
+ } else {
+ /* set interface speed */
+ mmc_return = mmc_boot_adjust_interface_speed(host, card);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Error adjusting interface speed!\n",
+ mmc_return);
+ return mmc_return;
+ }
+
+ /* enable wide bus */
+ mmc_return =
+ mmc_boot_set_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n",
+ mmc_return, card->rca);
+ return mmc_return;
+ }
+ }
+
+ /* Just checking whether we're in TRAN state after changing speed and bus width */
+ mmc_return = mmc_boot_get_card_status(card, 0, &status);
+ if (mmc_return != MMC_BOOT_E_SUCCESS) {
+ return mmc_return;
+ }
+
+ if (MMC_BOOT_CARD_STATUS(status) != MMC_BOOT_TRAN_STATE)
+ return MMC_BOOT_E_FAILURE;
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+void mmc_display_ext_csd(void)
+{
+ dprintf(SPEW, "part_config: %x\n", ext_csd_buf[179]);
+ dprintf(SPEW, "erase_group_def: %x\n", ext_csd_buf[175]);
+ dprintf(SPEW, "user_wp: %x\n", ext_csd_buf[171]);
+}
+
+void mmc_display_csd(void)
+{
+ dprintf(SPEW, "erase_grpsize: %d\n", mmc_card.csd.erase_grp_size);
+ dprintf(SPEW, "erase_grpmult: %d\n", mmc_card.csd.erase_grp_mult);
+ dprintf(SPEW, "wp_grpsize: %d\n", mmc_card.csd.wp_grp_size);
+ dprintf(SPEW, "wp_grpen: %d\n", mmc_card.csd.wp_grp_enable);
+ dprintf(SPEW, "perm_wp: %d\n", mmc_card.csd.perm_wp);
+ dprintf(SPEW, "temp_wp: %d\n", mmc_card.csd.temp_wp);
+}
+
+/*
+ * Entry point to MMC boot process
+ */
+unsigned int mmc_boot_main(unsigned char slot, unsigned int base)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ memset((struct mmc_boot_host *)&mmc_host, 0,
+ sizeof(struct mmc_boot_host));
+ memset((struct mmc_boot_card *)&mmc_card, 0,
+ sizeof(struct mmc_boot_card));
+
+ mmc_slot = slot;
+ mmc_boot_mci_base = base;
+
+ /* Initialize necessary data structure and enable/set clock and power */
+ dprintf(SPEW, " Initializing MMC host data structure and clock!\n");
+ mmc_ret = mmc_boot_init(&mmc_host);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "MMC Boot: Error Initializing MMC Card!!!\n");
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ /* Initialize and identify cards connected to host */
+ mmc_ret = mmc_boot_init_and_identify_cards(&mmc_host, &mmc_card);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "MMC Boot: Failed detecting MMC/SDC @ slot%d\n", slot);
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ mmc_display_csd();
+ mmc_display_ext_csd();
+
+ mmc_ret = partition_read_table(&mmc_host, &mmc_card);
+ return mmc_ret;
+}
+
+/*
+ * MMC write function
+ */
+unsigned int
+mmc_write(unsigned long long data_addr, unsigned int data_len, unsigned int *in)
+{
+ int val = 0;
+ unsigned int write_size = ((unsigned)(0xFFFFFF / 512)) * 512;
+ unsigned offset = 0;
+ unsigned int *sptr = in;
+
+ if (data_len % 512)
+ data_len = ROUND_TO_PAGE(data_len, 511);
+
+ while (data_len > write_size) {
+ val = mmc_boot_write_to_card(&mmc_host, &mmc_card,
+ data_addr + offset, write_size,
+ sptr);
+ if (val) {
+ return val;
+ }
+
+ sptr += (write_size / sizeof(unsigned));
+ offset += write_size;
+ data_len -= write_size;
+ }
+ if (data_len) {
+ val = mmc_boot_write_to_card(&mmc_host, &mmc_card,
+ data_addr + offset, data_len,
+ sptr);
+ }
+ return val;
+}
+
+/*
+ * MMC read function
+ */
+
+unsigned int
+mmc_read(unsigned long long data_addr, unsigned int *out, unsigned int data_len)
+{
+ int val = 0;
+ val =
+ mmc_boot_read_from_card(&mmc_host, &mmc_card, data_addr, data_len,
+ out);
+ return val;
+}
+
+/*
+ * Function to read registers from MMC or SD card
+ */
+static unsigned int
+mmc_boot_read_reg(struct mmc_boot_card *card,
+ unsigned int data_len,
+ unsigned int command, unsigned int addr, unsigned int *out)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_reg = 0;
+
+ /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
+ mmc_reg = readl(MMC_BOOT_MCI_CLK);
+ mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+ writel(mmc_reg, MMC_BOOT_MCI_CLK);
+
+ /* Write data timeout period to MCI_DATA_TIMER register. */
+ /* Data timeout period should be in card bus clock periods */
+ mmc_reg = 0xFFFFFFFF;
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER);
+ writel(data_len, MMC_BOOT_MCI_DATA_LENGTH);
+
+ /* Set appropriate fields and write the MCI_DATA_CTL register. */
+ /* Set ENABLE bit to 1 to enable the data transfer. */
+ mmc_reg =
+ MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (data_len <<
+ MMC_BOOT_MCI_BLKSIZE_POS);
+
+#if MMC_BOOT_ADM
+ mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE;
+#endif
+
+ writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL);
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = command;
+ cmd.argument = addr;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ /* send command */
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Read the transfer data from SDCC FIFO. */
+ mmc_ret =
+ mmc_boot_fifo_data_transfer(out, data_len, MMC_BOOT_DATA_READ);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
+ Card(RCA:%x)\n", mmc_ret,
+ card->rca);
+ return mmc_ret;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Function to set/clear power-on write protection for the user area partitions
+ */
+static unsigned int
+mmc_boot_set_clr_power_on_wp_user(struct mmc_boot_card *card,
+ unsigned int addr,
+ unsigned int size, unsigned char set_clear_wp)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int wp_group_size, loop_count;
+ unsigned int status;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ /* Disabling PERM_WP for USER AREA (CMD6) */
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ MMC_BOOT_EXT_USER_WP,
+ MMC_BOOT_US_PERM_WP_DIS);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Sending CMD13 to check card status */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+ break;
+ }
+ while ((mmc_ret == MMC_BOOT_E_SUCCESS) &&
+ (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ mmc_ret = mmc_boot_send_ext_cmd(card, ext_csd_buf);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Make sure power-on write protection for user area is not disabled
+ and permanent write protection for user area is not enabled */
+
+ if ((IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PERM_WP_EN))
+ ||
+ (IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PWR_WP_DIS)))
+ {
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) {
+ /* wp_group_size = 512KB * HC_WP_GRP_SIZE * HC_ERASE_GRP_SIZE.
+ Getting write protect group size in sectors here. */
+
+ wp_group_size =
+ (512 * 1024) * ext_csd_buf[MMC_BOOT_EXT_HC_WP_GRP_SIZE] *
+ ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] /
+ MMC_BOOT_WR_BLOCK_LEN;
+ } else {
+ /* wp_group_size = (WP_GRP_SIZE + 1) * (ERASE_GRP_SIZE + 1)
+ * (ERASE_GRP_MULT + 1).
+ This is defined as the number of write blocks directly */
+
+ wp_group_size = (card->csd.erase_grp_size + 1) *
+ (card->csd.erase_grp_mult + 1) * (card->csd.wp_grp_size +
+ 1);
+ }
+
+ if (wp_group_size == 0) {
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ /* Setting POWER_ON_WP for USER AREA (CMD6) */
+
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ MMC_BOOT_EXT_USER_WP,
+ MMC_BOOT_US_PWR_WP_EN);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Sending CMD13 to check card status */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+ break;
+ }
+ while ((mmc_ret == MMC_BOOT_E_SUCCESS) &&
+ (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Calculating the loop count for sending SET_WRITE_PROTECT (CMD28)
+ or CLEAR_WRITE_PROTECT (CMD29).
+ We are write protecting the partitions in blocks of write protect
+ group sizes only */
+
+ if (size % wp_group_size) {
+ loop_count = (size / wp_group_size) + 1;
+ } else {
+ loop_count = (size / wp_group_size);
+ }
+
+ if (set_clear_wp)
+ cmd.cmd_index = CMD28_SET_WRITE_PROTECT;
+ else
+ cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT;
+
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1B;
+
+ for (unsigned int i = 0; i < loop_count; i++) {
+ /* Sending CMD28 for each WP group size
+ address is in sectors already */
+ cmd.argument = (addr + (i * wp_group_size));
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Checking ADDR_OUT_OF_RANGE error in CMD28 response */
+ if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) {
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ /* Sending CMD13 to check card status */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+ break;
+ }
+ while ((mmc_ret == MMC_BOOT_E_SUCCESS) &&
+ (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Function to get Write Protect status of the given sector
+ */
+static unsigned int
+mmc_boot_get_wp_status(struct mmc_boot_card *card, unsigned int sector)
+{
+ unsigned int rc = MMC_BOOT_E_SUCCESS;
+ memset(wp_status_buf, 0, 8);
+
+ rc = mmc_boot_read_reg(card, 8, CMD31_SEND_WRITE_PROT_TYPE, sector,
+ (unsigned int *)wp_status_buf);
+ return rc;
+}
+
+/*
+ * Test Function for setting Write protect for given sector
+ */
+static unsigned int
+mmc_wp(unsigned int sector, unsigned int size, unsigned char set_clear_wp)
+{
+ unsigned int rc = MMC_BOOT_E_SUCCESS;
+
+ /* Checking whether group write protection feature is available */
+ if (mmc_card.csd.wp_grp_enable) {
+ rc = mmc_boot_get_wp_status(&mmc_card, sector);
+ rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size,
+ set_clear_wp);
+ rc = mmc_boot_get_wp_status(&mmc_card, sector);
+ return rc;
+ } else
+ return MMC_BOOT_E_FAILURE;
+}
+
+void mmc_wp_test(void)
+{
+ unsigned int mmc_ret = 0;
+ mmc_ret = mmc_wp(0xE06000, 0x5000, 1);
+}
+
+unsigned mmc_get_psn(void)
+{
+ return mmc_card.cid.psn;
+}
+
+/*
+ * Read/write data from/to SDC FIFO.
+ */
+static unsigned int
+mmc_boot_fifo_data_transfer(unsigned int *data_ptr,
+ unsigned int data_len, unsigned char direction)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+#if MMC_BOOT_ADM
+ adm_result_t ret;
+ adm_dir_t adm_dir;
+
+ if (direction == MMC_BOOT_DATA_READ) {
+ adm_dir = ADM_MMC_READ;
+ } else {
+ adm_dir = ADM_MMC_WRITE;
+ }
+
+ ret = adm_transfer_mmc_data(mmc_slot,
+ (unsigned char *)data_ptr, data_len,
+ adm_dir);
+
+ if (ret != ADM_RESULT_SUCCESS) {
+ dprintf(CRITICAL, "MMC ADM transfer error: %d\n", ret);
+ mmc_ret = MMC_BOOT_E_FAILURE;
+ }
+#else
+
+ if (direction == MMC_BOOT_DATA_READ) {
+ mmc_ret = mmc_boot_fifo_read(data_ptr, data_len);
+ } else {
+ mmc_ret = mmc_boot_fifo_write(data_ptr, data_len);
+ }
+#endif
+ return mmc_ret;
+}
+
+/*
+ * Read data to SDC FIFO.
+ */
+static unsigned int
+mmc_boot_fifo_read(unsigned int *mmc_ptr, unsigned int data_len)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_status = 0;
+ unsigned int mmc_count = 0;
+ unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL |
+ MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN;
+
+ /* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL
+ bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
+ DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
+ Continue the reads until the whole transfer data is received */
+
+ do {
+ mmc_ret = MMC_BOOT_E_SUCCESS;
+ mmc_status = readl(MMC_BOOT_MCI_STATUS);
+
+ if (mmc_status & read_error) {
+ mmc_ret = mmc_boot_status_error(mmc_status);
+ break;
+ }
+
+ if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) {
+ unsigned read_count = 1;
+ if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) {
+ read_count = MMC_BOOT_MCI_HFIFO_COUNT;
+ }
+
+ for (unsigned int i = 0; i < read_count; i++) {
+ /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */
+ *mmc_ptr = readl(MMC_BOOT_MCI_FIFO +
+ (mmc_count %
+ MMC_BOOT_MCI_FIFO_SIZE));
+ mmc_ptr++;
+ /* increase mmc_count by word size */
+ mmc_count += sizeof(unsigned int);
+ }
+ /* quit if we have read enough of data */
+ if (mmc_count == data_len)
+ break;
+ } else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) {
+ break;
+ }
+ }
+ while (1);
+
+ return mmc_ret;
+}
+
+/*
+ * Write data to SDC FIFO.
+ */
+static unsigned int
+mmc_boot_fifo_write(unsigned int *mmc_ptr, unsigned int data_len)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int mmc_status = 0;
+ unsigned int mmc_count = 0;
+ unsigned int write_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL |
+ MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_TX_UNDRUN;
+
+ /* Write the transfer data to SDCC3 FIFO */
+ do {
+ mmc_ret = MMC_BOOT_E_SUCCESS;
+ mmc_status = readl(MMC_BOOT_MCI_STATUS);
+
+ if (mmc_status & write_error) {
+ mmc_ret = mmc_boot_status_error(mmc_status);
+ break;
+ }
+
+ /* Write the data in MCI_FIFO register as long as TXFIFO_FULL bit of
+ MCI_STATUS register is 0. Continue the writes until the whole
+ transfer data is written. */
+ if (((data_len - mmc_count) >= MMC_BOOT_MCI_FIFO_SIZE / 2) &&
+ (mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_HFULL)) {
+ for (int i = 0; i < MMC_BOOT_MCI_HFIFO_COUNT; i++) {
+ /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */
+ writel(*mmc_ptr, MMC_BOOT_MCI_FIFO +
+ (mmc_count % MMC_BOOT_MCI_FIFO_SIZE));
+ mmc_ptr++;
+ /* increase mmc_count by word size */
+ mmc_count += sizeof(unsigned int);
+ }
+
+ } else if (!(mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_FULL)
+ && (mmc_count != data_len)) {
+ /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */
+ writel(*mmc_ptr, MMC_BOOT_MCI_FIFO +
+ (mmc_count % MMC_BOOT_MCI_FIFO_SIZE));
+ mmc_ptr++;
+ /* increase mmc_count by word size */
+ mmc_count += sizeof(unsigned int);
+ } else if ((mmc_status & MMC_BOOT_MCI_STAT_DATA_END)) {
+ break; //success
+ }
+
+ }
+ while (1);
+ return mmc_ret;
+}
+
+/*
+ * CMD35_ERASE_GROUP_START
+ */
+
+static unsigned int
+mmc_boot_send_erase_group_start(struct mmc_boot_card *card,
+ unsigned long long data_addr)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ if (card == NULL)
+ return MMC_BOOT_E_INVAL;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = CMD35_ERASE_GROUP_START;
+ cmd.argument = data_addr;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Checking for address error */
+ if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+
+}
+
+/*
+ * CMD36 ERASE GROUP END
+ */
+static unsigned int
+mmc_boot_send_erase_group_end(struct mmc_boot_card *card,
+ unsigned long long data_addr)
+{
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+ if (card == NULL)
+ return MMC_BOOT_E_INVAL;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = CMD36_ERASE_GROUP_END;
+ cmd.argument = data_addr;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1;
+
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Checking for address error */
+ if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) {
+ return MMC_BOOT_E_BLOCKLEN_ERR;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * CMD38 ERASE
+ */
+static unsigned int mmc_boot_send_erase(struct mmc_boot_card *card)
+{
+
+ struct mmc_boot_command cmd;
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned int status;
+
+ if (card == NULL)
+ return MMC_BOOT_E_INVAL;
+
+ memset((struct mmc_boot_command *)&cmd, 0,
+ sizeof(struct mmc_boot_command));
+
+ cmd.cmd_index = CMD38_ERASE;
+ cmd.argument = 0x00000000;
+ cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+ cmd.resp_type = MMC_BOOT_RESP_R1B;
+
+ /* Checking if the card is in the transfer state */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+ break;
+ }
+ while ((mmc_ret == MMC_BOOT_E_SUCCESS) &&
+ (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+ mmc_ret = mmc_boot_send_command(&cmd);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ /* Checking for write protect */
+ if (cmd.resp[0] & MMC_BOOT_R1_WP_ERASE_SKIP) {
+ dprintf(CRITICAL, "Write protect enabled for sector \n");
+ return;
+ }
+
+ /* Checking if the erase operation for the card is compelete */
+ do {
+ mmc_ret = mmc_boot_get_card_status(card, 0, &status);
+ if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+ break;
+ }
+ while ((mmc_ret == MMC_BOOT_E_SUCCESS) &&
+ (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ return mmc_ret;
+ }
+
+ return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Function to erase data on the eMMC card
+ */
+unsigned int
+mmc_erase_card(unsigned long long data_addr, unsigned long long size)
+{
+ unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+ unsigned long long erase_grp_size;
+ unsigned long long data_end = 0x00000000;
+ unsigned long long loop_count;
+ unsigned int out[512] = { 0 };
+
+ /* Converting size to sectors */
+ size = size / 512;
+
+ if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) {
+ erase_grp_size =
+ (512 * ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] * 1024);
+ erase_grp_size = erase_grp_size / 512;
+ } else {
+ erase_grp_size = (mmc_card.csd.erase_grp_size + 1) *
+ (mmc_card.csd.erase_grp_mult + 1);
+ }
+
+ if (erase_grp_size == 0) {
+ return MMC_BOOT_E_FAILURE;
+ }
+
+ if (size % erase_grp_size) {
+ dprintf(CRITICAL, "Overflow beyond ERASE_GROUP_SIZE:%llu\n",
+ (size % erase_grp_size));
+
+ }
+ loop_count = (size / erase_grp_size);
+ /*
+ *In case the partition size is less than the erase_grp_size
+ 0 is written to the first block of the partition.
+ */
+ if (loop_count < 1) {
+ mmc_ret = mmc_write(data_addr, 512, (unsigned int *)out);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS)
+ return mmc_ret;
+ else
+ return MMC_BOOT_E_SUCCESS;
+ } else {
+ data_addr = ((mmc_card.type != MMC_BOOT_TYPE_MMCHC) &&
+ (mmc_card.type != MMC_BOOT_TYPE_SDHC))
+ ? (unsigned int)data_addr : (unsigned int)(data_addr / 512);
+ data_end = data_addr + erase_grp_size * (loop_count - 1);
+ }
+
+ /* Sending CMD35 */
+ mmc_ret = mmc_boot_send_erase_group_start(&mmc_card, data_addr);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error %d: Failure sending erase group start "
+ "command to the card (RCA:%x)\n", mmc_ret,
+ mmc_card.rca);
+ return mmc_ret;
+ }
+
+ /* Sending CMD36 */
+ mmc_ret = mmc_boot_send_erase_group_end(&mmc_card, data_end - 1);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Error %d: Failure sending erase group end "
+ "command to the card (RCA:%x)\n", mmc_ret,
+ mmc_card.rca);
+ return mmc_ret;
+ }
+
+ for (unsigned long long i = 0; i < loop_count; i++) {
+ /* Sending CMD38 */
+ mmc_ret = mmc_boot_send_erase(&mmc_card);
+ if (mmc_ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL,
+ "Error %d: Failure sending erase command "
+ "to the card (RCA:%x)\n", mmc_ret,
+ mmc_card.rca);
+ return mmc_ret;
+
+ }
+ }
+ dprintf(CRITICAL, "ERASE SUCCESSFULLY COMPLETED\n");
+ return MMC_BOOT_E_SUCCESS;
+}
+
+struct mmc_boot_host *get_mmc_host(void)
+{
+ return &mmc_host;
+}
+
+struct mmc_boot_card *get_mmc_card(void)
+{
+ return &mmc_card;
+}
diff --git a/platform/msm_shared/nand.c b/platform/msm_shared/nand.c
index e710082..4d1cc98 100644
--- a/platform/msm_shared/nand.c
+++ b/platform/msm_shared/nand.c
@@ -45,15 +45,14 @@
void platform_config_interleaved_mode_gpios(void);
typedef struct dmov_ch dmov_ch;
-struct dmov_ch
-{
+struct dmov_ch {
volatile unsigned cmd;
volatile unsigned result;
volatile unsigned status;
volatile unsigned config;
};
-static void dmov_prep_ch(dmov_ch *ch, unsigned id)
+static void dmov_prep_ch(dmov_ch * ch, unsigned id)
{
ch->cmd = DMOV_CMD_PTR(id);
ch->result = DMOV_RSLT(id);
@@ -96,12 +95,12 @@
writel(DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(paddr(ptr)), ch.cmd);
- while(!(readl(ch.status) & DMOV_STATUS_RSLT_VALID)) ;
+ while (!(readl(ch.status) & DMOV_STATUS_RSLT_VALID)) ;
n = readl(ch.status);
- while(DMOV_STATUS_RSLT_COUNT(n)) {
+ while (DMOV_STATUS_RSLT_COUNT(n)) {
n = readl(ch.result);
- if(n != 0x80000002) {
+ if (n != 0x80000002) {
dprintf(CRITICAL, "ERROR: result: %x\n", n);
dprintf(CRITICAL, "ERROR: flush: %x %x %x %x\n",
readl(DMOV_FLUSH0(DMOV_NAND_CHAN)),
@@ -132,47 +131,43 @@
unsigned onenand;
};
-static struct flash_identification supported_flash[] =
-{
- /* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz onenand Manuf */
- {0x00000000, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0}, /*ONFI*/
- {0x1500aaec, 0xFF00FFFF, (256<<20), 0, 2048, (2048<<6), 64, 0}, /*Sams*/
- {0x5500baec, 0xFF00FFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Sams*/
- {0x1500aa98, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 0}, /*Tosh*/
- {0x5500ba98, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Tosh*/
- {0xd580b12c, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Micr*/
- {0x5590bc2c, 0xFFFFFFFF, (512<<20), 1, 2048, (2048<<6), 64, 0}, /*Micr*/
- {0x1580aa2c, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 0}, /*Micr*/
- {0x1590aa2c, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 0}, /*Micr*/
- {0x1590ac2c, 0xFFFFFFFF, (512<<20), 0, 2048, (2048<<6), 64, 0}, /*Micr*/
- {0x5580baad, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Hynx*/
- {0x5510baad, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Hynx*/
- {0x004000ec, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 1}, /*Sams*/
- {0x005c00ec, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 1}, /*Sams*/
- {0x005800ec, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 1}, /*Sams*/
- {0x6600bcec, 0xFF00FFFF, (512<<20), 1, 4096, (4096<<6), 128, 0}, /*Sams*/
- {0x5580ba2c, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Hynx*/
- {0x6600b3ec, 0xFFFFFFFF, (512<<20), 1, 4096, (4096<<6), 128, 0}, /*Sams*/
- {0x2600482c, 0xFF00FFFF, (2048<<20), 0, 4096, (4096<<7), 224 , 0}, /*8bit bch ecc*/
- /* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
- /* Note: Onenand flag is 0 for NAND Flash and 1 for OneNAND flash */
- /* Note: The First row will be filled at runtime during ONFI probe */
+static struct flash_identification supported_flash[] = {
+ /* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz onenand Manuf */
+ {0x00000000, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0}, /*ONFI*/ {0x1500aaec, 0xFF00FFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 0}, /*Sams */
+ {0x5500baec, 0xFF00FFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Sams */
+ {0x1500aa98, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 0}, /*Tosh */
+ {0x5500ba98, 0xFFFFFFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Tosh */
+ {0xd580b12c, 0xFFFFFFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Micr */
+ {0x5590bc2c, 0xFFFFFFFF, (512 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Micr */
+ {0x1580aa2c, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 0}, /*Micr */
+ {0x1590aa2c, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 0}, /*Micr */
+ {0x1590ac2c, 0xFFFFFFFF, (512 << 20), 0, 2048, (2048 << 6), 64, 0}, /*Micr */
+ {0x5580baad, 0xFFFFFFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Hynx */
+ {0x5510baad, 0xFFFFFFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Hynx */
+ {0x004000ec, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 1}, /*Sams */
+ {0x005c00ec, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 1}, /*Sams */
+ {0x005800ec, 0xFFFFFFFF, (256 << 20), 0, 2048, (2048 << 6), 64, 1}, /*Sams */
+ {0x6600bcec, 0xFF00FFFF, (512 << 20), 1, 4096, (4096 << 6), 128, 0}, /*Sams */
+ {0x5580ba2c, 0xFFFFFFFF, (256 << 20), 1, 2048, (2048 << 6), 64, 0}, /*Hynx */
+ {0x6600b3ec, 0xFFFFFFFF, (512 << 20), 1, 4096, (4096 << 6), 128, 0}, /*Sams */
+ {0x2600482c, 0xFF00FFFF, (2048 << 20), 0, 4096, (4096 << 7), 224, 0}, /*8bit bch ecc */
+ /* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
+ /* Note: Onenand flag is 0 for NAND Flash and 1 for OneNAND flash */
+ /* Note: The First row will be filled at runtime during ONFI probe */
};
+
static void set_nand_configuration(char type)
{
- if(type == TYPE_MODEM_PARTITION)
- {
+ if (type == TYPE_MODEM_PARTITION) {
CFG0 = CFG0_M;
CFG1 = CFG1_M;
- }
- else
- {
+ } else {
CFG0 = CFG0_A;
CFG1 = CFG1_A;
}
}
-static void flash_nand_read_id(dmov_s *cmdlist, unsigned *ptrlist)
+static void flash_nand_read_id(dmov_s * cmdlist, unsigned *ptrlist)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -185,7 +180,7 @@
data[4] = 0;
data[5] = 0;
data[6] = 0;
- data[7] = 0xAAD40000; /* Default value for CFG0 for reading device id */
+ data[7] = 0xAAD40000; /* Default value for CFG0 for reading device id */
/* Read NAND device id */
cmd[0].cmd = 0 | CMD_OCB;
@@ -247,8 +242,8 @@
return;
}
-static int flash_nand_block_isbad(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_nand_block_isbad(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -259,7 +254,7 @@
cwperpage = (flash_pagesize >> 9);
/* Check first page of this block */
- if(page & num_pages_per_blk_mask)
+ if (page & num_pages_per_blk_mask)
page = page - (page & num_pages_per_blk_mask);
/* Check bad block marker */
@@ -268,24 +263,24 @@
/* addr0 */
if (CFG1 & CFG1_WIDE_FLASH)
data[1] = enable_bch_ecc ?
- ((page << 16) | ((532*(cwperpage-1)) >> 1)):
- ((page << 16) | ((528*(cwperpage-1)) >> 1));
+ ((page << 16) | ((532 * (cwperpage - 1)) >> 1)) :
+ ((page << 16) | ((528 * (cwperpage - 1)) >> 1));
else
data[1] = enable_bch_ecc ?
- ((page << 16) | (532*(cwperpage-1))):
- ((page << 16) | (528*(cwperpage-1)));
+ ((page << 16) | (532 * (cwperpage - 1))) :
+ ((page << 16) | (528 * (cwperpage - 1)));
- data[2] = (page >> 16) & 0xff; /* addr1 */
- data[3] = 0 | 4; /* chipsel */
- data[4] = NAND_CFG0_RAW & ~(7U << 6); /* cfg0 */
- data[5] = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH); /* cfg1 */
+ data[2] = (page >> 16) & 0xff; /* addr1 */
+ data[3] = 0 | 4; /* chipsel */
+ data[4] = NAND_CFG0_RAW & ~(7U << 6); /* cfg0 */
+ data[5] = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH); /* cfg1 */
if (enable_bch_ecc) {
- data[6] = ECC_BCH_CFG; /* ECC CFG */
+ data[6] = ECC_BCH_CFG; /* ECC CFG */
}
data[7] = 1;
data[8] = CLEAN_DATA_32; /* flash status */
- data[9] = CLEAN_DATA_32; /* buf status */
+ data[9] = CLEAN_DATA_32; /* buf status */
cmd[0].cmd = DST_CRCI_NAND_CMD | CMD_OCB;
cmd[0].src = paddr(&data[0]);
@@ -313,8 +308,11 @@
cmd[4].cmd = CMD_OCU | CMD_LC;
cmd[4].src = NAND_FLASH_BUFFER + (flash_pagesize - (enable_bch_ecc ?
- (532*(cwperpage-1)):
- (528*(cwperpage-1))));
+ (532 *
+ (cwperpage -
+ 1)) : (528 *
+ (cwperpage
+ - 1))));
cmd[4].dst = paddr(&buf);
cmd[4].len = 4;
@@ -327,9 +325,10 @@
#endif
/* we fail if there was an operation error, a mpu error, or the
- ** erase success bit was not set.
- */
- if(data[8] & 0x110) return -1;
+ ** erase success bit was not set.
+ */
+ if (data[8] & 0x110)
+ return -1;
/* Check for bad block marker byte */
if (CFG1 & CFG1_WIDE_FLASH) {
@@ -343,8 +342,9 @@
return 0;
}
-static int flash_nand_block_isbad_interleave(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_nand_block_isbad_interleave(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -353,10 +353,10 @@
char buf10[4];
unsigned cwperpage;
- cwperpage = ((flash_pagesize >> 1)>> 9);
+ cwperpage = ((flash_pagesize >> 1) >> 9);
/* Check first page of this block */
- if(page & 63)
+ if (page & 63)
page = page - (page & 63);
/* Check bad block marker */
@@ -364,27 +364,27 @@
/* addr0 */
if (CFG1 & CFG1_WIDE_FLASH)
- data[1] = (page << 16) | ((528*(cwperpage-1)) >> 1);
+ data[1] = (page << 16) | ((528 * (cwperpage - 1)) >> 1);
else
- data[1] = (page << 16) | (528*(cwperpage-1));
+ data[1] = (page << 16) | (528 * (cwperpage - 1));
- data[2] = (page >> 16) & 0xff; /* addr1 */
- data[3] = 0 | 4; /* chipsel CS0 */
- data[4] = 0 | 5; /* chipsel CS1 */
- data[5] = NAND_CFG0_RAW & ~(7U << 6); /* cfg0 */
- data[6] = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH); /* cfg1 */
+ data[2] = (page >> 16) & 0xff; /* addr1 */
+ data[3] = 0 | 4; /* chipsel CS0 */
+ data[4] = 0 | 5; /* chipsel CS1 */
+ data[5] = NAND_CFG0_RAW & ~(7U << 6); /* cfg0 */
+ data[6] = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH); /* cfg1 */
data[7] = 1;
data[8] = CLEAN_DATA_32; /* NC01 flash status */
data[9] = CLEAN_DATA_32; /* NC01 buf01 status */
data[10] = CLEAN_DATA_32; /* NC10 flash status */
data[11] = CLEAN_DATA_32; /* NC10 buf10 status */
- data[12] = 0x00000A3C; /* adm_mux_data_ack_req_nc01 */
- data[13] = 0x0000053C; /* adm_mux_cmd_ack_req_nc01 */
- data[14] = 0x00000F28; /* adm_mux_data_ack_req_nc10 */
- data[15] = 0x00000F14; /* adm_mux_cmd_ack_req_nc10 */
- data[16] = 0x00000FC0; /* adm_default_mux */
- data[17] = 0x00000805; /* enable CS1 */
- data[18] = 0x00000801; /* disable CS1 */
+ data[12] = 0x00000A3C; /* adm_mux_data_ack_req_nc01 */
+ data[13] = 0x0000053C; /* adm_mux_cmd_ack_req_nc01 */
+ data[14] = 0x00000F28; /* adm_mux_data_ack_req_nc10 */
+ data[15] = 0x00000F14; /* adm_mux_cmd_ack_req_nc10 */
+ data[16] = 0x00000FC0; /* adm_default_mux */
+ data[17] = 0x00000805; /* enable CS1 */
+ data[18] = 0x00000801; /* disable CS1 */
/* enable CS1 */
cmd[0].cmd = 0;
@@ -426,7 +426,9 @@
cmd[6].len = 8;
cmd[7].cmd = 0;
- cmd[7].src = NC01(NAND_FLASH_BUFFER) + (flash_pagesize - (528*(cwperpage-1)));
+ cmd[7].src =
+ NC01(NAND_FLASH_BUFFER) + (flash_pagesize -
+ (528 * (cwperpage - 1)));
cmd[7].dst = paddr(&buf01);
cmd[7].len = 4;
@@ -469,7 +471,9 @@
cmd[14].len = 8;
cmd[15].cmd = 0;
- cmd[15].src = NC10(NAND_FLASH_BUFFER) + (flash_pagesize - (528*(cwperpage-1)));
+ cmd[15].src =
+ NC10(NAND_FLASH_BUFFER) + (flash_pagesize -
+ (528 * (cwperpage - 1)));
cmd[15].dst = paddr(&buf10);
cmd[15].len = 4;
@@ -494,25 +498,26 @@
#endif
/* we fail if there was an operation error, a mpu error, or the
- ** erase success bit was not set.
- */
- if((data[8] & 0x110) || (data[10] & 0x110)) return -1;
+ ** erase success bit was not set.
+ */
+ if ((data[8] & 0x110) || (data[10] & 0x110))
+ return -1;
/* Check for bad block marker byte */
if (CFG1 & CFG1_WIDE_FLASH) {
if ((buf01[0] != 0xFF || buf01[1] != 0xFF) ||
- (buf10[0] != 0xFF || buf10[1] != 0xFF))
+ (buf10[0] != 0xFF || buf10[1] != 0xFF))
return 1;
- } else {
- if (buf01[0] != 0xFF || buf10[0] != 0xFF)
+ } else {
+ if (buf01[0] != 0xFF || buf10[0] != 0xFF)
return 1;
- }
+ }
return 0;
}
-static int flash_nand_erase_block(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_nand_erase_block(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -520,13 +525,15 @@
int isbad = 0;
/* only allow erasing on block boundaries */
- if(page & num_pages_per_blk_mask) return -1;
+ if (page & num_pages_per_blk_mask)
+ return -1;
/* Check for bad block and erase only if block is not marked bad */
isbad = flash_nand_block_isbad(cmdlist, ptrlist, page);
if (isbad) {
- dprintf(INFO, "skipping @ %d (bad block)\n", page / num_pages_per_blk);
+ dprintf(INFO, "skipping @ %d (bad block)\n",
+ page / num_pages_per_blk);
return -1;
}
@@ -537,7 +544,7 @@
data[3] = 0 | 4;
data[4] = 1;
data[5] = 0xeeeeeeee;
- data[6] = CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
+ data[6] = CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
data[7] = CFG1;
data[8] = ECC_BCH_CFG;
data[9] = 0x00000020;
@@ -588,14 +595,17 @@
/* we fail if there was an operation error, a mpu error, or the
** erase success bit was not set.
*/
- if(data[5] & 0x110) return -1;
- if(!(data[5] & 0x80)) return -1;
+ if (data[5] & 0x110)
+ return -1;
+ if (!(data[5] & 0x80))
+ return -1;
return 0;
}
-static int flash_nand_erase_block_interleave(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_nand_erase_block_interleave(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -603,7 +613,8 @@
int isbad = 0;
/* only allow erasing on block boundaries */
- if(page & 63) return -1;
+ if (page & 63)
+ return -1;
/* Check for bad block and erase only if block is not marked bad */
isbad = flash_nand_block_isbad(cmdlist, ptrlist, page);
@@ -622,13 +633,13 @@
data[5] = 1;
data[6] = 0xeeeeeeee;
data[7] = 0xeeeeeeee;
- data[8] = CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
+ data[8] = CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
data[9] = CFG1;
- data[10] = 0x00000A3C; /* adm_mux_data_ack_req_nc01 */
- data[11] = 0x0000053C; /* adm_mux_cmd_ack_req_nc01 */
- data[12] = 0x00000F28; /* adm_mux_data_ack_req_nc10 */
- data[13] = 0x00000F14; /* adm_mux_cmd_ack_req_nc10 */
- data[14] = 0x00000FC0; /* adm_default_mux */
+ data[10] = 0x00000A3C; /* adm_mux_data_ack_req_nc01 */
+ data[11] = 0x0000053C; /* adm_mux_cmd_ack_req_nc01 */
+ data[12] = 0x00000F28; /* adm_mux_data_ack_req_nc10 */
+ data[13] = 0x00000F14; /* adm_mux_cmd_ack_req_nc10 */
+ data[14] = 0x00000FC0; /* adm_default_mux */
data[15] = 0x00000805; /* enable CS1 */
data[16] = 0x00000801; /* disable CS1 */
@@ -734,8 +745,10 @@
/* we fail if there was an operation error, a mpu error, or the
** erase success bit was not set.
*/
- if(data[6] & 0x110 || data[7] & 0x110) return -1;
- if(!(data[6] & 0x80) || !(data[7] & 0x80)) return -1;
+ if (data[6] & 0x110 || data[7] & 0x110)
+ return -1;
+ if (!(data[6] & 0x80) || !(data[7] & 0x80))
+ return -1;
return 0;
}
@@ -782,14 +795,15 @@
} result[16];
};
-static int _flash_nand_read_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, void *_addr, void *_spareaddr)
+static int
+_flash_nand_read_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, void *_addr, void *_spareaddr)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct data_flash_io *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned spareaddr = (unsigned) _spareaddr;
+ struct data_flash_io *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned spareaddr = (unsigned)_spareaddr;
unsigned n;
int isbad = 0;
unsigned cwperpage;
@@ -804,27 +818,27 @@
* 1 : The block is bad
* 0 : The block is good
*/
- if(bbtbl[block] == -1) {
+ if (bbtbl[block] == -1) {
isbad = flash_nand_block_isbad(cmdlist, ptrlist, page);
- if(isbad) {
+ if (isbad) {
/* Found bad , set the bad table entry */
bbtbl[block] = 1;
return -2;
} else {
/* Found good block , set the table entry &
- * continue reading the data
- */
+ * continue reading the data
+ */
bbtbl[block] = 0;
}
- } else if(bbtbl[block] == 1) {
- /* If the block is already identified as bad, return error*/
+ } else if (bbtbl[block] == 1) {
+ /* If the block is already identified as bad, return error */
return -2;
}
data->cmd = NAND_CMD_PAGE_READ_ECC;
data->addr0 = page << 16;
data->addr1 = (page >> 16) & 0xff;
- data->chipsel = 0 | 4; /* flash0 + undoc bit */
+ data->chipsel = 0 | 4; /* flash0 + undoc bit */
/* GO bit for the EXEC register */
data->exec = 1;
@@ -844,7 +858,7 @@
cmd->len = 4;
cmd++;
- for(n = 0; n < cwperpage; n++) {
+ for (n = 0; n < cwperpage; n++) {
/* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst */
cmd->cmd = DST_CRCI_NAND_CMD;
cmd->src = paddr(&data->cmd);
@@ -889,7 +903,9 @@
cmd->cmd = 0;
cmd->src = NAND_FLASH_BUFFER;
cmd->dst = addr + n * 516;
- cmd->len = ((n < (cwperpage -1 )) ? 516 : (512 - ((cwperpage - 1) << 2)));
+ cmd->len =
+ ((n <
+ (cwperpage - 1)) ? 516 : (512 - ((cwperpage - 1) << 2)));
cmd++;
}
@@ -913,18 +929,20 @@
#if VERBOSE
dprintf(INFO, "read page %d: status: %x %x %x %x\n",
page, data[5], data[6], data[7], data[8]);
- for(n = 0; n < 4; n++) {
- ptr = (unsigned*)(addr + 512 * n);
- dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
- ptr = (unsigned*)(spareaddr + 16 * n);
- dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
+ for (n = 0; n < 4; n++) {
+ ptr = (unsigned *)(addr + 512 * n);
+ dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1],
+ ptr[2], ptr[3]);
+ ptr = (unsigned *)(spareaddr + 16 * n);
+ dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0],
+ ptr[1], ptr[2], ptr[3]);
}
#endif
/* if any of the writes failed (0x10), or there was a
** protection violation (0x100), we lose
*/
- for(n = 0; n < cwperpage; n++) {
+ for (n = 0; n < cwperpage; n++) {
if (data->result[n].flash_status & 0x110) {
return -1;
}
@@ -933,14 +951,15 @@
return 0;
}
-static int flash_nand_read_page_interleave(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, void *_addr, void *_spareaddr)
+static int
+flash_nand_read_page_interleave(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, void *_addr, void *_spareaddr)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct interleave_data_flash_io *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned spareaddr = (unsigned) _spareaddr;
+ struct interleave_data_flash_io *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned spareaddr = (unsigned)_spareaddr;
unsigned n;
int isbad = 0;
unsigned cwperpage;
@@ -954,13 +973,13 @@
data->cmd = NAND_CMD_PAGE_READ_ECC;
data->addr0 = page << 16;
data->addr1 = (page >> 16) & 0xff;
- data->chipsel_cs0 = 0 | 4; /* flash0 + undoc bit */
- data->chipsel_cs1 = 0 | 5; /* flash0 + undoc bit */
+ data->chipsel_cs0 = 0 | 4; /* flash0 + undoc bit */
+ data->chipsel_cs1 = 0 | 5; /* flash0 + undoc bit */
data->ebi2_chip_select_cfg0 = 0x00000805;
data->adm_mux_data_ack_req_nc01 = 0x00000A3C;
- data->adm_mux_cmd_ack_req_nc01 = 0x0000053C;
+ data->adm_mux_cmd_ack_req_nc01 = 0x0000053C;
data->adm_mux_data_ack_req_nc10 = 0x00000F28;
- data->adm_mux_cmd_ack_req_nc10 = 0x00000F14;
+ data->adm_mux_cmd_ack_req_nc10 = 0x00000F14;
data->adm_default_mux = 0x00000FC0;
data->default_ebi2_chip_select_cfg0 = 0x00000801;
@@ -1011,7 +1030,7 @@
* for NC10!
*/
cmd->cmd = 0;
- cmd->src = paddr(&data->chipsel_cs1);
+ cmd->src = paddr(&data->chipsel_cs1);
cmd->dst = NC10(NAND_FLASH_CHIP_SELECT);
cmd->len = 4;
cmd++;
@@ -1037,9 +1056,10 @@
/* if 'only' the last code word */
if (n == cwperpage - 1) {
- /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
+ /* MASK CMD ACK/REQ --> NC01 (0x53C) */
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc01);
+ cmd->src =
+ paddr(&data->adm_mux_cmd_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1058,9 +1078,10 @@
cmd->len = 4;
cmd++;
- /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
+ /* MASK DATA ACK/REQ --> NC01 (0xA3C) */
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_data_ack_req_nc01);
+ cmd->src =
+ paddr(&data->adm_mux_data_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1077,9 +1098,10 @@
cmd->len = 4;
cmd++;
} else {
- /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
+ /* MASK CMD ACK/REQ --> NC10 (0xF14) */
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc10);
+ cmd->src =
+ paddr(&data->adm_mux_cmd_ack_req_nc10);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1091,7 +1113,7 @@
cmd->len = 4;
cmd++;
- /* kick the execute register for NC01*/
+ /* kick the execute register for NC01 */
cmd->cmd = 0;
cmd->src = paddr(&data->exec);
cmd->dst = NC01(NAND_EXEC_CMD);
@@ -1100,9 +1122,8 @@
}
}
-
if (n % 2 == 0) {
- /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
+ /* MASK CMD ACK/REQ --> NC01 (0x53C) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1123,7 +1144,7 @@
cmd->len = 4;
cmd++;
- /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
+ /* MASK DATA ACK/REQ --> NC10 (0xF28) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_data_ack_req_nc10);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1146,7 +1167,11 @@
cmd->cmd = 0;
cmd->src = NC01(NAND_FLASH_BUFFER);
cmd->dst = addr + n * 516;
- cmd->len = ((n < (cwperpage -1 )) ? 516 : (512 - ((cwperpage - 1) << 2)));
+ cmd->len =
+ ((n <
+ (cwperpage - 1)) ? 516 : (512 -
+ ((cwperpage -
+ 1) << 2)));
cmd++;
} else {
if (n != cwperpage - 1) {
@@ -1154,7 +1179,8 @@
* NC10 (0xF14)
*/
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc10);
+ cmd->src =
+ paddr(&data->adm_mux_cmd_ack_req_nc10);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1177,7 +1203,8 @@
* NC01 (0xA3C)
*/
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_data_ack_req_nc01);
+ cmd->src =
+ paddr(&data->adm_mux_data_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1198,7 +1225,8 @@
* NC01 (0xA3C)
*/
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_data_ack_req_nc01);
+ cmd->src =
+ paddr(&data->adm_mux_data_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
@@ -1219,7 +1247,11 @@
cmd->cmd = 0;
cmd->src = NC10(NAND_FLASH_BUFFER);
cmd->dst = addr + n * 516;
- cmd->len = ((n < (cwperpage -1 )) ? 516 : (512 - ((cwperpage - 1) << 2)));
+ cmd->len =
+ ((n <
+ (cwperpage - 1)) ? 516 : (512 -
+ ((cwperpage -
+ 1) << 2)));
cmd++;
if (n == (cwperpage - 1)) {
@@ -1228,7 +1260,7 @@
*/
cmd->cmd = 0;
cmd->src = NC10(NAND_FLASH_BUFFER) +
- (512 - ((cwperpage -1) << 2));
+ (512 - ((cwperpage - 1) << 2));
cmd->dst = spareaddr;
cmd->len = 16;
cmd++;
@@ -1250,7 +1282,7 @@
/* disable CS1 */
cmd->cmd = 0;
- cmd->src = paddr(&data->default_ebi2_chip_select_cfg0);
+ cmd->src = paddr(&data->default_ebi2_chip_select_cfg0);
cmd->dst = EBI2_CHIP_SELECT_CFG0;
cmd->len = 4;
cmd++;
@@ -1261,36 +1293,22 @@
#if VERBOSE
dprintf(INFO, "read page %d: status: %x %x %x %x %x %x %x %x \
- %x %x %x %x %x %x %x %x \n", page,
- data->result[0].flash_status[0],
- data->result[1].flash_status[1],
- data->result[2].flash_status[2],
- data->result[3].flash_status[3],
- data->result[4].flash_status[4],
- data->result[5].flash_status[5],
- data->result[6].flash_status[6],
- data->result[7].flash_status[7],
- data->result[8].flash_status[8],
- data->result[9].flash_status[9],
- data->result[10].flash_status[10],
- data->result[11].flash_status[11],
- data->result[12].flash_status[12],
- data->result[13].flash_status[13],
- data->result[14].flash_status[14],
- data->result[15].flash_status[15]);
+ %x %x %x %x %x %x %x %x \n", page, data->result[0].flash_status[0], data->result[1].flash_status[1], data->result[2].flash_status[2], data->result[3].flash_status[3], data->result[4].flash_status[4], data->result[5].flash_status[5], data->result[6].flash_status[6], data->result[7].flash_status[7], data->result[8].flash_status[8], data->result[9].flash_status[9], data->result[10].flash_status[10], data->result[11].flash_status[11], data->result[12].flash_status[12], data->result[13].flash_status[13], data->result[14].flash_status[14], data->result[15].flash_status[15]);
- for(n = 0; n < 4; n++) {
- ptr = (unsigned*)(addr + 512 * n);
- dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
- ptr = (unsigned*)(spareaddr + 16 * n);
- dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
+ for (n = 0; n < 4; n++) {
+ ptr = (unsigned *)(addr + 512 * n);
+ dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1],
+ ptr[2], ptr[3]);
+ ptr = (unsigned *)(spareaddr + 16 * n);
+ dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0],
+ ptr[1], ptr[2], ptr[3]);
}
#endif
/* if any of the writes failed (0x10), or there was a
** protection violation (0x100), we lose
*/
- for(n = 0; n < cwperpage; n++) {
+ for (n = 0; n < cwperpage; n++) {
if (data->result[n].flash_status & 0x110) {
return -1;
}
@@ -1299,38 +1317,40 @@
return 0;
}
-static int _flash_nand_write_page(dmov_s *cmdlist, unsigned *ptrlist, unsigned page,
- const void *_addr, const void *_spareaddr, unsigned raw_mode)
+static int
+_flash_nand_write_page(dmov_s * cmdlist, unsigned *ptrlist, unsigned page,
+ const void *_addr, const void *_spareaddr,
+ unsigned raw_mode)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct data_flash_io *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned spareaddr = (unsigned) _spareaddr;
+ struct data_flash_io *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned spareaddr = (unsigned)_spareaddr;
unsigned n;
unsigned cwperpage;
cwperpage = (flash_pagesize >> 9);
unsigned modem_partition = 0;
- if (CFG0 == CFG0_M)
- {
+ if (CFG0 == CFG0_M) {
modem_partition = 1;
}
data->cmd = NAND_CMD_PRG_PAGE;
data->addr0 = page << 16;
data->addr1 = (page >> 16) & 0xff;
- data->chipsel = 0 | 4; /* flash0 + undoc bit */
+ data->chipsel = 0 | 4; /* flash0 + undoc bit */
data->clrfstatus = 0x00000020;
data->clrrstatus = 0x000000C0;
- if (!raw_mode){
+ if (!raw_mode) {
data->cfg0 = CFG0;
data->cfg1 = CFG1;
if (enable_bch_ecc) {
data->ecc_bch_cfg = ECC_BCH_CFG;
}
- }else{
- data->cfg0 = (NAND_CFG0_RAW & ~(7 << 6)) |((cwperpage-1) << 6);
+ } else {
+ data->cfg0 =
+ (NAND_CFG0_RAW & ~(7 << 6)) | ((cwperpage - 1) << 6);
data->cfg1 = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH);
}
@@ -1349,8 +1369,8 @@
cmd->len = 4;
cmd++;
- for(n = 0; n < cwperpage; n++) {
- /* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst */
+ for (n = 0; n < cwperpage; n++) {
+ /* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst */
cmd->cmd = DST_CRCI_NAND_CMD;
cmd->src = paddr(&data->cmd);
cmd->dst = NAND_FLASH_CMD;
@@ -1381,17 +1401,21 @@
/* write data block */
cmd->cmd = 0;
cmd->dst = NAND_FLASH_BUFFER;
- if (!raw_mode){
- if(modem_partition){
+ if (!raw_mode) {
+ if (modem_partition) {
cmd->src = addr + n * 512;
cmd->len = 512;
- }else{
+ } else {
cmd->src = addr + n * 516;
- cmd->len = ((n < (cwperpage - 1)) ? 516 : (512 - ((cwperpage - 1) << 2)));
+ cmd->len =
+ ((n <
+ (cwperpage - 1)) ? 516 : (512 -
+ ((cwperpage -
+ 1) << 2)));
}
- }else{
+ } else {
cmd->src = addr;
- cmd->len = 528;
+ cmd->len = 528;
}
cmd++;
@@ -1399,7 +1423,8 @@
/* write extra data */
cmd->cmd = 0;
cmd->src = spareaddr;
- cmd->dst = NAND_FLASH_BUFFER + (512 - ((cwperpage - 1) << 2));
+ cmd->dst =
+ NAND_FLASH_BUFFER + (512 - ((cwperpage - 1) << 2));
cmd->len = (cwperpage << 2);
cmd++;
}
@@ -1450,18 +1475,20 @@
** protection violation (0x100), or the program success
** bit (0x80) is unset, we lose
*/
- for(n = 0; n < cwperpage; n++) {
- if(data->result[n].flash_status & 0x110) return -1;
- if(!(data->result[n].flash_status & 0x80)) return -1;
+ for (n = 0; n < cwperpage; n++) {
+ if (data->result[n].flash_status & 0x110)
+ return -1;
+ if (!(data->result[n].flash_status & 0x80))
+ return -1;
}
#if VERIFY_WRITE
n = _flash_read_page(cmdlist, ptrlist, page, flash_data,
- flash_data + 2048);
+ flash_data + 2048);
if (n != 0)
return -1;
if (memcmp(flash_data, _addr, 2048) ||
- memcmp(flash_data + 2048, _spareaddr, 16)) {
+ memcmp(flash_data + 2048, _spareaddr, 16)) {
dprintf(CRITICAL, "verify error @ page %d\n", page);
return -1;
}
@@ -1469,38 +1496,40 @@
return 0;
}
-static int flash_nand_write_page_interleave(dmov_s *cmdlist, unsigned *ptrlist, unsigned page,
- const void *_addr, const void *_spareaddr, unsigned raw_mode)
+static int
+flash_nand_write_page_interleave(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, const void *_addr,
+ const void *_spareaddr, unsigned raw_mode)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct interleave_data_flash_io *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned spareaddr = (unsigned) _spareaddr;
+ struct interleave_data_flash_io *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned spareaddr = (unsigned)_spareaddr;
unsigned n;
unsigned cwperpage, cwcount;
- cwperpage = (flash_pagesize >> 9) * 2; /* double for interleave mode */
+ cwperpage = (flash_pagesize >> 9) * 2; /* double for interleave mode */
cwcount = (cwperpage << 1);
data->cmd = NAND_CMD_PRG_PAGE;
data->addr0 = page << 16;
data->addr1 = (page >> 16) & 0xff;
- data->chipsel_cs0 = 0 | 4; /* flash0 + undoc bit */
- data->chipsel_cs1 = 0 | 5; /* flash0 + undoc bit */
+ data->chipsel_cs0 = 0 | 4; /* flash0 + undoc bit */
+ data->chipsel_cs1 = 0 | 5; /* flash0 + undoc bit */
data->ebi2_chip_select_cfg0 = 0x00000805;
data->adm_mux_data_ack_req_nc01 = 0x00000A3C;
- data->adm_mux_cmd_ack_req_nc01 = 0x0000053C;
+ data->adm_mux_cmd_ack_req_nc01 = 0x0000053C;
data->adm_mux_data_ack_req_nc10 = 0x00000F28;
- data->adm_mux_cmd_ack_req_nc10 = 0x00000F14;
+ data->adm_mux_cmd_ack_req_nc10 = 0x00000F14;
data->adm_default_mux = 0x00000FC0;
data->default_ebi2_chip_select_cfg0 = 0x00000801;
- if (!raw_mode){
+ if (!raw_mode) {
data->cfg0 = CFG0;
data->cfg1 = CFG1;
- }else{
- data->cfg0 = (NAND_CFG0_RAW & ~(7 << 6)) |((cwcount-1) << 6);
+ } else {
+ data->cfg0 = (NAND_CFG0_RAW & ~(7 << 6)) | ((cwcount - 1) << 6);
data->cfg1 = NAND_CFG1_RAW | (CFG1 & CFG1_WIDE_FLASH);
}
@@ -1554,21 +1583,21 @@
cmd++;
cmd->cmd = 0;
- cmd->src =paddr(&data->cfg0);
+ cmd->src = paddr(&data->cfg0);
cmd->dst = NC01(NAND_DEV0_CFG0);
cmd->len = 8;
cmd++;
/* config CFG1 for CS1 */
cmd->cmd = 0;
- cmd->src =paddr(&data->cfg0);
+ cmd->src = paddr(&data->cfg0);
cmd->dst = NC10(NAND_DEV1_CFG0);
cmd->len = 8;
cmd++;
}
if (n % 2 == 0) {
- /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
+ /* MASK CMD ACK/REQ --> NC10 (0xF14) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc10);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1582,7 +1611,7 @@
cmd->len = 4;
cmd++;
} else {
- /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
+ /* MASK CMD ACK/REQ --> NC01 (0x53C) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_cmd_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1598,12 +1627,16 @@
}
cmd->cmd = 0;
- if (!raw_mode){
+ if (!raw_mode) {
cmd->src = addr + n * 516;
- cmd->len = ((n < (cwperpage - 1)) ? 516 : (512 - ((cwperpage - 1) << 2)));
- }else{
+ cmd->len =
+ ((n <
+ (cwperpage - 1)) ? 516 : (512 -
+ ((cwperpage -
+ 1) << 2)));
+ } else {
cmd->src = addr;
- cmd->len = 528;
+ cmd->len = 528;
}
if (n % 2 == 0)
@@ -1616,7 +1649,9 @@
/* write extra data */
cmd->cmd = 0;
cmd->src = spareaddr;
- cmd->dst = NC10(NAND_FLASH_BUFFER) + (512 - ((cwperpage - 1) << 2));
+ cmd->dst =
+ NC10(NAND_FLASH_BUFFER) + (512 -
+ ((cwperpage - 1) << 2));
cmd->len = (cwperpage << 2);
cmd++;
}
@@ -1629,19 +1664,20 @@
cmd->len = 4;
cmd++;
if (n != 0) {
- /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
+ /* MASK DATA ACK/REQ --> NC01 (0xA3C) */
cmd->cmd = 0;
- cmd->src = paddr(&data->adm_mux_data_ack_req_nc01);
+ cmd->src =
+ paddr(&data->adm_mux_data_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
cmd->len = 4;
cmd++;
/* block on data ready from NC10, then
- * read the status register
- */
+ * read the status register
+ */
cmd->cmd = SRC_CRCI_NAND_DATA;
cmd->src = NC10(NAND_FLASH_STATUS);
- cmd->dst = paddr(&data->result[n-1]);
+ cmd->dst = paddr(&data->result[n - 1]);
cmd->len = 4;
cmd++;
}
@@ -1653,7 +1689,7 @@
cmd->len = 4;
cmd++;
- /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
+ /* MASK DATA ACK/REQ --> NC10 (0xF28) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_data_ack_req_nc10);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1665,13 +1701,13 @@
*/
cmd->cmd = SRC_CRCI_NAND_DATA;
cmd->src = NC01(NAND_FLASH_STATUS);
- cmd->dst = paddr(&data->result[n-1]);
+ cmd->dst = paddr(&data->result[n - 1]);
cmd->len = 4;
cmd++;
}
}
- /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
+ /* MASK DATA ACK/REQ --> NC01 (0xA3C) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_mux_data_ack_req_nc01);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1684,7 +1720,7 @@
*/
cmd->cmd = SRC_CRCI_NAND_DATA;
cmd->src = NC10(NAND_FLASH_STATUS);
- cmd->dst = paddr(&data->result[n-1]);
+ cmd->dst = paddr(&data->result[n - 1]);
cmd->len = 4;
cmd++;
@@ -1694,7 +1730,7 @@
cmd->dst = NAND_EBI2_ECC_BUF_CFG;
cmd->len = 4;
- /* MASK DATA ACK/REQ --> NC01 (0xFC0)*/
+ /* MASK DATA ACK/REQ --> NC01 (0xFC0) */
cmd->cmd = 0;
cmd->src = paddr(&data->adm_default_mux);
cmd->dst = EBI2_NAND_ADM_MUX;
@@ -1713,42 +1749,28 @@
dmov_exec_cmdptr(DMOV_NAND_CHAN, ptr);
#if VERBOSE
-dprintf(INFO, "write page %d: status: %x %x %x %x %x %x %x %x \
- %x %x %x %x %x %x %x %x \n", page,
- data->result[0].flash_status[0],
- data->result[1].flash_status[1],
- data->result[2].flash_status[2],
- data->result[3].flash_status[3],
- data->result[4].flash_status[4],
- data->result[5].flash_status[5],
- data->result[6].flash_status[6],
- data->result[7].flash_status[7],
- data->result[8].flash_status[8],
- data->result[9].flash_status[9],
- data->result[10].flash_status[10],
- data->result[11].flash_status[11],
- data->result[12].flash_status[12],
- data->result[13].flash_status[13],
- data->result[14].flash_status[14],
- data->result[15].flash_status[15]);
+ dprintf(INFO, "write page %d: status: %x %x %x %x %x %x %x %x \
+ %x %x %x %x %x %x %x %x \n", page, data->result[0].flash_status[0], data->result[1].flash_status[1], data->result[2].flash_status[2], data->result[3].flash_status[3], data->result[4].flash_status[4], data->result[5].flash_status[5], data->result[6].flash_status[6], data->result[7].flash_status[7], data->result[8].flash_status[8], data->result[9].flash_status[9], data->result[10].flash_status[10], data->result[11].flash_status[11], data->result[12].flash_status[12], data->result[13].flash_status[13], data->result[14].flash_status[14], data->result[15].flash_status[15]);
#endif
/* if any of the writes failed (0x10), or there was a
** protection violation (0x100), or the program success
** bit (0x80) is unset, we lose
*/
- for(n = 0; n < cwperpage; n++) {
- if(data->result[n].flash_status & 0x110) return -1;
- if(!(data->result[n].flash_status & 0x80)) return -1;
+ for (n = 0; n < cwperpage; n++) {
+ if (data->result[n].flash_status & 0x110)
+ return -1;
+ if (!(data->result[n].flash_status & 0x80))
+ return -1;
}
#if VERIFY_WRITE
n = _flash_read_page(cmdlist, ptrlist, page, flash_data,
- flash_data + 2048);
+ flash_data + 2048);
if (n != 0)
return -1;
if (memcmp(flash_data, _addr, 2048) ||
- memcmp(flash_data + 2048, _spareaddr, 16)) {
+ memcmp(flash_data + 2048, _spareaddr, 16)) {
dprintf(CRITICAL, "verify error @ page %d\n", page);
return -1;
}
@@ -1757,19 +1779,20 @@
}
char empty_buf[528];
-static int flash_nand_mark_badblock(dmov_s *cmdlist, unsigned *ptrlist, unsigned page)
+static int
+flash_nand_mark_badblock(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
- memset(empty_buf,0,528);
- /* Going to first page of the block */
- if(page & num_pages_per_blk_mask)
- page = page - (page & num_pages_per_blk_mask);
- return _flash_nand_write_page(cmdlist, ptrlist, page, empty_buf, 0, 1);
+ memset(empty_buf, 0, 528);
+ /* Going to first page of the block */
+ if (page & num_pages_per_blk_mask)
+ page = page - (page & num_pages_per_blk_mask);
+ return _flash_nand_write_page(cmdlist, ptrlist, page, empty_buf, 0, 1);
}
unsigned nand_cfg0;
unsigned nand_cfg1;
-static int flash_nand_read_config(dmov_s *cmdlist, unsigned *ptrlist)
+static int flash_nand_read_config(dmov_s * cmdlist, unsigned *ptrlist)
{
static unsigned CFG0_TMP, CFG1_TMP;
cmdlist[0].cmd = CMD_OCB;
@@ -1786,7 +1809,7 @@
dmov_exec_cmdptr(DMOV_NAND_CHAN, ptrlist);
- if((CFG0_TMP == 0) || (CFG1_TMP == 0)) {
+ if ((CFG0_TMP == 0) || (CFG1_TMP == 0)) {
return -1;
}
@@ -1797,37 +1820,36 @@
}
dprintf(INFO, "nandcfg: %x %x (initial)\n", CFG0, CFG1);
- CFG0_A = (((flash_pagesize >> 9) - 1) << 6) /* 4/8 cw/pg for 2/4k */
- | (516 << 9) /* 516 user data bytes */
- | (10 << 19) /* 10 parity bytes */
- | (5 << 27) /* 5 address cycles */
- | (0 << 30) /* Do not read status before data */
- | (1 << 31) /* Send read cmd */
- /* 0 spare bytes for 16 bit nand or 1 spare bytes for 8 bit */
- | ((nand_cfg1 & CFG1_WIDE_FLASH) ? (0 << 23) :
- (enable_bch_ecc ? (2 << 23) : (1 << 23))); /* 2 spare bytes for 8 bit bch ecc */
- CFG1_A = (0 << 0) /* Enable ecc */
- | (7 << 2) /* 8 recovery cycles */
- | (0 << 5) /* Allow CS deassertion */
- | ((flash_pagesize - ((enable_bch_ecc ? 532 : 528) *
- ((flash_pagesize >> 9) - 1)) + 1) << 6) /* Bad block marker location */
- | (0 << 16) /* Bad block in user data area */
- | (2 << 17) /* 6 cycle tWB/tRB */
- | (nand_cfg1 & CFG1_WIDE_FLASH); /* preserve wide flash flag */
+ CFG0_A = (((flash_pagesize >> 9) - 1) << 6) /* 4/8 cw/pg for 2/4k */
+ |(516 << 9) /* 516 user data bytes */
+ |(10 << 19) /* 10 parity bytes */
+ |(5 << 27) /* 5 address cycles */
+ |(0 << 30) /* Do not read status before data */
+ |(1 << 31)
+ /* Send read cmd */
+ /* 0 spare bytes for 16 bit nand or 1 spare bytes for 8 bit */
+ |((nand_cfg1 & CFG1_WIDE_FLASH) ? (0 << 23) : (enable_bch_ecc ? (2 << 23) : (1 << 23))); /* 2 spare bytes for 8 bit bch ecc */
+ CFG1_A = (0 << 0) /* Enable ecc */
+ |(7 << 2) /* 8 recovery cycles */
+ |(0 << 5) /* Allow CS deassertion */
+ |((flash_pagesize - ((enable_bch_ecc ? 532 : 528) * ((flash_pagesize >> 9) - 1)) + 1) << 6) /* Bad block marker location */
+ |(0 << 16) /* Bad block in user data area */
+ |(2 << 17) /* 6 cycle tWB/tRB */
+ |(nand_cfg1 & CFG1_WIDE_FLASH); /* preserve wide flash flag */
NAND_CFG0_RAW = CFG0_RAW;
NAND_CFG1_RAW = CFG1_RAW;
if (enable_bch_ecc) {
- CFG1_A |= (1 << 27); /* Enable BCH engine */
- ECC_BCH_CFG = (0 << 0) /* Enable ECC*/
- | (0 << 1) /* Enable/Disable SW reset of ECC engine */
- | (1 << 4) /* 8bit ecc*/
- | ((nand_cfg1 & CFG1_WIDE_FLASH) ? (14 << 8) : (13 << 8))/*parity bytes*/
- | (516 << 16) /* 516 user data bytes */
- | (1 << 30); /* Turn on ECC engine clocks always */
- NAND_CFG0_RAW = CFG0_RAW_BCHECC; /* CW size is increased to 532B */
- }
+ CFG1_A |= (1 << 27); /* Enable BCH engine */
+ ECC_BCH_CFG = (0 << 0) /* Enable ECC */
+ |(0 << 1) /* Enable/Disable SW reset of ECC engine */
+ |(1 << 4) /* 8bit ecc */
+ |((nand_cfg1 & CFG1_WIDE_FLASH) ? (14 << 8) : (13 << 8)) /*parity bytes */
+ |(516 << 16) /* 516 user data bytes */
+ |(1 << 30); /* Turn on ECC engine clocks always */
+ NAND_CFG0_RAW = CFG0_RAW_BCHECC; /* CW size is increased to 532B */
+ }
dprintf(INFO, "nandcfg(Apps): %x %x (used)\n", CFG0_A, CFG1_A);
@@ -1836,43 +1858,46 @@
if (flash_info.type == FLASH_16BIT_NAND_DEVICE) {
nand_cfg1 |= CFG1_WIDE_FLASH;
}
- CFG0_M = (((flash_pagesize >> 9) - 1) << 6) /* 4/8 cw/pg for 2/4k */
- | (512 << 9) /* 512 user data bytes */
- | (10 << 19) /* 10 parity bytes */
- | (5 << 27) /* 5 address cycles */
- | (0 << 30) /* Do not read status before data */
- | (1 << 31) /* Send read cmd */
- | ((nand_cfg1 & CFG1_WIDE_FLASH) ? (4 << 23) : (5 << 23));
- CFG1_M = (0 << 0) /* Enable ecc */
- | (7 << 2) /* 8 recovery cycles */
- | (0 << 5) /* Allow CS deassertion */
- | ((flash_pagesize - (528 * ((flash_pagesize >> 9) - 1)) + 1) << 6) /* Bad block marker location */
- | (0 << 16) /* Bad block in user data area */
- | (2 << 17) /* 6 cycle tWB/tRB */
- | (nand_cfg1 & CFG1_WIDE_FLASH); /* preserve wide flash flag */
+ CFG0_M = (((flash_pagesize >> 9) - 1) << 6) /* 4/8 cw/pg for 2/4k */
+ |(512 << 9) /* 512 user data bytes */
+ |(10 << 19) /* 10 parity bytes */
+ |(5 << 27) /* 5 address cycles */
+ |(0 << 30) /* Do not read status before data */
+ |(1 << 31) /* Send read cmd */
+ |((nand_cfg1 & CFG1_WIDE_FLASH) ? (4 << 23) : (5 << 23));
+ CFG1_M = (0 << 0) /* Enable ecc */
+ |(7 << 2) /* 8 recovery cycles */
+ |(0 << 5) /* Allow CS deassertion */
+ |((flash_pagesize - (528 * ((flash_pagesize >> 9) - 1)) + 1) << 6) /* Bad block marker location */
+ |(0 << 16) /* Bad block in user data area */
+ |(2 << 17) /* 6 cycle tWB/tRB */
+ |(nand_cfg1 & CFG1_WIDE_FLASH); /* preserve wide flash flag */
dprintf(INFO, "nandcfg(Modem): %x %x (used)\n", CFG0_M, CFG1_M);
return 0;
}
/* OneNAND programming functions */
-static void flash_onenand_read_id(dmov_s *cmdlist, unsigned *ptrlist)
+static void flash_onenand_read_id(dmov_s * cmdlist, unsigned *ptrlist)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
unsigned *data = ptrlist + 4;
data[0] = SFLASH_BCFG;
- data[1] = SFLASH_PREPCMD(8, 0, 0, NAND_SFCMD_DATXS, NAND_SFCMD_ASYNC, NAND_SFCMD_REGRD);
+ data[1] =
+ SFLASH_PREPCMD(8, 0, 0, NAND_SFCMD_DATXS, NAND_SFCMD_ASYNC,
+ NAND_SFCMD_REGRD);
data[2] = (ONENAND_DEVICE_ID << 16) | (ONENAND_MANUFACTURER_ID);
data[3] = (ONENAND_DATA_BUFFER_SIZE << 16) | (ONENAND_VERSION_ID);
- data[4] = (ONENAND_AMOUNT_OF_BUFFERS << 16) | (ONENAND_BOOT_BUFFER_SIZE);
+ data[4] =
+ (ONENAND_AMOUNT_OF_BUFFERS << 16) | (ONENAND_BOOT_BUFFER_SIZE);
data[5] = (CLEAN_DATA_16 << 16) | (ONENAND_TECHNOLOGY);
- data[6] = CLEAN_DATA_32; //status
- data[7] = CLEAN_DATA_32; //register read
- data[8] = CLEAN_DATA_32; //register read
- data[9] = CLEAN_DATA_32; //register read
- data[10] = CLEAN_DATA_32; //register read
+ data[6] = CLEAN_DATA_32; //status
+ data[7] = CLEAN_DATA_32; //register read
+ data[8] = CLEAN_DATA_32; //register read
+ data[9] = CLEAN_DATA_32; //register read
+ data[10] = CLEAN_DATA_32; //register read
data[11] = 1;
data[12] = 0 | 4;
@@ -1933,11 +1958,10 @@
flash_info.id = data[7];
flash_info.vendor = data[7] & CLEAN_DATA_16;
- flash_info.device = (data[7] >> 16) & CLEAN_DATA_16;
+ flash_info.device = (data[7] >> 16) & CLEAN_DATA_16;
return;
}
-
struct data_onenand_erase {
unsigned sfbcfg;
unsigned sfcmd[4];
@@ -1959,47 +1983,44 @@
unsigned data6;
};
+static int _flash_onenand_read_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, void *_addr,
+ void *_spareaddr, unsigned raw_mode);
-static int _flash_onenand_read_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, void *_addr,
- void *_spareaddr, unsigned raw_mode);
-
-
-static int flash_onenand_block_isbad(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_onenand_block_isbad(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
unsigned char page_data[2112];
unsigned char *oobptr = &(page_data[2048]);
/* Going to first page of the block */
- if(page & num_pages_per_blk_mask)
+ if (page & num_pages_per_blk_mask)
page = page - (page & num_pages_per_blk_mask);
/* Reading page in raw mode */
- if (_flash_onenand_read_page(cmdlist, ptrlist,page, page_data, 0, 1))
+ if (_flash_onenand_read_page(cmdlist, ptrlist, page, page_data, 0, 1))
return 1;
/* Checking if block is bad */
- if ((oobptr[0] != 0xFF) || (oobptr[1] != 0xFF) ||
- (oobptr[16] != 0xFF) || (oobptr[17] != 0xFF) ||
- (oobptr[32] != 0xFF) || (oobptr[33] != 0xFF) ||
- (oobptr[48] != 0xFF) || (oobptr[49] != 0xFF)
- )
- {
+ if ((oobptr[0] != 0xFF) || (oobptr[1] != 0xFF) ||
+ (oobptr[16] != 0xFF) || (oobptr[17] != 0xFF) ||
+ (oobptr[32] != 0xFF) || (oobptr[33] != 0xFF) ||
+ (oobptr[48] != 0xFF) || (oobptr[49] != 0xFF)) {
return 1;
}
return 0;
}
-static int flash_onenand_erase_block(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page)
+static int
+flash_onenand_erase_block(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
struct data_onenand_erase *data = (void *)ptrlist + 4;
int isbad = 0;
unsigned erasesize = (flash_pagesize * num_pages_per_blk);
- unsigned onenand_startaddr1 = DEVICE_FLASHCORE_0 | (page * flash_pagesize)/erasesize;
+ unsigned onenand_startaddr1 =
+ DEVICE_FLASHCORE_0 | (page * flash_pagesize) / erasesize;
unsigned onenand_startaddr8 = 0x0000;
unsigned onenand_startaddr2 = DEVICE_BUFFERRAM_0 << 15;
unsigned onenand_startbuffer = DATARAM0_0 << 8;
@@ -2008,74 +2029,61 @@
unsigned interrupt_status;
unsigned ecc_status;
- if((page * flash_pagesize) & (erasesize-1)) return -1;
+ if ((page * flash_pagesize) & (erasesize - 1))
+ return -1;
/* Check for bad block and erase only if block is not marked bad */
isbad = flash_onenand_block_isbad(cmdlist, ptrlist, page);
- if (isbad)
- {
- dprintf(INFO, "skipping @ %d (bad block)\n", page / num_pages_per_blk);
+ if (isbad) {
+ dprintf(INFO, "skipping @ %d (bad block)\n",
+ page / num_pages_per_blk);
return -1;
}
- /*Erase block*/
+ /*Erase block */
onenand_startaddr1 = DEVICE_FLASHCORE_0 |
- ((page * flash_pagesize) / (erasesize));
+ ((page * flash_pagesize) / (erasesize));
onenand_startaddr8 = 0x0000;
onenand_startaddr2 = DEVICE_BUFFERRAM_0 << 15;
onenand_startbuffer = DATARAM0_0 << 8;
-
data->sfbcfg = SFLASH_BCFG;
data->sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
data->sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_INTHI);
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_INTHI);
data->sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGRD);
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGRD);
data->sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
data->sfexec = 1;
data->sfstat[0] = CLEAN_DATA_32;
data->sfstat[1] = CLEAN_DATA_32;
data->sfstat[2] = CLEAN_DATA_32;
data->sfstat[3] = CLEAN_DATA_32;
- data->addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr1 = (ONENAND_START_ADDRESS_8 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->addr2 = (ONENAND_START_BUFFER << 16) |
- (ONENAND_START_ADDRESS_2);
- data->addr3 = (ONENAND_ECC_STATUS << 16) |
- (ONENAND_COMMAND);
+ data->addr0 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr1 =
+ (ONENAND_START_ADDRESS_8 << 16) | (ONENAND_START_ADDRESS_1);
+ data->addr2 = (ONENAND_START_BUFFER << 16) | (ONENAND_START_ADDRESS_2);
+ data->addr3 = (ONENAND_ECC_STATUS << 16) | (ONENAND_COMMAND);
data->addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
- (ONENAND_INTERRUPT_STATUS);
- data->addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr6 = (ONENAND_START_ADDRESS_3 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->data0 = (ONENAND_CLRINTR << 16) |
- (ONENAND_SYSCFG1_ECCENA);
- data->data1 = (onenand_startaddr8 << 16) |
- (onenand_startaddr1);
- data->data2 = (onenand_startbuffer << 16) |
- (onenand_startaddr2);
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDERAS);
- data->data4 = (CLEAN_DATA_16 << 16) |
- (CLEAN_DATA_16);
- data->data5 = (ONENAND_CLRINTR << 16) |
- (ONENAND_SYSCFG1_ECCENA);
- data->data6 = (ONENAND_STARTADDR3_RES << 16) |
- (ONENAND_STARTADDR1_RES);
+ (ONENAND_INTERRUPT_STATUS);
+ data->addr5 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr6 =
+ (ONENAND_START_ADDRESS_3 << 16) | (ONENAND_START_ADDRESS_1);
+ data->data0 = (ONENAND_CLRINTR << 16) | (ONENAND_SYSCFG1_ECCENA);
+ data->data1 = (onenand_startaddr8 << 16) | (onenand_startaddr1);
+ data->data2 = (onenand_startbuffer << 16) | (onenand_startaddr2);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDERAS);
+ data->data4 = (CLEAN_DATA_16 << 16) | (CLEAN_DATA_16);
+ data->data5 = (ONENAND_CLRINTR << 16) | (ONENAND_SYSCFG1_ECCENA);
+ data->data6 = (ONENAND_STARTADDR3_RES << 16) | (ONENAND_STARTADDR1_RES);
/***************************************************************/
/* Write the necessary address registers in the onenand device */
@@ -2145,7 +2153,7 @@
cmd++;
/***************************************************************/
- /* Wait for the interrupt from the Onenand device controller */
+ /* Wait for the interrupt from the Onenand device controller */
/***************************************************************/
/* Block on cmd ready and write CMD register */
@@ -2209,7 +2217,7 @@
cmd++;
/***************************************************************/
- /* Restore the necessary registers to proper values */
+ /* Restore the necessary registers to proper values */
/***************************************************************/
/* Block on cmd ready and write CMD register */
@@ -2243,29 +2251,24 @@
#if VERBOSE
dprintf(INFO, "\n%s: sflash status %x %x %x %x\n", __func__,
- data->sfstat[0],
- data->sfstat[1],
- data->sfstat[2],
- data->sfstat[3]);
+ data->sfstat[0],
+ data->sfstat[1], data->sfstat[2], data->sfstat[3]);
dprintf(INFO, "%s: controller_status = %x\n", __func__,
- controller_status);
+ controller_status);
dprintf(INFO, "%s: interrupt_status = %x\n", __func__,
- interrupt_status);
- dprintf(INFO, "%s: ecc_status = %x\n", __func__,
- ecc_status);
+ interrupt_status);
+ dprintf(INFO, "%s: ecc_status = %x\n", __func__, ecc_status);
#endif
/* Check for errors, protection violations etc */
if ((controller_status != 0)
- || (data->sfstat[0] & 0x110)
- || (data->sfstat[1] & 0x110)
- || (data->sfstat[2] & 0x110)
- || (data->sfstat[3] & 0x110)) {
- dprintf(CRITICAL, "%s: ECC/MPU/OP error\n", __func__);
- return -1;
+ || (data->sfstat[0] & 0x110)
+ || (data->sfstat[1] & 0x110)
+ || (data->sfstat[2] & 0x110) || (data->sfstat[3] & 0x110)) {
+ dprintf(CRITICAL, "%s: ECC/MPU/OP error\n", __func__);
+ return -1;
}
-
#if VERBOSE
dprintf(INFO, "status: %x\n", data[5]);
#endif
@@ -2273,106 +2276,94 @@
return 0;
}
-
struct data_onenand_read {
- unsigned sfbcfg;
- unsigned sfcmd[9];
- unsigned sfexec;
- unsigned sfstat[9];
- unsigned addr0;
- unsigned addr1;
- unsigned addr2;
- unsigned addr3;
- unsigned addr4;
- unsigned addr5;
- unsigned addr6;
- unsigned data0;
- unsigned data1;
- unsigned data2;
- unsigned data3;
- unsigned data4;
- unsigned data5;
- unsigned data6;
- unsigned macro[5];
+ unsigned sfbcfg;
+ unsigned sfcmd[9];
+ unsigned sfexec;
+ unsigned sfstat[9];
+ unsigned addr0;
+ unsigned addr1;
+ unsigned addr2;
+ unsigned addr3;
+ unsigned addr4;
+ unsigned addr5;
+ unsigned addr6;
+ unsigned data0;
+ unsigned data1;
+ unsigned data2;
+ unsigned data3;
+ unsigned data4;
+ unsigned data5;
+ unsigned data6;
+ unsigned macro[5];
};
-
-static int _flash_onenand_read_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, void *_addr, void *_spareaddr,
- unsigned raw_mode)
+static int
+_flash_onenand_read_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, void *_addr, void *_spareaddr,
+ unsigned raw_mode)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct data_onenand_read *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned curr_addr = (unsigned) _addr;
+ struct data_onenand_read *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned curr_addr = (unsigned)_addr;
#if VERBOSE
- unsigned spareaddr = (unsigned) _spareaddr;
+ unsigned spareaddr = (unsigned)_spareaddr;
#endif
unsigned i;
unsigned erasesize = (flash_pagesize * num_pages_per_blk);
unsigned writesize = flash_pagesize;
unsigned onenand_startaddr1 = DEVICE_FLASHCORE_0 |
- ((unsigned)(page * flash_pagesize) / erasesize);
+ ((unsigned)(page * flash_pagesize) / erasesize);
unsigned onenand_startaddr8 = (((unsigned)(page * flash_pagesize) &
- (erasesize - 1)) / writesize) << 2;
+ (erasesize - 1)) / writesize) << 2;
unsigned onenand_startaddr2 = DEVICE_BUFFERRAM_0 << 15;
unsigned onenand_startbuffer = DATARAM0_0 << 8;
- unsigned onenand_sysconfig1 = (raw_mode == 1) ? ONENAND_SYSCFG1_ECCDIS :\
- ONENAND_SYSCFG1_ECCENA;
+ unsigned onenand_sysconfig1 = (raw_mode == 1) ? ONENAND_SYSCFG1_ECCDIS :
+ ONENAND_SYSCFG1_ECCENA;
unsigned controller_status;
unsigned interrupt_status;
unsigned ecc_status;
- if (raw_mode != 1)
- {
+ if (raw_mode != 1) {
int isbad = 0;
isbad = flash_onenand_block_isbad(cmdlist, ptrlist, page);
if (isbad)
return -2;
}
-
//static int oobfree_offset[8] = {2, 14, 18, 30, 34, 46, 50, 62};
//static int oobfree_length[8] = {3, 2, 3, 2, 3, 2, 3, 2};
data->sfbcfg = SFLASH_BCFG;
- data->sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
- data->sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_INTHI);
- data->sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGRD);
- data->sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATRD);
- data->sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATRD);
- data->sfcmd[5] = SFLASH_PREPCMD(256, 0, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATRD);
- data->sfcmd[6] = SFLASH_PREPCMD(256, 0, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATRD);
- data->sfcmd[7] = SFLASH_PREPCMD(32, 0, 0,
- NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATRD);
- data->sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
- NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
+ data->sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
+ data->sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_INTHI);
+ data->sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGRD);
+ data->sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATRD);
+ data->sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATRD);
+ data->sfcmd[5] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATRD);
+ data->sfcmd[6] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATRD);
+ data->sfcmd[7] = SFLASH_PREPCMD(32, 0, 0,
+ NAND_SFCMD_DATXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATRD);
+ data->sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
+ NAND_SFCMD_CMDXS,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
data->sfexec = 1;
data->sfstat[0] = CLEAN_DATA_32;
data->sfstat[1] = CLEAN_DATA_32;
@@ -2384,34 +2375,25 @@
data->sfstat[7] = CLEAN_DATA_32;
data->sfstat[8] = CLEAN_DATA_32;
- data->addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr1 = (ONENAND_START_ADDRESS_8 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->addr2 = (ONENAND_START_BUFFER << 16) |
- (ONENAND_START_ADDRESS_2);
- data->addr3 = (ONENAND_ECC_STATUS << 16) |
- (ONENAND_COMMAND);
+ data->addr0 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr1 =
+ (ONENAND_START_ADDRESS_8 << 16) | (ONENAND_START_ADDRESS_1);
+ data->addr2 = (ONENAND_START_BUFFER << 16) | (ONENAND_START_ADDRESS_2);
+ data->addr3 = (ONENAND_ECC_STATUS << 16) | (ONENAND_COMMAND);
data->addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
- (ONENAND_INTERRUPT_STATUS);
- data->addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr6 = (ONENAND_START_ADDRESS_3 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->data0 = (ONENAND_CLRINTR << 16) |
- (onenand_sysconfig1);
- data->data1 = (onenand_startaddr8 << 16) |
- (onenand_startaddr1);
- data->data2 = (onenand_startbuffer << 16) |
- (onenand_startaddr2);
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDLOADSPARE);
- data->data4 = (CLEAN_DATA_16 << 16) |
- (CLEAN_DATA_16);
- data->data5 = (ONENAND_CLRINTR << 16) |
- (ONENAND_SYSCFG1_ECCENA);
- data->data6 = (ONENAND_STARTADDR3_RES << 16) |
- (ONENAND_STARTADDR1_RES);
+ (ONENAND_INTERRUPT_STATUS);
+ data->addr5 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr6 =
+ (ONENAND_START_ADDRESS_3 << 16) | (ONENAND_START_ADDRESS_1);
+ data->data0 = (ONENAND_CLRINTR << 16) | (onenand_sysconfig1);
+ data->data1 = (onenand_startaddr8 << 16) | (onenand_startaddr1);
+ data->data2 = (onenand_startbuffer << 16) | (onenand_startaddr2);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDLOADSPARE);
+ data->data4 = (CLEAN_DATA_16 << 16) | (CLEAN_DATA_16);
+ data->data5 = (ONENAND_CLRINTR << 16) | (ONENAND_SYSCFG1_ECCENA);
+ data->data6 = (ONENAND_STARTADDR3_RES << 16) | (ONENAND_STARTADDR1_RES);
data->macro[0] = 0x0200;
data->macro[1] = 0x0300;
data->macro[2] = 0x0400;
@@ -2419,7 +2401,7 @@
data->macro[4] = 0x8010;
/*************************************************************/
- /* Write necessary address registers in the onenand device */
+ /* Write necessary address registers in the onenand device */
/*************************************************************/
/* Enable and configure the SFlash controller */
@@ -2510,9 +2492,8 @@
cmd->len = 4;
cmd++;
-
/*************************************************************/
- /* Read necessary status registers from the onenand device */
+ /* Read necessary status registers from the onenand device */
/*************************************************************/
/* Block on cmd ready and write CMD register */
@@ -2550,98 +2531,95 @@
cmd->len = 4;
cmd++;
-
/*************************************************************/
- /* Read the data ram area from the onenand buffer ram */
+ /* Read the data ram area from the onenand buffer ram */
/*************************************************************/
if (addr) {
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDLOAD);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDLOAD);
for (i = 0; i < 4; i++) {
- /* Block on cmd ready and write CMD register */
- cmd->cmd = DST_CRCI_NAND_CMD;
- cmd->src = paddr(&data->sfcmd[3+i]);
- cmd->dst = NAND_SFLASHC_CMD;
- cmd->len = 4;
- cmd++;
+ /* Block on cmd ready and write CMD register */
+ cmd->cmd = DST_CRCI_NAND_CMD;
+ cmd->src = paddr(&data->sfcmd[3 + i]);
+ cmd->dst = NAND_SFLASHC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Write the MACRO1 register */
- cmd->cmd = 0;
- cmd->src = paddr(&data->macro[i]);
- cmd->dst = NAND_MACRO1_REG;
- cmd->len = 4;
- cmd++;
+ /* Write the MACRO1 register */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->macro[i]);
+ cmd->dst = NAND_MACRO1_REG;
+ cmd->len = 4;
+ cmd++;
- /* Kick the execute command */
- cmd->cmd = 0;
- cmd->src = paddr(&data->sfexec);
- cmd->dst = NAND_SFLASHC_EXEC_CMD;
- cmd->len = 4;
- cmd++;
+ /* Kick the execute command */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->sfexec);
+ cmd->dst = NAND_SFLASHC_EXEC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Block on data rdy, & read status register */
- cmd->cmd = SRC_CRCI_NAND_DATA;
- cmd->src = NAND_SFLASHC_STATUS;
- cmd->dst = paddr(&data->sfstat[3+i]);
- cmd->len = 4;
- cmd++;
+ /* Block on data rdy, & read status register */
+ cmd->cmd = SRC_CRCI_NAND_DATA;
+ cmd->src = NAND_SFLASHC_STATUS;
+ cmd->dst = paddr(&data->sfstat[3 + i]);
+ cmd->len = 4;
+ cmd++;
- /* Transfer nand ctlr buf contents to usr buf */
- cmd->cmd = 0;
- cmd->src = NAND_FLASH_BUFFER;
- cmd->dst = curr_addr;
- cmd->len = 512;
- curr_addr += 512;
- cmd++;
+ /* Transfer nand ctlr buf contents to usr buf */
+ cmd->cmd = 0;
+ cmd->src = NAND_FLASH_BUFFER;
+ cmd->dst = curr_addr;
+ cmd->len = 512;
+ curr_addr += 512;
+ cmd++;
}
}
/* Read oob bytes in Raw Mode */
- if (raw_mode == 1)
- {
- /* Block on cmd ready and write CMD register */
- cmd->cmd = DST_CRCI_NAND_CMD;
- cmd->src = paddr(&data->sfcmd[7]);
- cmd->dst = NAND_SFLASHC_CMD;
- cmd->len = 4;
- cmd++;
+ if (raw_mode == 1) {
+ /* Block on cmd ready and write CMD register */
+ cmd->cmd = DST_CRCI_NAND_CMD;
+ cmd->src = paddr(&data->sfcmd[7]);
+ cmd->dst = NAND_SFLASHC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Write the MACRO1 register */
- cmd->cmd = 0;
- cmd->src = paddr(&data->macro[4]);
- cmd->dst = NAND_MACRO1_REG;
- cmd->len = 4;
- cmd++;
+ /* Write the MACRO1 register */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->macro[4]);
+ cmd->dst = NAND_MACRO1_REG;
+ cmd->len = 4;
+ cmd++;
- /* Kick the execute command */
- cmd->cmd = 0;
- cmd->src = paddr(&data->sfexec);
- cmd->dst = NAND_SFLASHC_EXEC_CMD;
- cmd->len = 4;
- cmd++;
+ /* Kick the execute command */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->sfexec);
+ cmd->dst = NAND_SFLASHC_EXEC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Block on data rdy, & read status register */
- cmd->cmd = SRC_CRCI_NAND_DATA;
- cmd->src = NAND_SFLASHC_STATUS;
- cmd->dst = paddr(&data->sfstat[7]);
- cmd->len = 4;
- cmd++;
+ /* Block on data rdy, & read status register */
+ cmd->cmd = SRC_CRCI_NAND_DATA;
+ cmd->src = NAND_SFLASHC_STATUS;
+ cmd->dst = paddr(&data->sfstat[7]);
+ cmd->len = 4;
+ cmd++;
- /* Transfer nand ctlr buf contents to usr buf */
- cmd->cmd = 0;
- cmd->src = NAND_FLASH_BUFFER;
- cmd->dst = curr_addr;
- cmd->len = 64;
- curr_addr += 64;
- cmd++;
+ /* Transfer nand ctlr buf contents to usr buf */
+ cmd->cmd = 0;
+ cmd->src = NAND_FLASH_BUFFER;
+ cmd->dst = curr_addr;
+ cmd->len = 64;
+ curr_addr += 64;
+ cmd++;
}
/*************************************************************/
- /* Restore the necessary registers to proper values */
+ /* Restore the necessary registers to proper values */
/*************************************************************/
/* Block on cmd ready and write CMD register */
@@ -2665,70 +2643,58 @@
cmd->len = 4;
cmd++;
+ ptr[0] = (paddr(cmdlist) >> 3) | CMD_PTR_LP;
- ptr[0] = (paddr(cmdlist) >> 3) | CMD_PTR_LP;
+ dmov_exec_cmdptr(DMOV_NAND_CHAN, ptr);
- dmov_exec_cmdptr(DMOV_NAND_CHAN, ptr);
-
-
- ecc_status = (data->data3 >> 16) &
- 0x0000FFFF;
- interrupt_status = (data->data4 >> 0) &
- 0x0000FFFF;
- controller_status = (data->data4 >> 16) &
- 0x0000FFFF;
+ ecc_status = (data->data3 >> 16) & 0x0000FFFF;
+ interrupt_status = (data->data4 >> 0) & 0x0000FFFF;
+ controller_status = (data->data4 >> 16) & 0x0000FFFF;
#if VERBOSE
- dprintf(INFO, "\n%s: sflash status %x %x %x %x %x %x %x"
- "%x %x\n", __func__,
- data->sfstat[0],
- data->sfstat[1],
- data->sfstat[2],
- data->sfstat[3],
- data->sfstat[4],
- data->sfstat[5],
- data->sfstat[6],
- data->sfstat[7]);
+ dprintf(INFO, "\n%s: sflash status %x %x %x %x %x %x %x"
+ "%x %x\n", __func__,
+ data->sfstat[0],
+ data->sfstat[1],
+ data->sfstat[2],
+ data->sfstat[3],
+ data->sfstat[4],
+ data->sfstat[5], data->sfstat[6], data->sfstat[7]);
- dprintf(INFO, "%s: controller_status = %x\n", __func__,
- controller_status);
- dprintf(INFO, "%s: interrupt_status = %x\n", __func__,
- interrupt_status);
- dprintf(INFO, "%s: ecc_status = %x\n", __func__,
- ecc_status);
+ dprintf(INFO, "%s: controller_status = %x\n", __func__,
+ controller_status);
+ dprintf(INFO, "%s: interrupt_status = %x\n", __func__,
+ interrupt_status);
+ dprintf(INFO, "%s: ecc_status = %x\n", __func__, ecc_status);
#endif
- /* Check for errors, protection violations etc */
- if ((controller_status != 0)
- || (data->sfstat[0] & 0x110)
- || (data->sfstat[1] & 0x110)
- || (data->sfstat[2] & 0x110)
- || ((data->sfstat[3] & 0x110) &&
- (addr))
- || ((data->sfstat[4] & 0x110) &&
- (addr))
- || ((data->sfstat[5] & 0x110) &&
- (addr))
- || ((data->sfstat[6] & 0x110) &&
- (addr))) {
- dprintf(INFO, "%s: ECC/MPU/OP error\n", __func__);
- return -1;
- }
-
+ /* Check for errors, protection violations etc */
+ if ((controller_status != 0)
+ || (data->sfstat[0] & 0x110)
+ || (data->sfstat[1] & 0x110)
+ || (data->sfstat[2] & 0x110)
+ || ((data->sfstat[3] & 0x110) && (addr))
+ || ((data->sfstat[4] & 0x110) && (addr))
+ || ((data->sfstat[5] & 0x110) &&
+ (addr)) || ((data->sfstat[6] & 0x110) && (addr))) {
+ dprintf(INFO, "%s: ECC/MPU/OP error\n", __func__);
+ return -1;
+ }
#if VERBOSE
dprintf(INFO, "read page %d: status: %x %x %x %x\n",
- page, data[5], data[6], data[7], data[8]);
- for(n = 0; n < 4; n++) {
- ptr = (unsigned*)(addr + 512 * n);
- dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
- ptr = (unsigned*)(spareaddr + 16 * n);
- dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0], ptr[1], ptr[2], ptr[3]);
+ page, data[5], data[6], data[7], data[8]);
+ for (n = 0; n < 4; n++) {
+ ptr = (unsigned *)(addr + 512 * n);
+ dprintf(INFO, "data%d: %x %x %x %x\n", n, ptr[0], ptr[1],
+ ptr[2], ptr[3]);
+ ptr = (unsigned *)(spareaddr + 16 * n);
+ dprintf(INFO, "spare data%d %x %x %x %x\n", n, ptr[0],
+ ptr[1], ptr[2], ptr[3]);
}
#endif
return 0;
}
-
struct data_onenand_write {
unsigned sfbcfg;
unsigned sfcmd[9];
@@ -2751,16 +2717,17 @@
unsigned macro[5];
};
-static int _flash_onenand_write_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, const void *_addr,
- const void *_spareaddr, unsigned raw_mode)
+static int
+_flash_onenand_write_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, const void *_addr,
+ const void *_spareaddr, unsigned raw_mode)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
- struct data_onenand_write *data = (void*) (ptrlist + 4);
- unsigned addr = (unsigned) _addr;
- unsigned addr_curr = (unsigned) _addr;
- char * spareaddr = (char *) _spareaddr;
+ struct data_onenand_write *data = (void *)(ptrlist + 4);
+ unsigned addr = (unsigned)_addr;
+ unsigned addr_curr = (unsigned)_addr;
+ char *spareaddr = (char *)_spareaddr;
unsigned i, j, k;
unsigned erasesize = (flash_pagesize * num_pages_per_blk);
@@ -2768,11 +2735,11 @@
unsigned onenand_startaddr1 = (page * flash_pagesize) / erasesize;
unsigned onenand_startaddr8 = (((unsigned)(page * flash_pagesize) &
- (erasesize-1)) / writesize) << 2;
+ (erasesize - 1)) / writesize) << 2;
unsigned onenand_startaddr2 = DEVICE_BUFFERRAM_0 << 15;
unsigned onenand_startbuffer = DATARAM0_0 << 8;
- unsigned onenand_sysconfig1 = (raw_mode == 1) ? ONENAND_SYSCFG1_ECCDIS :\
- ONENAND_SYSCFG1_ECCENA;
+ unsigned onenand_sysconfig1 = (raw_mode == 1) ? ONENAND_SYSCFG1_ECCDIS :
+ ONENAND_SYSCFG1_ECCENA;
unsigned controller_status;
unsigned interrupt_status;
@@ -2780,49 +2747,40 @@
char flash_oob[64];
- unsigned oobfree_offset[8] = {2, 14, 18, 30, 34, 46, 50, 62};
- unsigned oobfree_length[8] = {3, 2, 3, 2, 3, 2, 3, 2};
+ unsigned oobfree_offset[8] = { 2, 14, 18, 30, 34, 46, 50, 62 };
+ unsigned oobfree_length[8] = { 3, 2, 3, 2, 3, 2, 3, 2 };
for (i = 0; i < 64; i++)
flash_oob[i] = 0xFF;
data->sfbcfg = SFLASH_BCFG;
- data->sfcmd[0] = SFLASH_PREPCMD(256, 0, 0,
+ data->sfcmd[0] = SFLASH_PREPCMD(256, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATWR);
- data->sfcmd[1] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATWR);
+ data->sfcmd[1] = SFLASH_PREPCMD(256, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATWR);
- data->sfcmd[2] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATWR);
+ data->sfcmd[2] = SFLASH_PREPCMD(256, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATWR);
- data->sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATWR);
+ data->sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATWR);
- data->sfcmd[4] = SFLASH_PREPCMD(32, 0, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATWR);
+ data->sfcmd[4] = SFLASH_PREPCMD(32, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_DATWR);
- data->sfcmd[5] = SFLASH_PREPCMD(7, 0, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_DATWR);
+ data->sfcmd[5] = SFLASH_PREPCMD(7, 0, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
- data->sfcmd[6] = SFLASH_PREPCMD(0, 0, 32,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
+ data->sfcmd[6] = SFLASH_PREPCMD(0, 0, 32,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_INTHI);
- data->sfcmd[7] = SFLASH_PREPCMD(3, 7, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_INTHI);
+ data->sfcmd[7] = SFLASH_PREPCMD(3, 7, 0,
NAND_SFCMD_DATXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGRD);
- data->sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGRD);
+ data->sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
NAND_SFCMD_CMDXS,
- NAND_SFCMD_ASYNC,
- NAND_SFCMD_REGWR);
+ NAND_SFCMD_ASYNC, NAND_SFCMD_REGWR);
data->sfexec = 1;
data->sfstat[0] = CLEAN_DATA_32;
@@ -2834,45 +2792,34 @@
data->sfstat[6] = CLEAN_DATA_32;
data->sfstat[7] = CLEAN_DATA_32;
data->sfstat[8] = CLEAN_DATA_32;
- data->addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr1 = (ONENAND_START_ADDRESS_8 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->addr2 = (ONENAND_START_BUFFER << 16) |
- (ONENAND_START_ADDRESS_2);
- data->addr3 = (ONENAND_ECC_STATUS << 16) |
- (ONENAND_COMMAND);
+ data->addr0 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr1 =
+ (ONENAND_START_ADDRESS_8 << 16) | (ONENAND_START_ADDRESS_1);
+ data->addr2 = (ONENAND_START_BUFFER << 16) | (ONENAND_START_ADDRESS_2);
+ data->addr3 = (ONENAND_ECC_STATUS << 16) | (ONENAND_COMMAND);
data->addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
- (ONENAND_INTERRUPT_STATUS);
- data->addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
- (ONENAND_SYSTEM_CONFIG_1);
- data->addr6 = (ONENAND_START_ADDRESS_3 << 16) |
- (ONENAND_START_ADDRESS_1);
- data->data0 = (ONENAND_CLRINTR << 16) |
- (onenand_sysconfig1);
- data->data1 = (onenand_startaddr8 << 16) |
- (onenand_startaddr1);
- data->data2 = (onenand_startbuffer << 16) |
- (onenand_startaddr2);
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDPROGSPARE);
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDPROGSPARE);
- data->data4 = (CLEAN_DATA_16 << 16) |
- (CLEAN_DATA_16);
- data->data5 = (ONENAND_CLRINTR << 16) |
- (ONENAND_SYSCFG1_ECCENA);
- data->data6 = (ONENAND_STARTADDR3_RES << 16) |
- (ONENAND_STARTADDR1_RES);
+ (ONENAND_INTERRUPT_STATUS);
+ data->addr5 =
+ (ONENAND_INTERRUPT_STATUS << 16) | (ONENAND_SYSTEM_CONFIG_1);
+ data->addr6 =
+ (ONENAND_START_ADDRESS_3 << 16) | (ONENAND_START_ADDRESS_1);
+ data->data0 = (ONENAND_CLRINTR << 16) | (onenand_sysconfig1);
+ data->data1 = (onenand_startaddr8 << 16) | (onenand_startaddr1);
+ data->data2 = (onenand_startbuffer << 16) | (onenand_startaddr2);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDPROGSPARE);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDPROGSPARE);
+ data->data4 = (CLEAN_DATA_16 << 16) | (CLEAN_DATA_16);
+ data->data5 = (ONENAND_CLRINTR << 16) | (ONENAND_SYSCFG1_ECCENA);
+ data->data6 = (ONENAND_STARTADDR3_RES << 16) | (ONENAND_STARTADDR1_RES);
data->macro[0] = 0x0200;
data->macro[1] = 0x0300;
data->macro[2] = 0x0400;
data->macro[3] = 0x0500;
data->macro[4] = 0x8010;
-
/*************************************************************/
- /* Write the data ram area in the onenand buffer ram */
+ /* Write the data ram area in the onenand buffer ram */
/*************************************************************/
/* Enable and configure the SFlash controller */
@@ -2883,47 +2830,46 @@
cmd++;
if (addr) {
- data->data3 = (CLEAN_DATA_16 << 16) |
- (ONENAND_CMDPROG);
+ data->data3 = (CLEAN_DATA_16 << 16) | (ONENAND_CMDPROG);
for (i = 0; i < 4; i++) {
- /* Block on cmd ready and write CMD register */
- cmd->cmd = DST_CRCI_NAND_CMD;
- cmd->src = paddr(&data->sfcmd[i]);
- cmd->dst = NAND_SFLASHC_CMD;
- cmd->len = 4;
- cmd++;
+ /* Block on cmd ready and write CMD register */
+ cmd->cmd = DST_CRCI_NAND_CMD;
+ cmd->src = paddr(&data->sfcmd[i]);
+ cmd->dst = NAND_SFLASHC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Trnsfr usr buf contents to nand ctlr buf */
- cmd->cmd = 0;
- cmd->src = paddr(addr_curr);
- cmd->dst = NAND_FLASH_BUFFER;
- cmd->len = 512;
- if(!raw_mode)
- addr_curr += 512;
- cmd++;
+ /* Trnsfr usr buf contents to nand ctlr buf */
+ cmd->cmd = 0;
+ cmd->src = paddr(addr_curr);
+ cmd->dst = NAND_FLASH_BUFFER;
+ cmd->len = 512;
+ if (!raw_mode)
+ addr_curr += 512;
+ cmd++;
- /* Write the MACRO1 register */
- cmd->cmd = 0;
- cmd->src = paddr(&data->macro[i]);
- cmd->dst = NAND_MACRO1_REG;
- cmd->len = 4;
- cmd++;
+ /* Write the MACRO1 register */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->macro[i]);
+ cmd->dst = NAND_MACRO1_REG;
+ cmd->len = 4;
+ cmd++;
- /* Kick the execute command */
- cmd->cmd = 0;
- cmd->src = paddr(&data->sfexec);
- cmd->dst = NAND_SFLASHC_EXEC_CMD;
- cmd->len = 4;
- cmd++;
+ /* Kick the execute command */
+ cmd->cmd = 0;
+ cmd->src = paddr(&data->sfexec);
+ cmd->dst = NAND_SFLASHC_EXEC_CMD;
+ cmd->len = 4;
+ cmd++;
- /* Block on data rdy, & read status register */
- cmd->cmd = SRC_CRCI_NAND_DATA;
- cmd->src = NAND_SFLASHC_STATUS;
- cmd->dst = paddr(&data->sfstat[i]);
- cmd->len = 4;
- cmd++;
+ /* Block on data rdy, & read status register */
+ cmd->cmd = SRC_CRCI_NAND_DATA;
+ cmd->src = NAND_SFLASHC_STATUS;
+ cmd->dst = paddr(&data->sfstat[i]);
+ cmd->len = 4;
+ cmd++;
}
}
@@ -2935,24 +2881,23 @@
cmd->len = 4;
cmd++;
- if (spareaddr)
- {
- // Auto mode
- for (i = 0, k = 0; i < 8; i++) {
- for (j = 0; j < oobfree_length[i]; j++) {
- flash_oob[j+oobfree_offset[i]] = spareaddr[k];
- k++;
- }
- }
+ if (spareaddr) {
+ // Auto mode
+ for (i = 0, k = 0; i < 8; i++) {
+ for (j = 0; j < oobfree_length[i]; j++) {
+ flash_oob[j + oobfree_offset[i]] = spareaddr[k];
+ k++;
+ }
+ }
- cmd->cmd = 0;
- cmd->src = paddr(&flash_oob);
- cmd->dst = NAND_FLASH_BUFFER;
- cmd->len = 64;
- cmd++;
+ cmd->cmd = 0;
+ cmd->src = paddr(&flash_oob);
+ cmd->dst = NAND_FLASH_BUFFER;
+ cmd->len = 64;
+ cmd++;
}
- if (raw_mode){
+ if (raw_mode) {
cmd->cmd = 0;
cmd->src = paddr(addr_curr);
cmd->dst = NAND_FLASH_BUFFER;
@@ -2982,7 +2927,7 @@
cmd++;
/*************************************************************/
- /* Write necessary address registers in the onenand device */
+ /* Write necessary address registers in the onenand device */
/*************************************************************/
/* Block on cmd ready and write CMD register */
@@ -3067,7 +3012,7 @@
cmd++;
/*************************************************************/
- /* Read necessary status registers from the onenand device */
+ /* Read necessary status registers from the onenand device */
/*************************************************************/
/* Block on cmd ready and write CMD register */
@@ -3105,9 +3050,8 @@
cmd->len = 4;
cmd++;
-
/*************************************************************/
- /* Restore the necessary registers to proper values */
+ /* Restore the necessary registers to proper values */
/*************************************************************/
/* Block on cmd ready and write CMD register */
@@ -3131,80 +3075,69 @@
cmd->len = 4;
cmd++;
-
ptr[0] = (paddr(cmdlist) >> 3) | CMD_PTR_LP;
dmov_exec_cmdptr(DMOV_NAND_CHAN, ptr);
ecc_status = (data->data3 >> 16) & 0x0000FFFF;
- interrupt_status = (data->data4 >> 0)&0x0000FFFF;
- controller_status = (data->data4 >> 16)&0x0000FFFF;
+ interrupt_status = (data->data4 >> 0) & 0x0000FFFF;
+ controller_status = (data->data4 >> 16) & 0x0000FFFF;
#if VERBOSE
- dprintf(INFO, "\n%s: sflash status %x %x %x %x %x %x %x %x %x\n", __func__,
- data->sfstat[0],
- data->sfstat[1],
- data->sfstat[2],
- data->sfstat[3],
- data->sfstat[4],
- data->sfstat[5],
- data->sfstat[6],
- data->sfstat[7],
- data->sfstat[8]);
+ dprintf(INFO, "\n%s: sflash status %x %x %x %x %x %x %x %x %x\n",
+ __func__, data->sfstat[0], data->sfstat[1], data->sfstat[2],
+ data->sfstat[3], data->sfstat[4], data->sfstat[5],
+ data->sfstat[6], data->sfstat[7], data->sfstat[8]);
dprintf(INFO, "%s: controller_status = %x\n", __func__,
- controller_status);
+ controller_status);
dprintf(INFO, "%s: interrupt_status = %x\n", __func__,
- interrupt_status);
- dprintf(INFO, "%s: ecc_status = %x\n", __func__,
- ecc_status);
+ interrupt_status);
+ dprintf(INFO, "%s: ecc_status = %x\n", __func__, ecc_status);
#endif
/* Check for errors, protection violations etc */
if ((controller_status != 0)
- || (data->sfstat[5] & 0x110)
- || (data->sfstat[6] & 0x110)
- || (data->sfstat[7] & 0x110)
- || (data->sfstat[8] & 0x110)
- || ((data->sfstat[0] & 0x110) &&
- (addr))
- || ((data->sfstat[1] & 0x110) &&
- (addr))
- || ((data->sfstat[2] & 0x110) &&
- (addr))
- || ((data->sfstat[3] & 0x110) &&
- (addr))) {
+ || (data->sfstat[5] & 0x110)
+ || (data->sfstat[6] & 0x110)
+ || (data->sfstat[7] & 0x110)
+ || (data->sfstat[8] & 0x110)
+ || ((data->sfstat[0] & 0x110) && (addr))
+ || ((data->sfstat[1] & 0x110) && (addr))
+ || ((data->sfstat[2] & 0x110) &&
+ (addr)) || ((data->sfstat[3] & 0x110) && (addr))) {
dprintf(CRITICAL, "%s: ECC/MPU/OP error\n", __func__);
return -1;
}
-
return 0;
}
-static int flash_onenand_mark_badblock(dmov_s *cmdlist, unsigned *ptrlist, unsigned page)
+static int
+flash_onenand_mark_badblock(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
- memset(empty_buf,0,528);
- /* Going to first page of the block */
- if(page & num_pages_per_blk_mask)
- page = page - (page & num_pages_per_blk_mask);
- return _flash_onenand_write_page(cmdlist, ptrlist, page, empty_buf, 0, 1);
+ memset(empty_buf, 0, 528);
+ /* Going to first page of the block */
+ if (page & num_pages_per_blk_mask)
+ page = page - (page & num_pages_per_blk_mask);
+ return _flash_onenand_write_page(cmdlist, ptrlist, page, empty_buf, 0,
+ 1);
}
-static int flash_mark_badblock(dmov_s *cmdlist, unsigned *ptrlist, unsigned page)
+static int
+flash_mark_badblock(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
- switch(flash_info.type) {
- case FLASH_8BIT_NAND_DEVICE:
- case FLASH_16BIT_NAND_DEVICE:
- return flash_nand_mark_badblock(cmdlist, ptrlist, page);
- case FLASH_ONENAND_DEVICE:
- return flash_onenand_mark_badblock(cmdlist, ptrlist, page);
- default:
- return -1;
+ switch (flash_info.type) {
+ case FLASH_8BIT_NAND_DEVICE:
+ case FLASH_16BIT_NAND_DEVICE:
+ return flash_nand_mark_badblock(cmdlist, ptrlist, page);
+ case FLASH_ONENAND_DEVICE:
+ return flash_onenand_mark_badblock(cmdlist, ptrlist, page);
+ default:
+ return -1;
}
}
-
-unsigned flash_ctrl_hwinfo(dmov_s *cmdlist, unsigned *ptrlist)
+unsigned flash_ctrl_hwinfo(dmov_s * cmdlist, unsigned *ptrlist)
{
dmov_s *cmd = cmdlist;
unsigned *ptr = ptrlist;
@@ -3214,7 +3147,7 @@
data[0] = 0xeeeeeeee;
- cmd[0].cmd = CMD_LC | CMD_OCB | CMD_OCU ;
+ cmd[0].cmd = CMD_LC | CMD_OCB | CMD_OCU;
cmd[0].src = NAND_HW_INFO;
cmd[0].dst = paddr(&data[0]);
cmd[0].len = 4;
@@ -3227,7 +3160,7 @@
}
/* Wrapper functions */
-static void flash_read_id(dmov_s *cmdlist, unsigned *ptrlist)
+static void flash_read_id(dmov_s * cmdlist, unsigned *ptrlist)
{
int dev_found = 0;
unsigned index;
@@ -3235,36 +3168,34 @@
// Try to read id
flash_nand_read_id(cmdlist, ptrlist);
// Check if we support the device
- for (index=1;
- index < (sizeof(supported_flash)/sizeof(struct flash_identification));
- index++)
- {
+ for (index = 1;
+ index <
+ (sizeof(supported_flash) / sizeof(struct flash_identification));
+ index++) {
if ((flash_info.id & supported_flash[index].mask) ==
- (supported_flash[index].flash_id &
- (supported_flash[index].mask))) {
+ (supported_flash[index].
+ flash_id & (supported_flash[index].mask))) {
dev_found = 1;
break;
}
}
- if(!dev_found) {
+ if (!dev_found) {
flash_onenand_read_id(cmdlist, ptrlist);
- for (index=1;
- index < (sizeof(supported_flash)/sizeof(struct flash_identification));
- index++)
- {
+ for (index = 1;
+ index <
+ (sizeof(supported_flash) /
+ sizeof(struct flash_identification)); index++) {
if ((flash_info.id & supported_flash[index].mask) ==
- (supported_flash[index].flash_id &
- (supported_flash[index].mask))) {
- dev_found = 1;
- break;
+ (supported_flash[index].
+ flash_id & (supported_flash[index].mask))) {
+ dev_found = 1;
+ break;
}
}
}
-
-
- if(dev_found) {
+ if (dev_found) {
if (supported_flash[index].widebus)
flash_info.type = FLASH_16BIT_NAND_DEVICE;
else
@@ -3275,29 +3206,27 @@
flash_pagesize = flash_info.page_size;
flash_info.block_size = supported_flash[index].blksize;
flash_info.spare_size = supported_flash[index].oobsize;
- if (flash_info.block_size && flash_info.page_size)
- {
+ if (flash_info.block_size && flash_info.page_size) {
flash_info.num_blocks = supported_flash[index].density;
flash_info.num_blocks /= (flash_info.block_size);
- }
- else
- {
+ } else {
flash_info.num_blocks = 0;
}
ASSERT(flash_info.num_blocks);
// Use this for getting the next/current blocks
num_pages_per_blk = flash_info.block_size / flash_pagesize;
num_pages_per_blk_mask = num_pages_per_blk - 1;
- //Look for 8bit BCH ECC Nand, TODO: ECC Correctability >= 8
- if((flash_ctrl_hwinfo(cmdlist,ptrlist) == 0x307) && flash_info.id == 0x2600482c) {
+ //Look for 8bit BCH ECC Nand, TODO: ECC Correctability >= 8
+ if ((flash_ctrl_hwinfo(cmdlist, ptrlist) == 0x307)
+ && flash_info.id == 0x2600482c) {
enable_bch_ecc = 1;
}
return;
}
-
// Assume 8 bit nand device for backward compatability
if (dev_found == 0) {
- dprintf(INFO, "Device not supported. Assuming 8 bit NAND device\n");
+ dprintf(INFO,
+ "Device not supported. Assuming 8 bit NAND device\n");
flash_info.type = FLASH_8BIT_NAND_DEVICE;
}
dprintf(INFO, "nandid: 0x%x maker=0x%02x device=0x%02x page_size=%d\n",
@@ -3308,64 +3237,75 @@
flash_info.num_blocks);
}
-static int flash_erase_block(dmov_s *cmdlist, unsigned *ptrlist, unsigned page)
+static int flash_erase_block(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
- switch(flash_info.type) {
- case FLASH_8BIT_NAND_DEVICE:
- case FLASH_16BIT_NAND_DEVICE:
- return flash_nand_erase_block(cmdlist, ptrlist, page);
- case FLASH_ONENAND_DEVICE:
- return flash_onenand_erase_block(cmdlist, ptrlist, page);
- default:
- return -1;
+ switch (flash_info.type) {
+ case FLASH_8BIT_NAND_DEVICE:
+ case FLASH_16BIT_NAND_DEVICE:
+ return flash_nand_erase_block(cmdlist, ptrlist, page);
+ case FLASH_ONENAND_DEVICE:
+ return flash_onenand_erase_block(cmdlist, ptrlist, page);
+ default:
+ return -1;
}
}
-static int _flash_read_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, void *_addr, void *_spareaddr)
+static int
+_flash_read_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, void *_addr, void *_spareaddr)
{
- switch(flash_info.type) {
- case FLASH_8BIT_NAND_DEVICE:
- case FLASH_16BIT_NAND_DEVICE:
- if(interleaved_mode)
- return flash_nand_read_page_interleave(cmdlist, ptrlist, page, _addr, _spareaddr);
- else
- return _flash_nand_read_page(cmdlist, ptrlist, page, _addr, _spareaddr);
- case FLASH_ONENAND_DEVICE:
- return _flash_onenand_read_page(cmdlist, ptrlist, page, _addr, _spareaddr, 0);
- default:
- return -1;
+ switch (flash_info.type) {
+ case FLASH_8BIT_NAND_DEVICE:
+ case FLASH_16BIT_NAND_DEVICE:
+ if (interleaved_mode)
+ return flash_nand_read_page_interleave(cmdlist, ptrlist,
+ page, _addr,
+ _spareaddr);
+ else
+ return _flash_nand_read_page(cmdlist, ptrlist, page,
+ _addr, _spareaddr);
+ case FLASH_ONENAND_DEVICE:
+ return _flash_onenand_read_page(cmdlist, ptrlist, page, _addr,
+ _spareaddr, 0);
+ default:
+ return -1;
}
}
-static int _flash_block_isbad(dmov_s *cmdlist, unsigned *ptrlist, unsigned page)
+static int
+_flash_block_isbad(dmov_s * cmdlist, unsigned *ptrlist, unsigned page)
{
- switch(flash_info.type) {
- case FLASH_8BIT_NAND_DEVICE:
- case FLASH_16BIT_NAND_DEVICE:
- return flash_nand_block_isbad(cmdlist, ptrlist, page);
- case FLASH_ONENAND_DEVICE:
- return flash_onenand_block_isbad(cmdlist, ptrlist, page);
- default:
- return -1;
+ switch (flash_info.type) {
+ case FLASH_8BIT_NAND_DEVICE:
+ case FLASH_16BIT_NAND_DEVICE:
+ return flash_nand_block_isbad(cmdlist, ptrlist, page);
+ case FLASH_ONENAND_DEVICE:
+ return flash_onenand_block_isbad(cmdlist, ptrlist, page);
+ default:
+ return -1;
}
}
-static int _flash_write_page(dmov_s *cmdlist, unsigned *ptrlist,
- unsigned page, const void *_addr,
- const void *_spareaddr)
+static int
+_flash_write_page(dmov_s * cmdlist, unsigned *ptrlist,
+ unsigned page, const void *_addr, const void *_spareaddr)
{
- switch(flash_info.type) {
- case FLASH_8BIT_NAND_DEVICE:
- case FLASH_16BIT_NAND_DEVICE:
- if(interleaved_mode)
- return flash_nand_write_page_interleave(cmdlist, ptrlist, page, _addr, _spareaddr, 0);
- else
- return _flash_nand_write_page(cmdlist, ptrlist, page, _addr, _spareaddr, 0);
- case FLASH_ONENAND_DEVICE:
- return _flash_onenand_write_page(cmdlist, ptrlist, page, _addr, _spareaddr, 0);
- default:
- return -1;
+ switch (flash_info.type) {
+ case FLASH_8BIT_NAND_DEVICE:
+ case FLASH_16BIT_NAND_DEVICE:
+ if (interleaved_mode)
+ return flash_nand_write_page_interleave(cmdlist,
+ ptrlist, page,
+ _addr,
+ _spareaddr, 0);
+ else
+ return _flash_nand_write_page(cmdlist, ptrlist, page,
+ _addr, _spareaddr, 0);
+ case FLASH_ONENAND_DEVICE:
+ return _flash_onenand_write_page(cmdlist, ptrlist, page, _addr,
+ _spareaddr, 0);
+ default:
+ return -1;
}
}
@@ -3385,17 +3325,20 @@
flash_spare = memalign(32, 128);
flash_read_id(flash_cmdlist, flash_ptrlist);
- if((FLASH_8BIT_NAND_DEVICE == flash_info.type)
- ||(FLASH_16BIT_NAND_DEVICE == flash_info.type)) {
- if(flash_nand_read_config(flash_cmdlist, flash_ptrlist)) {
- dprintf(CRITICAL, "ERROR: could not read CFG0/CFG1 state\n");
+ if ((FLASH_8BIT_NAND_DEVICE == flash_info.type)
+ || (FLASH_16BIT_NAND_DEVICE == flash_info.type)) {
+ if (flash_nand_read_config(flash_cmdlist, flash_ptrlist)) {
+ dprintf(CRITICAL,
+ "ERROR: could not read CFG0/CFG1 state\n");
ASSERT(0);
}
}
/* Create a bad block table */
- bbtbl = (unsigned int *) malloc(sizeof(unsigned int) * flash_info.num_blocks);
- for(i = 0 ; i < flash_info.num_blocks ; i++)
- bbtbl[i] = -1 ;
+ bbtbl =
+ (unsigned int *)malloc(sizeof(unsigned int) *
+ flash_info.num_blocks);
+ for (i = 0; i < flash_info.num_blocks; i++)
+ bbtbl[i] = -1;
}
struct ptable *flash_get_ptable(void)
@@ -3420,25 +3363,32 @@
unsigned count = ptn->length;
set_nand_configuration(ptn->type);
- while(count-- > 0) {
- if(flash_erase_block(flash_cmdlist, flash_ptrlist, block * num_pages_per_blk)) {
- dprintf(INFO, "cannot erase @ %d (bad block?)\n", block);
+ while (count-- > 0) {
+ if (flash_erase_block
+ (flash_cmdlist, flash_ptrlist, block * num_pages_per_blk)) {
+ dprintf(INFO, "cannot erase @ %d (bad block?)\n",
+ block);
}
block++;
}
return 0;
}
-int flash_read_ext(struct ptentry *ptn, unsigned extra_per_page,
- unsigned offset, void *data, unsigned bytes)
+int
+flash_read_ext(struct ptentry *ptn, unsigned extra_per_page,
+ unsigned offset, void *data, unsigned bytes)
{
- unsigned page = (ptn->start * num_pages_per_blk) + (offset / flash_pagesize);
+ unsigned page =
+ (ptn->start * num_pages_per_blk) + (offset / flash_pagesize);
unsigned lastpage = (ptn->start + ptn->length) * num_pages_per_blk;
- unsigned count = (bytes + flash_pagesize - 1 + extra_per_page) / (flash_pagesize + extra_per_page);
- unsigned *spare = (unsigned*) flash_spare;
+ unsigned count =
+ (bytes + flash_pagesize - 1 + extra_per_page) / (flash_pagesize +
+ extra_per_page);
+ unsigned *spare = (unsigned *)flash_spare;
unsigned errors = 0;
unsigned char *image = data;
- unsigned current_block = (page - (page & num_pages_per_blk_mask)) / num_pages_per_blk;
+ unsigned current_block =
+ (page - (page & num_pages_per_blk_mask)) / num_pages_per_blk;
unsigned start_block = ptn->start;
int result = 0;
int isbad = 0;
@@ -3446,15 +3396,17 @@
set_nand_configuration(TYPE_APPS_PARTITION);
- if(offset & (flash_pagesize - 1))
+ if (offset & (flash_pagesize - 1))
return -1;
// Adjust page offset based on number of bad blocks from start to current page
- if (start_block < current_block)
- {
+ if (start_block < current_block) {
start_block_count = (current_block - start_block);
- while (start_block_count && (start_block < (ptn->start + ptn->length))) {
- isbad = _flash_block_isbad(flash_cmdlist, flash_ptrlist, start_block*num_pages_per_blk);
+ while (start_block_count
+ && (start_block < (ptn->start + ptn->length))) {
+ isbad =
+ _flash_block_isbad(flash_cmdlist, flash_ptrlist,
+ start_block * num_pages_per_blk);
if (isbad)
page += num_pages_per_blk;
else
@@ -3463,21 +3415,23 @@
}
}
- while((page < lastpage) && !start_block_count) {
- if(count == 0) {
- dprintf(INFO, "flash_read_image: success (%d errors)\n", errors);
+ while ((page < lastpage) && !start_block_count) {
+ if (count == 0) {
+ dprintf(INFO, "flash_read_image: success (%d errors)\n",
+ errors);
return 0;
}
- result = _flash_read_page(flash_cmdlist, flash_ptrlist, page, image, spare);
+ result =
+ _flash_read_page(flash_cmdlist, flash_ptrlist, page, image,
+ spare);
if (result == -1) {
// bad page, go to next page
page++;
errors++;
continue;
- }
- else if (result == -2) {
+ } else if (result == -2) {
// bad block, go to next block same offset
page += num_pages_per_blk;
errors++;
@@ -3496,61 +3450,79 @@
return 0xffffffff;
}
-int flash_write(struct ptentry *ptn, unsigned extra_per_page, const void *data,
- unsigned bytes)
+int
+flash_write(struct ptentry *ptn, unsigned extra_per_page, const void *data,
+ unsigned bytes)
{
unsigned page = ptn->start * num_pages_per_blk;
unsigned lastpage = (ptn->start + ptn->length) * num_pages_per_blk;
- unsigned *spare = (unsigned*) flash_spare;
+ unsigned *spare = (unsigned *)flash_spare;
const unsigned char *image = data;
unsigned wsize = flash_pagesize + extra_per_page;
unsigned n;
int r;
- if ((flash_info.type == FLASH_ONENAND_DEVICE) && (ptn->type == TYPE_MODEM_PARTITION))
- {
+ if ((flash_info.type == FLASH_ONENAND_DEVICE)
+ && (ptn->type == TYPE_MODEM_PARTITION)) {
dprintf(CRITICAL, "flash_write_image: feature not supported\n");
return -1;
}
set_nand_configuration(ptn->type);
- for(n = 0; n < 16; n++) spare[n] = 0xffffffff;
+ for (n = 0; n < 16; n++)
+ spare[n] = 0xffffffff;
- while(bytes > 0) {
- if(bytes < wsize) {
- dprintf(CRITICAL, "flash_write_image: image undersized (%d < %d)\n", bytes, wsize);
+ while (bytes > 0) {
+ if (bytes < wsize) {
+ dprintf(CRITICAL,
+ "flash_write_image: image undersized (%d < %d)\n",
+ bytes, wsize);
return -1;
}
- if(page >= lastpage) {
+ if (page >= lastpage) {
dprintf(CRITICAL, "flash_write_image: out of space\n");
return -1;
}
- if((page & num_pages_per_blk_mask) == 0) {
- if(flash_erase_block(flash_cmdlist, flash_ptrlist, page)) {
- dprintf(INFO, "flash_write_image: bad block @ %d\n", page / num_pages_per_blk);
+ if ((page & num_pages_per_blk_mask) == 0) {
+ if (flash_erase_block
+ (flash_cmdlist, flash_ptrlist, page)) {
+ dprintf(INFO,
+ "flash_write_image: bad block @ %d\n",
+ page / num_pages_per_blk);
page += num_pages_per_blk;
continue;
}
}
- if(extra_per_page) {
- r = _flash_write_page(flash_cmdlist, flash_ptrlist, page, image, image + flash_pagesize);
+ if (extra_per_page) {
+ r = _flash_write_page(flash_cmdlist, flash_ptrlist,
+ page, image,
+ image + flash_pagesize);
} else {
- r = _flash_write_page(flash_cmdlist, flash_ptrlist, page, image, spare);
+ r = _flash_write_page(flash_cmdlist, flash_ptrlist,
+ page, image, spare);
}
- if(r) {
- dprintf(INFO, "flash_write_image: write failure @ page %d (src %d)\n", page, image - (const unsigned char *)data);
+ if (r) {
+ dprintf(INFO,
+ "flash_write_image: write failure @ page %d (src %d)\n",
+ page, image - (const unsigned char *)data);
image -= (page & num_pages_per_blk_mask) * wsize;
bytes += (page & num_pages_per_blk_mask) * wsize;
page &= ~num_pages_per_blk_mask;
- if(flash_erase_block(flash_cmdlist, flash_ptrlist, page)) {
- dprintf(INFO, "flash_write_image: erase failure @ page %d\n", page);
+ if (flash_erase_block
+ (flash_cmdlist, flash_ptrlist, page)) {
+ dprintf(INFO,
+ "flash_write_image: erase failure @ page %d\n",
+ page);
}
if (ptn->type != TYPE_MODEM_PARTITION) {
- flash_mark_badblock(flash_cmdlist, flash_ptrlist, page);
+ flash_mark_badblock(flash_cmdlist,
+ flash_ptrlist, page);
}
- dprintf(INFO, "flash_write_image: restart write @ page %d (src %d)\n", page, image - (const unsigned char *)data);
+ dprintf(INFO,
+ "flash_write_image: restart write @ page %d (src %d)\n",
+ page, image - (const unsigned char *)data);
page += num_pages_per_blk;
continue;
}
@@ -3561,9 +3533,10 @@
/* erase any remaining pages in the partition */
page = (page + num_pages_per_blk_mask) & (~num_pages_per_blk_mask);
- while(page < lastpage){
- if(flash_erase_block(flash_cmdlist, flash_ptrlist, page)) {
- dprintf(INFO, "flash_write_image: bad block @ %d\n", page / num_pages_per_blk);
+ while (page < lastpage) {
+ if (flash_erase_block(flash_cmdlist, flash_ptrlist, page)) {
+ dprintf(INFO, "flash_write_image: bad block @ %d\n",
+ page / num_pages_per_blk);
}
page += num_pages_per_blk;
}
@@ -3575,8 +3548,8 @@
#if 0
static int flash_read_page(unsigned page, void *data, void *extra)
{
- return _flash_read_page(flash_cmdlist, flash_ptrlist,
- page, data, extra);
+ return _flash_read_page(flash_cmdlist, flash_ptrlist, page, data,
+ extra);
}
#endif
@@ -3587,16 +3560,15 @@
void enable_interleave_mode(int status)
{
- interleaved_mode = status;
- if(status)
- {
- flash_pagesize *= 2;
- platform_config_interleaved_mode_gpios();
- }
- return;
+ interleaved_mode = status;
+ if (status) {
+ flash_pagesize *= 2;
+ platform_config_interleaved_mode_gpios();
+ }
+ return;
}
int flash_ecc_bch_enabled()
{
- return enable_bch_ecc;
+ return enable_bch_ecc;
}
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index e131185..68e54f1 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -31,8 +31,10 @@
#include "mmc.h"
#include "partition_parser.h"
-char *ext3_partitions[] = {"system", "userdata", "persist", "cache", "tombstones"};
-char *vfat_partitions[] = {"modem", "mdm", "NONE"};
+char *ext3_partitions[] =
+ { "system", "userdata", "persist", "cache", "tombstones" };
+char *vfat_partitions[] = { "modem", "mdm", "NONE" };
+
unsigned int ext3_count = 0;
unsigned int vfat_count = 0;
@@ -41,374 +43,368 @@
unsigned partition_count = 0;
//TODO: Remove the dependency of mmc in these functions
-unsigned int partition_read_table( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card)
+unsigned int
+partition_read_table(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card)
{
- unsigned int ret;
+ unsigned int ret;
- /* Read MBR of the card */
- ret = mmc_boot_read_mbr( mmc_host, mmc_card );
- if( ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "MMC Boot: MBR read failed!\n" );
- return MMC_BOOT_E_FAILURE;
- }
+ /* Read MBR of the card */
+ ret = mmc_boot_read_mbr(mmc_host, mmc_card);
+ if (ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "MMC Boot: MBR read failed!\n");
+ return MMC_BOOT_E_FAILURE;
+ }
- /* Read GPT of the card if exist */
- if(gpt_partitions_exist){
- ret = mmc_boot_read_gpt(mmc_host, mmc_card);
- if( ret != MMC_BOOT_E_SUCCESS )
- {
- dprintf(CRITICAL, "MMC Boot: GPT read failed!\n" );
- return MMC_BOOT_E_FAILURE;
- }
- }
- return MMC_BOOT_E_SUCCESS;
+ /* Read GPT of the card if exist */
+ if (gpt_partitions_exist) {
+ ret = mmc_boot_read_gpt(mmc_host, mmc_card);
+ if (ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "MMC Boot: GPT read failed!\n");
+ return MMC_BOOT_E_FAILURE;
+ }
+ }
+ return MMC_BOOT_E_SUCCESS;
}
/*
* Read MBR from MMC card and fill partition table.
*/
-unsigned int mmc_boot_read_mbr( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card)
+unsigned int
+mmc_boot_read_mbr(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card)
{
- unsigned char buffer[BLOCK_SIZE];
- unsigned int dtype;
- unsigned int dfirstsec;
- unsigned int EBR_first_sec;
- unsigned int EBR_current_sec;
- int ret = MMC_BOOT_E_SUCCESS;
- int idx, i;
+ unsigned char buffer[BLOCK_SIZE];
+ unsigned int dtype;
+ unsigned int dfirstsec;
+ unsigned int EBR_first_sec;
+ unsigned int EBR_current_sec;
+ int ret = MMC_BOOT_E_SUCCESS;
+ int idx, i;
- /* Print out the MBR first */
- ret = mmc_boot_read_from_card( mmc_host, mmc_card, 0,
- BLOCK_SIZE,
- (unsigned int *)buffer);
- if (ret)
- {
- dprintf(CRITICAL, "Could not read partition from mmc\n");
- return ret;
- }
+ /* Print out the MBR first */
+ ret = mmc_boot_read_from_card(mmc_host, mmc_card, 0,
+ BLOCK_SIZE, (unsigned int *)buffer);
+ if (ret) {
+ dprintf(CRITICAL, "Could not read partition from mmc\n");
+ return ret;
+ }
- /* Check to see if signature exists */
- ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
- if (ret)
- {
- return ret;
- }
+ /* Check to see if signature exists */
+ ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
+ if (ret) {
+ return ret;
+ }
- /*
- * Process each of the four partitions in the MBR by reading the table
- * information into our mbr table.
- */
- partition_count = 0;
- idx = TABLE_ENTRY_0;
- for (i = 0; i < 4; i++)
- {
- /* Type 0xEE indicates end of MBR and GPT partitions exist */
- dtype = buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
- if (dtype == MBR_PROTECTED_TYPE){
- gpt_partitions_exist = 1;
- return ret;
- }
- partition_entries[partition_count].dtype = dtype;
- partition_entries[partition_count].attribute_flag =
- buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_STATUS];
- partition_entries[partition_count].first_lba =
- GET_LWORD_FROM_BYTE(&buffer[idx +
- i * TABLE_ENTRY_SIZE +
- OFFSET_FIRST_SEC]);
- partition_entries[partition_count].size =
- GET_LWORD_FROM_BYTE(&buffer[idx +
- i * TABLE_ENTRY_SIZE +
- OFFSET_SIZE]);
- dfirstsec = partition_entries[partition_count].first_lba;
- mbr_fill_name(&partition_entries[partition_count],
- partition_entries[partition_count].dtype);
- partition_count++;
- if (partition_count == NUM_PARTITIONS)
- return ret;
- }
+ /*
+ * Process each of the four partitions in the MBR by reading the table
+ * information into our mbr table.
+ */
+ partition_count = 0;
+ idx = TABLE_ENTRY_0;
+ for (i = 0; i < 4; i++) {
+ /* Type 0xEE indicates end of MBR and GPT partitions exist */
+ dtype = buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
+ if (dtype == MBR_PROTECTED_TYPE) {
+ gpt_partitions_exist = 1;
+ return ret;
+ }
+ partition_entries[partition_count].dtype = dtype;
+ partition_entries[partition_count].attribute_flag =
+ buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_STATUS];
+ partition_entries[partition_count].first_lba =
+ GET_LWORD_FROM_BYTE(&buffer[idx +
+ i * TABLE_ENTRY_SIZE +
+ OFFSET_FIRST_SEC]);
+ partition_entries[partition_count].size =
+ GET_LWORD_FROM_BYTE(&buffer[idx +
+ i * TABLE_ENTRY_SIZE +
+ OFFSET_SIZE]);
+ dfirstsec = partition_entries[partition_count].first_lba;
+ mbr_fill_name(&partition_entries[partition_count],
+ partition_entries[partition_count].dtype);
+ partition_count++;
+ if (partition_count == NUM_PARTITIONS)
+ return ret;
+ }
- /* See if the last partition is EBR, if not, parsing is done */
- if (dtype != MBR_EBR_TYPE)
- {
- return ret;
- }
+ /* See if the last partition is EBR, if not, parsing is done */
+ if (dtype != MBR_EBR_TYPE) {
+ return ret;
+ }
- EBR_first_sec = dfirstsec;
- EBR_current_sec = dfirstsec;
+ EBR_first_sec = dfirstsec;
+ EBR_current_sec = dfirstsec;
- ret = mmc_boot_read_from_card( mmc_host, mmc_card,
- (EBR_first_sec * 512),
- BLOCK_SIZE,
- (unsigned int *)buffer);
- if (ret)
- {
- return ret;
- }
- /* Loop to parse the EBR */
- for (i = 0;; i++)
- {
- ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
- if (ret)
- {
- ret = MMC_BOOT_E_SUCCESS;
- break;
- }
- partition_entries[partition_count].attribute_flag =
- buffer[TABLE_ENTRY_0 + OFFSET_STATUS];
- partition_entries[partition_count].dtype =
- buffer[TABLE_ENTRY_0 + OFFSET_TYPE];
- partition_entries[partition_count].first_lba =
- GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 +
- OFFSET_FIRST_SEC]) +
- EBR_current_sec;
- partition_entries[partition_count].size =
- GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 +
- OFFSET_SIZE]);
- mbr_fill_name(&(partition_entries[partition_count]),
- partition_entries[partition_count].dtype);
- partition_count++;
- if (partition_count == NUM_PARTITIONS)
- return ret;
+ ret = mmc_boot_read_from_card(mmc_host, mmc_card,
+ (EBR_first_sec * 512),
+ BLOCK_SIZE, (unsigned int *)buffer);
+ if (ret) {
+ return ret;
+ }
+ /* Loop to parse the EBR */
+ for (i = 0;; i++) {
+ ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
+ if (ret) {
+ ret = MMC_BOOT_E_SUCCESS;
+ break;
+ }
+ partition_entries[partition_count].attribute_flag =
+ buffer[TABLE_ENTRY_0 + OFFSET_STATUS];
+ partition_entries[partition_count].dtype =
+ buffer[TABLE_ENTRY_0 + OFFSET_TYPE];
+ partition_entries[partition_count].first_lba =
+ GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 +
+ OFFSET_FIRST_SEC]) +
+ EBR_current_sec;
+ partition_entries[partition_count].size =
+ GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_0 + OFFSET_SIZE]);
+ mbr_fill_name(&(partition_entries[partition_count]),
+ partition_entries[partition_count].dtype);
+ partition_count++;
+ if (partition_count == NUM_PARTITIONS)
+ return ret;
- dfirstsec =
- GET_LWORD_FROM_BYTE(&buffer[TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
- if(dfirstsec == 0)
- {
- /* Getting to the end of the EBR tables */
- break;
- }
- /* More EBR to follow - read in the next EBR sector */
- dprintf(SPEW, "Reading EBR block from 0x%X\n", EBR_first_sec
- + dfirstsec);
- ret = mmc_boot_read_from_card( mmc_host, mmc_card,
- ((EBR_first_sec + dfirstsec) * 512),
- BLOCK_SIZE,
- (unsigned int *)buffer);
- if (ret)
- {
- return ret;
- }
- EBR_current_sec = EBR_first_sec + dfirstsec;
- }
- return ret;
+ dfirstsec =
+ GET_LWORD_FROM_BYTE(&buffer
+ [TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
+ if (dfirstsec == 0) {
+ /* Getting to the end of the EBR tables */
+ break;
+ }
+ /* More EBR to follow - read in the next EBR sector */
+ dprintf(SPEW, "Reading EBR block from 0x%X\n", EBR_first_sec
+ + dfirstsec);
+ ret = mmc_boot_read_from_card(mmc_host, mmc_card,
+ ((EBR_first_sec +
+ dfirstsec) * 512), BLOCK_SIZE,
+ (unsigned int *)buffer);
+ if (ret) {
+ return ret;
+ }
+ EBR_current_sec = EBR_first_sec + dfirstsec;
+ }
+ return ret;
}
/*
* Read GPT from MMC and fill partition table
*/
-unsigned int mmc_boot_read_gpt( struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card)
+unsigned int
+mmc_boot_read_gpt(struct mmc_boot_host *mmc_host,
+ struct mmc_boot_card *mmc_card)
{
- int ret = MMC_BOOT_E_SUCCESS;
- unsigned int header_size;
- unsigned long long first_usable_lba;
- unsigned long long backup_header_lba;
- unsigned int max_partition_count = 0;
- unsigned int partition_entry_size;
- unsigned char data[BLOCK_SIZE];
- unsigned int i = 0; /* Counter for each 512 block */
- unsigned int j = 0; /* Counter for each 128 entry in the 512 block */
- unsigned int n = 0; /* Counter for UTF-16 -> 8 conversion */
- unsigned char UTF16_name[MAX_GPT_NAME_SIZE];
- /* LBA of first partition -- 1 Block after Protected MBR + 1 for PT */
- unsigned long long partition_0 = 2;
- partition_count = 0;
+ int ret = MMC_BOOT_E_SUCCESS;
+ unsigned int header_size;
+ unsigned long long first_usable_lba;
+ unsigned long long backup_header_lba;
+ unsigned int max_partition_count = 0;
+ unsigned int partition_entry_size;
+ unsigned char data[BLOCK_SIZE];
+ unsigned int i = 0; /* Counter for each 512 block */
+ unsigned int j = 0; /* Counter for each 128 entry in the 512 block */
+ unsigned int n = 0; /* Counter for UTF-16 -> 8 conversion */
+ unsigned char UTF16_name[MAX_GPT_NAME_SIZE];
+ /* LBA of first partition -- 1 Block after Protected MBR + 1 for PT */
+ unsigned long long partition_0 = 2;
+ partition_count = 0;
- /* Print out the GPT first */
- ret = mmc_boot_read_from_card( mmc_host, mmc_card,
- PROTECTIVE_MBR_SIZE,
- BLOCK_SIZE,
- (unsigned int *)data);
- if (ret)
- dprintf(CRITICAL, "GPT: Could not read primary gpt from mmc\n");
+ /* Print out the GPT first */
+ ret = mmc_boot_read_from_card(mmc_host, mmc_card,
+ PROTECTIVE_MBR_SIZE,
+ BLOCK_SIZE, (unsigned int *)data);
+ if (ret)
+ dprintf(CRITICAL, "GPT: Could not read primary gpt from mmc\n");
- ret = partition_parse_gpt_header(data, &first_usable_lba,
- &partition_entry_size, &header_size,
- &max_partition_count);
- if (ret)
- {
- dprintf(INFO, "GPT: (WARNING) Primary signature invalid\n" );
+ ret = partition_parse_gpt_header(data, &first_usable_lba,
+ &partition_entry_size, &header_size,
+ &max_partition_count);
+ if (ret) {
+ dprintf(INFO, "GPT: (WARNING) Primary signature invalid\n");
- /* Check the backup gpt */
- backup_header_lba = GET_LLWORD_FROM_BYTE(&data[BACKUP_HEADER_OFFSET]);
- ret = mmc_boot_read_from_card( mmc_host, mmc_card,
- (backup_header_lba * BLOCK_SIZE),
- BLOCK_SIZE,
- (unsigned int *)data);
+ /* Check the backup gpt */
+ backup_header_lba =
+ GET_LLWORD_FROM_BYTE(&data[BACKUP_HEADER_OFFSET]);
+ ret =
+ mmc_boot_read_from_card(mmc_host, mmc_card,
+ (backup_header_lba * BLOCK_SIZE),
+ BLOCK_SIZE, (unsigned int *)data);
- if (ret)
- {
- dprintf(CRITICAL, "GPT: Could not read backup gpt from mmc\n");
- return ret;
- }
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Could not read backup gpt from mmc\n");
+ return ret;
+ }
- ret = partition_parse_gpt_header(data, &first_usable_lba,
- &partition_entry_size, &header_size,
- &max_partition_count);
- if (ret)
- {
- dprintf(CRITICAL, "GPT: Primary and backup signatures invalid\n");
- return ret;
- }
- partition_0 = backup_header_lba - (max_partition_count / 4);
- }
+ ret = partition_parse_gpt_header(data, &first_usable_lba,
+ &partition_entry_size,
+ &header_size,
+ &max_partition_count);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Primary and backup signatures invalid\n");
+ return ret;
+ }
+ partition_0 = backup_header_lba - (max_partition_count / 4);
+ }
- /* Read GPT Entries */
- for(i = 0; i < (max_partition_count/4); i++)
- {
- ret = mmc_boot_read_from_card( mmc_host, mmc_card,
- (partition_0 * BLOCK_SIZE) +
- (i * BLOCK_SIZE),
- BLOCK_SIZE,
- (uint32_t *)data);
+ /* Read GPT Entries */
+ for (i = 0; i < (max_partition_count / 4); i++) {
+ ret = mmc_boot_read_from_card(mmc_host, mmc_card,
+ (partition_0 * BLOCK_SIZE) +
+ (i * BLOCK_SIZE),
+ BLOCK_SIZE, (uint32_t *) data);
- if (ret)
- {
- dprintf(CRITICAL,
- "GPT: mmc read card failed reading partition entries.\n" );
- return ret;
- }
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: mmc read card failed reading partition entries.\n");
+ return ret;
+ }
- for(j=0; j < 4; j++)
- {
- memcpy(&(partition_entries[partition_count].type_guid),
- &data[(j * partition_entry_size)],
- PARTITION_TYPE_GUID_SIZE);
- if (partition_entries[partition_count].type_guid[0] == 0x00 &&
- partition_entries[partition_count].type_guid[1] == 0x00)
- {
- i = max_partition_count;
- break;
- }
- memcpy(&(partition_entries[partition_count].unique_partition_guid),
- &data[(j * partition_entry_size) +
- UNIQUE_GUID_OFFSET], UNIQUE_PARTITION_GUID_SIZE);
- partition_entries[partition_count].first_lba =
- GET_LLWORD_FROM_BYTE(&data[(j * partition_entry_size) +
- FIRST_LBA_OFFSET]);
- partition_entries[partition_count].last_lba =
- GET_LLWORD_FROM_BYTE(&data[(j * partition_entry_size) +
- LAST_LBA_OFFSET]);
- partition_entries[partition_count].size =
- partition_entries[partition_count].last_lba -
- partition_entries[partition_count].first_lba;
- partition_entries[partition_count].attribute_flag =
- GET_LLWORD_FROM_BYTE(&data[(j * partition_entry_size) +
- ATTRIBUTE_FLAG_OFFSET]);
+ for (j = 0; j < 4; j++) {
+ memcpy(&(partition_entries[partition_count].type_guid),
+ &data[(j * partition_entry_size)],
+ PARTITION_TYPE_GUID_SIZE);
+ if (partition_entries[partition_count].type_guid[0] ==
+ 0x00
+ && partition_entries[partition_count].
+ type_guid[1] == 0x00) {
+ i = max_partition_count;
+ break;
+ }
+ memcpy(&
+ (partition_entries[partition_count].
+ unique_partition_guid),
+ &data[(j * partition_entry_size) +
+ UNIQUE_GUID_OFFSET],
+ UNIQUE_PARTITION_GUID_SIZE);
+ partition_entries[partition_count].first_lba =
+ GET_LLWORD_FROM_BYTE(&data
+ [(j * partition_entry_size) +
+ FIRST_LBA_OFFSET]);
+ partition_entries[partition_count].last_lba =
+ GET_LLWORD_FROM_BYTE(&data
+ [(j * partition_entry_size) +
+ LAST_LBA_OFFSET]);
+ partition_entries[partition_count].size =
+ partition_entries[partition_count].last_lba -
+ partition_entries[partition_count].first_lba;
+ partition_entries[partition_count].attribute_flag =
+ GET_LLWORD_FROM_BYTE(&data
+ [(j * partition_entry_size) +
+ ATTRIBUTE_FLAG_OFFSET]);
- memset(&UTF16_name, 0x00, MAX_GPT_NAME_SIZE);
- memcpy(UTF16_name, &data[(j * partition_entry_size) +
- PARTITION_NAME_OFFSET],
- MAX_GPT_NAME_SIZE);
- /*
- * Currently partition names in *.xml are UTF-8 and lowercase
- * Only supporting english for now so removing 2nd byte of UTF-16
- */
- for(n = 0; n < MAX_GPT_NAME_SIZE/2; n++){
- partition_entries[partition_count].name[n] = UTF16_name[n*2];
- }
- partition_count++;
- }
- }
- return ret;
+ memset(&UTF16_name, 0x00, MAX_GPT_NAME_SIZE);
+ memcpy(UTF16_name, &data[(j * partition_entry_size) +
+ PARTITION_NAME_OFFSET],
+ MAX_GPT_NAME_SIZE);
+ /*
+ * Currently partition names in *.xml are UTF-8 and lowercase
+ * Only supporting english for now so removing 2nd byte of UTF-16
+ */
+ for (n = 0; n < MAX_GPT_NAME_SIZE / 2; n++) {
+ partition_entries[partition_count].name[n] =
+ UTF16_name[n * 2];
+ }
+ partition_count++;
+ }
+ }
+ return ret;
}
static unsigned int write_mbr_in_blocks(unsigned size, unsigned char *mbrImage)
{
- unsigned int dtype;
- unsigned int dfirstsec;
- unsigned int ebrSectorOffset;
- unsigned char *ebrImage;
- unsigned char *lastAddress;
- int idx, i;
- unsigned int ret;
+ unsigned int dtype;
+ unsigned int dfirstsec;
+ unsigned int ebrSectorOffset;
+ unsigned char *ebrImage;
+ unsigned char *lastAddress;
+ int idx, i;
+ unsigned int ret;
- /* Write the first block */
- ret = mmc_write(0, BLOCK_SIZE, (unsigned int *) mbrImage);
- if (ret)
- {
- dprintf(CRITICAL, "Failed to write mbr partition\n");
- goto end;
- }
- dprintf(SPEW, "write of first MBR block ok\n");
- /*
- Loop through the MBR table to see if there is an EBR.
- If found, then figure out where to write the first EBR
- */
- idx = TABLE_ENTRY_0;
- for (i = 0; i < 4; i++)
- {
- dtype = mbrImage[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
- if (MBR_EBR_TYPE == dtype)
- {
- dprintf(SPEW, "EBR found.\n");
- break;
- }
- }
- if (MBR_EBR_TYPE != dtype)
- {
- dprintf(SPEW, "No EBR in this image\n");
- goto end;
- }
- /* EBR exists. Write each EBR block to mmc */
- ebrImage = mbrImage + BLOCK_SIZE;
- ebrSectorOffset= GET_LWORD_FROM_BYTE(&mbrImage[idx + i * TABLE_ENTRY_SIZE + OFFSET_FIRST_SEC]);
- dfirstsec = 0;
- dprintf(SPEW, "first EBR to be written at sector 0x%X\n", dfirstsec);
- lastAddress = mbrImage + size;
- while (ebrImage < lastAddress)
- {
- dprintf(SPEW, "writing to 0x%X\n", (ebrSectorOffset + dfirstsec) * BLOCK_SIZE);
- ret = mmc_write((ebrSectorOffset + dfirstsec) * BLOCK_SIZE,
- BLOCK_SIZE, (unsigned int *) ebrImage);
- if (ret)
- {
- dprintf(CRITICAL, "Failed to write EBR block to sector 0x%X\n", dfirstsec);
- goto end;
- }
- dfirstsec = GET_LWORD_FROM_BYTE(&ebrImage[TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
- ebrImage += BLOCK_SIZE;
- }
- dprintf(INFO, "MBR written to mmc successfully\n");
-end:
- return ret;
+ /* Write the first block */
+ ret = mmc_write(0, BLOCK_SIZE, (unsigned int *)mbrImage);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to write mbr partition\n");
+ goto end;
+ }
+ dprintf(SPEW, "write of first MBR block ok\n");
+ /*
+ Loop through the MBR table to see if there is an EBR.
+ If found, then figure out where to write the first EBR
+ */
+ idx = TABLE_ENTRY_0;
+ for (i = 0; i < 4; i++) {
+ dtype = mbrImage[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
+ if (MBR_EBR_TYPE == dtype) {
+ dprintf(SPEW, "EBR found.\n");
+ break;
+ }
+ }
+ if (MBR_EBR_TYPE != dtype) {
+ dprintf(SPEW, "No EBR in this image\n");
+ goto end;
+ }
+ /* EBR exists. Write each EBR block to mmc */
+ ebrImage = mbrImage + BLOCK_SIZE;
+ ebrSectorOffset =
+ GET_LWORD_FROM_BYTE(&mbrImage
+ [idx + i * TABLE_ENTRY_SIZE +
+ OFFSET_FIRST_SEC]);
+ dfirstsec = 0;
+ dprintf(SPEW, "first EBR to be written at sector 0x%X\n", dfirstsec);
+ lastAddress = mbrImage + size;
+ while (ebrImage < lastAddress) {
+ dprintf(SPEW, "writing to 0x%X\n",
+ (ebrSectorOffset + dfirstsec) * BLOCK_SIZE);
+ ret =
+ mmc_write((ebrSectorOffset + dfirstsec) * BLOCK_SIZE,
+ BLOCK_SIZE, (unsigned int *)ebrImage);
+ if (ret) {
+ dprintf(CRITICAL,
+ "Failed to write EBR block to sector 0x%X\n",
+ dfirstsec);
+ goto end;
+ }
+ dfirstsec =
+ GET_LWORD_FROM_BYTE(&ebrImage
+ [TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
+ ebrImage += BLOCK_SIZE;
+ }
+ dprintf(INFO, "MBR written to mmc successfully\n");
+ end:
+ return ret;
}
/* Write the MBR/EBR to the MMC. */
-unsigned int write_mbr(unsigned size, unsigned char *mbrImage,
- struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card)
+unsigned int
+write_mbr(unsigned size, unsigned char *mbrImage,
+ struct mmc_boot_host *mmc_host, struct mmc_boot_card *mmc_card)
{
- unsigned int ret;
+ unsigned int ret;
- /* Verify that passed in block is a valid MBR */
- ret = partition_verify_mbr_signature(size, mbrImage);
- if (ret)
- {
- goto end;
- }
+ /* Verify that passed in block is a valid MBR */
+ ret = partition_verify_mbr_signature(size, mbrImage);
+ if (ret) {
+ goto end;
+ }
- /* Write the MBR/EBR to mmc */
- ret = write_mbr_in_blocks(size, mbrImage);
- if (ret)
- {
- dprintf(CRITICAL, "Failed to write MBR block to mmc.\n" );
- goto end;
- }
- /* Re-read the MBR partition into mbr table */
- ret = mmc_boot_read_mbr( mmc_host, mmc_card );
- if (ret)
- {
- dprintf(CRITICAL, "Failed to re-read mbr partition.\n");
- goto end;
- }
- partition_dump();
-end:
- return ret;
+ /* Write the MBR/EBR to mmc */
+ ret = write_mbr_in_blocks(size, mbrImage);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to write MBR block to mmc.\n");
+ goto end;
+ }
+ /* Re-read the MBR partition into mbr table */
+ ret = mmc_boot_read_mbr(mmc_host, mmc_card);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to re-read mbr partition.\n");
+ goto end;
+ }
+ partition_dump();
+ end:
+ return ret;
}
/*
@@ -416,16 +412,16 @@
*/
int reflect(int data, int len)
{
- int ref = 0;
+ int ref = 0;
- for(int i=0; i < len; i++) {
- if(data & 0x1) {
- ref |= (1 << ((len - 1) - i));
- }
- data = (data >> 1);
- }
+ for (int i = 0; i < len; i++) {
+ if (data & 0x1) {
+ ref |= (1 << ((len - 1) - i));
+ }
+ data = (data >> 1);
+ }
- return ref;
+ return ref;
}
/*
@@ -433,526 +429,515 @@
*/
unsigned int calculate_crc32(unsigned char *buffer, int len)
{
- int byte_length = 8; /*length of unit (i.e. byte)*/
- int msb = 0;
- int polynomial = 0x104C11DB7; /* IEEE 32bit polynomial*/
- unsigned int regs = 0xFFFFFFFF; /* init to all ones */
- int regs_mask = 0xFFFFFFFF; /* ensure only 32 bit answer */
- int regs_msb = 0;
- unsigned int reflected_regs;
+ int byte_length = 8; /*length of unit (i.e. byte) */
+ int msb = 0;
+ int polynomial = 0x104C11DB7; /* IEEE 32bit polynomial */
+ unsigned int regs = 0xFFFFFFFF; /* init to all ones */
+ int regs_mask = 0xFFFFFFFF; /* ensure only 32 bit answer */
+ int regs_msb = 0;
+ unsigned int reflected_regs;
- for( int i=0; i < len; i++)
- {
- int data_byte = buffer[i];
- data_byte = reflect(data_byte,8);
- for(int j=0; j < byte_length; j++)
- {
- msb = data_byte >> (byte_length-1); /* get MSB */
- msb &= 1; /* ensure just 1 bit */
- regs_msb = (regs>>31) & 1; /* MSB of regs */
- regs = regs<<1; /* shift regs for CRC-CCITT */
- if(regs_msb ^ msb) /* MSB is a 1 */
- {
- regs = regs ^ polynomial; /* XOR with generator poly */
- }
- regs = regs & regs_mask; /* Mask off excess upper bits */
- data_byte <<= 1; /* get to next bit */
- }
- }
- regs = regs & regs_mask;
- reflected_regs = reflect(regs, 32) ^ 0xFFFFFFFF;
+ for (int i = 0; i < len; i++) {
+ int data_byte = buffer[i];
+ data_byte = reflect(data_byte, 8);
+ for (int j = 0; j < byte_length; j++) {
+ msb = data_byte >> (byte_length - 1); /* get MSB */
+ msb &= 1; /* ensure just 1 bit */
+ regs_msb = (regs >> 31) & 1; /* MSB of regs */
+ regs = regs << 1; /* shift regs for CRC-CCITT */
+ if (regs_msb ^ msb) { /* MSB is a 1 */
+ regs = regs ^ polynomial; /* XOR with generator poly */
+ }
+ regs = regs & regs_mask; /* Mask off excess upper bits */
+ data_byte <<= 1; /* get to next bit */
+ }
+ }
+ regs = regs & regs_mask;
+ reflected_regs = reflect(regs, 32) ^ 0xFFFFFFFF;
- return reflected_regs;
+ return reflected_regs;
}
/*
* Write the GPT Partition Entry Array to the MMC.
*/
-static unsigned int write_gpt_partition_array(unsigned char * header,
- unsigned int partition_array_start,
- unsigned int array_size)
+static unsigned int
+write_gpt_partition_array(unsigned char *header,
+ unsigned int partition_array_start,
+ unsigned int array_size)
{
- unsigned int ret = MMC_BOOT_E_INVAL;
- unsigned long long partition_entry_lba;
- unsigned long long partition_entry_array_start_location;
+ unsigned int ret = MMC_BOOT_E_INVAL;
+ unsigned long long partition_entry_lba;
+ unsigned long long partition_entry_array_start_location;
- partition_entry_lba = GET_LLWORD_FROM_BYTE(&header[PARTITION_ENTRIES_OFFSET]);
- partition_entry_array_start_location = partition_entry_lba * BLOCK_SIZE;
+ partition_entry_lba =
+ GET_LLWORD_FROM_BYTE(&header[PARTITION_ENTRIES_OFFSET]);
+ partition_entry_array_start_location = partition_entry_lba * BLOCK_SIZE;
- ret = mmc_write( partition_entry_array_start_location, array_size,
- (unsigned int *) partition_array_start);
- if( ret )
- {
- dprintf(CRITICAL, "GPT: FAILED to write the partition entry array\n");
- goto end;
- }
+ ret = mmc_write(partition_entry_array_start_location, array_size,
+ (unsigned int *)partition_array_start);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: FAILED to write the partition entry array\n");
+ goto end;
+ }
-end:
- return ret;
+ end:
+ return ret;
}
-static void patch_gpt(unsigned char *gptImage,
- struct mmc_boot_card * mmc_card,
- unsigned int array_size,
- unsigned int max_part_count,
- unsigned int part_entry_size)
+static void
+patch_gpt(unsigned char *gptImage,
+ struct mmc_boot_card *mmc_card,
+ unsigned int array_size,
+ unsigned int max_part_count, unsigned int part_entry_size)
{
- unsigned int partition_entry_array_start;
- unsigned char * primary_gpt_header;
- unsigned char * secondary_gpt_header;
- unsigned int offset;
- unsigned long long card_size_sec;
- int total_part=0;
- unsigned int last_part_offset;
- unsigned int crc_value;
+ unsigned int partition_entry_array_start;
+ unsigned char *primary_gpt_header;
+ unsigned char *secondary_gpt_header;
+ unsigned int offset;
+ unsigned long long card_size_sec;
+ int total_part = 0;
+ unsigned int last_part_offset;
+ unsigned int crc_value;
- /* Get size of MMC */
- card_size_sec = (mmc_card->capacity)/512;
- /* Working around cap at 4GB */
- if( card_size_sec == 0 )
- {
- card_size_sec = 4*1024*1024*2 - 1;
- }
+ /* Get size of MMC */
+ card_size_sec = (mmc_card->capacity) / 512;
+ /* Working around cap at 4GB */
+ if (card_size_sec == 0) {
+ card_size_sec = 4 * 1024 * 1024 * 2 - 1;
+ }
- /* Patching primary header */
- primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
- PUT_LONG_LONG( primary_gpt_header + BACKUP_HEADER_OFFSET,
- ((long long)(card_size_sec - 1)) );
- PUT_LONG_LONG( primary_gpt_header + LAST_USABLE_LBA_OFFSET,
- ((long long)(card_size_sec - 34)) );
+ /* Patching primary header */
+ primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
+ PUT_LONG_LONG(primary_gpt_header + BACKUP_HEADER_OFFSET,
+ ((long long)(card_size_sec - 1)));
+ PUT_LONG_LONG(primary_gpt_header + LAST_USABLE_LBA_OFFSET,
+ ((long long)(card_size_sec - 34)));
- /* Patching backup GPT */
- offset = (2 * array_size );
- secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
- PUT_LONG_LONG( secondary_gpt_header + PRIMARY_HEADER_OFFSET,
- ((long long)(card_size_sec - 1)) );
- PUT_LONG_LONG( secondary_gpt_header + LAST_USABLE_LBA_OFFSET,
- ((long long)(card_size_sec - 34)) );
- PUT_LONG_LONG( secondary_gpt_header + PARTITION_ENTRIES_OFFSET,
- ((long long)(card_size_sec - 33)) );
+ /* Patching backup GPT */
+ offset = (2 * array_size);
+ secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
+ PUT_LONG_LONG(secondary_gpt_header + PRIMARY_HEADER_OFFSET,
+ ((long long)(card_size_sec - 1)));
+ PUT_LONG_LONG(secondary_gpt_header + LAST_USABLE_LBA_OFFSET,
+ ((long long)(card_size_sec - 34)));
+ PUT_LONG_LONG(secondary_gpt_header + PARTITION_ENTRIES_OFFSET,
+ ((long long)(card_size_sec - 33)));
- /* Find last partition */
- while(*(primary_gpt_header +BLOCK_SIZE+ total_part* ENTRY_SIZE)!= 0)
- {
- total_part++;
- }
+ /* Find last partition */
+ while (*(primary_gpt_header + BLOCK_SIZE + total_part * ENTRY_SIZE) !=
+ 0) {
+ total_part++;
+ }
- /* Patching last partition */
- last_part_offset = (total_part-1)*ENTRY_SIZE +
- PARTITION_ENTRY_LAST_LBA;
- PUT_LONG_LONG( primary_gpt_header + BLOCK_SIZE + last_part_offset,
- (long long)(card_size_sec - 34) );
- PUT_LONG_LONG( primary_gpt_header + BLOCK_SIZE + last_part_offset+
- array_size,
- (long long)(card_size_sec - 34) );
+ /* Patching last partition */
+ last_part_offset =
+ (total_part - 1) * ENTRY_SIZE + PARTITION_ENTRY_LAST_LBA;
+ PUT_LONG_LONG(primary_gpt_header + BLOCK_SIZE + last_part_offset,
+ (long long)(card_size_sec - 34));
+ PUT_LONG_LONG(primary_gpt_header + BLOCK_SIZE + last_part_offset +
+ array_size, (long long)(card_size_sec - 34));
- /* Updating CRC of the Partition entry array in both headers */
- partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
- crc_value = calculate_crc32( partition_entry_array_start,
- max_part_count * part_entry_size);
- PUT_LONG ( primary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
+ /* Updating CRC of the Partition entry array in both headers */
+ partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
+ crc_value = calculate_crc32(partition_entry_array_start,
+ max_part_count * part_entry_size);
+ PUT_LONG(primary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
- crc_value = calculate_crc32( partition_entry_array_start + array_size,
- max_part_count * part_entry_size);
- PUT_LONG ( secondary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
+ crc_value = calculate_crc32(partition_entry_array_start + array_size,
+ max_part_count * part_entry_size);
+ PUT_LONG(secondary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
- /* Clearing CRC fields to calculate */
- PUT_LONG ( primary_gpt_header + HEADER_CRC_OFFSET,0 );
- crc_value = calculate_crc32( primary_gpt_header, 92);
- PUT_LONG ( primary_gpt_header + HEADER_CRC_OFFSET, crc_value);
+ /* Clearing CRC fields to calculate */
+ PUT_LONG(primary_gpt_header + HEADER_CRC_OFFSET, 0);
+ crc_value = calculate_crc32(primary_gpt_header, 92);
+ PUT_LONG(primary_gpt_header + HEADER_CRC_OFFSET, crc_value);
- PUT_LONG ( secondary_gpt_header + HEADER_CRC_OFFSET, 0);
- crc_value = (calculate_crc32( secondary_gpt_header, 92));
- PUT_LONG ( secondary_gpt_header + HEADER_CRC_OFFSET, crc_value);
+ PUT_LONG(secondary_gpt_header + HEADER_CRC_OFFSET, 0);
+ crc_value = (calculate_crc32(secondary_gpt_header, 92));
+ PUT_LONG(secondary_gpt_header + HEADER_CRC_OFFSET, crc_value);
}
/*
* Write the GPT to the MMC.
*/
-unsigned int write_gpt(unsigned size, unsigned char *gptImage,
- struct mmc_boot_host * mmc_host,
- struct mmc_boot_card * mmc_card)
+unsigned int
+write_gpt(unsigned size, unsigned char *gptImage,
+ struct mmc_boot_host *mmc_host, struct mmc_boot_card *mmc_card)
{
- unsigned int ret = MMC_BOOT_E_INVAL;
- unsigned int header_size;
- unsigned long long first_usable_lba;
- unsigned long long backup_header_lba;
- unsigned int max_partition_count = 0;
- unsigned int partition_entry_size;
- unsigned int partition_entry_array_start;
- unsigned char * primary_gpt_header;
- unsigned char * secondary_gpt_header;
- unsigned int offset;
- unsigned int partition_entry_array_size;
- unsigned long long primary_header_location; /* address on the emmc card */
- unsigned long long secondary_header_location; /* address on the emmc card */
+ unsigned int ret = MMC_BOOT_E_INVAL;
+ unsigned int header_size;
+ unsigned long long first_usable_lba;
+ unsigned long long backup_header_lba;
+ unsigned int max_partition_count = 0;
+ unsigned int partition_entry_size;
+ unsigned int partition_entry_array_start;
+ unsigned char *primary_gpt_header;
+ unsigned char *secondary_gpt_header;
+ unsigned int offset;
+ unsigned int partition_entry_array_size;
+ unsigned long long primary_header_location; /* address on the emmc card */
+ unsigned long long secondary_header_location; /* address on the emmc card */
- /* Verify that passed block has a valid GPT primary header */
- primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
- ret = partition_parse_gpt_header(primary_gpt_header, &first_usable_lba,
- &partition_entry_size, &header_size,
- &max_partition_count);
- if( ret )
- {
- dprintf(CRITICAL, "GPT: Primary signature invalid cannot write GPT\n");
- goto end;
- }
+ /* Verify that passed block has a valid GPT primary header */
+ primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
+ ret = partition_parse_gpt_header(primary_gpt_header, &first_usable_lba,
+ &partition_entry_size, &header_size,
+ &max_partition_count);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Primary signature invalid cannot write GPT\n");
+ goto end;
+ }
- /* Verify that passed block has a valid backup GPT HEADER */
- partition_entry_array_size = partition_entry_size * max_partition_count;
- if(partition_entry_array_size < MIN_PARTITION_ARRAY_SIZE)
- {
- partition_entry_array_size = MIN_PARTITION_ARRAY_SIZE;
- }
- offset = (2 * partition_entry_array_size );
- secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
- ret = partition_parse_gpt_header ( secondary_gpt_header , &first_usable_lba,
- &partition_entry_size, &header_size,
- &max_partition_count);
- if( ret )
- {
- dprintf(CRITICAL, "GPT: Backup signature invalid cannot write GPT\n");
- goto end;
- }
+ /* Verify that passed block has a valid backup GPT HEADER */
+ partition_entry_array_size = partition_entry_size * max_partition_count;
+ if (partition_entry_array_size < MIN_PARTITION_ARRAY_SIZE) {
+ partition_entry_array_size = MIN_PARTITION_ARRAY_SIZE;
+ }
+ offset = (2 * partition_entry_array_size);
+ secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
+ ret =
+ partition_parse_gpt_header(secondary_gpt_header, &first_usable_lba,
+ &partition_entry_size, &header_size,
+ &max_partition_count);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Backup signature invalid cannot write GPT\n");
+ goto end;
+ }
- /* Patching the primary and the backup header of the GPT table */
- patch_gpt(gptImage ,mmc_card ,partition_entry_array_size ,
- max_partition_count, partition_entry_size);
+ /* Patching the primary and the backup header of the GPT table */
+ patch_gpt(gptImage, mmc_card, partition_entry_array_size,
+ max_partition_count, partition_entry_size);
- /* Erasing the eMMC card before writing */
- ret = mmc_erase_card (0x00000000 , mmc_card->capacity);
- if(ret)
- {
- dprintf(CRITICAL , "Failed to erase the eMMC card\n");
- goto end;
- }
+ /* Erasing the eMMC card before writing */
+ ret = mmc_erase_card(0x00000000, mmc_card->capacity);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to erase the eMMC card\n");
+ goto end;
+ }
- /* Writing protective MBR*/
- ret = mmc_write(0 ,PROTECTIVE_MBR_SIZE ,(unsigned int *) gptImage);
- if(ret)
- {
- dprintf(CRITICAL, "Failed to write Protective MBR\n");
- goto end;
- }
- /* Writing the primary GPT header */
- primary_header_location = PROTECTIVE_MBR_SIZE;
- ret = mmc_write(primary_header_location , BLOCK_SIZE ,
- (unsigned int *)primary_gpt_header);
- if (ret)
- {
- dprintf(CRITICAL, "Failed to write GPT header\n");
- goto end;
- }
+ /* Writing protective MBR */
+ ret = mmc_write(0, PROTECTIVE_MBR_SIZE, (unsigned int *)gptImage);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to write Protective MBR\n");
+ goto end;
+ }
+ /* Writing the primary GPT header */
+ primary_header_location = PROTECTIVE_MBR_SIZE;
+ ret = mmc_write(primary_header_location, BLOCK_SIZE,
+ (unsigned int *)primary_gpt_header);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to write GPT header\n");
+ goto end;
+ }
- /* Writing the backup GPT header */
- backup_header_lba = GET_LLWORD_FROM_BYTE
- (&primary_gpt_header[BACKUP_HEADER_OFFSET]);
- secondary_header_location = backup_header_lba * BLOCK_SIZE;
- ret = mmc_write(secondary_header_location, BLOCK_SIZE ,
- (unsigned int *)secondary_gpt_header);
- if (ret)
- {
- dprintf(CRITICAL, "Failed to write GPT backup header\n");
- goto end;
- }
+ /* Writing the backup GPT header */
+ backup_header_lba = GET_LLWORD_FROM_BYTE
+ (&primary_gpt_header[BACKUP_HEADER_OFFSET]);
+ secondary_header_location = backup_header_lba * BLOCK_SIZE;
+ ret = mmc_write(secondary_header_location, BLOCK_SIZE,
+ (unsigned int *)secondary_gpt_header);
+ if (ret) {
+ dprintf(CRITICAL, "Failed to write GPT backup header\n");
+ goto end;
+ }
- /* Writing the partition entries array for the primary header */
- partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
- ret =write_gpt_partition_array( primary_gpt_header ,
- partition_entry_array_start,
- partition_entry_array_size);
- if( ret )
- {
- dprintf(CRITICAL, "GPT: Could not write GPT Partition entries array\n");
- goto end;
- }
+ /* Writing the partition entries array for the primary header */
+ partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
+ ret = write_gpt_partition_array(primary_gpt_header,
+ partition_entry_array_start,
+ partition_entry_array_size);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Could not write GPT Partition entries array\n");
+ goto end;
+ }
- /*Writing the partition entries array for the backup header */
- partition_entry_array_start =primary_gpt_header + BLOCK_SIZE+
- partition_entry_array_size;
- ret = write_gpt_partition_array( secondary_gpt_header ,
- partition_entry_array_start,
- partition_entry_array_size);
- if( ret )
- {
- dprintf(CRITICAL, "GPT: Could not write GPT Partition entries array\n");
- goto end;
- }
+ /*Writing the partition entries array for the backup header */
+ partition_entry_array_start = primary_gpt_header + BLOCK_SIZE +
+ partition_entry_array_size;
+ ret = write_gpt_partition_array(secondary_gpt_header,
+ partition_entry_array_start,
+ partition_entry_array_size);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Could not write GPT Partition entries array\n");
+ goto end;
+ }
- /* Re-read the GPT partition table */
- dprintf(INFO, "Re-reading the GPT Partition Table\n");
- ret = mmc_boot_read_gpt( mmc_host, mmc_card);
- if( ret )
- {
- dprintf( CRITICAL , "GPT: Failure to re- read the GPT Partition table\n");
- goto end;
- }
- partition_dump();
- dprintf( CRITICAL, "GPT: Partition Table written\n");
- memset(primary_gpt_header , 0x00 , size);
+ /* Re-read the GPT partition table */
+ dprintf(INFO, "Re-reading the GPT Partition Table\n");
+ ret = mmc_boot_read_gpt(mmc_host, mmc_card);
+ if (ret) {
+ dprintf(CRITICAL,
+ "GPT: Failure to re- read the GPT Partition table\n");
+ goto end;
+ }
+ partition_dump();
+ dprintf(CRITICAL, "GPT: Partition Table written\n");
+ memset(primary_gpt_header, 0x00, size);
-end:
- return ret;
+ end:
+ return ret;
}
-unsigned int write_partition(unsigned size, unsigned char* partition)
+unsigned int write_partition(unsigned size, unsigned char *partition)
{
- unsigned int ret = MMC_BOOT_E_INVAL;
- unsigned int partition_type;
- struct mmc_boot_host* mmc_host;
- struct mmc_boot_card* mmc_card;
+ unsigned int ret = MMC_BOOT_E_INVAL;
+ unsigned int partition_type;
+ struct mmc_boot_host *mmc_host;
+ struct mmc_boot_card *mmc_card;
- if (partition == 0)
- {
- dprintf(CRITICAL, "NULL partition\n");
- goto end;
- }
+ if (partition == 0) {
+ dprintf(CRITICAL, "NULL partition\n");
+ goto end;
+ }
- ret = partition_get_type(size, partition, &partition_type);
- if (ret != MMC_BOOT_E_SUCCESS)
- {
- goto end;
- }
+ ret = partition_get_type(size, partition, &partition_type);
+ if (ret != MMC_BOOT_E_SUCCESS) {
+ goto end;
+ }
- mmc_host = get_mmc_host();
- mmc_card = get_mmc_card();
+ mmc_host = get_mmc_host();
+ mmc_card = get_mmc_card();
- switch (partition_type)
- {
- case PARTITION_TYPE_MBR:
- dprintf(INFO, "Writing MBR partition\n");
- ret = write_mbr(size, partition, mmc_host, mmc_card);
- break;
+ switch (partition_type) {
+ case PARTITION_TYPE_MBR:
+ dprintf(INFO, "Writing MBR partition\n");
+ ret = write_mbr(size, partition, mmc_host, mmc_card);
+ break;
- case PARTITION_TYPE_GPT:
- dprintf(INFO, "Writing GPT partition\n");
- ret = write_gpt(size, partition, mmc_host, mmc_card);
- dprintf( CRITICAL, "Re-Flash all the partitions\n");
- break;
+ case PARTITION_TYPE_GPT:
+ dprintf(INFO, "Writing GPT partition\n");
+ ret = write_gpt(size, partition, mmc_host, mmc_card);
+ dprintf(CRITICAL, "Re-Flash all the partitions\n");
+ break;
- default:
- dprintf(CRITICAL, "Invalid partition\n");
- ret = MMC_BOOT_E_INVAL;
- goto end;
- }
+ default:
+ dprintf(CRITICAL, "Invalid partition\n");
+ ret = MMC_BOOT_E_INVAL;
+ goto end;
+ }
-end:
- return ret;
+ end:
+ return ret;
}
+
/*
* Fill name for android partition found.
*/
-static void mbr_fill_name (struct partition_entry *partition_ent,
- unsigned int type)
+static void
+mbr_fill_name(struct partition_entry *partition_ent, unsigned int type)
{
- switch(type)
- {
- memset(partition_ent->name, 0, MAX_GPT_NAME_SIZE);
- case MBR_MODEM_TYPE:
- case MBR_MODEM_TYPE2:
- /* if already assigned last name available then return */
- if(!strcmp((const char *)vfat_partitions[vfat_count], "NONE"))
- return;
- strlcpy((char *)partition_ent->name,
- (const char *)vfat_partitions[vfat_count],
- sizeof(partition_ent->name));
- vfat_count++;
- break;
- case MBR_SBL1_TYPE:
- memcpy(partition_ent->name,"sbl1",4);
- break;
- case MBR_SBL2_TYPE:
- memcpy(partition_ent->name,"sbl2",4);
- break;
- case MBR_SBL3_TYPE:
- memcpy(partition_ent->name,"sbl3",4);
- break;
- case MBR_RPM_TYPE:
- memcpy(partition_ent->name,"rpm",3);
- break;
- case MBR_TZ_TYPE:
- memcpy(partition_ent->name,"tz",2);
- break;
- case MBR_ABOOT_TYPE:
- memcpy(partition_ent->name,"aboot",5);
- break;
- case MBR_BOOT_TYPE:
- memcpy(partition_ent->name,"boot",4);
- break;
- case MBR_MODEM_ST1_TYPE:
- memcpy(partition_ent->name,"modem_st1",9);
- break;
- case MBR_MODEM_ST2_TYPE:
- memcpy(partition_ent->name,"modem_st2",9);
- break;
- case MBR_EFS2_TYPE:
- memcpy(partition_ent->name,"efs2",4);
- break;
- case MBR_USERDATA_TYPE:
- if (ext3_count == sizeof(ext3_partitions) / sizeof(char*))
- return;
- strlcpy((char *)partition_ent->name,
- (const char *)ext3_partitions[ext3_count],
- sizeof(partition_ent->name));
- ext3_count++;
- break;
- case MBR_RECOVERY_TYPE:
- memcpy(partition_ent->name,"recovery",8);
- break;
- case MBR_MISC_TYPE:
- memcpy(partition_ent->name,"misc",4);
- break;
- };
+ switch (type) {
+ memset(partition_ent->name, 0, MAX_GPT_NAME_SIZE);
+ case MBR_MODEM_TYPE:
+ case MBR_MODEM_TYPE2:
+ /* if already assigned last name available then return */
+ if (!strcmp((const char *)vfat_partitions[vfat_count], "NONE"))
+ return;
+ strlcpy((char *)partition_ent->name,
+ (const char *)vfat_partitions[vfat_count],
+ sizeof(partition_ent->name));
+ vfat_count++;
+ break;
+ case MBR_SBL1_TYPE:
+ memcpy(partition_ent->name, "sbl1", 4);
+ break;
+ case MBR_SBL2_TYPE:
+ memcpy(partition_ent->name, "sbl2", 4);
+ break;
+ case MBR_SBL3_TYPE:
+ memcpy(partition_ent->name, "sbl3", 4);
+ break;
+ case MBR_RPM_TYPE:
+ memcpy(partition_ent->name, "rpm", 3);
+ break;
+ case MBR_TZ_TYPE:
+ memcpy(partition_ent->name, "tz", 2);
+ break;
+ case MBR_ABOOT_TYPE:
+ memcpy(partition_ent->name, "aboot", 5);
+ break;
+ case MBR_BOOT_TYPE:
+ memcpy(partition_ent->name, "boot", 4);
+ break;
+ case MBR_MODEM_ST1_TYPE:
+ memcpy(partition_ent->name, "modem_st1", 9);
+ break;
+ case MBR_MODEM_ST2_TYPE:
+ memcpy(partition_ent->name, "modem_st2", 9);
+ break;
+ case MBR_EFS2_TYPE:
+ memcpy(partition_ent->name, "efs2", 4);
+ break;
+ case MBR_USERDATA_TYPE:
+ if (ext3_count == sizeof(ext3_partitions) / sizeof(char *))
+ return;
+ strlcpy((char *)partition_ent->name,
+ (const char *)ext3_partitions[ext3_count],
+ sizeof(partition_ent->name));
+ ext3_count++;
+ break;
+ case MBR_RECOVERY_TYPE:
+ memcpy(partition_ent->name, "recovery", 8);
+ break;
+ case MBR_MISC_TYPE:
+ memcpy(partition_ent->name, "misc", 4);
+ break;
+ };
}
/*
* Find index of parition in array of partition entries
*/
-unsigned partition_get_index (const char * name)
+unsigned partition_get_index(const char *name)
{
- unsigned int input_string_length = strlen(name);
- unsigned n;
+ unsigned int input_string_length = strlen(name);
+ unsigned n;
- for(n = 0; n < partition_count; n++){
- if(!memcmp(name, &partition_entries[n].name, input_string_length) &&
- input_string_length == strlen((const char *)&partition_entries[n].name))
- {
- return n;
- }
- }
- return INVALID_PTN;
+ for (n = 0; n < partition_count; n++) {
+ if (!memcmp
+ (name, &partition_entries[n].name, input_string_length)
+ && input_string_length ==
+ strlen((const char *)&partition_entries[n].name)) {
+ return n;
+ }
+ }
+ return INVALID_PTN;
}
/* Get size of the partition */
-unsigned long long partition_get_size (int index)
+unsigned long long partition_get_size(int index)
{
- if (index == INVALID_PTN)
- return 0;
- else{
- return partition_entries[index].size * BLOCK_SIZE;
- }
+ if (index == INVALID_PTN)
+ return 0;
+ else {
+ return partition_entries[index].size * BLOCK_SIZE;
+ }
}
/* Get offset of the partition */
-unsigned long long partition_get_offset (int index)
+unsigned long long partition_get_offset(int index)
{
- if (index == INVALID_PTN)
- return 0;
- else{
- return partition_entries[index].first_lba * BLOCK_SIZE;
- }
+ if (index == INVALID_PTN)
+ return 0;
+ else {
+ return partition_entries[index].first_lba * BLOCK_SIZE;
+ }
}
/* Debug: Print all parsed partitions */
void partition_dump()
{
- unsigned i = 0;
- for (i=0; i< partition_count; i++){
- dprintf(SPEW,
- "ptn[%d]:Name[%s] Size[%llu] Type[%u] First[%llu] Last[%llu]\n",
- i, partition_entries[i].name, partition_entries[i].size,
- partition_entries[i].dtype, partition_entries[i].first_lba,
- partition_entries[i].last_lba);
- }
+ unsigned i = 0;
+ for (i = 0; i < partition_count; i++) {
+ dprintf(SPEW,
+ "ptn[%d]:Name[%s] Size[%llu] Type[%u] First[%llu] Last[%llu]\n",
+ i, partition_entries[i].name, partition_entries[i].size,
+ partition_entries[i].dtype,
+ partition_entries[i].first_lba,
+ partition_entries[i].last_lba);
+ }
}
-unsigned int partition_verify_mbr_signature(unsigned size,
- unsigned char* buffer)
+unsigned int
+partition_verify_mbr_signature(unsigned size, unsigned char *buffer)
{
- /* Avoid checking past end of buffer */
- if ((TABLE_SIGNATURE + 1) > size)
- {
- return MMC_BOOT_E_FAILURE;
- }
- /* Check to see if signature exists */
- if ((buffer[TABLE_SIGNATURE] != MMC_MBR_SIGNATURE_BYTE_0) ||
- (buffer[TABLE_SIGNATURE + 1] != MMC_MBR_SIGNATURE_BYTE_1))
- {
- dprintf(CRITICAL, "MBR signature does not match.\n" );
- return MMC_BOOT_E_FAILURE;
- }
- return MMC_BOOT_E_SUCCESS;
+ /* Avoid checking past end of buffer */
+ if ((TABLE_SIGNATURE + 1) > size) {
+ return MMC_BOOT_E_FAILURE;
+ }
+ /* Check to see if signature exists */
+ if ((buffer[TABLE_SIGNATURE] != MMC_MBR_SIGNATURE_BYTE_0) ||
+ (buffer[TABLE_SIGNATURE + 1] != MMC_MBR_SIGNATURE_BYTE_1)) {
+ dprintf(CRITICAL, "MBR signature does not match.\n");
+ return MMC_BOOT_E_FAILURE;
+ }
+ return MMC_BOOT_E_SUCCESS;
}
-unsigned int mbr_partition_get_type(unsigned size, unsigned char* partition,
- unsigned int *partition_type)
+unsigned int
+mbr_partition_get_type(unsigned size, unsigned char *partition,
+ unsigned int *partition_type)
{
- unsigned int type_offset = TABLE_ENTRY_0 + OFFSET_TYPE;
+ unsigned int type_offset = TABLE_ENTRY_0 + OFFSET_TYPE;
- if (size < type_offset)
- {
- goto end;
- }
+ if (size < type_offset) {
+ goto end;
+ }
- *partition_type = partition[type_offset];
-end:
- return MMC_BOOT_E_SUCCESS;
+ *partition_type = partition[type_offset];
+ end:
+ return MMC_BOOT_E_SUCCESS;
}
-unsigned int partition_get_type(unsigned size, unsigned char* partition,
- unsigned int *partition_type)
+unsigned int
+partition_get_type(unsigned size, unsigned char *partition,
+ unsigned int *partition_type)
{
- unsigned int ret = MMC_BOOT_E_SUCCESS;
+ unsigned int ret = MMC_BOOT_E_SUCCESS;
- /*
- * If the block contains the MBR signature, then it's likely either
- * MBR or MBR with protective type (GPT). If the MBR signature is
- * not there, then it could be the GPT backup.
- */
+ /*
+ * If the block contains the MBR signature, then it's likely either
+ * MBR or MBR with protective type (GPT). If the MBR signature is
+ * not there, then it could be the GPT backup.
+ */
- /* First check the MBR signature */
- ret = partition_verify_mbr_signature(size, partition);
- if (ret == MMC_BOOT_E_SUCCESS)
- {
- unsigned int mbr_partition_type = PARTITION_TYPE_MBR;
+ /* First check the MBR signature */
+ ret = partition_verify_mbr_signature(size, partition);
+ if (ret == MMC_BOOT_E_SUCCESS) {
+ unsigned int mbr_partition_type = PARTITION_TYPE_MBR;
- /* MBR signature verified. This could be MBR, MBR + EBR, or GPT */
- ret = mbr_partition_get_type(size, partition, &mbr_partition_type);
- if (ret != MMC_BOOT_E_SUCCESS)
- {
- dprintf(CRITICAL, "Cannot get TYPE of partition");
- }
- else if (MBR_PROTECTED_TYPE == mbr_partition_type)
- {
- *partition_type = PARTITION_TYPE_GPT;
- }
- else
- {
- *partition_type = PARTITION_TYPE_MBR;
- }
- }
- else
- {
- /*
- * This could be the GPT backup. Make that assumption for now.
- * Anybody who treats the block as GPT backup should check the
- * signature.
- */
- *partition_type = PARTITION_TYPE_GPT_BACKUP;
- }
- return ret;
+ /* MBR signature verified. This could be MBR, MBR + EBR, or GPT */
+ ret =
+ mbr_partition_get_type(size, partition,
+ &mbr_partition_type);
+ if (ret != MMC_BOOT_E_SUCCESS) {
+ dprintf(CRITICAL, "Cannot get TYPE of partition");
+ } else if (MBR_PROTECTED_TYPE == mbr_partition_type) {
+ *partition_type = PARTITION_TYPE_GPT;
+ } else {
+ *partition_type = PARTITION_TYPE_MBR;
+ }
+ } else {
+ /*
+ * This could be the GPT backup. Make that assumption for now.
+ * Anybody who treats the block as GPT backup should check the
+ * signature.
+ */
+ *partition_type = PARTITION_TYPE_GPT_BACKUP;
+ }
+ return ret;
}
/*
* Parse the gpt header and get the required header fields
* Return 0 on valid signature
*/
-unsigned int partition_parse_gpt_header(unsigned char * buffer,
- unsigned long long * first_usable_lba,
- unsigned int * partition_entry_size,
- unsigned int * header_size,
- unsigned int * max_partition_count)
+unsigned int
+partition_parse_gpt_header(unsigned char *buffer,
+ unsigned long long *first_usable_lba,
+ unsigned int *partition_entry_size,
+ unsigned int *header_size,
+ unsigned int *max_partition_count)
{
- /* Check GPT Signature */
- if( ((uint32_t *) buffer)[0] != GPT_SIGNATURE_2 ||
- ((uint32_t *) buffer)[1] != GPT_SIGNATURE_1 )
- return 1;
+ /* Check GPT Signature */
+ if (((uint32_t *) buffer)[0] != GPT_SIGNATURE_2 ||
+ ((uint32_t *) buffer)[1] != GPT_SIGNATURE_1)
+ return 1;
- *header_size = GET_LWORD_FROM_BYTE(&buffer[HEADER_SIZE_OFFSET]);
- *first_usable_lba = GET_LLWORD_FROM_BYTE(&buffer[FIRST_USABLE_LBA_OFFSET]);
- *max_partition_count = GET_LWORD_FROM_BYTE(&buffer[PARTITION_COUNT_OFFSET]);
- *partition_entry_size = GET_LWORD_FROM_BYTE(&buffer[PENTRY_SIZE_OFFSET]);
+ *header_size = GET_LWORD_FROM_BYTE(&buffer[HEADER_SIZE_OFFSET]);
+ *first_usable_lba =
+ GET_LLWORD_FROM_BYTE(&buffer[FIRST_USABLE_LBA_OFFSET]);
+ *max_partition_count =
+ GET_LWORD_FROM_BYTE(&buffer[PARTITION_COUNT_OFFSET]);
+ *partition_entry_size =
+ GET_LWORD_FROM_BYTE(&buffer[PENTRY_SIZE_OFFSET]);
- return 0;
+ return 0;
}
diff --git a/platform/msm_shared/proc_comm.c b/platform/msm_shared/proc_comm.c
index c6d078d..74adc38 100644
--- a/platform/msm_shared/proc_comm.c
+++ b/platform/msm_shared/proc_comm.c
@@ -33,55 +33,55 @@
#include <dev/gpio.h>
#include <platform/iomap.h>
-#define ACPU_CLK 0 /* Applications processor clock */
-#define ADM_CLK 1 /* Applications data mover clock */
-#define ADSP_CLK 2 /* ADSP clock */
-#define EBI1_CLK 3 /* External bus interface 1 clock */
-#define EBI2_CLK 4 /* External bus interface 2 clock */
-#define ECODEC_CLK 5 /* External CODEC clock */
-#define EMDH_CLK 6 /* External MDDI host clock */
-#define GP_CLK 7 /* General purpose clock */
-#define GRP_CLK 8 /* Graphics clock */
-#define I2C_CLK 9 /* I2C clock */
-#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
-#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
-#define IMEM_CLK 12 /* Internal graphics memory clock */
-#define MDC_CLK 13 /* MDDI client clock */
-#define MDP_CLK 14 /* Mobile display processor clock */
-#define PBUS_CLK 15 /* Peripheral bus clock */
-#define PCM_CLK 16 /* PCM clock */
-#define PMDH_CLK 17 /* Primary MDDI host clock */
-#define SDAC_CLK 18 /* Stereo DAC clock */
-#define SDC1_CLK 19 /* Secure Digital Card clocks */
+#define ACPU_CLK 0 /* Applications processor clock */
+#define ADM_CLK 1 /* Applications data mover clock */
+#define ADSP_CLK 2 /* ADSP clock */
+#define EBI1_CLK 3 /* External bus interface 1 clock */
+#define EBI2_CLK 4 /* External bus interface 2 clock */
+#define ECODEC_CLK 5 /* External CODEC clock */
+#define EMDH_CLK 6 /* External MDDI host clock */
+#define GP_CLK 7 /* General purpose clock */
+#define GRP_CLK 8 /* Graphics clock */
+#define I2C_CLK 9 /* I2C clock */
+#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
+#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
+#define IMEM_CLK 12 /* Internal graphics memory clock */
+#define MDC_CLK 13 /* MDDI client clock */
+#define MDP_CLK 14 /* Mobile display processor clock */
+#define PBUS_CLK 15 /* Peripheral bus clock */
+#define PCM_CLK 16 /* PCM clock */
+#define PMDH_CLK 17 /* Primary MDDI host clock */
+#define SDAC_CLK 18 /* Stereo DAC clock */
+#define SDC1_CLK 19 /* Secure Digital Card clocks */
#define SDC1_PCLK 20
#define SDC2_CLK 21
#define SDC2_PCLK 22
-#define SDC3_CLK 23
-#define SDC3_PCLK 24
+#define SDC3_CLK 23
+#define SDC3_PCLK 24
#define SDC4_CLK 25
#define SDC4_PCLK 26
-#define TSIF_CLK 27 /* Transport Stream Interface clocks */
+#define TSIF_CLK 27 /* Transport Stream Interface clocks */
#define TSIF_REF_CLK 28
-#define TV_DAC_CLK 29 /* TV clocks */
+#define TV_DAC_CLK 29 /* TV clocks */
#define TV_ENC_CLK 30
-#define UART1_CLK 31 /* UART clocks */
+#define UART1_CLK 31 /* UART clocks */
#define UART2_CLK 32
#define UART3_CLK 33
#define UART1DM_CLK 34
#define UART2DM_CLK 35
-#define USB_HS_CLK 36 /* High speed USB core clock */
-#define USB_HS_PCLK 37 /* High speed USB pbus clock */
-#define USB_OTG_CLK 38 /* Full speed USB clock */
-#define VDC_CLK 39 /* Video controller clock */
-#define VFE_CLK 40 /* Camera / Video Front End clock */
-#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
+#define USB_HS_CLK 36 /* High speed USB core clock */
+#define USB_HS_PCLK 37 /* High speed USB pbus clock */
+#define USB_OTG_CLK 38 /* Full speed USB clock */
+#define VDC_CLK 39 /* Video controller clock */
+#define VFE_CLK 40 /* Camera / Video Front End clock */
+#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
/* qsd8k adds... */
#define MDP_LCDC_PCLK_CLK 42
#define MDP_LCDC_PAD_PCLK_CLK 43
#define MDP_VSYNC_CLK 44
-#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
+#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
/* msm7x30 adds... */
#define PMDH_P_CLK 82
#define MDP_P_CLK 86
@@ -123,16 +123,16 @@
PCOM_GPIO_TLMM_UNCONFIG_GROUP,
PCOM_NV_READ_HIGH_BITS,
PCOM_NV_WRITE_HIGH_BITS,
- PCOM_RPC_GPIO_TLMM_CONFIG_EX = 0x25,
+ PCOM_RPC_GPIO_TLMM_CONFIG_EX = 0x25,
PCOM_NUM_CMDS,
};
enum {
- PCOM_INVALID_STATUS = 0x0,
- PCOM_READY,
- PCOM_CMD_RUNNING,
- PCOM_CMD_SUCCESS,
- PCOM_CMD_FAIL,
+ PCOM_INVALID_STATUS = 0x0,
+ PCOM_READY,
+ PCOM_CMD_RUNNING,
+ PCOM_CMD_SUCCESS,
+ PCOM_CMD_FAIL,
};
#ifndef PLATFORM_MSM7X30
@@ -141,9 +141,9 @@
static inline void notify_other_proc_comm(void)
{
#ifndef PLATFORM_MSM7X30
- writel(1, MSM_A2M_INT(6));
+ writel(1, MSM_A2M_INT(6));
#else
- writel(1<<6, (MSM_GCC_BASE + 0x8));
+ writel(1 << 6, (MSM_GCC_BASE + 0x8));
#endif
}
@@ -162,8 +162,8 @@
int ret = -1;
unsigned status;
-// dprintf(INFO, "proc_comm(%d,%d,%d)\n",
-// cmd, data1 ? *data1 : 0, data2 ? *data2 : 0);
+// dprintf(INFO, "proc_comm(%d,%d,%d)\n",
+// cmd, data1 ? *data1 : 0, data2 ? *data2 : 0);
while (readl(MDM_STATUS) != PCOM_READY) {
/* XXX check for A9 reset */
}
@@ -178,14 +178,14 @@
* proc comm processing
*/
writel(cmd, APP_COMMAND);
-// dprintf(INFO, "proc_comm tx\n");
+// dprintf(INFO, "proc_comm tx\n");
notify_other_proc_comm();
while (readl(APP_COMMAND) != PCOM_CMD_DONE) {
/* XXX check for A9 reset */
}
status = readl(APP_STATUS);
-// dprintf(INFO, "proc_comm status %d\n", status);
+// dprintf(INFO, "proc_comm status %d\n", status);
if (status != PCOM_CMD_FAIL) {
if (data1)
@@ -193,11 +193,11 @@
if (data2)
*data2 = readl(APP_DATA2);
ret = 0;
- /*
- * Write command idle to indicate non HLOS that
- * apps has finished reading the status & data
- * of proc comm command
- */
+ /*
+ * Write command idle to indicate non HLOS that
+ * apps has finished reading the status & data
+ * of proc comm command
+ */
writel(PCOM_CMD_IDLE, APP_COMMAND);
}
@@ -224,7 +224,7 @@
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, 0)) {
return -1;
} else {
- return (int) id;
+ return (int)id;
}
}
@@ -242,7 +242,7 @@
clock_enable(MDP_LCDC_PAD_PCLK_CLK);
}
-void mdp_clock_init (unsigned rate)
+void mdp_clock_init(unsigned rate)
{
clock_set_rate(MDP_CLK, rate);
clock_enable(MDP_CLK);
@@ -279,57 +279,54 @@
clock_enable(clock_id);
clock_set_rate(clock_id, rate);
#ifdef PLATFORM_MSM7X30
- clock_enable (PMDH_P_CLK);
+ clock_enable(PMDH_P_CLK);
#endif
}
void reboot(unsigned reboot_reason)
{
- msm_proc_comm(PCOM_RESET_CHIP, &reboot_reason, 0);
- for (;;) ;
+ msm_proc_comm(PCOM_RESET_CHIP, &reboot_reason, 0);
+ for (;;) ;
}
-int mmc_clock_enable_disable (unsigned id, unsigned enable)
+int mmc_clock_enable_disable(unsigned id, unsigned enable)
{
- if(enable)
- {
- return clock_enable(id); //Enable mmc clock rate
- }
- else
- {
- return clock_disable(id); //Disable mmc clock rate
+ if (enable) {
+ return clock_enable(id); //Enable mmc clock rate
+ } else {
+ return clock_disable(id); //Disable mmc clock rate
}
}
int mmc_clock_set_rate(unsigned id, unsigned rate)
{
- return clock_set_rate(id, rate); //Set mmc clock rate
+ return clock_set_rate(id, rate); //Set mmc clock rate
}
int mmc_clock_get_rate(unsigned id)
{
- return clock_get_rate(id); //Get mmc clock rate
+ return clock_get_rate(id); //Get mmc clock rate
}
int gpio_tlmm_config(unsigned config, unsigned disable)
{
- return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
+ return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
}
int vreg_set_level(unsigned id, unsigned mv)
{
- return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
+ return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
}
int vreg_enable(unsigned id)
{
- int enable = 1;
- return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
+ int enable = 1;
+ return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
}
int vreg_disable(unsigned id)
{
- int enable = 0;
- return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
+ int enable = 0;
+ return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
}
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index af90fbb..be4a9ca 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -62,8 +62,8 @@
/* Set each interrupt line to use N-N software model
* and edge sensitive, active high
*/
- for (i=32; i < num_irq; i += 16)
- writel(0xffffffff, GIC_DIST_CONFIG + i * 4/16 );
+ for (i = 32; i < num_irq; i += 16)
+ writel(0xffffffff, GIC_DIST_CONFIG + i * 4 / 16);
writel(0xffffffff, GIC_DIST_CONFIG + 4);
@@ -71,22 +71,22 @@
for (i = 32; i < num_irq; i += 4)
writel(cpumask, GIC_DIST_TARGET + i * 4 / 4);
- /* Set priority of all interrupts*/
+ /* Set priority of all interrupts */
/*
* In bootloader we dont care about priority so
* setting up equal priorities for all
*/
- for (i=0; i < num_irq; i += 4)
- writel(0xa0a0a0a0, GIC_DIST_PRI + i * 4/4);
+ for (i = 0; i < num_irq; i += 4)
+ writel(0xa0a0a0a0, GIC_DIST_PRI + i * 4 / 4);
- /* Disabling interrupts*/
- for (i=0; i < num_irq; i += 32)
- writel(0xffffffff, GIC_DIST_ENABLE_CLEAR + i * 4/32);
+ /* Disabling interrupts */
+ for (i = 0; i < num_irq; i += 32)
+ writel(0xffffffff, GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
writel(0x0000ffff, GIC_DIST_ENABLE_SET);
- /*Enabling GIC*/
+ /*Enabling GIC */
writel(1, GIC_DIST_CTRL);
}
@@ -129,7 +129,7 @@
/* Mask interrupt */
status_t mask_interrupt(unsigned int vector)
{
- uint32_t reg = GIC_DIST_ENABLE_CLEAR + (vector/32)*4;
+ uint32_t reg = GIC_DIST_ENABLE_CLEAR + (vector / 32) * 4;
uint32_t bit = 1 << (vector & 31);
writel(bit, reg);
@@ -140,7 +140,7 @@
/* Un-mask interrupt */
status_t unmask_interrupt(unsigned int vector)
{
- uint32_t reg = GIC_DIST_ENABLE_SET + (vector/32)*4;
+ uint32_t reg = GIC_DIST_ENABLE_SET + (vector / 32) * 4;
uint32_t bit = 1 << (vector & 31);
writel(bit, reg);
@@ -158,4 +158,3 @@
handler[vector].arg = arg;
exit_critical_section();
}
-
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index ad83f58..4905a9e 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -54,11 +54,10 @@
{
struct scm_command *cmd;
size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
- resp_size;
+ resp_size;
cmd = malloc(len);
- if (cmd)
- {
+ if (cmd) {
cmd->len = len;
cmd->buf_offset = offsetof(struct scm_command, buf);
cmd->resp_hdr_offset = cmd->buf_offset + cmd_size;
@@ -83,8 +82,8 @@
*
* Returns a pointer to a response for a command.
*/
-static inline struct scm_response *scm_command_to_response(
- const struct scm_command *cmd)
+static inline struct scm_response *scm_command_to_response(const struct
+ scm_command *cmd)
{
return (void *)cmd + cmd->resp_hdr_offset;
}
@@ -115,15 +114,9 @@
{
uint32_t context_id;
register uint32_t r0 __asm__("r0") = 1;
- register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t) & context_id;
register uint32_t r2 __asm__("r2") = cmd_addr;
- __asm__(
- "1:smc #0 @ switch to secure world\n"
- "cmp r0, #1 \n"
- "beq 1b \n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- : "r3", "cc");
+ __asm__("1:smc #0 @ switch to secure world\n" "cmp r0, #1 \n" "beq 1b \n": "=r"(r0): "r"(r0), "r"(r1), "r"(r2):"r3", "cc");
return r0;
}
@@ -138,8 +131,9 @@
*
* Sends a command to the SCM and waits for the command to finish processing.
*/
-int scm_call(uint32_t svc_id, uint32_t cmd_id, const void *cmd_buf, size_t cmd_len,
- void *resp_buf, size_t resp_len)
+int
+scm_call(uint32_t svc_id, uint32_t cmd_id, const void *cmd_buf,
+ size_t cmd_len, void *resp_buf, size_t resp_len)
{
int ret;
struct scm_command *cmd;
@@ -153,28 +147,28 @@
if (cmd_buf)
memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
- ret = smc((uint32_t)cmd);
+ ret = smc((uint32_t) cmd);
if (ret)
goto out;
- if(resp_len)
- {
+ if (resp_len) {
rsp = scm_command_to_response(cmd);
- while (!rsp->is_complete);
+ while (!rsp->is_complete) ;
if (resp_buf)
- memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
+ memcpy(resp_buf, scm_get_response_buffer(rsp),
+ resp_len);
}
-out:
+ out:
free_scm_command(cmd);
return ret;
}
/* SCM Decrypt Command */
-void setup_decrypt_cmd ( decrypt_img_req* dec_cmd,
- uint32_t** img_ptr,
- uint32_t* img_len_ptr)
+void
+setup_decrypt_cmd(decrypt_img_req * dec_cmd,
+ uint32_t ** img_ptr, uint32_t * img_len_ptr)
{
dec_cmd->common_req.len = sizeof(decrypt_img_req);
dec_cmd->common_req.buf_offset = sizeof(scm_command);
@@ -185,7 +179,7 @@
dec_cmd->img_len_ptr = img_len_ptr;
}
-int decrypt_img_scm(uint32_t** img_ptr, uint32_t* img_len_ptr)
+int decrypt_img_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr)
{
int ret = 0;
decrypt_img_req decrypt_cmd;
@@ -194,13 +188,15 @@
setup_decrypt_cmd(&decrypt_cmd, img_ptr, img_len_ptr);
/* Since TZ cannot access cached data, cmd must be flushed to main memory */
- arch_clean_invalidate_cache_range((addr_t) &decrypt_cmd, sizeof(decrypt_cmd));
+ arch_clean_invalidate_cache_range((addr_t) & decrypt_cmd,
+ sizeof(decrypt_cmd));
/* Invalidate img ptr and len from cache so that we read the updated data
* from the main memory.
*/
arch_clean_invalidate_cache_range((addr_t) img_ptr, sizeof(img_ptr));
- arch_clean_invalidate_cache_range((addr_t) img_len_ptr, sizeof(img_len_ptr));
+ arch_clean_invalidate_cache_range((addr_t) img_len_ptr,
+ sizeof(img_len_ptr));
ret = smc(&decrypt_cmd);
@@ -220,7 +216,7 @@
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
- /*no response*/
+ /*no response */
resp_buf = NULL;
resp_len = 0;
@@ -244,7 +240,7 @@
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
- /*response*/
+ /*response */
resp_len = sizeof(resp_buf);
svc_id = SCM_SVC_FUSE;
@@ -253,4 +249,3 @@
scm_call(svc_id, cmd_id, cmd_buf, cmd_len, &resp_buf, resp_len);
return resp_buf;
}
-
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index 63df5c3..00a1872 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -66,26 +66,28 @@
return 0;
}
-unsigned smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len, int offset)
+unsigned
+smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len,
+ int offset)
{
- struct smem_alloc_info *ainfo;
- unsigned *dest = buf;
- unsigned src;
- unsigned size = len;
+ struct smem_alloc_info *ainfo;
+ unsigned *dest = buf;
+ unsigned src;
+ unsigned size = len;
- if (((len & 0x3) != 0) || (((unsigned)buf & 0x3) != 0))
- return 1;
+ if (((len & 0x3) != 0) || (((unsigned)buf & 0x3) != 0))
+ return 1;
- if (type < SMEM_FIRST_VALID_TYPE || type > SMEM_LAST_VALID_TYPE)
- return 1;
+ if (type < SMEM_FIRST_VALID_TYPE || type > SMEM_LAST_VALID_TYPE)
+ return 1;
- ainfo = &smem->alloc_info[type];
- if (readl(&ainfo->allocated) == 0)
- return 1;
+ ainfo = &smem->alloc_info[type];
+ if (readl(&ainfo->allocated) == 0)
+ return 1;
- src = MSM_SHARED_BASE + readl(&ainfo->offset) + offset;
- for (; size > 0; src += 4, size -= 4)
- *(dest++) = readl(src);
+ src = MSM_SHARED_BASE + readl(&ainfo->offset) + offset;
+ for (; size > 0; src += 4, size -= 4)
+ *(dest++) = readl(src);
- return 0;
+ return 0;
}
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 9bbed30..e3a1389 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -33,24 +33,21 @@
#include <sys/types.h>
-struct smem_proc_comm
-{
+struct smem_proc_comm {
unsigned command;
unsigned status;
unsigned data1;
unsigned data2;
};
-struct smem_heap_info
-{
+struct smem_heap_info {
unsigned initialized;
unsigned free_offset;
unsigned heap_remaining;
unsigned reserved;
};
-struct smem_alloc_info
-{
+struct smem_alloc_info {
unsigned allocated;
unsigned offset;
unsigned size;
@@ -58,174 +55,160 @@
};
struct smem {
- struct smem_proc_comm proc_comm[4];
- unsigned version_info[32];
- struct smem_heap_info heap_info;
- struct smem_alloc_info alloc_info[128];
+ struct smem_proc_comm proc_comm[4];
+ unsigned version_info[32];
+ struct smem_heap_info heap_info;
+ struct smem_alloc_info alloc_info[128];
};
-struct smem_board_info_v2
-{
- unsigned format;
- unsigned msm_id;
- unsigned msm_version;
- char build_id[32];
- unsigned raw_msm_id;
- unsigned raw_msm_version;
+struct smem_board_info_v2 {
+ unsigned format;
+ unsigned msm_id;
+ unsigned msm_version;
+ char build_id[32];
+ unsigned raw_msm_id;
+ unsigned raw_msm_version;
};
-struct smem_board_info_v3
-{
- unsigned format;
- unsigned msm_id;
- unsigned msm_version;
- char build_id[32];
- unsigned raw_msm_id;
- unsigned raw_msm_version;
- unsigned hw_platform;
+struct smem_board_info_v3 {
+ unsigned format;
+ unsigned msm_id;
+ unsigned msm_version;
+ char build_id[32];
+ unsigned raw_msm_id;
+ unsigned raw_msm_version;
+ unsigned hw_platform;
};
-struct smem_board_info_v4
-{
- struct smem_board_info_v3 board_info_v3;
- unsigned platform_version;
- unsigned buffer_align; //Need for 8 bytes alignment while reading from shared memory.
+struct smem_board_info_v4 {
+ struct smem_board_info_v3 board_info_v3;
+ unsigned platform_version;
+ unsigned buffer_align; //Need for 8 bytes alignment while reading from shared memory.
};
-struct smem_board_info_v5
-{
- struct smem_board_info_v3 board_info_v3;
- unsigned platform_version;
- unsigned fused_chip;
+struct smem_board_info_v5 {
+ struct smem_board_info_v3 board_info_v3;
+ unsigned platform_version;
+ unsigned fused_chip;
};
-struct smem_board_info_v6
-{
- struct smem_board_info_v3 board_info_v3;
- unsigned platform_version;
- unsigned fused_chip;
- unsigned platform_subtype;
- unsigned buffer_align; //Need for 8 bytes alignment while reading from shared memory.
+struct smem_board_info_v6 {
+ struct smem_board_info_v3 board_info_v3;
+ unsigned platform_version;
+ unsigned fused_chip;
+ unsigned platform_subtype;
+ unsigned buffer_align; //Need for 8 bytes alignment while reading from shared memory.
};
-typedef struct
-{
- unsigned key_len;
- unsigned iv_len;
- unsigned char key[32];
- unsigned char iv[32];
-}boot_symmetric_key_info;
+typedef struct {
+ unsigned key_len;
+ unsigned iv_len;
+ unsigned char key[32];
+ unsigned char iv[32];
+} boot_symmetric_key_info;
-typedef struct
-{
- unsigned int update_status;
- unsigned int bl_error_code;
-}boot_ssd_status;
+typedef struct {
+ unsigned int update_status;
+ unsigned int bl_error_code;
+} boot_ssd_status;
#if PLATFORM_MSM7X30
-typedef struct
-{
- boot_symmetric_key_info key_info;
- uint32_t boot_flags;
- uint32_t boot_key_press[5];
- uint32_t time_tick;
- boot_ssd_status status;
- uint8_t buff_align[4];
-}boot_info_for_apps;
+typedef struct {
+ boot_symmetric_key_info key_info;
+ uint32_t boot_flags;
+ uint32_t boot_key_press[5];
+ uint32_t time_tick;
+ boot_ssd_status status;
+ uint8_t buff_align[4];
+} boot_info_for_apps;
#elif PLATFORM_MSM7K
-typedef struct
-{
- uint32_t apps_img_start_addr;
- uint32_t boot_flags;
- boot_ssd_status status;
-}boot_info_for_apps;
+typedef struct {
+ uint32_t apps_img_start_addr;
+ uint32_t boot_flags;
+ boot_ssd_status status;
+} boot_info_for_apps;
#elif PLATFORM_MSM7X27A
-typedef struct
-{
- uint32_t apps_img_start_addr;
- uint32_t boot_flags;
- boot_ssd_status status;
- boot_symmetric_key_info key_info;
- uint16_t boot_key_press[10];
- uint32_t timetick;
- uint8_t PAD[28];
-}boot_info_for_apps;
+typedef struct {
+ uint32_t apps_img_start_addr;
+ uint32_t boot_flags;
+ boot_ssd_status status;
+ boot_symmetric_key_info key_info;
+ uint16_t boot_key_press[10];
+ uint32_t timetick;
+ uint8_t PAD[28];
+} boot_info_for_apps;
#else
/* Dummy structure to keep it for other targets */
-typedef struct
-{
- uint32_t boot_flags;
- boot_ssd_status status;
-}boot_info_for_apps;
+typedef struct {
+ uint32_t boot_flags;
+ boot_ssd_status status;
+} boot_info_for_apps;
#endif
/* chip information */
enum {
- UNKNOWN = 0,
- MDM9200 = 57,
- MDM9600 = 58,
- MSM8260 = 70,
- MSM8660 = 71,
- APQ8060 = 86,
- MSM8960 = 87,
- MSM7225A = 88,
- MSM7625A = 89,
- MSM7227A = 90,
- MSM7627A = 91,
- ESM7227A = 92,
- ESM7225A = 96,
- ESM7627A = 97,
- MSM7225AA = 98,
- MSM7625AA = 99,
- ESM7225AA = 100,
- MSM7227AA = 101,
- MSM7627AA = 102,
- ESM7227AA = 103,
- APQ8064 = 109,
- MSM8930 = 116,
- MSM8630 = 117,
- MSM8230 = 118,
- APQ8030 = 119,
- MSM8627 = 120,
- MSM8227 = 121,
- MSM8660A = 122,
- MSM8260A = 123,
- APQ8060A = 124,
+ UNKNOWN = 0,
+ MDM9200 = 57,
+ MDM9600 = 58,
+ MSM8260 = 70,
+ MSM8660 = 71,
+ APQ8060 = 86,
+ MSM8960 = 87,
+ MSM7225A = 88,
+ MSM7625A = 89,
+ MSM7227A = 90,
+ MSM7627A = 91,
+ ESM7227A = 92,
+ ESM7225A = 96,
+ ESM7627A = 97,
+ MSM7225AA = 98,
+ MSM7625AA = 99,
+ ESM7225AA = 100,
+ MSM7227AA = 101,
+ MSM7627AA = 102,
+ ESM7227AA = 103,
+ APQ8064 = 109,
+ MSM8930 = 116,
+ MSM8630 = 117,
+ MSM8230 = 118,
+ APQ8030 = 119,
+ MSM8627 = 120,
+ MSM8227 = 121,
+ MSM8660A = 122,
+ MSM8260A = 123,
+ APQ8060A = 124,
};
-enum platform
-{
- HW_PLATFORM_UNKNOWN = 0,
- HW_PLATFORM_SURF = 1,
- HW_PLATFORM_FFA = 2,
- HW_PLATFORM_FLUID = 3,
- HW_PLATFORM_SVLTE = 4,
- HW_PLATFORM_QT = 6,
- HW_PLATFORM_MTP = 8,
- HW_PLATFORM_LIQUID = 9,
- HW_PLATFORM_DRAGON = 10,
- HW_PLATFORM_32BITS = 0x7FFFFFFF
+enum platform {
+ HW_PLATFORM_UNKNOWN = 0,
+ HW_PLATFORM_SURF = 1,
+ HW_PLATFORM_FFA = 2,
+ HW_PLATFORM_FLUID = 3,
+ HW_PLATFORM_SVLTE = 4,
+ HW_PLATFORM_QT = 6,
+ HW_PLATFORM_MTP = 8,
+ HW_PLATFORM_LIQUID = 9,
+ HW_PLATFORM_DRAGON = 10,
+ HW_PLATFORM_32BITS = 0x7FFFFFFF
};
-enum platform_subtype
-{
- HW_PLATFORM_SUBTYPE_UNKNOWN = 0,
- HW_PLATFORM_SUBTYPE_MDM = 1,
- HW_PLATFORM_SUBTYPE_CSFB = 1,
- HW_PLATFORM_SUBTYPE_SVLTE1 = 2,
- HW_PLATFORM_SUBTYPE_SVLTE2A = 3,
- HW_PLATFORM_SUBTYPE_32BITS = 0x7FFFFFFF
+enum platform_subtype {
+ HW_PLATFORM_SUBTYPE_UNKNOWN = 0,
+ HW_PLATFORM_SUBTYPE_MDM = 1,
+ HW_PLATFORM_SUBTYPE_CSFB = 1,
+ HW_PLATFORM_SUBTYPE_SVLTE1 = 2,
+ HW_PLATFORM_SUBTYPE_SVLTE2A = 3,
+ HW_PLATFORM_SUBTYPE_32BITS = 0x7FFFFFFF
};
-
typedef enum {
SMEM_SPINLOCK_ARRAY = 7,
@@ -250,39 +233,39 @@
/* SMEM RAM Partition */
enum {
- DEFAULT_ATTRB = ~0x0,
- READ_ONLY = 0x0,
- READWRITE,
+ DEFAULT_ATTRB = ~0x0,
+ READ_ONLY = 0x0,
+ READWRITE,
};
enum {
- DEFAULT_CATEGORY = ~0x0,
- SMI = 0x0,
- EBI1,
- EBI2,
- QDSP6,
- IRAM,
- IMEM,
- EBI0_CS0,
- EBI0_CS1,
- EBI1_CS0,
- EBI1_CS1,
- SDRAM = 0xE,
+ DEFAULT_CATEGORY = ~0x0,
+ SMI = 0x0,
+ EBI1,
+ EBI2,
+ QDSP6,
+ IRAM,
+ IMEM,
+ EBI0_CS0,
+ EBI0_CS1,
+ EBI1_CS0,
+ EBI1_CS1,
+ SDRAM = 0xE,
};
enum {
- DEFAULT_DOMAIN = 0x0,
- APPS_DOMAIN,
- MODEM_DOMAIN,
- SHARED_DOMAIN,
+ DEFAULT_DOMAIN = 0x0,
+ APPS_DOMAIN,
+ MODEM_DOMAIN,
+ SHARED_DOMAIN,
};
enum {
- SYS_MEMORY = 1, /* system memory*/
- BOOT_REGION_MEMORY1, /* boot loader memory 1*/
- BOOT_REGION_MEMORY2, /* boot loader memory 2,reserved*/
- APPSBL_MEMORY, /* apps boot loader memory*/
- APPS_MEMORY, /* apps usage memory*/
+ SYS_MEMORY = 1, /* system memory */
+ BOOT_REGION_MEMORY1, /* boot loader memory 1 */
+ BOOT_REGION_MEMORY2, /* boot loader memory 2,reserved */
+ APPSBL_MEMORY, /* apps boot loader memory */
+ APPS_MEMORY, /* apps usage memory */
};
struct smem_ram_ptn {
@@ -322,7 +305,8 @@
#define PWR_ON_EVENT_USB_CHG 0x20
#define PWR_ON_EVENT_WALL_CHG 0x40
-unsigned smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len, int offset);
+unsigned smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len,
+ int offset);
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
-#endif /* __PLATFORM_MSM_SHARED_SMEM_H */
+#endif /* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 47e3df1..149f06b 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -77,7 +77,7 @@
smem_apps_flash_start = 0xffffffff;
i = smem_read_alloc_entry(SMEM_AARM_PARTITION_TABLE,
- &smem_ptable, sizeof(smem_ptable));
+ &smem_ptable, sizeof(smem_ptable));
if (i != 0)
return;
@@ -91,7 +91,7 @@
for (i = 0; i < smem_ptable.len; i++) {
if (!strcmp(smem_ptable.parts[i].name, "0:APPS"))
- break;
+ break;
}
if (i == smem_ptable.len)
return;
@@ -112,23 +112,21 @@
smem_ptable.magic[1] != _SMEM_PTABLE_MAGIC_2)
return;
- for (i = 0; i < 16; i++)
- {
- char * token;
- char * pname = NULL;
+ for (i = 0; i < 16; i++) {
+ char *token;
+ char *pname = NULL;
struct smem_ptn *p = &smem_ptable.parts[i];
- if (p->name[0] == '\0')
- continue;
+ if (p->name[0] == '\0')
+ continue;
token = strtok(p->name, ":");
- while (token)
- {
+ while (token) {
pname = token;
- token = strtok (NULL, ":");
+ token = strtok(NULL, ":");
}
- if(pname)
- {
+ if (pname) {
ptable_add(flash_ptable, pname, p->start,
- p->size, 0, TYPE_MODEM_PARTITION, PERM_WRITEABLE);
+ p->size, 0, TYPE_MODEM_PARTITION,
+ PERM_WRITEABLE);
}
}
}
@@ -139,7 +137,8 @@
unsigned i;
i = smem_read_alloc_entry(SMEM_USABLE_RAM_PARTITION_TABLE,
- smem_ram_ptable, sizeof(struct smem_ram_ptable));
+ smem_ram_ptable,
+ sizeof(struct smem_ram_ptable));
if (i != 0)
return 0;
@@ -152,5 +151,3 @@
return 1;
}
-
-
diff --git a/platform/msm_shared/timer.c b/platform/msm_shared/timer.c
index 4707f3e..2949c8d 100644
--- a/platform/msm_shared/timer.c
+++ b/platform/msm_shared/timer.c
@@ -60,11 +60,11 @@
return timer_callback(timer_arg, ticks);
}
-status_t platform_set_periodic_timer(
- platform_timer_callback callback,
- void *arg, time_t interval)
+status_t
+platform_set_periodic_timer(platform_timer_callback callback,
+ void *arg, time_t interval)
{
- uint32_t tick_count = interval * platform_tick_rate()/1000;
+ uint32_t tick_count = interval * platform_tick_rate() / 1000;
enter_critical_section();
@@ -83,7 +83,6 @@
return 0;
}
-
time_t current_time(void)
{
return ticks;
@@ -91,7 +90,7 @@
static void wait_for_timer_op(void)
{
- while( readl(SPSS_TIMER_STATUS) & SPSS_TIMER_STATUS_DGT_EN );
+ while (readl(SPSS_TIMER_STATUS) & SPSS_TIMER_STATUS_DGT_EN) ;
}
void platform_uninit_timer(void)
@@ -104,32 +103,32 @@
void mdelay(unsigned msecs)
{
- msecs *= 33;
+ msecs *= 33;
- writel(0, GPT_CLEAR);
- writel(0, GPT_ENABLE);
- while(readl(GPT_COUNT_VAL) != 0) ;
+ writel(0, GPT_CLEAR);
+ writel(0, GPT_ENABLE);
+ while (readl(GPT_COUNT_VAL) != 0) ;
- writel(GPT_ENABLE_EN, GPT_ENABLE);
- while(readl(GPT_COUNT_VAL) < msecs) ;
+ writel(GPT_ENABLE_EN, GPT_ENABLE);
+ while (readl(GPT_COUNT_VAL) < msecs) ;
- writel(0, GPT_ENABLE);
- writel(0, GPT_CLEAR);
+ writel(0, GPT_ENABLE);
+ writel(0, GPT_CLEAR);
}
void udelay(unsigned usecs)
{
- usecs = (usecs * 33 + 1000 - 33) / 1000;
+ usecs = (usecs * 33 + 1000 - 33) / 1000;
- writel(0, GPT_CLEAR);
- writel(0, GPT_ENABLE);
- while(readl(GPT_COUNT_VAL) != 0);
+ writel(0, GPT_CLEAR);
+ writel(0, GPT_ENABLE);
+ while (readl(GPT_COUNT_VAL) != 0) ;
- writel(GPT_ENABLE_EN, GPT_ENABLE);
- while(readl(GPT_COUNT_VAL) < usecs);
+ writel(GPT_ENABLE_EN, GPT_ENABLE);
+ while (readl(GPT_COUNT_VAL) < usecs) ;
- writel(0, GPT_ENABLE);
- writel(0, GPT_CLEAR);
+ writel(0, GPT_ENABLE);
+ writel(0, GPT_CLEAR);
}
/* Return current time in micro seconds */
diff --git a/platform/msm_shared/uart.c b/platform/msm_shared/uart.c
index af6dcd9..e9feb4a 100644
--- a/platform/msm_shared/uart.c
+++ b/platform/msm_shared/uart.c
@@ -117,7 +117,6 @@
#define UART_MISR 0x0010
#define UART_ISR 0x0014
-
static unsigned uart_ready = 0;
#if PLATFORM_MSM7X30
static unsigned uart_base = MSM_UART2_BASE;
@@ -132,12 +131,12 @@
void uart_init(void)
{
- uwr(0x0A, UART_CR); /* disable TX and RX */
-
- uwr(0x30, UART_CR); /* reset error status */
- uwr(0x10, UART_CR); /* reset receiver */
- uwr(0x20, UART_CR); /* reset transmitter */
-
+ uwr(0x0A, UART_CR); /* disable TX and RX */
+
+ uwr(0x30, UART_CR); /* reset error status */
+ uwr(0x10, UART_CR); /* reset receiver */
+ uwr(0x20, UART_CR); /* reset transmitter */
+
#if PLATFORM_QSD8K || PLATFORM_MSM7X30 || PLATFORM_MSM7X27A
/* TCXO */
uwr(0x06, UART_MREG);
@@ -149,31 +148,31 @@
uwr(0xC0, UART_MREG);
uwr(0xAF, UART_NREG);
uwr(0x80, UART_DREG);
- uwr(0x19, UART_MNDREG);
+ uwr(0x19, UART_MNDREG);
#endif
-
- uwr(0x10, UART_CR); /* reset RX */
- uwr(0x20, UART_CR); /* reset TX */
- uwr(0x30, UART_CR); /* reset error status */
- uwr(0x40, UART_CR); /* reset RX break */
- uwr(0x70, UART_CR); /* rest? */
- uwr(0xD0, UART_CR); /* reset */
-
- uwr(0x7BF, UART_IPR); /* stale timeout = 630 * bitrate */
+
+ uwr(0x10, UART_CR); /* reset RX */
+ uwr(0x20, UART_CR); /* reset TX */
+ uwr(0x30, UART_CR); /* reset error status */
+ uwr(0x40, UART_CR); /* reset RX break */
+ uwr(0x70, UART_CR); /* rest? */
+ uwr(0xD0, UART_CR); /* reset */
+
+ uwr(0x7BF, UART_IPR); /* stale timeout = 630 * bitrate */
uwr(0, UART_IMR);
- uwr(115, UART_RFWR); /* RX watermark = 58 * 2 - 1 */
- uwr(10, UART_TFWR); /* TX watermark */
-
- uwr(0, UART_RFWR);
-
+ uwr(115, UART_RFWR); /* RX watermark = 58 * 2 - 1 */
+ uwr(10, UART_TFWR); /* TX watermark */
+
+ uwr(0, UART_RFWR);
+
uwr(UART_CSR_115200, UART_CSR);
uwr(0, UART_IRDA);
uwr(0x1E, UART_HCR);
-// uwr(0x7F4, UART_MR1); /* RFS/ CTS/ 500chr RFR */
+// uwr(0x7F4, UART_MR1); /* RFS/ CTS/ 500chr RFR */
uwr(16, UART_MR1);
- uwr(0x34, UART_MR2); /* 8N1 */
-
- uwr(0x05, UART_CR); /* enable TX & RX */
+ uwr(0x34, UART_MR2); /* 8N1 */
+
+ uwr(0x05, UART_CR); /* enable TX & RX */
uart_ready = 1;
}
@@ -187,10 +186,9 @@
return 0;
}
-int uart_putc (int port, char c)
+int uart_putc(int port, char c)
{
- if(c == '\n')
- {
+ if (c == '\n') {
_uart_putc(0, '\r');
}
_uart_putc(0, c);
@@ -206,4 +204,3 @@
return urd(UART_RF);
}
-
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 3ac657f..614bd56 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -1,479 +1,459 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Code Aurora Forum, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <string.h>
-#include <stdlib.h>
-#include <debug.h>
-#include <reg.h>
-#include <sys/types.h>
-#include <platform/iomap.h>
-#include <platform/irqs.h>
-#include <platform/interrupts.h>
-#include <platform/clock.h>
-#include <platform/gpio.h>
-#include <uart_dm.h>
-#include <gsbi.h>
-
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-extern void dsb(void);
-
-static int uart_init_flag = 0;
-
-/* Note:
- * This is a basic implementation of UART_DM protocol. More focus has been
- * given on simplicity than efficiency. Few of the things to be noted are:
- * - RX path may not be suitable for multi-threaded scenaraio because of the
- * use of static variables. TX path shouldn't have any problem though. If
- * multi-threaded support is required, a simple data-structure can
- * be maintained for each thread.
- * - Right now we are using polling method than interrupt based.
- * - We are using legacy UART protocol without Data Mover.
- * - Not all interrupts and error events are handled.
- * - While waiting Watchdog hasn't been taken into consideration.
- */
-
-
-#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \
- word = 0; \
- for(int j=0; j < (int)cnt; j++) \
- { \
- word |= (a[j] & 0xff) \
- << (j * 8); \
- } \
- }
-
-
-/* Static Function Prototype Declarations */
-static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id);
-static unsigned int msm_boot_uart_replace_lr_with_cr(char* data_in,
- int num_of_chars,
- char *data_out,
- int *num_of_chars_out);
-static unsigned int msm_boot_uart_dm_init(uint8_t id);
-static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int* data,
- int wait);
-static unsigned int msm_boot_uart_dm_write(uint8_t id, char* data,
- unsigned int num_of_chars);
-static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id);
-static unsigned int msm_boot_uart_dm_reset(uint8_t id);
-
-/* Keep track of gsbi vs port mapping.
- */
-static uint8_t gsbi_lookup[4];
-
-/* Extern functions */
-void udelay(unsigned usecs);
-
-
-/*
- * Helper function to replace Line Feed char "\n" with
- * Carriage Return "\r\n".
- * Currently keeping it simple than efficient
- */
-static unsigned int msm_boot_uart_replace_lr_with_cr(char* data_in,
- int num_of_chars,
- char *data_out,
- int *num_of_chars_out )
-{
- int i = 0, j = 0;
-
- if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0))
- {
- return MSM_BOOT_UART_DM_E_INVAL;
- }
-
- for (i=0, j=0; i < num_of_chars; i++, j++)
- {
- if ( data_in[i] == '\n' )
- {
- data_out[j++] = '\r';
- }
-
- data_out[j] = data_in[i];
- }
-
- *num_of_chars_out = j;
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/*
- * Initialize and configure GSBI for operation
- */
-static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id)
-{
- /* Configure the uart clock */
- clock_config_uart_dm(id);
- dsb();
-
- /* Configure GPIO to provide connectivity between GSBI
- product ports and chip pads */
- gpio_config_uart_dm(id);
- dsb();
-
- /* Configure Data Mover for GSBI operation.
- * Currently not supported. */
-
- /* Configure GSBI for UART_DM protocol.
- * I2C on 2 ports, UART (without HS flow control) on the other 2. */
- writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,
- GSBI_CTRL_REG(id));
- dsb();
-
- /* Configure clock selection register for tx and rx rates.
- * Selecting 115.2k for both RX and TX.
- */
- writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));
- dsb();
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/*
- * Reset the UART
- */
-static unsigned int msm_boot_uart_dm_reset(uint8_t id)
-{
- writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-
-/*
- * Initialize UART_DM - configure clock and required registers.
- */
-static unsigned int msm_boot_uart_dm_init(uint8_t id)
-{
- /* Configure GSBI for uart dm */
- msm_boot_uart_dm_gsbi_init(id);
-
- /* Configure UART mode registers MR1 and MR2 */
- /* Hardware flow control isn't supported */
- writel(0x0, MSM_BOOT_UART_DM_MR1(id));
-
- /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
- writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(id));
-
- /* Configure Interrupt Mask register IMR */
- writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(id));
-
- /* Configure Tx and Rx watermarks configuration registers */
- /* TX watermark value is set to 0 - interrupt is generated when
- * FIFO level is less than or equal to 0 */
- writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(id));
-
- /* RX watermark value*/
- writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(id));
-
- /* Configure Interrupt Programming Register*/
- /* Set initial Stale timeout value*/
- writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(id));
-
- /* Configure IRDA if required */
- /* Disabling IRDA mode */
- writel(0x0, MSM_BOOT_UART_DM_IRDA(id));
-
- /* Configure and enable sim interface if required */
-
- /* Configure hunt character value in HCR register */
- /* Keep it in reset state */
- writel(0x0, MSM_BOOT_UART_DM_HCR(id));
-
- /* Configure Rx FIFO base address */
- /* Both TX/RX shares same SRAM and default is half-n-half.
- * Sticking with default value now.
- * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
- * We have found RAM_ADDR_WIDTH = 0x7f */
-
- /* Issue soft reset command */
- msm_boot_uart_dm_reset(id);
-
- /* Enable/Disable Rx/Tx DM interfaces */
- /* Data Mover not currently utilized. */
- writel(0x0, MSM_BOOT_UART_DM_DMEN(id));
-
-
- /* Enable transmitter and receiver */
- writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(id));
-
- /* Initialize Receive Path */
- msm_boot_uart_dm_init_rx_transfer(id);
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-
-/*
- * Initialize Receive Path
- */
-static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id)
-{
- writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
- writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(id));
- writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/*
- * UART Receive operation
- * Reads a word from the RX FIFO.
- */
-static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int* data, int wait)
-{
- static int rx_last_snap_count = 0;
- static int rx_chars_read_since_last_xfer = 0;
-
- if (data == NULL)
- {
- return MSM_BOOT_UART_DM_E_INVAL;
- }
-
- /* We will be polling RXRDY status bit */
- while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_RXRDY))
- {
- /* if this is not a blocking call, we'll just return */
- if (!wait)
- {
- return MSM_BOOT_UART_DM_E_RX_NOT_READY;
- }
- }
-
- /* Check for Overrun error. We'll just reset Error Status */
- if (readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN)
- {
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
- }
-
- /* RX FIFO is ready; read a word. */
- *data = readl(MSM_BOOT_UART_DM_RF(id, 0));
-
- /* increment the total count of chars we've read so far */
- rx_chars_read_since_last_xfer += 4;
-
- /* Rx transfer ends when one of the conditions is met:
- * - The number of characters received since the end of the previous xfer
- * equals the value written to DMRX at Transfer Initialization
- * - A stale event occurred
- */
-
- /* If RX transfer has not ended yet */
- if (rx_last_snap_count == 0)
- {
- /* Check if we've received stale event */
- if (readl(MSM_BOOT_UART_DM_MISR(id)) & MSM_BOOT_UART_DM_RXSTALE)
- {
- /* Send command to reset stale interrupt */
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
- }
-
- /* Check if we haven't read more than DMRX value */
- else if ((unsigned int)rx_chars_read_since_last_xfer <
- readl(MSM_BOOT_UART_DM_DMRX(id)))
- {
- /* We can still continue reading before initializing RX transfer */
- return MSM_BOOT_UART_DM_E_SUCCESS;
- }
-
- /* If we've reached here it means RX xfer end conditions been met */
-
- /* Read UART_DM_RX_TOTAL_SNAP register to know how many valid chars
- * we've read so far since last transfer */
- rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id));
-
- }
-
- /* If there are still data left in FIFO we'll read them before
- * initializing RX Transfer again */
- if ((rx_last_snap_count - rx_chars_read_since_last_xfer) >= 0 )
- {
- return MSM_BOOT_UART_DM_E_SUCCESS;
- }
-
- msm_boot_uart_dm_init_rx_transfer(id);
- rx_last_snap_count = 0;
- rx_chars_read_since_last_xfer = 0;
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/*
- * UART transmit operation
- */
-static unsigned int msm_boot_uart_dm_write(uint8_t id, char* data,
- unsigned int num_of_chars)
-{
- unsigned int tx_word_count = 0;
- unsigned int tx_char_left = 0, tx_char = 0;
- unsigned int tx_word = 0;
- int i = 0;
- char* tx_data = NULL;
- char new_data[1024];
-
- if ((data == NULL) || (num_of_chars <= 0))
- {
- return MSM_BOOT_UART_DM_E_INVAL;
- }
-
- /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */
-
- msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i);
-
- tx_data = new_data;
- num_of_chars = i;
-
- /* Write to NO_CHARS_FOR_TX register number of characters
- * to be transmitted. However, before writing TX_FIFO must
- * be empty as indicated by TX_READY interrupt in IMR register
- */
-
- /* Check if transmit FIFO is empty.
- * If not we'll wait for TX_READY interrupt. */
- if (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXEMT))
- {
- while (!(readl(MSM_BOOT_UART_DM_ISR(id)) & MSM_BOOT_UART_DM_TX_READY))
- {
- udelay(1);
- /* Kick watchdog? */
- }
- }
-
- /* We are here. FIFO is ready to be written. */
- /* Write number of characters to be written */
- writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id));
-
- /* Clear TX_READY interrupt */
- writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(id));
-
- /* We use four-character word FIFO. So we need to divide data into
- * four characters and write in UART_DM_TF register */
- tx_word_count = (num_of_chars % 4)? ((num_of_chars / 4) + 1) :
- (num_of_chars / 4);
- tx_char_left = num_of_chars;
-
- for (i = 0; i < (int)tx_word_count; i++)
- {
- tx_char = (tx_char_left < 4)? tx_char_left : 4;
- PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
-
- /* Wait till TX FIFO has space */
- while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXRDY))
- {
- udelay(1);
- }
-
- /* TX FIFO has space. Write the chars */
- writel(tx_word, MSM_BOOT_UART_DM_TF(id, 0));
- tx_char_left = num_of_chars - (i+1)*4;
- tx_data = tx_data + 4;
- }
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-/* Defining functions that's exposed to outside world and in coformance to
- * existing uart implemention. These functions are being called to initialize
- * UART and print debug messages in bootloader.
- */
-void uart_init(uint8_t gsbi_id)
-{
- static uint8_t port = 0;
- char *data = "Android Bootloader - UART_DM Initialized!!!\n";
-
- msm_boot_uart_dm_init(gsbi_id);
- msm_boot_uart_dm_write(gsbi_id, data, 44);
-
- ASSERT(port < ARRAY_SIZE(gsbi_lookup));
- gsbi_lookup[port++] = gsbi_id;
-
- /* Set UART init flag */
- uart_init_flag = 1;
-}
-
-
-/* UART_DM uses four character word FIFO where as UART core
- * uses a character FIFO. so it's really inefficient to try
- * to write single character. But that's how dprintf has been
- * implemented.
- */
-int uart_putc(int port, char c)
-{
- uint8_t gsbi_id = gsbi_lookup[port];
-
- /* Don't do anything if UART is not initialized */
- if(!uart_init_flag)
- return;
-
- msm_boot_uart_dm_write(gsbi_id, &c, 1);
-
- return 0;
-}
-
-/* UART_DM uses four character word FIFO whereas uart_getc
- * is supposed to read only one character. So we need to
- * read a word and keep track of each character in the word.
- */
-int uart_getc(int port, bool wait)
-{
- int byte;
- static unsigned int word = 0;
- uint8_t gsbi_id = gsbi_lookup[port];
-
- /* Don't do anything if UART is not initialized */
- if(!uart_init_flag)
- return;
-
- if (!word)
- {
- /* Read from FIFO only if it's a first read or all the four
- * characters out of a word have been read */
- if (msm_boot_uart_dm_read(gsbi_id, &word, wait) !=
- MSM_BOOT_UART_DM_E_SUCCESS)
- {
- return -1;
- }
-
- }
-
- byte = (int) word & 0xff;
- word = word >> 8;
-
- return byte;
-}
-
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include <debug.h>
+#include <reg.h>
+#include <sys/types.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/interrupts.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <uart_dm.h>
+#include <gsbi.h>
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+extern void dsb(void);
+
+static int uart_init_flag = 0;
+
+/* Note:
+ * This is a basic implementation of UART_DM protocol. More focus has been
+ * given on simplicity than efficiency. Few of the things to be noted are:
+ * - RX path may not be suitable for multi-threaded scenaraio because of the
+ * use of static variables. TX path shouldn't have any problem though. If
+ * multi-threaded support is required, a simple data-structure can
+ * be maintained for each thread.
+ * - Right now we are using polling method than interrupt based.
+ * - We are using legacy UART protocol without Data Mover.
+ * - Not all interrupts and error events are handled.
+ * - While waiting Watchdog hasn't been taken into consideration.
+ */
+
+#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \
+ word = 0; \
+ for(int j=0; j < (int)cnt; j++) \
+ { \
+ word |= (a[j] & 0xff) \
+ << (j * 8); \
+ } \
+ }
+
+/* Static Function Prototype Declarations */
+static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id);
+static unsigned int msm_boot_uart_replace_lr_with_cr(char *data_in,
+ int num_of_chars,
+ char *data_out,
+ int *num_of_chars_out);
+static unsigned int msm_boot_uart_dm_init(uint8_t id);
+static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int *data,
+ int wait);
+static unsigned int msm_boot_uart_dm_write(uint8_t id, char *data,
+ unsigned int num_of_chars);
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id);
+static unsigned int msm_boot_uart_dm_reset(uint8_t id);
+
+/* Keep track of gsbi vs port mapping.
+ */
+static uint8_t gsbi_lookup[4];
+
+/* Extern functions */
+void udelay(unsigned usecs);
+
+/*
+ * Helper function to replace Line Feed char "\n" with
+ * Carriage Return "\r\n".
+ * Currently keeping it simple than efficient
+ */
+static unsigned int
+msm_boot_uart_replace_lr_with_cr(char *data_in,
+ int num_of_chars,
+ char *data_out, int *num_of_chars_out)
+{
+ int i = 0, j = 0;
+
+ if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+ for (i = 0, j = 0; i < num_of_chars; i++, j++) {
+ if (data_in[i] == '\n') {
+ data_out[j++] = '\r';
+ }
+
+ data_out[j] = data_in[i];
+ }
+
+ *num_of_chars_out = j;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * Initialize and configure GSBI for operation
+ */
+static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id)
+{
+ /* Configure the uart clock */
+ clock_config_uart_dm(id);
+ dsb();
+
+ /* Configure GPIO to provide connectivity between GSBI
+ product ports and chip pads */
+ gpio_config_uart_dm(id);
+ dsb();
+
+ /* Configure Data Mover for GSBI operation.
+ * Currently not supported. */
+
+ /* Configure GSBI for UART_DM protocol.
+ * I2C on 2 ports, UART (without HS flow control) on the other 2. */
+ writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,
+ GSBI_CTRL_REG(id));
+ dsb();
+
+ /* Configure clock selection register for tx and rx rates.
+ * Selecting 115.2k for both RX and TX.
+ */
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));
+ dsb();
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * Reset the UART
+ */
+static unsigned int msm_boot_uart_dm_reset(uint8_t id)
+{
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * Initialize UART_DM - configure clock and required registers.
+ */
+static unsigned int msm_boot_uart_dm_init(uint8_t id)
+{
+ /* Configure GSBI for uart dm */
+ msm_boot_uart_dm_gsbi_init(id);
+
+ /* Configure UART mode registers MR1 and MR2 */
+ /* Hardware flow control isn't supported */
+ writel(0x0, MSM_BOOT_UART_DM_MR1(id));
+
+ /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(id));
+
+ /* Configure Interrupt Mask register IMR */
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(id));
+
+ /* Configure Tx and Rx watermarks configuration registers */
+ /* TX watermark value is set to 0 - interrupt is generated when
+ * FIFO level is less than or equal to 0 */
+ writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(id));
+
+ /* RX watermark value */
+ writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(id));
+
+ /* Configure Interrupt Programming Register */
+ /* Set initial Stale timeout value */
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(id));
+
+ /* Configure IRDA if required */
+ /* Disabling IRDA mode */
+ writel(0x0, MSM_BOOT_UART_DM_IRDA(id));
+
+ /* Configure and enable sim interface if required */
+
+ /* Configure hunt character value in HCR register */
+ /* Keep it in reset state */
+ writel(0x0, MSM_BOOT_UART_DM_HCR(id));
+
+ /* Configure Rx FIFO base address */
+ /* Both TX/RX shares same SRAM and default is half-n-half.
+ * Sticking with default value now.
+ * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
+ * We have found RAM_ADDR_WIDTH = 0x7f */
+
+ /* Issue soft reset command */
+ msm_boot_uart_dm_reset(id);
+
+ /* Enable/Disable Rx/Tx DM interfaces */
+ /* Data Mover not currently utilized. */
+ writel(0x0, MSM_BOOT_UART_DM_DMEN(id));
+
+ /* Enable transmitter and receiver */
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(id));
+
+ /* Initialize Receive Path */
+ msm_boot_uart_dm_init_rx_transfer(id);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * Initialize Receive Path
+ */
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id)
+{
+ writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(id));
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * UART Receive operation
+ * Reads a word from the RX FIFO.
+ */
+static unsigned int
+msm_boot_uart_dm_read(uint8_t id, unsigned int *data, int wait)
+{
+ static int rx_last_snap_count = 0;
+ static int rx_chars_read_since_last_xfer = 0;
+
+ if (data == NULL) {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+ /* We will be polling RXRDY status bit */
+ while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_RXRDY)) {
+ /* if this is not a blocking call, we'll just return */
+ if (!wait) {
+ return MSM_BOOT_UART_DM_E_RX_NOT_READY;
+ }
+ }
+
+ /* Check for Overrun error. We'll just reset Error Status */
+ if (readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
+ MSM_BOOT_UART_DM_CR(id));
+ }
+
+ /* RX FIFO is ready; read a word. */
+ *data = readl(MSM_BOOT_UART_DM_RF(id, 0));
+
+ /* increment the total count of chars we've read so far */
+ rx_chars_read_since_last_xfer += 4;
+
+ /* Rx transfer ends when one of the conditions is met:
+ * - The number of characters received since the end of the previous xfer
+ * equals the value written to DMRX at Transfer Initialization
+ * - A stale event occurred
+ */
+
+ /* If RX transfer has not ended yet */
+ if (rx_last_snap_count == 0) {
+ /* Check if we've received stale event */
+ if (readl(MSM_BOOT_UART_DM_MISR(id)) & MSM_BOOT_UART_DM_RXSTALE) {
+ /* Send command to reset stale interrupt */
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
+ MSM_BOOT_UART_DM_CR(id));
+ }
+
+ /* Check if we haven't read more than DMRX value */
+ else if ((unsigned int)rx_chars_read_since_last_xfer <
+ readl(MSM_BOOT_UART_DM_DMRX(id))) {
+ /* We can still continue reading before initializing RX transfer */
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+ }
+
+ /* If we've reached here it means RX xfer end conditions been met */
+
+ /* Read UART_DM_RX_TOTAL_SNAP register to know how many valid chars
+ * we've read so far since last transfer */
+ rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id));
+
+ }
+
+ /* If there are still data left in FIFO we'll read them before
+ * initializing RX Transfer again */
+ if ((rx_last_snap_count - rx_chars_read_since_last_xfer) >= 0) {
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+ }
+
+ msm_boot_uart_dm_init_rx_transfer(id);
+ rx_last_snap_count = 0;
+ rx_chars_read_since_last_xfer = 0;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * UART transmit operation
+ */
+static unsigned int
+msm_boot_uart_dm_write(uint8_t id, char *data, unsigned int num_of_chars)
+{
+ unsigned int tx_word_count = 0;
+ unsigned int tx_char_left = 0, tx_char = 0;
+ unsigned int tx_word = 0;
+ int i = 0;
+ char *tx_data = NULL;
+ char new_data[1024];
+
+ if ((data == NULL) || (num_of_chars <= 0)) {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+ /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */
+
+ msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i);
+
+ tx_data = new_data;
+ num_of_chars = i;
+
+ /* Write to NO_CHARS_FOR_TX register number of characters
+ * to be transmitted. However, before writing TX_FIFO must
+ * be empty as indicated by TX_READY interrupt in IMR register
+ */
+
+ /* Check if transmit FIFO is empty.
+ * If not we'll wait for TX_READY interrupt. */
+ if (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXEMT)) {
+ while (!
+ (readl(MSM_BOOT_UART_DM_ISR(id)) &
+ MSM_BOOT_UART_DM_TX_READY)) {
+ udelay(1);
+ /* Kick watchdog? */
+ }
+ }
+
+ /* We are here. FIFO is ready to be written. */
+ /* Write number of characters to be written */
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id));
+
+ /* Clear TX_READY interrupt */
+ writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(id));
+
+ /* We use four-character word FIFO. So we need to divide data into
+ * four characters and write in UART_DM_TF register */
+ tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) :
+ (num_of_chars / 4);
+ tx_char_left = num_of_chars;
+
+ for (i = 0; i < (int)tx_word_count; i++) {
+ tx_char = (tx_char_left < 4) ? tx_char_left : 4;
+ PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
+
+ /* Wait till TX FIFO has space */
+ while (!
+ (readl(MSM_BOOT_UART_DM_SR(id)) &
+ MSM_BOOT_UART_DM_SR_TXRDY)) {
+ udelay(1);
+ }
+
+ /* TX FIFO has space. Write the chars */
+ writel(tx_word, MSM_BOOT_UART_DM_TF(id, 0));
+ tx_char_left = num_of_chars - (i + 1) * 4;
+ tx_data = tx_data + 4;
+ }
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/* Defining functions that's exposed to outside world and in coformance to
+ * existing uart implemention. These functions are being called to initialize
+ * UART and print debug messages in bootloader.
+ */
+void uart_init(uint8_t gsbi_id)
+{
+ static uint8_t port = 0;
+ char *data = "Android Bootloader - UART_DM Initialized!!!\n";
+
+ msm_boot_uart_dm_init(gsbi_id);
+ msm_boot_uart_dm_write(gsbi_id, data, 44);
+
+ ASSERT(port < ARRAY_SIZE(gsbi_lookup));
+ gsbi_lookup[port++] = gsbi_id;
+
+ /* Set UART init flag */
+ uart_init_flag = 1;
+}
+
+/* UART_DM uses four character word FIFO where as UART core
+ * uses a character FIFO. so it's really inefficient to try
+ * to write single character. But that's how dprintf has been
+ * implemented.
+ */
+int uart_putc(int port, char c)
+{
+ uint8_t gsbi_id = gsbi_lookup[port];
+
+ /* Don't do anything if UART is not initialized */
+ if (!uart_init_flag)
+ return;
+
+ msm_boot_uart_dm_write(gsbi_id, &c, 1);
+
+ return 0;
+}
+
+/* UART_DM uses four character word FIFO whereas uart_getc
+ * is supposed to read only one character. So we need to
+ * read a word and keep track of each character in the word.
+ */
+int uart_getc(int port, bool wait)
+{
+ int byte;
+ static unsigned int word = 0;
+ uint8_t gsbi_id = gsbi_lookup[port];
+
+ /* Don't do anything if UART is not initialized */
+ if (!uart_init_flag)
+ return;
+
+ if (!word) {
+ /* Read from FIFO only if it's a first read or all the four
+ * characters out of a word have been read */
+ if (msm_boot_uart_dm_read(gsbi_id, &word, wait) !=
+ MSM_BOOT_UART_DM_E_SUCCESS) {
+ return -1;
+ }
+
+ }
+
+ byte = (int)word & 0xff;
+ word = word >> 8;
+
+ return byte;
+}
diff --git a/target/mdm9615/atags.c b/target/mdm9615/atags.c
index f9b636f..e3ccef7 100644
--- a/target/mdm9615/atags.c
+++ b/target/mdm9615/atags.c
@@ -37,19 +37,16 @@
#define SIZE_23M (23 * SIZE_1M)
#define SIZE_88M (11 * SIZE_8M)
-unsigned* target_atag_mem(unsigned* ptr)
+unsigned *target_atag_mem(unsigned *ptr)
{
struct smem_ram_ptable ram_ptable;
uint8_t i = 0;
- if (smem_ram_ptable_init(&ram_ptable))
- {
- for (i = 0; i < ram_ptable.len; i++)
- {
+ if (smem_ram_ptable_init(&ram_ptable)) {
+ for (i = 0; i < ram_ptable.len; i++) {
if (ram_ptable.parts[i].category == SDRAM &&
- ram_ptable.parts[i].type == SYS_MEMORY &&
- ram_ptable.parts[i].start == 0x40000000)
- {
+ ram_ptable.parts[i].type == SYS_MEMORY &&
+ ram_ptable.parts[i].start == 0x40000000) {
ASSERT(ram_ptable.parts[i].size >= SIZE_15M);
*ptr++ = 4;
@@ -63,9 +60,7 @@
*ptr++ = ram_ptable.parts[i].start + SIZE_88M;
}
}
- }
- else
- {
+ } else {
dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
ASSERT(0);
}
@@ -75,7 +70,7 @@
void *target_get_scratch_address(void)
{
- return((void *)SCRATCH_ADDR);
+ return ((void *)SCRATCH_ADDR);
}
unsigned target_get_max_flash_size(void)
diff --git a/target/mdm9615/init.c b/target/mdm9615/init.c
index ed569bc..83ce379 100644
--- a/target/mdm9615/init.c
+++ b/target/mdm9615/init.c
@@ -52,9 +52,11 @@
unsigned target_msm_id = 0;
/* Partition names for fastboot flash */
-char *apps_ptn_names[] = {"aboot", "boot", "system"};
+char *apps_ptn_names[] = { "aboot", "boot", "system" };
+
/* Partitions should be in this order */
-char *ptable_ptn_names[] = {"APPSBL", "APPS", "EFS2APPS"};
+char *ptable_ptn_names[] = { "APPSBL", "APPS", "EFS2APPS" };
+
unsigned ptn_name_count = 3;
unsigned modem_ptn_count = 7;
@@ -75,8 +77,8 @@
dprintf(INFO, "target_init()\n");
/* Initialize PMIC driver */
- pmic.read = (pm8921_read_func) &pa1_ssbi2_read_bytes;
- pmic.write = (pm8921_write_func) &pa1_ssbi2_write_bytes;
+ pmic.read = (pm8921_read_func) & pa1_ssbi2_read_bytes;
+ pmic.write = (pm8921_write_func) & pa1_ssbi2_write_bytes;
pm8921_init(&pmic);
@@ -114,20 +116,18 @@
target_msm_id = MDM9600;
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if(format == 4)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format == 4) {
board_info_len = sizeof(board_info_v4);
- smem_status = smem_read_alloc_entry(
- SMEM_BOARD_INFO_LOCATION,
- &board_info_v4, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v4,
+ board_info_len);
+ if (!smem_status) {
id = board_info_v4.board_info_v3.hw_platform;
target_msm_id =
- board_info_v4.board_info_v3.msm_id;
+ board_info_v4.board_info_v3.msm_id;
}
}
}
@@ -147,7 +147,7 @@
writel(0, MSM_PSHOLD_CTL_SU);
mdelay(10000);
- dprintf (CRITICAL, "Rebooting failed\n");
+ dprintf(CRITICAL, "Rebooting failed\n");
return;
}
@@ -159,7 +159,8 @@
/*
* Return 1 to trigger to fastboot
*/
-int fastboot_trigger(void) {
+int fastboot_trigger(void)
+{
int ret;
ret = fake_key_get_state();
/* Want to trigger when dip switch is off */
@@ -170,15 +171,13 @@
{
uint32_t ptn_index, i = 0;
uint32_t name_size;
- struct ptentry * ptentry_ptr = flash_ptable.parts;
+ struct ptentry *ptentry_ptr = flash_ptable.parts;
- for(ptn_index=0; ptn_index < modem_ptn_count; ptn_index++)
- {
+ for (ptn_index = 0; ptn_index < modem_ptn_count; ptn_index++) {
name_size = strlen(ptentry_ptr[ptn_index].name);
- for(i=0; i < name_size; i++)
- {
+ for (i = 0; i < name_size; i++) {
ptentry_ptr[ptn_index].name[i] =
- tolower(ptentry_ptr[ptn_index].name[i]);
+ tolower(ptentry_ptr[ptn_index].name[i]);
}
}
}
@@ -188,15 +187,13 @@
uint32_t ptn_index, name_index = 0;
uint32_t end = 0xffffffff;
uint32_t name_size = strlen(ptable_ptn_names[name_index]);
- struct ptentry * ptentry_ptr = flash_ptable.parts;
+ struct ptentry *ptentry_ptr = flash_ptable.parts;
- for(ptn_index=0; ptentry_ptr[ptn_index].start != end; ptn_index++)
- {
+ for (ptn_index = 0; ptentry_ptr[ptn_index].start != end; ptn_index++) {
if (!(strncmp(ptentry_ptr[ptn_index].name,
- ptable_ptn_names[name_index], name_size)))
- {
+ ptable_ptn_names[name_index], name_size))) {
name_size = strlen(apps_ptn_names[name_index]);
- name_size++; /* For null termination */
+ name_size++; /* For null termination */
/* Update the partition names to something familiar */
if (name_size <= MAX_PTENTRY_NAME)
@@ -206,7 +203,7 @@
/* Aboot uses modem page layout, leave aboot ptn */
if (name_index != 0)
ptentry_ptr[ptn_index].type =
- TYPE_APPS_PARTITION;
+ TYPE_APPS_PARTITION;
/* Don't go out of bounds */
name_index++;
@@ -218,11 +215,12 @@
/* Update the end to be actual end for grow partition */
ptn_index--;
- for (;ptentry_ptr[ptn_index].length != end; ptn_index++){};
+ for (; ptentry_ptr[ptn_index].length != end; ptn_index++) {
+ };
/* If SMEM ptable is updated already then don't manually update this */
if (ptentry_ptr[ptn_index].start != end)
ptentry_ptr[ptn_index].length =
- ((struct flash_info*)flash_get_info())->num_blocks -
- ptentry_ptr[ptn_index].start;
+ ((struct flash_info *)flash_get_info())->num_blocks -
+ ptentry_ptr[ptn_index].start;
}
diff --git a/target/mdm9615/keypad.c b/target/mdm9615/keypad.c
index afbe879..93eeeeb 100644
--- a/target/mdm9615/keypad.c
+++ b/target/mdm9615/keypad.c
@@ -39,7 +39,7 @@
int ret;
/* GPIO 49 connects to Boot Config5 */
gpio_tlmm_config(49, 0, GPIO_OUTPUT, GPIO_PULL_DOWN,
- GPIO_2MA, GPIO_ENABLE);
+ GPIO_2MA, GPIO_ENABLE);
ret = readl(GPIO_IN_OUT_ADDR(49));
return ret;
diff --git a/target/msm7627a/atags.c b/target/msm7627a/atags.c
index 5369864..7ada101 100644
--- a/target/msm7627a/atags.c
+++ b/target/msm7627a/atags.c
@@ -33,36 +33,35 @@
#define SIZE_1M 0x00100000
#define ROUND_TO_MB(x) ((x >> 20) << 20)
-unsigned* target_atag_mem(unsigned* ptr)
+unsigned *target_atag_mem(unsigned *ptr)
{
struct smem_ram_ptable ram_ptable;
unsigned i = 0;
- if (smem_ram_ptable_init(&ram_ptable))
- {
- for (i = 0; i < ram_ptable.len; i++)
- {
+ if (smem_ram_ptable_init(&ram_ptable)) {
+ for (i = 0; i < ram_ptable.len; i++) {
if ((ram_ptable.parts[i].attr == READWRITE)
- && (ram_ptable.parts[i].domain == APPS_DOMAIN)
- && (ram_ptable.parts[i].start != 0x0)
- && (!(ROUND_TO_MB(ram_ptable.parts[i].size) <= SIZE_1M)))
- {
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].start != 0x0)
+ &&
+ (!(ROUND_TO_MB(ram_ptable.parts[i].size) <=
+ SIZE_1M))) {
/* ATAG_MEM */
*ptr++ = 4;
*ptr++ = 0x54410002;
/* RAM parition are reported correctly by NON-HLOS
Use the size passed directly */
if (target_is_emmc_boot())
- *ptr++ = ROUND_TO_MB(ram_ptable.parts[i].size);
+ *ptr++ =
+ ROUND_TO_MB(ram_ptable.parts[i].
+ size);
else
*ptr++ = ram_ptable.parts[i].size;
*ptr++ = ram_ptable.parts[i].start;
}
}
- }
- else
- {
+ } else {
dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
ASSERT(0);
}
@@ -71,6 +70,5 @@
unsigned target_get_max_flash_size(void)
{
- return (180 * 1024 * 1024);
+ return (180 * 1024 * 1024);
}
-
diff --git a/target/msm7627a/init.c b/target/msm7627a/init.c
index 70ab020..011dd1c 100644
--- a/target/msm7627a/init.c
+++ b/target/msm7627a/init.c
@@ -72,42 +72,43 @@
*/
static struct ptentry board_part_list_default[] = {
{
- .start = 0,
- .length = 10 /* In MB */,
- .name = "boot",
- },
+ .start = 0,
+ .length = 10 /* In MB */ ,
+ .name = "boot",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 180 /* In MB */,
- .name = "system",
- },
+ .start = DIFF_START_ADDR,
+ .length = 180 /* In MB */ ,
+ .name = "system",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 40 /* In MB */,
- .name = "cache",
- },
+ .start = DIFF_START_ADDR,
+ .length = 40 /* In MB */ ,
+ .name = "cache",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 4 /* In MB */,
- .name = "misc",
- },
+ .start = DIFF_START_ADDR,
+ .length = 4 /* In MB */ ,
+ .name = "misc",
+ },
{
- .start = DIFF_START_ADDR,
- .length = VARIABLE_LENGTH,
- .name = "userdata",
- },
+ .start = DIFF_START_ADDR,
+ .length = VARIABLE_LENGTH,
+ .name = "userdata",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 4 /* In MB */,
- .name = "persist",
- },
+ .start = DIFF_START_ADDR,
+ .length = 4 /* In MB */ ,
+ .name = "persist",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 10 /* In MB */,
- .name = "recovery",
- },
+ .start = DIFF_START_ADDR,
+ .length = 10 /* In MB */ ,
+ .name = "recovery",
+ },
};
-static int num_parts = sizeof(board_part_list_default)/sizeof(struct ptentry);
+
+static int num_parts = sizeof(board_part_list_default) / sizeof(struct ptentry);
/*
* Define partition table for Bch ecc NAND and increase the cache partition size
@@ -115,41 +116,42 @@
*/
static struct ptentry board_part_list_bchecc[] = {
{
- .start = 0,
- .length = 10 /* In MB */,
- .name = "boot",
- },
+ .start = 0,
+ .length = 10 /* In MB */ ,
+ .name = "boot",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 180 /* In MB */,
- .name = "system",
- },
+ .start = DIFF_START_ADDR,
+ .length = 180 /* In MB */ ,
+ .name = "system",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 40 /* In MB */,
- .name = "cache",
- },
+ .start = DIFF_START_ADDR,
+ .length = 40 /* In MB */ ,
+ .name = "cache",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 4 /* In MB */,
- .name = "misc",
- },
+ .start = DIFF_START_ADDR,
+ .length = 4 /* In MB */ ,
+ .name = "misc",
+ },
{
- .start = DIFF_START_ADDR,
- .length = VARIABLE_LENGTH,
- .name = "userdata",
- },
+ .start = DIFF_START_ADDR,
+ .length = VARIABLE_LENGTH,
+ .name = "userdata",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 4 /* In MB */,
- .name = "persist",
- },
+ .start = DIFF_START_ADDR,
+ .length = 4 /* In MB */ ,
+ .name = "persist",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 10 /* In MB */,
- .name = "recovery",
- },
+ .start = DIFF_START_ADDR,
+ .length = 10 /* In MB */ ,
+ .name = "recovery",
+ },
};
+
void smem_ptable_init(void);
unsigned smem_get_apps_flash_start(void);
@@ -164,7 +166,7 @@
struct ptentry *board_part_list;
unsigned total_num_of_blocks;
unsigned next_ptr_start_adr = 0;
- unsigned blocks_per_1MB = 8; /* Default value of 2k page size on 256MB flash drive*/
+ unsigned blocks_per_1MB = 8; /* Default value of 2k page size on 256MB flash drive */
int i;
dprintf(INFO, "target_init()\n");
@@ -181,14 +183,12 @@
display_image_on_screen();
#endif
- if (target_is_emmc_boot())
- {
+ if (target_is_emmc_boot()) {
/* Must wait for modem-up before we can intialize MMC.
*/
- while (readl(MSM_SHARED_BASE + 0x14) != 1);
+ while (readl(MSM_SHARED_BASE + 0x14) != 1) ;
- if(mmc_boot_main(MMC_SLOT, MSM_SDC3_BASE))
- {
+ if (mmc_boot_main(MMC_SLOT, MSM_SDC3_BASE)) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
}
@@ -204,7 +204,7 @@
offset = smem_get_apps_flash_start();
if (offset == 0xffffffff)
- while(1);
+ while (1) ;
total_num_of_blocks = flash_info->num_blocks;
blocks_per_1MB = (1 << 20) / (flash_info->block_size);
@@ -218,27 +218,29 @@
struct ptentry *ptn = &board_part_list[i];
unsigned len = ((ptn->length) * blocks_per_1MB);
- if(ptn->start != 0)
- ASSERT(ptn->start == DIFF_START_ADDR);
+ if (ptn->start != 0)
+ ASSERT(ptn->start == DIFF_START_ADDR);
ptn->start = next_ptr_start_adr;
- if(ptn->length == VARIABLE_LENGTH)
- {
+ if (ptn->length == VARIABLE_LENGTH) {
unsigned length_for_prt = 0;
unsigned j;
- for (j = i+1; j < num_parts; j++)
- {
- struct ptentry *temp_ptn = &board_part_list[j];
- ASSERT(temp_ptn->length != VARIABLE_LENGTH);
- length_for_prt += ((temp_ptn->length) * blocks_per_1MB);
+ for (j = i + 1; j < num_parts; j++) {
+ struct ptentry *temp_ptn = &board_part_list[j];
+ ASSERT(temp_ptn->length != VARIABLE_LENGTH);
+ length_for_prt +=
+ ((temp_ptn->length) * blocks_per_1MB);
}
- len = (total_num_of_blocks - 1) - (offset + ptn->start + length_for_prt);
+ len =
+ (total_num_of_blocks - 1) - (offset + ptn->start +
+ length_for_prt);
ASSERT(len >= 0);
}
next_ptr_start_adr = ptn->start + len;
ptable_add(&flash_ptable, ptn->name, offset + ptn->start,
- len, ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
+ len, ptn->flags, TYPE_APPS_PARTITION,
+ PERM_WRITEABLE);
}
smem_add_modem_partitions(&flash_ptable);
@@ -262,66 +264,70 @@
target_msm_id = MSM7225A;
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if(format == 4)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format == 4) {
board_info_len = sizeof(board_info_v4);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v4, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v4,
+ board_info_len);
+ if (!smem_status) {
id = board_info_v4.board_info_v3.hw_platform;
- target_msm_id = board_info_v4.board_info_v3.msm_id;
+ target_msm_id =
+ board_info_v4.board_info_v3.msm_id;
}
}
/* Detect SURF v/s FFA v/s QRD */
- switch(id)
- {
- case 0x1:
- /* Set the machine type based on msm ID */
- if (target_msm_id == MSM7225A || target_msm_id == MSM7625A || \
- target_msm_id == ESM7225A || (target_msm_id >= MSM7225AA \
- && target_msm_id <= ESM7225AA))
- hw_platform = MSM7X25A_SURF;
- else
- hw_platform = MSM7X27A_SURF;
- break;
- case 0x2:
- if (target_msm_id == MSM7225A || target_msm_id == MSM7625A || \
- target_msm_id == ESM7225A || (target_msm_id >= MSM7225AA \
- && target_msm_id <= ESM7225AA))
- hw_platform = MSM7X25A_FFA;
- else
- hw_platform = MSM7X27A_FFA;
- break;
- case 0xB:
- hw_platform = MSM7X27A_QRD1;
- break;
- default:
- if (target_msm_id == MSM7225A || target_msm_id == MSM7625A || \
- target_msm_id == ESM7225A || (target_msm_id >= MSM7225AA \
- && target_msm_id <= ESM7225AA))
- hw_platform = MSM7X25A_SURF;
- else
- hw_platform = MSM7X27A_SURF;
+ switch (id) {
+ case 0x1:
+ /* Set the machine type based on msm ID */
+ if (target_msm_id == MSM7225A
+ || target_msm_id == MSM7625A
+ || target_msm_id == ESM7225A
+ || (target_msm_id >= MSM7225AA
+ && target_msm_id <= ESM7225AA))
+ hw_platform = MSM7X25A_SURF;
+ else
+ hw_platform = MSM7X27A_SURF;
+ break;
+ case 0x2:
+ if (target_msm_id == MSM7225A
+ || target_msm_id == MSM7625A
+ || target_msm_id == ESM7225A
+ || (target_msm_id >= MSM7225AA
+ && target_msm_id <= ESM7225AA))
+ hw_platform = MSM7X25A_FFA;
+ else
+ hw_platform = MSM7X27A_FFA;
+ break;
+ case 0xB:
+ hw_platform = MSM7X27A_QRD1;
+ break;
+ default:
+ if (target_msm_id == MSM7225A
+ || target_msm_id == MSM7625A
+ || target_msm_id == ESM7225A
+ || (target_msm_id >= MSM7225AA
+ && target_msm_id <= ESM7225AA))
+ hw_platform = MSM7X25A_SURF;
+ else
+ hw_platform = MSM7X27A_SURF;
};
- /* Set msm ID for target variants based on values read from smem*/
- switch(target_msm_id)
- {
- case MSM7225A:
- case MSM7625A:
- case ESM7225A:
- case MSM7225AA:
- case MSM7625AA:
- case ESM7225AA:
- target_msm_id = MSM7625A;
- break;
- default:
- target_msm_id = MSM7627A;
+ /* Set msm ID for target variants based on values read from smem */
+ switch (target_msm_id) {
+ case MSM7225A:
+ case MSM7625A:
+ case ESM7225A:
+ case MSM7225AA:
+ case MSM7625AA:
+ case ESM7225AA:
+ target_msm_id = MSM7625A;
+ break;
+ default:
+ target_msm_id = MSM7627A;
}
}
return;
@@ -374,12 +380,12 @@
unsigned check_reboot_mode(void)
{
- unsigned mode[2] = {0, 0};
+ unsigned mode[2] = { 0, 0 };
unsigned int mode_len = sizeof(mode);
unsigned smem_status;
smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
- &mode, mode_len );
+ &mode, mode_len);
/*
* SMEM value is relied upon on power shutdown. Check either of SMEM
@@ -387,13 +393,13 @@
*/
check_fota_cookie();
- if((mode[0] == RECOVERY_MODE) || (fota_cookie[0] == FOTA_COOKIE))
+ if ((mode[0] == RECOVERY_MODE) || (fota_cookie[0] == FOTA_COOKIE))
return RECOVERY_MODE;
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for reboot mode\n");
- return 0;
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for reboot mode\n");
+ return 0;
}
return mode[0];
}
@@ -405,10 +411,10 @@
unsigned smem_status;
smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
- &power_on_status, status_len);
- if (smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for power on reason\n");
+ &power_on_status, status_len);
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for power on reason\n");
}
return power_on_status;
@@ -429,8 +435,8 @@
void target_serialno(unsigned char *buf)
{
unsigned int serialno;
- serialno = mmc_get_psn();
- sprintf(buf,"%x",serialno);
+ serialno = mmc_get_psn();
+ sprintf(buf, "%x", serialno);
}
int emmc_recovery_init(void)
@@ -440,4 +446,3 @@
return rc;
}
#endif
-
diff --git a/target/msm7627a/keypad.c b/target/msm7627a/keypad.c
index 4d9fde9..9b16248 100644
--- a/target/msm7627a/keypad.c
+++ b/target/msm7627a/keypad.c
@@ -41,16 +41,17 @@
/* don't turn this on without updating the ffa support */
#define SCAN_FUNCTION_KEYS 0
-static unsigned int halibut_row_gpios[] = {31, 32, 33, 34, 35};
-static unsigned int halibut_col_gpios[] = {36, 37, 38, 39, 40};
+static unsigned int halibut_row_gpios[] = { 31, 32, 33, 34, 35 };
+static unsigned int halibut_col_gpios[] = { 36, 37, 38, 39, 40 };
-static unsigned int halibut_row_gpios_qrd[] = {31, 32};
-static unsigned int halibut_col_gpios_qrd[] = {36, 37};
+static unsigned int halibut_row_gpios_qrd[] = { 31, 32 };
+static unsigned int halibut_col_gpios_qrd[] = { 36, 37 };
#define KEYMAP_INDEX(row, col) ((row)*ARRAY_SIZE(halibut_col_gpios) + (col))
#define KEYMAP_INDEX_QRD(row, col) ((row)*ARRAY_SIZE(halibut_col_gpios_qrd) + (col))
-static const unsigned short halibut_keymap[ARRAY_SIZE(halibut_col_gpios) * ARRAY_SIZE(halibut_row_gpios)] = {
+static const unsigned short halibut_keymap[ARRAY_SIZE(halibut_col_gpios) *
+ ARRAY_SIZE(halibut_row_gpios)] = {
[KEYMAP_INDEX(0, 0)] = KEY_7,
[KEYMAP_INDEX(0, 1)] = KEY_DOWN,
[KEYMAP_INDEX(0, 2)] = KEY_UP,
@@ -75,39 +76,43 @@
[KEYMAP_INDEX(3, 3)] = KEY_2,
[KEYMAP_INDEX(3, 4)] = KEY_SOFT2,
- [KEYMAP_INDEX(4, 0)] = KEY_MENU, /*R-*/
- [KEYMAP_INDEX(4, 1)] = KEY_HOME, /*L+*/
- [KEYMAP_INDEX(4, 2)] = KEY_BACK, /*L-*/
+ [KEYMAP_INDEX(4, 0)] = KEY_MENU, /*R- */
+ [KEYMAP_INDEX(4, 1)] = KEY_HOME, /*L+ */
+ [KEYMAP_INDEX(4, 2)] = KEY_BACK, /*L- */
[KEYMAP_INDEX(4, 3)] = KEY_VOLUMEUP,
[KEYMAP_INDEX(4, 4)] = KEY_VOLUMEDOWN,
};
-static const unsigned short halibut_keymap_qrd[ARRAY_SIZE(halibut_col_gpios_qrd) * ARRAY_SIZE(halibut_row_gpios_qrd)] = {
+static const unsigned short halibut_keymap_qrd[ARRAY_SIZE(halibut_col_gpios_qrd)
+ *
+ ARRAY_SIZE
+ (halibut_row_gpios_qrd)] = {
[KEYMAP_INDEX_QRD(0, 0)] = KEY_VOLUMEUP,
[KEYMAP_INDEX_QRD(0, 1)] = KEY_VOLUMEDOWN,
};
static struct gpio_keypad_info halibut_keypad_info_surf = {
- .keymap = halibut_keymap,
- .output_gpios = halibut_row_gpios,
- .input_gpios = halibut_col_gpios,
- .noutputs = ARRAY_SIZE(halibut_row_gpios),
- .ninputs = ARRAY_SIZE(halibut_col_gpios),
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
- .flags = GPIOKPF_DRIVE_INACTIVE,
+ .keymap = halibut_keymap,
+ .output_gpios = halibut_row_gpios,
+ .input_gpios = halibut_col_gpios,
+ .noutputs = ARRAY_SIZE(halibut_row_gpios),
+ .ninputs = ARRAY_SIZE(halibut_col_gpios),
+ .settle_time = 5 /* msec */ ,
+ .poll_time = 20 /* msec */ ,
+ .flags = GPIOKPF_DRIVE_INACTIVE,
};
static struct gpio_keypad_info halibut_keypad_info_qrd = {
- .keymap = halibut_keymap_qrd,
- .output_gpios = halibut_row_gpios_qrd,
- .input_gpios = halibut_col_gpios_qrd,
- .noutputs = ARRAY_SIZE(halibut_row_gpios_qrd),
- .ninputs = ARRAY_SIZE(halibut_col_gpios_qrd),
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
- .flags = GPIOKPF_DRIVE_INACTIVE,
+ .keymap = halibut_keymap_qrd,
+ .output_gpios = halibut_row_gpios_qrd,
+ .input_gpios = halibut_col_gpios_qrd,
+ .noutputs = ARRAY_SIZE(halibut_row_gpios_qrd),
+ .ninputs = ARRAY_SIZE(halibut_col_gpios_qrd),
+ .settle_time = 5 /* msec */ ,
+ .poll_time = 20 /* msec */ ,
+ .flags = GPIOKPF_DRIVE_INACTIVE,
};
+
void keypad_init(void)
{
unsigned int mach_id;
diff --git a/target/msm7627a/panel.c b/target/msm7627a/panel.c
index b7f6854..f5d336c 100644
--- a/target/msm7627a/panel.c
+++ b/target/msm7627a/panel.c
@@ -37,93 +37,94 @@
void config_renesas_dsi_video_mode(void)
{
- unsigned char dst_format = 3; /* RGB888 */
- unsigned char traffic_mode = 2; /* non burst mode with sync start events */
- unsigned char lane_en = 3; /* 3 Lanes -- Enables Data Lane0, 1, 2 */
- unsigned long low_pwr_stop_mode = 1;
- unsigned char eof_bllp_pwr = 0x9; /* Needed or else will have blank line at top of display */
- unsigned char interleav = 0;
+ unsigned char dst_format = 3; /* RGB888 */
+ unsigned char traffic_mode = 2; /* non burst mode with sync start events */
+ unsigned char lane_en = 3; /* 3 Lanes -- Enables Data Lane0, 1, 2 */
+ unsigned long low_pwr_stop_mode = 1;
+ unsigned char eof_bllp_pwr = 0x9; /* Needed or else will have blank line at top of display */
+ unsigned char interleav = 0;
- unsigned short display_wd = REN_MIPI_FB_WIDTH;
- unsigned short display_ht = REN_MIPI_FB_HEIGHT;
- unsigned short image_wd = REN_MIPI_FB_WIDTH;
- unsigned short image_ht = REN_MIPI_FB_HEIGHT;
- unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
- unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
- unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
- unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
- unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
- unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
+ unsigned short display_wd = REN_MIPI_FB_WIDTH;
+ unsigned short display_ht = REN_MIPI_FB_HEIGHT;
+ unsigned short image_wd = REN_MIPI_FB_WIDTH;
+ unsigned short image_ht = REN_MIPI_FB_HEIGHT;
+ unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
+ unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
+ unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
+ unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
+ unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
+ dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n");
+ dprintf(SPEW, "Traffic mode: burst mode\n");
+ if (machine_is_7x25a()) {
+ dprintf(CRITICAL,
+ "Entered 7x25A in config_renesas_dsi_video_mode\n");
+ dprintf(SPEW, "Data Lane: 1 lane\n");
+ display_wd = REN_MIPI_FB_WIDTH_HVGA;
+ display_ht = REN_MIPI_FB_HEIGHT_HVGA;
+ image_wd = REN_MIPI_FB_WIDTH_HVGA;
+ image_ht = REN_MIPI_FB_HEIGHT_HVGA;
+ hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA;
+ hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA;
+ vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA;
+ vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES_HVGA;
+ hsync_width = MIPI_HSYNC_PULSE_WIDTH_HVGA;
+ vsync_width = MIPI_VSYNC_PULSE_WIDTH_HVGA;
+ lane_en = 1;
+ } else {
+ dprintf(SPEW, "Data Lane: 2 lane\n");
+ }
- dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n");
- dprintf(SPEW, "Traffic mode: burst mode\n");
- if(machine_is_7x25a()) {
- dprintf(CRITICAL, "Entered 7x25A in config_renesas_dsi_video_mode\n");
- dprintf(SPEW, "Data Lane: 1 lane\n");
- display_wd = REN_MIPI_FB_WIDTH_HVGA;
- display_ht = REN_MIPI_FB_HEIGHT_HVGA;
- image_wd = REN_MIPI_FB_WIDTH_HVGA;
- image_ht = REN_MIPI_FB_HEIGHT_HVGA;
- hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA;
- hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA;
- vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA;
- vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES_HVGA;
- hsync_width = MIPI_HSYNC_PULSE_WIDTH_HVGA;
- vsync_width = MIPI_VSYNC_PULSE_WIDTH_HVGA;
- lane_en = 1;
- } else {
- dprintf(SPEW, "Data Lane: 2 lane\n");
- }
+ writel(0x00000000, MDP_DSI_VIDEO_EN);
- writel(0x00000000, MDP_DSI_VIDEO_EN);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000002, DSI_CLK_CTRL);
+ writel(0x00000006, DSI_CLK_CTRL);
+ writel(0x0000000e, DSI_CLK_CTRL);
+ writel(0x0000001e, DSI_CLK_CTRL);
+ writel(0x0000003e, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000002, DSI_CLK_CTRL);
- writel(0x00000006, DSI_CLK_CTRL);
- writel(0x0000000e, DSI_CLK_CTRL);
- writel(0x0000001e, DSI_CLK_CTRL);
- writel(0x0000003e, DSI_CLK_CTRL);
+ writel(0, DSI_CTRL);
- writel(0, DSI_CTRL);
+ writel(0, DSI_ERR_INT_MASK0);
- writel(0, DSI_ERR_INT_MASK0);
+ writel(0x02020202, DSI_INT_CTRL);
- writel(0x02020202, DSI_INT_CTRL);
+ writel(((hsync_porch_bp + display_wd) << 16) | hsync_porch_bp,
+ DSI_VIDEO_MODE_ACTIVE_H);
- writel(((hsync_porch_bp + display_wd)<<16) | hsync_porch_bp,
- DSI_VIDEO_MODE_ACTIVE_H);
+ writel(((vsync_porch_bp + display_ht) << 16) | vsync_porch_bp,
+ DSI_VIDEO_MODE_ACTIVE_V);
- writel(((vsync_porch_bp + display_ht)<<16) | vsync_porch_bp,
- DSI_VIDEO_MODE_ACTIVE_V);
+ writel(((display_ht + vsync_porch_fp + vsync_porch_bp) << 16) |
+ (display_wd + hsync_porch_fp + hsync_porch_bp),
+ DSI_VIDEO_MODE_TOTAL);
+ writel((hsync_width) << 16 | 0, DSI_VIDEO_MODE_HSYNC);
- writel(((display_ht + vsync_porch_fp + vsync_porch_bp)<< 16) |
- (display_wd + hsync_porch_fp + hsync_porch_bp ),
- DSI_VIDEO_MODE_TOTAL );
- writel((hsync_width)<<16 | 0, DSI_VIDEO_MODE_HSYNC);
+ writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
- writel(0<<16 | 0, DSI_VIDEO_MODE_VSYNC);
+ writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
- writel(vsync_width<<16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
+ writel(1, DSI_EOT_PACKET_CTRL);
- writel(1, DSI_EOT_PACKET_CTRL);
+ writel(0x00000100, DSI_MISR_VIDEO_CTRL);
- writel(0x00000100, DSI_MISR_VIDEO_CTRL);
+ writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
+ eof_bllp_pwr << 12 | traffic_mode << 8 | dst_format << 4 | 0x0,
+ DSI_VIDEO_MODE_CTRL);
- writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | traffic_mode << 8
- | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
+ writel(0x67, DSI_CAL_STRENGTH_CTRL);
+ writel(0x80006711, DSI_CAL_CTRL);
+ writel(0x00010100, DSI_MISR_VIDEO_CTRL);
- writel(0x67, DSI_CAL_STRENGTH_CTRL);
- writel(0x80006711, DSI_CAL_CTRL);
- writel(0x00010100, DSI_MISR_VIDEO_CTRL);
+ writel(0x00010100, DSI_INT_CTRL);
+ writel(0x02010202, DSI_INT_CTRL);
+ writel(0x02030303, DSI_INT_CTRL);
- writel(0x00010100, DSI_INT_CTRL);
- writel(0x02010202, DSI_INT_CTRL);
- writel(0x02030303, DSI_INT_CTRL);
-
- writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
- | 0x103, DSI_CTRL);
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
+ | 0x103, DSI_CTRL);
}
diff --git a/target/msm7627a/tools/mkheader.c b/target/msm7627a/tools/mkheader.c
index 6029e0d..0eac822 100644
--- a/target/msm7627a/tools/mkheader.c
+++ b/target/msm7627a/tools/mkheader.c
@@ -39,36 +39,48 @@
#include <sys/stat.h>
-int print_usage(){
- fprintf(stderr,"usage: mkheader <bin> <hdr> <none|unified-boot>\n");
- fprintf(stderr," mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <emmc>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
- fprintf(stderr,"bin: Input raw appsbl binary\n");
- fprintf(stderr,"hdr: Output of appsbl header location\n");
- fprintf(stderr,"outbin: Output of the signed or unsigned apps boot location\n");
- fprintf(stderr,"maxsize: Maximum size for certificate chain\n");
- fprintf(stderr,"emmc: This flag takes value 1 or 0, 1 - emmc 0 - nand\n");
- fprintf(stderr,"certchain: Output of the certchain location\n");
- fprintf(stderr,"files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
- fprintf(stderr,"certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <emmc>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate chain\n");
+ fprintf(stderr,
+ "emmc: This flag takes value 1 or 0, 1 - emmc 0 - nand\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
return -1;
}
-int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size){
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
unsigned bytes_left = size;
char buf[buff_size];
int ret = 0;
- while(bytes_left){
+ while (bytes_left) {
fread(buf, sizeof(char), buff_size, in);
- if(!feof(in)){
+ if (!feof(in)) {
bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
- }else
+ } else
bytes_left = 0;
}
- ret = ferror(in) | ferror(out);
- if(ret)
+ ret = ferror(in) | ferror(out);
+ if (ret)
fprintf(stderr, "ERROR: Occured during file concatenation\n");
return ret;
}
@@ -88,26 +100,27 @@
int emmc = 0;
int fd;
- if(argc < 3) {
+ if (argc < 3) {
return print_usage();
}
if (argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
+ if (!strcmp("unified-boot", argv[3])) {
unified_boot = 1;
- }else if(!strcmp("secure-boot",argv[3])){
+ } else if (!strcmp("secure-boot", argv[3])) {
fprintf(stderr,
"ERROR: Missing arguments: [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
- }else if(!strcmp("unsecure-boot",argv[3])){
- fprintf(stderr,"ERROR: Missing arguments: outbin directory\n");
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr,
+ "ERROR: Missing arguments: outbin directory\n");
return print_usage();
}
}
if (argc > 4) {
- if(!strcmp("secure-boot",argv[3])) {
- if(argc < 9 && argc != 7) {
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 7) {
fprintf(stderr,
"ERROR: Missing argument(s): [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
@@ -116,16 +129,16 @@
emmc = 1;
}
secure_boot = 1;
- signature_size = 256; //Support SHA 256
+ signature_size = 256; //Support SHA 256
cert_chain_size = atoi(argv[5]);
- }
+ }
}
- if(stat(argv[1], &s)) {
+ if (stat(argv[1], &s)) {
perror("cannot stat binary");
return -1;
}
- if(unified_boot || emmc) {
+ if (unified_boot || emmc) {
magic = unified_boot_magic;
magic_len = sizeof(unified_boot_magic);
} else {
@@ -136,24 +149,23 @@
size = s.st_size;
base = 0;
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000003; //Flash_partition_version /* nand */
- magic[2] = 0x00000000; //image source pointer
- magic[3] = base; //image destination pointer
- magic[4] = size + cert_chain_size + signature_size; //image size
- magic[5] = size; //code size
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
magic[6] = base + size;
magic[7] = signature_size;
magic[8] = size + base + signature_size;
magic[9] = cert_chain_size;
- if (unified_boot == 1 || emmc == 1)
- {
- magic[10] = 0x33836685; /* cookie magic number */
- magic[11] = 0x00000001; /* cookie version */
- magic[12] = 0x00000002; /* file formats */
+ if (unified_boot == 1 || emmc == 1) {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
magic[13] = 0x00000000;
- magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[14] = 0x00000000; /* not setting size for boot.img */
magic[15] = 0x00000000;
magic[16] = 0x00000000;
magic[17] = 0x00000000;
@@ -162,11 +174,11 @@
}
fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
+ if (fd < 0) {
perror("cannot open header for writing");
return -1;
}
- if(write(fd, magic, magic_len) != magic_len) {
+ if (write(fd, magic, magic_len) != magic_len) {
perror("cannot write header");
close(fd);
unlink(argv[2]);
@@ -174,9 +186,9 @@
}
close(fd);
- if (secure_boot && argc > 7 ){
- FILE * input_file;
- FILE * output_file;
+ if (secure_boot && argc > 7) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
unsigned bytes_left;
@@ -184,13 +196,13 @@
int padding_size = 0;
int i;
- if((output_file = fopen(argv[6], "wb"))==NULL){
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
- for (i = 8; i < argc; i++){
- if((input_file = fopen(argv[i], "rb"))==NULL){
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -198,7 +210,7 @@
bytes_left = s.st_size;
current_cert_chain_size += bytes_left;
if (cat(input_file, output_file, bytes_left, buff_size))
- return -1;
+ return -1;
fclose(input_file);
}
@@ -206,67 +218,70 @@
memset(buf, 0xFF, sizeof(buf));
padding_size = cert_chain_size - current_cert_chain_size;
bytes_left = (padding_size > 0) ? padding_size : 0;
- while(bytes_left){
- if(!ferror(output_file))
- bytes_left -= fwrite(buf, sizeof(buf), buff_size, output_file);
- else{
- fprintf(stderr, "ERROR: Occured during certifcate chain padding\n");
+ while (bytes_left) {
+ if (!ferror(output_file))
+ bytes_left -=
+ fwrite(buf, sizeof(buf), buff_size,
+ output_file);
+ else {
+ fprintf(stderr,
+ "ERROR: Occured during certifcate chain padding\n");
return -1;
}
}
fclose(output_file);
//Concat and combine to signed image. Format [RAW APPSBOOT][PADDED CERT CHAIN]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
-
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Signature
- if((input_file = fopen(argv[7], "rb"))==NULL){
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[7], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Certifcate Chain
- if((input_file = fopen(argv[6], "rb"))==NULL){
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
- if(cat(input_file, output_file, (current_cert_chain_size + padding_size), buff_size))
+ if (cat
+ (input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
return -1;
fclose(input_file);
fclose(output_file);
- }else if(argc == 5 || argc == 7){
- FILE * input_file;
- FILE * output_file;
+ } else if (argc == 5 || argc == 7) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
//Concat and combine to unsigned image. Format [HDR][RAW APPSBOOT]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
-
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -276,12 +291,12 @@
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
fclose(output_file);
diff --git a/target/msm7630_surf/atags.c b/target/msm7630_surf/atags.c
index 6e1fd9c..9c564b5 100644
--- a/target/msm7630_surf/atags.c
+++ b/target/msm7630_surf/atags.c
@@ -33,83 +33,73 @@
#define EBI1_ADDR_128M 0x08000000
#define SIZE_1M 0x00100000
-
static int scratch_addr = -1;
-unsigned* target_atag_mem(unsigned* ptr)
+unsigned *target_atag_mem(unsigned *ptr)
{
- struct smem_ram_ptable ram_ptable;
- unsigned i = 0;
+ struct smem_ram_ptable ram_ptable;
+ unsigned i = 0;
- if (smem_ram_ptable_init(&ram_ptable))
- {
- for (i = 0; i < ram_ptable.len; i++)
- {
- if ((ram_ptable.parts[i].attr == READWRITE)
- && (ram_ptable.parts[i].domain == APPS_DOMAIN)
- && (ram_ptable.parts[i].type == APPS_MEMORY)
- && (ram_ptable.parts[i].category != IMEM))
- {
- /* ATAG_MEM */
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = ram_ptable.parts[i].size;
- *ptr++ = ram_ptable.parts[i].start;
- }
+ if (smem_ram_ptable_init(&ram_ptable)) {
+ for (i = 0; i < ram_ptable.len; i++) {
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].type == APPS_MEMORY)
+ && (ram_ptable.parts[i].category != IMEM)) {
+ /* ATAG_MEM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = ram_ptable.parts[i].size;
+ *ptr++ = ram_ptable.parts[i].start;
+ }
- /* Check for modem bootloader memory that can be reclaimed */
- if ((ram_ptable.parts[i].attr == READWRITE)
- && (ram_ptable.parts[i].domain == APPS_DOMAIN)
- && (ram_ptable.parts[i].type == BOOT_REGION_MEMORY1))
- {
- /* ATAG_MEM_OSBL */
- *ptr++ = 4;
- *ptr++ = 0x5441000C;
- *ptr++ = ram_ptable.parts[i].size;
- *ptr++ = ram_ptable.parts[i].start;
- }
- }
- }
- else
- {
- dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
- ASSERT(0);
- }
+ /* Check for modem bootloader memory that can be reclaimed */
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].type ==
+ BOOT_REGION_MEMORY1)) {
+ /* ATAG_MEM_OSBL */
+ *ptr++ = 4;
+ *ptr++ = 0x5441000C;
+ *ptr++ = ram_ptable.parts[i].size;
+ *ptr++ = ram_ptable.parts[i].start;
+ }
+ }
+ } else {
+ dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
+ ASSERT(0);
+ }
- return ptr;
+ return ptr;
}
void *target_get_scratch_address(void)
{
- struct smem_ram_ptable ram_ptable;
- unsigned i = 0;
+ struct smem_ram_ptable ram_ptable;
+ unsigned i = 0;
- if (smem_ram_ptable_init(&ram_ptable))
- {
- for (i = 0; i < ram_ptable.len; i++)
- {
- if ((ram_ptable.parts[i].attr == READWRITE)
- && (ram_ptable.parts[i].domain == APPS_DOMAIN)
- && (ram_ptable.parts[i].start != 0x0))
- {
- if (ram_ptable.parts[i].size >= FASTBOOT_BUF_SIZE)
- {
- scratch_addr = ram_ptable.parts[i].start;
- break;
- }
- }
- }
- }
- else
- {
- dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
- ASSERT(0);
- }
+ if (smem_ram_ptable_init(&ram_ptable)) {
+ for (i = 0; i < ram_ptable.len; i++) {
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].start != 0x0)) {
+ if (ram_ptable.parts[i].size >=
+ FASTBOOT_BUF_SIZE) {
+ scratch_addr =
+ ram_ptable.parts[i].start;
+ break;
+ }
+ }
+ }
+ } else {
+ dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
+ ASSERT(0);
+ }
- return (void *)((scratch_addr == -1) ? EBI1_ADDR_128M : scratch_addr);
+ return (void *)((scratch_addr == -1) ? EBI1_ADDR_128M : scratch_addr);
}
unsigned target_get_max_flash_size(void)
{
- return (180 * 1024 * 1024);
+ return (180 * 1024 * 1024);
}
diff --git a/target/msm7630_surf/init.c b/target/msm7630_surf/init.c
index d148999..4a59275 100644
--- a/target/msm7630_surf/init.c
+++ b/target/msm7630_surf/init.c
@@ -51,7 +51,8 @@
#define DIFF_START_ADDR 0xF0F0F0F0
#define NUM_PAGES_PER_BLOCK 0x40
-static unsigned mmc_sdc_base[] = { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE};
+static unsigned mmc_sdc_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
static struct ptable flash_ptable;
static int hw_platform_type = -1;
@@ -66,47 +67,48 @@
*/
static struct ptentry board_part_list[] = {
{
- .start = 0,
- .length = 5 /* In MB */,
- .name = "boot",
- },
+ .start = 0,
+ .length = 5 /* In MB */ ,
+ .name = "boot",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 180 /* In MB */,
- .name = "system",
- },
+ .start = DIFF_START_ADDR,
+ .length = 180 /* In MB */ ,
+ .name = "system",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 5 /* In MB */,
- .name = "cache",
- },
+ .start = DIFF_START_ADDR,
+ .length = 5 /* In MB */ ,
+ .name = "cache",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 1 /* In MB */,
- .name = "misc",
- },
+ .start = DIFF_START_ADDR,
+ .length = 1 /* In MB */ ,
+ .name = "misc",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 1 /* In MB */,
- .name = "devinfo",
- },
+ .start = DIFF_START_ADDR,
+ .length = 1 /* In MB */ ,
+ .name = "devinfo",
+ },
{
- .start = DIFF_START_ADDR,
- .length = VARIABLE_LENGTH,
- .name = "userdata",
- },
+ .start = DIFF_START_ADDR,
+ .length = VARIABLE_LENGTH,
+ .name = "userdata",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 3 /* In MB */,
- .name = "persist",
- },
+ .start = DIFF_START_ADDR,
+ .length = 3 /* In MB */ ,
+ .name = "persist",
+ },
{
- .start = DIFF_START_ADDR,
- .length = 5 /* In MB */,
- .name = "recovery",
- },
+ .start = DIFF_START_ADDR,
+ .length = 5 /* In MB */ ,
+ .name = "recovery",
+ },
};
-static int num_parts = sizeof(board_part_list)/sizeof(struct ptentry);
+
+static int num_parts = sizeof(board_part_list) / sizeof(struct ptentry);
void smem_ptable_init(void);
unsigned smem_get_apps_flash_start(void);
@@ -114,7 +116,7 @@
void keypad_init(void);
-static int emmc_boot = -1; /* set to uninitialized */
+static int emmc_boot = -1; /* set to uninitialized */
int target_is_emmc_boot(void);
static int platform_version = -1;
static int target_msm_id = -1;
@@ -123,45 +125,45 @@
int target_is_interleaved_mode(void)
{
- struct smem_board_info_v4 board_info_v4;
- unsigned int board_info_len = 0;
- unsigned smem_status;
- char *build_type;
- unsigned format = 0;
+ struct smem_board_info_v4 board_info_v4;
+ unsigned int board_info_len = 0;
+ unsigned smem_status;
+ char *build_type;
+ unsigned format = 0;
- if (interleaved_mode_enabled != -1)
- {
- return interleaved_mode_enabled;
- }
-
- smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if ((format == 3) || (format == 4))
- {
- if (format == 4)
- board_info_len = sizeof(board_info_v4);
- else
- board_info_len = sizeof(board_info_v4.board_info_v3);
-
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v4, board_info_len);
- if(!smem_status)
- {
- build_type = (char *)(board_info_v4.board_info_v3.build_id) + 9;
-
- interleaved_mode_enabled = 0;
-
- if (*build_type == 'C')
- {
- interleaved_mode_enabled = 1;
- }
- }
+ if (interleaved_mode_enabled != -1) {
+ return interleaved_mode_enabled;
}
- }
- return interleaved_mode_enabled;
+ smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if ((format == 3) || (format == 4)) {
+ if (format == 4)
+ board_info_len = sizeof(board_info_v4);
+ else
+ board_info_len =
+ sizeof(board_info_v4.board_info_v3);
+
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v4,
+ board_info_len);
+ if (!smem_status) {
+ build_type =
+ (char *)(board_info_v4.
+ board_info_v3.build_id) + 9;
+
+ interleaved_mode_enabled = 0;
+
+ if (*build_type == 'C') {
+ interleaved_mode_enabled = 1;
+ }
+ }
+ }
+ }
+
+ return interleaved_mode_enabled;
}
void target_init(void)
@@ -170,7 +172,7 @@
struct flash_info *flash_info;
unsigned total_num_of_blocks;
unsigned next_ptr_start_adr = 0;
- unsigned blocks_per_1MB = 8; /* Default value of 2k page size on 256MB flash drive*/
+ unsigned blocks_per_1MB = 8; /* Default value of 2k page size on 256MB flash drive */
unsigned base_addr;
unsigned char slot;
int i;
@@ -189,22 +191,19 @@
display_image_on_screen();
#endif
- if (target_is_emmc_boot())
- {
+ if (target_is_emmc_boot()) {
/* Must wait for modem-up before we can intialize MMC.
*/
- while (readl(MSM_SHARED_BASE + 0x14) != 1);
+ while (readl(MSM_SHARED_BASE + 0x14) != 1) ;
/* Trying Slot 2 first */
slot = 2;
- base_addr = mmc_sdc_base[slot-1];
- if(mmc_boot_main(slot, base_addr))
- {
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
/* Trying Slot 4 next */
slot = 4;
- base_addr = mmc_sdc_base[slot-1];
- if(mmc_boot_main(slot, base_addr))
- {
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
}
@@ -222,7 +221,7 @@
offset = smem_get_apps_flash_start();
if (offset == 0xffffffff)
- while(1);
+ while (1) ;
total_num_of_blocks = flash_info->num_blocks;
blocks_per_1MB = (1 << 20) / (flash_info->block_size);
@@ -231,32 +230,35 @@
struct ptentry *ptn = &board_part_list[i];
unsigned len = ((ptn->length) * blocks_per_1MB);
- if(ptn->start != 0)
- ASSERT(ptn->start == DIFF_START_ADDR);
+ if (ptn->start != 0)
+ ASSERT(ptn->start == DIFF_START_ADDR);
ptn->start = next_ptr_start_adr;
- if(ptn->length == VARIABLE_LENGTH)
- {
+ if (ptn->length == VARIABLE_LENGTH) {
unsigned length_for_prt = 0;
unsigned j;
- for (j = i+1; j < num_parts; j++)
- {
- struct ptentry *temp_ptn = &board_part_list[j];
- ASSERT(temp_ptn->length != VARIABLE_LENGTH);
- length_for_prt += ((temp_ptn->length) * blocks_per_1MB);
+ for (j = i + 1; j < num_parts; j++) {
+ struct ptentry *temp_ptn = &board_part_list[j];
+ ASSERT(temp_ptn->length != VARIABLE_LENGTH);
+ length_for_prt +=
+ ((temp_ptn->length) * blocks_per_1MB);
}
- len = total_num_of_blocks - (offset + ptn->start + length_for_prt);
+ len =
+ total_num_of_blocks - (offset + ptn->start +
+ length_for_prt);
ASSERT(len >= 0);
}
next_ptr_start_adr = ptn->start + len;
- if(target_is_interleaved_mode()) {
- ptable_add(&flash_ptable, ptn->name, offset + (ptn->start / 2),
- (len / 2), ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
- }
- else {
- ptable_add(&flash_ptable, ptn->name, offset + ptn->start,
- len, ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
+ if (target_is_interleaved_mode()) {
+ ptable_add(&flash_ptable, ptn->name,
+ offset + (ptn->start / 2), (len / 2),
+ ptn->flags, TYPE_APPS_PARTITION,
+ PERM_WRITEABLE);
+ } else {
+ ptable_add(&flash_ptable, ptn->name,
+ offset + ptn->start, len, ptn->flags,
+ TYPE_APPS_PARTITION, PERM_WRITEABLE);
}
}
@@ -268,116 +270,130 @@
int target_platform_version(void)
{
- return platform_version;
+ return platform_version;
}
int target_is_msm8x55(void)
{
- if ((target_msm_id == MSM8255_ID) ||
- (target_msm_id == MSM8655_ID) ||
- (target_msm_id == APQ8055_ID))
- return 1;
- else
- return 0;
+ if ((target_msm_id == MSM8255_ID) ||
+ (target_msm_id == MSM8655_ID) || (target_msm_id == APQ8055_ID))
+ return 1;
+ else
+ return 0;
}
unsigned board_machtype(void)
{
- struct smem_board_info_v4 board_info_v4;
- unsigned int board_info_len = 0;
- enum platform platform_type = 0;
- unsigned smem_status;
- unsigned format = 0;
- if(hw_platform_type != -1)
- return hw_platform_type;
-
- smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if ((format == 3) || (format == 4))
- {
- if (format == 4)
- board_info_len = sizeof(board_info_v4);
- else
- board_info_len = sizeof(board_info_v4.board_info_v3);
-
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v4, board_info_len);
- if(!smem_status)
- {
- if(format == 4)
- platform_version = board_info_v4.platform_version;
-
- platform_type = board_info_v4.board_info_v3.hw_platform;
- target_msm_id = board_info_v4.board_info_v3.msm_id;
- switch (platform_type)
- {
- case HW_PLATFORM_SURF:
- hw_platform_type = ((target_is_msm8x55()) ?
- LINUX_MACHTYPE_8x55_SURF : LINUX_MACHTYPE_7x30_SURF); break;
- case HW_PLATFORM_FFA:
- hw_platform_type = ((target_is_msm8x55()) ?
- LINUX_MACHTYPE_8x55_FFA : LINUX_MACHTYPE_7x30_FFA); break;
- case HW_PLATFORM_FLUID:
- hw_platform_type = LINUX_MACHTYPE_7x30_FLUID; break;
- case HW_PLATFORM_SVLTE:
- hw_platform_type = LINUX_MACHTYPE_8x55_SVLTE_FFA; break;
- default:
- hw_platform_type = ((target_is_msm8x55()) ?
- LINUX_MACHTYPE_8x55_SURF : LINUX_MACHTYPE_7x30_SURF); break;
- }
+ struct smem_board_info_v4 board_info_v4;
+ unsigned int board_info_len = 0;
+ enum platform platform_type = 0;
+ unsigned smem_status;
+ unsigned format = 0;
+ if (hw_platform_type != -1)
return hw_platform_type;
- }
+
+ smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if ((format == 3) || (format == 4)) {
+ if (format == 4)
+ board_info_len = sizeof(board_info_v4);
+ else
+ board_info_len =
+ sizeof(board_info_v4.board_info_v3);
+
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v4,
+ board_info_len);
+ if (!smem_status) {
+ if (format == 4)
+ platform_version =
+ board_info_v4.platform_version;
+
+ platform_type =
+ board_info_v4.board_info_v3.hw_platform;
+ target_msm_id =
+ board_info_v4.board_info_v3.msm_id;
+ switch (platform_type) {
+ case HW_PLATFORM_SURF:
+ hw_platform_type =
+ ((target_is_msm8x55())?
+ LINUX_MACHTYPE_8x55_SURF :
+ LINUX_MACHTYPE_7x30_SURF);
+ break;
+ case HW_PLATFORM_FFA:
+ hw_platform_type =
+ ((target_is_msm8x55())?
+ LINUX_MACHTYPE_8x55_FFA :
+ LINUX_MACHTYPE_7x30_FFA);
+ break;
+ case HW_PLATFORM_FLUID:
+ hw_platform_type =
+ LINUX_MACHTYPE_7x30_FLUID;
+ break;
+ case HW_PLATFORM_SVLTE:
+ hw_platform_type =
+ LINUX_MACHTYPE_8x55_SVLTE_FFA;
+ break;
+ default:
+ hw_platform_type =
+ ((target_is_msm8x55())?
+ LINUX_MACHTYPE_8x55_SURF :
+ LINUX_MACHTYPE_7x30_SURF);
+ break;
+ }
+ return hw_platform_type;
+ }
+ }
}
- }
- hw_platform_type = LINUX_MACHTYPE_7x30_SURF;
- return hw_platform_type;
+ hw_platform_type = LINUX_MACHTYPE_7x30_SURF;
+ return hw_platform_type;
}
void reboot_device(unsigned reboot_reason)
{
- reboot(reboot_reason);
+ reboot(reboot_reason);
}
unsigned check_reboot_mode(void)
{
- unsigned mode[2] = {0, 0};
- unsigned int mode_len = sizeof(mode);
- unsigned smem_status;
+ unsigned mode[2] = { 0, 0 };
+ unsigned int mode_len = sizeof(mode);
+ unsigned smem_status;
- smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
- &mode, mode_len );
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for reboot mode\n");
- return 0;
- }
- return mode[0];
+ smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
+ &mode, mode_len);
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for reboot mode\n");
+ return 0;
+ }
+ return mode[0];
}
static unsigned target_check_power_on_reason(void)
{
- unsigned power_on_status = 0;
- unsigned int status_len = sizeof(power_on_status);
- unsigned smem_status;
+ unsigned power_on_status = 0;
+ unsigned int status_len = sizeof(power_on_status);
+ unsigned smem_status;
- smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
- &power_on_status, status_len);
+ smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
+ &power_on_status, status_len);
- if (smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for power on reason\n");
- }
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for power on reason\n");
+ }
- return power_on_status;
+ return power_on_status;
}
#if _EMMC_BOOT
void target_serialno(unsigned char *buf)
{
unsigned int serialno;
- serialno = mmc_get_psn();
+ serialno = mmc_get_psn();
snprintf(buf, 13, "%x", serialno);
}
diff --git a/target/msm7630_surf/keypad.c b/target/msm7630_surf/keypad.c
index 5733a86..4507f35 100644
--- a/target/msm7630_surf/keypad.c
+++ b/target/msm7630_surf/keypad.c
@@ -37,32 +37,32 @@
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#define BITS_IN_ELEMENT(x) (sizeof(x)[0] * 8)
-static unsigned char qwerty_keys_old[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-static unsigned char qwerty_keys_new[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+static unsigned char qwerty_keys_old[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+static unsigned char qwerty_keys_new[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
#define KEYMAP_INDEX(row, col) (row)* BITS_IN_ELEMENT(qwerty_keys_new) + (col)
static unsigned int qwerty_keymap[] = {
- [KEYMAP_INDEX(4, 2)] = KEY_BACK, /* -L on SURF & FFA */
- [KEYMAP_INDEX(3, 4)] = KEY_HOME, /* +R on SURF & FFA */
- [KEYMAP_INDEX(1, 3)] = KEY_VOLUMEUP, /* '+' of left side switch on FLUID */
- [KEYMAP_INDEX(1, 4)] = KEY_VOLUMEDOWN, /* '-' of left side switch on FLUID */
+ [KEYMAP_INDEX(4, 2)] = KEY_BACK, /* -L on SURF & FFA */
+ [KEYMAP_INDEX(3, 4)] = KEY_HOME, /* +R on SURF & FFA */
+ [KEYMAP_INDEX(1, 3)] = KEY_VOLUMEUP, /* '+' of left side switch on FLUID */
+ [KEYMAP_INDEX(1, 4)] = KEY_VOLUMEDOWN, /* '-' of left side switch on FLUID */
};
static struct qwerty_keypad_info qwerty_keypad = {
- .keymap = qwerty_keymap,
- .old_keys = qwerty_keys_old,
- .rec_keys = qwerty_keys_new,
- .rows = 5,
- .columns = 5,
- .num_of_reads = 6,
- .rd_func = &i2c_ssbi_read_bytes,
- .wr_func = &i2c_ssbi_write_bytes,
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
+ .keymap = qwerty_keymap,
+ .old_keys = qwerty_keys_old,
+ .rec_keys = qwerty_keys_new,
+ .rows = 5,
+ .columns = 5,
+ .num_of_reads = 6,
+ .rd_func = &i2c_ssbi_read_bytes,
+ .wr_func = &i2c_ssbi_write_bytes,
+ .settle_time = 5 /* msec */ ,
+ .poll_time = 20 /* msec */ ,
};
void keypad_init(void)
{
- ssbi_keypad_init(&qwerty_keypad);
+ ssbi_keypad_init(&qwerty_keypad);
}
diff --git a/target/msm7630_surf/tools/mkheader.c b/target/msm7630_surf/tools/mkheader.c
index fda8b67..4ebdde9 100644
--- a/target/msm7630_surf/tools/mkheader.c
+++ b/target/msm7630_surf/tools/mkheader.c
@@ -39,35 +39,46 @@
#include <sys/stat.h>
-int print_usage(){
- fprintf(stderr,"usage: mkheader <bin> <hdr> <none|unified-boot>\n");
- fprintf(stderr," mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
- fprintf(stderr,"bin: Input raw appsbl binary\n");
- fprintf(stderr,"hdr: Output of appsbl header location\n");
- fprintf(stderr,"outbin: Output of the signed or unsigned apps boot location\n");
- fprintf(stderr,"maxsize: Maximum size for certificate chain\n");
- fprintf(stderr,"certchain: Output of the certchain location\n");
- fprintf(stderr,"files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
- fprintf(stderr,"certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate chain\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
return -1;
}
-int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size){
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
unsigned bytes_left = size;
char buf[buff_size];
int ret = 0;
- while(bytes_left){
+ while (bytes_left) {
fread(buf, sizeof(char), buff_size, in);
- if(!feof(in)){
+ if (!feof(in)) {
bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
- }else
+ } else
bytes_left = 0;
}
ret = ferror(in) | ferror(out);
- if(ret)
+ if (ret)
fprintf(stderr, "ERROR: Occured during file concatenation\n");
return ret;
}
@@ -86,43 +97,43 @@
int secure_boot = 0;
int fd;
- if(argc < 3) {
+ if (argc < 3) {
return print_usage();
}
if (argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
+ if (!strcmp("unified-boot", argv[3])) {
unified_boot = 1;
- }else if(!strcmp("secure-boot",argv[3])){
+ } else if (!strcmp("secure-boot", argv[3])) {
fprintf(stderr,
"ERROR: Missing arguments: [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
- }
- else if(!strcmp("unsecure-boot",argv[3])){
- fprintf(stderr,"ERROR: Missing arguments: outbin directory\n");
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr,
+ "ERROR: Missing arguments: outbin directory\n");
return print_usage();
}
}
if (argc > 4) {
- if(!strcmp("secure-boot",argv[3])) {
- if(argc < 9 && argc != 6){
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 6) {
fprintf(stderr,
"ERROR: Missing argument(s): [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
- }
- secure_boot = 1;
- signature_size = 256; //Support SHA 256
+ }
+ secure_boot = 1;
+ signature_size = 256; //Support SHA 256
cert_chain_size = atoi(argv[5]);
- }
+ }
}
- if(stat(argv[1], &s)) {
+ if (stat(argv[1], &s)) {
perror("cannot stat binary");
return -1;
}
- if(unified_boot) {
+ if (unified_boot) {
magic = unified_boot_magic;
magic_len = sizeof(unified_boot_magic);
} else {
@@ -139,24 +150,23 @@
printf("Image Destination Pointer: 0x%x\n", base);
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000003; //Flash_partition_version /* nand */
- magic[2] = 0x00000000; //image source pointer
- magic[3] = base; //image destination pointer
- magic[4] = size + cert_chain_size + signature_size; //image size
- magic[5] = size; //code size
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
magic[6] = base + size;
magic[7] = signature_size;
magic[8] = size + base + signature_size;
magic[9] = cert_chain_size;
- if (unified_boot == 1)
- {
- magic[10] = 0x33836685; /* cookie magic number */
- magic[11] = 0x00000001; /* cookie version */
- magic[12] = 0x00000002; /* file formats */
+ if (unified_boot == 1) {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
magic[13] = 0x00000000;
- magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[14] = 0x00000000; /* not setting size for boot.img */
magic[15] = 0x00000000;
magic[16] = 0x00000000;
magic[17] = 0x00000000;
@@ -165,11 +175,11 @@
}
fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
+ if (fd < 0) {
perror("cannot open header for writing");
return -1;
}
- if(write(fd, magic, magic_len) != magic_len) {
+ if (write(fd, magic, magic_len) != magic_len) {
perror("cannot write header");
close(fd);
unlink(argv[2]);
@@ -177,9 +187,9 @@
}
close(fd);
- if (secure_boot && argc > 6){
- FILE * input_file;
- FILE * output_file;
+ if (secure_boot && argc > 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
unsigned bytes_left;
@@ -187,14 +197,14 @@
int padding_size = 0;
int i;
- if((output_file = fopen(argv[6], "wb"))==NULL){
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Certificate Chain Output File: %s\n", argv[6]);
- for (i = 8; i < argc; i++){
- if((input_file = fopen(argv[i], "rb"))==NULL){
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -210,32 +220,36 @@
memset(buf, 0xFF, sizeof(buf));
padding_size = cert_chain_size - current_cert_chain_size;
- if(padding_size <0){
- fprintf(stderr, "ERROR: Input certificate chain (Size=%d) is larger than the maximum specified (Size=%d)\n",
+ if (padding_size < 0) {
+ fprintf(stderr,
+ "ERROR: Input certificate chain (Size=%d) is larger than the maximum specified (Size=%d)\n",
current_cert_chain_size, cert_chain_size);
return -1;
}
bytes_left = (padding_size > 0) ? padding_size : 0;
- while(bytes_left){
- if(!ferror(output_file))
- bytes_left -= fwrite(buf, sizeof(buf), buff_size, output_file);
- else{
- fprintf(stderr, "ERROR: Occured during certifcate chain padding\n");
+ while (bytes_left) {
+ if (!ferror(output_file))
+ bytes_left -=
+ fwrite(buf, sizeof(buf), buff_size,
+ output_file);
+ else {
+ fprintf(stderr,
+ "ERROR: Occured during certifcate chain padding\n");
return -1;
}
}
fclose(output_file);
//Concat and combine to signed image. Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -245,51 +259,53 @@
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Signature
- if((input_file = fopen(argv[7], "rb"))==NULL){
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[7], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Certifcate Chain
- if((input_file = fopen(argv[6], "rb"))==NULL){
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
- if(cat(input_file, output_file, (current_cert_chain_size + padding_size), buff_size))
+ if (cat
+ (input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
return -1;
fclose(input_file);
fclose(output_file);
- }else if(argc == 5 || argc == 6){
- FILE * input_file;
- FILE * output_file;
+ } else if (argc == 5 || argc == 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
//Concat and combine to unsigned image. Format [HDR][RAW APPSBOOT]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -299,12 +315,12 @@
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
fclose(output_file);
diff --git a/target/msm8660_surf/atags.c b/target/msm8660_surf/atags.c
index 3c4ab16..1d016d5 100644
--- a/target/msm8660_surf/atags.c
+++ b/target/msm8660_surf/atags.c
@@ -30,73 +30,68 @@
#include <debug.h>
#include <smem.h>
-#define SIZE_44M 0x02C00000 // 44M
+#define SIZE_44M 0x02C00000 // 44M
#define EBI1_ADDR_1026M 0x40200000
-#define SIZE_128M 0x08000000 // 128M
+#define SIZE_128M 0x08000000 // 128M
#define EBI1_ADDR_1152M 0x48000000
-#define SIZE_256M 0x10000000 // 256M
+#define SIZE_256M 0x10000000 // 256M
#define EBI1_ADDR_1280M 0x50000000
-#define SIZE_768M 0x30000000 // 256M + 512M
-#define SIZE_1792M 0x70000000 // 256M + 512M + 1G
+#define SIZE_768M 0x30000000 // 256M + 512M
+#define SIZE_1792M 0x70000000 // 256M + 512M + 1G
#define EBI1_CS1_ADDR_BASE 0x00A40024
-unsigned* target_atag_mem(unsigned* ptr)
+unsigned *target_atag_mem(unsigned *ptr)
{
- unsigned value = 0;
+ unsigned value = 0;
- /* ATAG_MEM */
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = SIZE_44M;
- *ptr++ = EBI1_ADDR_1026M;
+ /* ATAG_MEM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = SIZE_44M;
+ *ptr++ = EBI1_ADDR_1026M;
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = SIZE_128M;
- *ptr++ = EBI1_ADDR_1152M;
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = SIZE_128M;
+ *ptr++ = EBI1_ADDR_1152M;
- value = readl(EBI1_CS1_ADDR_BASE);
- value = (value >> 8) & 0xFF;
+ value = readl(EBI1_CS1_ADDR_BASE);
+ value = (value >> 8) & 0xFF;
- if (value == 0x50)
- {
- /* For 512MB RAM*/
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = SIZE_256M;
- *ptr++ = EBI1_ADDR_1280M;
- }
- else if (value == 0x60)
- {
- /* For 1GB RAM*/
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = SIZE_768M;
- *ptr++ = EBI1_ADDR_1280M;
- }
- else if (value == 0x80)
- {
- /* For 2GB RAM*/
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- //*ptr++ = SIZE_1792M;
- *ptr++ = SIZE_768M;
- *ptr++ = EBI1_ADDR_1280M;
- }
+ if (value == 0x50) {
+ /* For 512MB RAM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = SIZE_256M;
+ *ptr++ = EBI1_ADDR_1280M;
+ } else if (value == 0x60) {
+ /* For 1GB RAM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = SIZE_768M;
+ *ptr++ = EBI1_ADDR_1280M;
+ } else if (value == 0x80) {
+ /* For 2GB RAM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ //*ptr++ = SIZE_1792M;
+ *ptr++ = SIZE_768M;
+ *ptr++ = EBI1_ADDR_1280M;
+ }
- return ptr;
+ return ptr;
}
void *target_get_scratch_address(void)
{
- return ((void *)SCRATCH_ADDR);
+ return ((void *)SCRATCH_ADDR);
}
unsigned target_get_max_flash_size(void)
{
- return (192 * 1024 * 1024);
+ return (192 * 1024 * 1024);
}
diff --git a/target/msm8660_surf/init.c b/target/msm8660_surf/init.c
index 01a0c67..f1fa1b3 100644
--- a/target/msm8660_surf/init.c
+++ b/target/msm8660_surf/init.c
@@ -48,7 +48,7 @@
#include <platform/scm-io.h>
#include <platform/machtype.h>
-static const uint8_t uart_gsbi_id = GSBI_ID_12;
+static const uint8_t uart_gsbi_id = GSBI_ID_12;
void keypad_init(void);
extern void dmb(void);
@@ -56,7 +56,7 @@
int target_is_emmc_boot(void);
void debug_led_write(char);
char debug_led_read();
-uint32_t platform_id_read (void);
+uint32_t platform_id_read(void);
void setup_fpga(void);
int pm8901_reset_pwr_off(int reset);
int pm8058_reset_pwr_off(int reset);
@@ -64,30 +64,29 @@
static void target_shutdown_for_rtc_alarm(void);
void target_init(void)
{
- target_shutdown_for_rtc_alarm();
- dprintf(INFO, "target_init()\n");
+ target_shutdown_for_rtc_alarm();
+ dprintf(INFO, "target_init()\n");
- setup_fpga();
+ setup_fpga();
- /* Setting Debug LEDs ON */
- debug_led_write(0xFF);
+ /* Setting Debug LEDs ON */
+ debug_led_write(0xFF);
#if (!ENABLE_NANDWRITE)
keys_init();
keypad_init();
#endif
- /* Display splash screen if enabled */
+ /* Display splash screen if enabled */
#if DISPLAY_SPLASH_SCREEN
- display_init();
- dprintf(SPEW, "Diplay initialized\n");
- display_image_on_screen();
+ display_init();
+ dprintf(SPEW, "Diplay initialized\n");
+ display_image_on_screen();
#endif
- if(mmc_boot_main(MMC_SLOT,MSM_SDC1_BASE))
- {
- dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
+ if (mmc_boot_main(MMC_SLOT, MSM_SDC1_BASE)) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
}
unsigned board_machtype(void)
@@ -103,124 +102,115 @@
unsigned platform_subtype = 0;
static unsigned mach_id = 0xFFFFFFFF;
- if(mach_id != 0xFFFFFFFF)
+ if (mach_id != 0xFFFFFFFF)
return mach_id;
/* Detect external msm if this is a "fusion" */
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if (format == 5)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format == 5) {
board_info_len = sizeof(board_info_v5);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v5, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v5,
+ board_info_len);
+ if (!smem_status) {
fused_chip = board_info_v5.fused_chip;
id = board_info_v5.board_info_v3.hw_platform;
}
- }
- else if (format == 6)
- {
+ } else if (format == 6) {
board_info_len = sizeof(board_info_v6);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v6, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v6,
+ board_info_len);
+ if (!smem_status) {
fused_chip = board_info_v6.fused_chip;
id = board_info_v6.board_info_v3.hw_platform;
- platform_subtype = board_info_v6.platform_subtype;
+ platform_subtype =
+ board_info_v6.platform_subtype;
}
}
}
/* Detect SURF v/s FFA v/s Fluid */
- switch(id)
- {
- case 0x1:
- hw_platform = HW_PLATFORM_SURF;
- break;
- case 0x2:
- hw_platform = HW_PLATFORM_FFA;
- break;
- case 0x3:
- hw_platform = HW_PLATFORM_FLUID;
- break;
- case 0x6:
- hw_platform = HW_PLATFORM_QT;
- break;
- case 0xA:
- hw_platform = HW_PLATFORM_DRAGON;
- break;
- default:
- /* Writing to Debug LED register and reading back to auto detect
- SURF and FFA. If we read back, it is SURF */
- debug_led_write(0xA5);
+ switch (id) {
+ case 0x1:
+ hw_platform = HW_PLATFORM_SURF;
+ break;
+ case 0x2:
+ hw_platform = HW_PLATFORM_FFA;
+ break;
+ case 0x3:
+ hw_platform = HW_PLATFORM_FLUID;
+ break;
+ case 0x6:
+ hw_platform = HW_PLATFORM_QT;
+ break;
+ case 0xA:
+ hw_platform = HW_PLATFORM_DRAGON;
+ break;
+ default:
+ /* Writing to Debug LED register and reading back to auto detect
+ SURF and FFA. If we read back, it is SURF */
+ debug_led_write(0xA5);
- if((debug_led_read() & 0xFF) == 0xA5)
- {
- debug_led_write(0);
- hw_platform = HW_PLATFORM_SURF;
- }
- else
- hw_platform = HW_PLATFORM_FFA;
+ if ((debug_led_read() & 0xFF) == 0xA5) {
+ debug_led_write(0);
+ hw_platform = HW_PLATFORM_SURF;
+ } else
+ hw_platform = HW_PLATFORM_FFA;
};
/* Use platform_subtype or fused_chip information to determine machine id */
- if (format >= 6)
- {
- switch(platform_subtype)
- {
- case HW_PLATFORM_SUBTYPE_CSFB:
- case HW_PLATFORM_SUBTYPE_SVLTE2A:
- if (hw_platform == HW_PLATFORM_SURF)
- mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
- else if (hw_platform == HW_PLATFORM_FFA)
- mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
- break;
- default:
- if (hw_platform == HW_PLATFORM_SURF)
- mach_id = LINUX_MACHTYPE_8660_SURF;
- else if (hw_platform == HW_PLATFORM_FFA)
- mach_id = LINUX_MACHTYPE_8660_FFA;
- else if (hw_platform == HW_PLATFORM_FLUID)
- mach_id = LINUX_MACHTYPE_8660_FLUID;
- else if (hw_platform == HW_PLATFORM_QT)
- mach_id = LINUX_MACHTYPE_8660_QT;
- else if (hw_platform == HW_PLATFORM_DRAGON)
- mach_id = LINUX_MACHTYPE_8x60_DRAGON;
- }
- }
- else if (format == 5)
- {
- switch(fused_chip)
- {
- case UNKNOWN:
- if (hw_platform == HW_PLATFORM_SURF)
- mach_id = LINUX_MACHTYPE_8660_SURF;
- else if (hw_platform == HW_PLATFORM_FFA)
- mach_id = LINUX_MACHTYPE_8660_FFA;
- else if (hw_platform == HW_PLATFORM_FLUID)
- mach_id = LINUX_MACHTYPE_8660_FLUID;
- else if (hw_platform == HW_PLATFORM_QT)
- mach_id = LINUX_MACHTYPE_8660_QT;
- else if (hw_platform == HW_PLATFORM_DRAGON)
- mach_id = LINUX_MACHTYPE_8x60_DRAGON;
- break;
-
- case MDM9200:
- case MDM9600:
- if (hw_platform == HW_PLATFORM_SURF)
- mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
- else if (hw_platform == HW_PLATFORM_FFA)
- mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
- break;
-
- default:
+ if (format >= 6) {
+ switch (platform_subtype) {
+ case HW_PLATFORM_SUBTYPE_CSFB:
+ case HW_PLATFORM_SUBTYPE_SVLTE2A:
+ if (hw_platform == HW_PLATFORM_SURF)
+ mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
+ else if (hw_platform == HW_PLATFORM_FFA)
+ mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
+ break;
+ default:
+ if (hw_platform == HW_PLATFORM_SURF)
+ mach_id = LINUX_MACHTYPE_8660_SURF;
+ else if (hw_platform == HW_PLATFORM_FFA)
mach_id = LINUX_MACHTYPE_8660_FFA;
+ else if (hw_platform == HW_PLATFORM_FLUID)
+ mach_id = LINUX_MACHTYPE_8660_FLUID;
+ else if (hw_platform == HW_PLATFORM_QT)
+ mach_id = LINUX_MACHTYPE_8660_QT;
+ else if (hw_platform == HW_PLATFORM_DRAGON)
+ mach_id = LINUX_MACHTYPE_8x60_DRAGON;
+ }
+ } else if (format == 5) {
+ switch (fused_chip) {
+ case UNKNOWN:
+ if (hw_platform == HW_PLATFORM_SURF)
+ mach_id = LINUX_MACHTYPE_8660_SURF;
+ else if (hw_platform == HW_PLATFORM_FFA)
+ mach_id = LINUX_MACHTYPE_8660_FFA;
+ else if (hw_platform == HW_PLATFORM_FLUID)
+ mach_id = LINUX_MACHTYPE_8660_FLUID;
+ else if (hw_platform == HW_PLATFORM_QT)
+ mach_id = LINUX_MACHTYPE_8660_QT;
+ else if (hw_platform == HW_PLATFORM_DRAGON)
+ mach_id = LINUX_MACHTYPE_8x60_DRAGON;
+ break;
+
+ case MDM9200:
+ case MDM9600:
+ if (hw_platform == HW_PLATFORM_SURF)
+ mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
+ else if (hw_platform == HW_PLATFORM_FFA)
+ mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
+ break;
+
+ default:
+ mach_id = LINUX_MACHTYPE_8660_FFA;
}
}
@@ -240,26 +230,26 @@
void reboot_device(unsigned reboot_reason)
{
- /* Reset WDG0 counter */
- writel(1,MSM_WDT0_RST);
- /* Disable WDG0 */
- writel(0,MSM_WDT0_EN);
- /* Set WDG0 bark time */
- writel(0x31F3,MSM_WDT0_BT);
- /* Enable WDG0 */
- writel(3,MSM_WDT0_EN);
- dmb();
- /* Enable WDG output */
- secure_writel(3,MSM_TCSR_BASE + TCSR_WDOG_CFG);
- mdelay(10000);
- dprintf (CRITICAL, "Rebooting failed\n");
- return;
+ /* Reset WDG0 counter */
+ writel(1, MSM_WDT0_RST);
+ /* Disable WDG0 */
+ writel(0, MSM_WDT0_EN);
+ /* Set WDG0 bark time */
+ writel(0x31F3, MSM_WDT0_BT);
+ /* Enable WDG0 */
+ writel(3, MSM_WDT0_EN);
+ dmb();
+ /* Enable WDG output */
+ secure_writel(3, MSM_TCSR_BASE + TCSR_WDOG_CFG);
+ mdelay(10000);
+ dprintf(CRITICAL, "Rebooting failed\n");
+ return;
}
unsigned check_reboot_mode(void)
{
unsigned restart_reason = 0;
- void *restart_reason_addr = (void *) 0x2A05F65C;
+ void *restart_reason_addr = (void *)0x2A05F65C;
/* Read reboot reason and scrub it */
restart_reason = readl(restart_reason_addr);
@@ -274,44 +264,44 @@
void setup_fpga()
{
- writel(0x147, GPIO_CFG133_ADDR);
- writel(0x144, GPIO_CFG135_ADDR);
- writel(0x144, GPIO_CFG136_ADDR);
- writel(0x144, GPIO_CFG137_ADDR);
- writel(0x144, GPIO_CFG138_ADDR);
- writel(0x144, GPIO_CFG139_ADDR);
- writel(0x144, GPIO_CFG140_ADDR);
- writel(0x144, GPIO_CFG141_ADDR);
- writel(0x144, GPIO_CFG142_ADDR);
- writel(0x144, GPIO_CFG143_ADDR);
- writel(0x144, GPIO_CFG144_ADDR);
- writel(0x144, GPIO_CFG145_ADDR);
- writel(0x144, GPIO_CFG146_ADDR);
- writel(0x144, GPIO_CFG147_ADDR);
- writel(0x144, GPIO_CFG148_ADDR);
- writel(0x144, GPIO_CFG149_ADDR);
- writel(0x144, GPIO_CFG150_ADDR);
- writel(0x147, GPIO_CFG151_ADDR);
- writel(0x147, GPIO_CFG152_ADDR);
- writel(0x147, GPIO_CFG153_ADDR);
- writel(0x3, GPIO_CFG154_ADDR);
- writel(0x147, GPIO_CFG155_ADDR);
- writel(0x147, GPIO_CFG156_ADDR);
- writel(0x147, GPIO_CFG157_ADDR);
- writel(0x3, GPIO_CFG158_ADDR);
+ writel(0x147, GPIO_CFG133_ADDR);
+ writel(0x144, GPIO_CFG135_ADDR);
+ writel(0x144, GPIO_CFG136_ADDR);
+ writel(0x144, GPIO_CFG137_ADDR);
+ writel(0x144, GPIO_CFG138_ADDR);
+ writel(0x144, GPIO_CFG139_ADDR);
+ writel(0x144, GPIO_CFG140_ADDR);
+ writel(0x144, GPIO_CFG141_ADDR);
+ writel(0x144, GPIO_CFG142_ADDR);
+ writel(0x144, GPIO_CFG143_ADDR);
+ writel(0x144, GPIO_CFG144_ADDR);
+ writel(0x144, GPIO_CFG145_ADDR);
+ writel(0x144, GPIO_CFG146_ADDR);
+ writel(0x144, GPIO_CFG147_ADDR);
+ writel(0x144, GPIO_CFG148_ADDR);
+ writel(0x144, GPIO_CFG149_ADDR);
+ writel(0x144, GPIO_CFG150_ADDR);
+ writel(0x147, GPIO_CFG151_ADDR);
+ writel(0x147, GPIO_CFG152_ADDR);
+ writel(0x147, GPIO_CFG153_ADDR);
+ writel(0x3, GPIO_CFG154_ADDR);
+ writel(0x147, GPIO_CFG155_ADDR);
+ writel(0x147, GPIO_CFG156_ADDR);
+ writel(0x147, GPIO_CFG157_ADDR);
+ writel(0x3, GPIO_CFG158_ADDR);
- writel(0x00000B31, EBI2_CHIP_SELECT_CFG0);
- writel(0xA3030020, EBI2_XMEM_CS3_CFG1);
+ writel(0x00000B31, EBI2_CHIP_SELECT_CFG0);
+ writel(0xA3030020, EBI2_XMEM_CS3_CFG1);
}
void debug_led_write(char val)
{
- writeb(val,SURF_DEBUG_LED_ADDR);
+ writeb(val, SURF_DEBUG_LED_ADDR);
}
char debug_led_read()
{
- return readb(SURF_DEBUG_LED_ADDR);
+ return readb(SURF_DEBUG_LED_ADDR);
}
unsigned target_baseband()
@@ -324,42 +314,44 @@
unsigned baseband = BASEBAND_MSM;
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if (format == 5)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format == 5) {
board_info_len = sizeof(board_info_v5);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v5, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v5,
+ board_info_len);
+ if (!smem_status) {
/* Check for LTE fused targets or APQ. Default to MSM */
if (board_info_v5.fused_chip == MDM9200)
baseband = BASEBAND_CSFB;
else if (board_info_v5.fused_chip == MDM9600)
baseband = BASEBAND_SVLTE2A;
- else if (board_info_v5.board_info_v3.msm_id == APQ8060)
+ else if (board_info_v5.board_info_v3.msm_id ==
+ APQ8060)
baseband = BASEBAND_APQ;
else
baseband = BASEBAND_MSM;
}
- }
- else if (format >= 6)
- {
+ } else if (format >= 6) {
board_info_len = sizeof(board_info_v6);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v6, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v6,
+ board_info_len);
+ if (!smem_status) {
/* Check for LTE fused targets or APQ. Default to MSM */
- if (board_info_v6.platform_subtype == HW_PLATFORM_SUBTYPE_CSFB)
+ if (board_info_v6.platform_subtype ==
+ HW_PLATFORM_SUBTYPE_CSFB)
baseband = BASEBAND_CSFB;
- else if (board_info_v6.platform_subtype == HW_PLATFORM_SUBTYPE_SVLTE2A)
+ else if (board_info_v6.platform_subtype ==
+ HW_PLATFORM_SUBTYPE_SVLTE2A)
baseband = BASEBAND_SVLTE2A;
- else if (board_info_v6.board_info_v3.msm_id == APQ8060)
+ else if (board_info_v6.board_info_v3.msm_id ==
+ APQ8060)
baseband = BASEBAND_APQ;
else
baseband = BASEBAND_MSM;
@@ -376,21 +368,21 @@
unsigned smem_status;
smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
- &power_on_status, status_len);
+ &power_on_status, status_len);
- if (smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for power on reason\n");
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for power on reason\n");
}
- dprintf(INFO,"Power on reason %u\n", power_on_status);
+ dprintf(INFO, "Power on reason %u\n", power_on_status);
return power_on_status;
}
static void target_shutdown_for_rtc_alarm(void)
{
- if (target_check_power_on_reason() == PWR_ON_EVENT_RTC_ALARM)
- {
- dprintf(CRITICAL, "Power on due to RTC alarm. Going to shutdown!!\n");
+ if (target_check_power_on_reason() == PWR_ON_EVENT_RTC_ALARM) {
+ dprintf(CRITICAL,
+ "Power on due to RTC alarm. Going to shutdown!!\n");
pm8058_rtc0_alarm_irq_disable();
shutdown_device();
}
@@ -407,10 +399,9 @@
void target_serialno(unsigned char *buf)
{
unsigned int serialno;
- if(target_is_emmc_boot())
- {
- serialno = mmc_get_psn();
- snprintf((char *) buf, 13, "%x", serialno);
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
}
}
@@ -454,4 +445,3 @@
rc = _emmc_recovery_init();
return rc;
}
-
diff --git a/target/msm8660_surf/keypad.c b/target/msm8660_surf/keypad.c
index 246039e..bb1d38d 100644
--- a/target/msm8660_surf/keypad.c
+++ b/target/msm8660_surf/keypad.c
@@ -36,53 +36,53 @@
#define BITS_IN_ELEMENT(x) (sizeof(x)[0] * 8)
#define KEYMAP_INDEX(row, col) (row)* BITS_IN_ELEMENT(qwerty_keys_new) + (col)
-static unsigned char qwerty_keys_old[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-static unsigned char qwerty_keys_new[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+static unsigned char qwerty_keys_old[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+static unsigned char qwerty_keys_new[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
static unsigned int qt_keymap[] = {
- [KEYMAP_INDEX(0, 3)] = KEY_BACK, /* Volume down key */
- [KEYMAP_INDEX(1, 3)] = KEY_HOME, /* Volume up key */
+ [KEYMAP_INDEX(0, 3)] = KEY_BACK, /* Volume down key */
+ [KEYMAP_INDEX(1, 3)] = KEY_HOME, /* Volume up key */
};
static struct qwerty_keypad_info qt_keypad = {
- .keymap = qt_keymap,
- .old_keys = qwerty_keys_old,
- .rec_keys = qwerty_keys_new,
- .rows = 3,
- .columns = 1,
- .num_of_reads = 3,
- .rd_func = &pa1_ssbi2_read_bytes,
- .wr_func = &pa1_ssbi2_write_bytes,
- .settle_time = 32 /* msec */,
- .poll_time = 10 /* msec */,
+ .keymap = qt_keymap,
+ .old_keys = qwerty_keys_old,
+ .rec_keys = qwerty_keys_new,
+ .rows = 3,
+ .columns = 1,
+ .num_of_reads = 3,
+ .rd_func = &pa1_ssbi2_read_bytes,
+ .wr_func = &pa1_ssbi2_write_bytes,
+ .settle_time = 32 /* msec */ ,
+ .poll_time = 10 /* msec */ ,
};
static unsigned int qwerty_keymap[] = {
- [KEYMAP_INDEX(1, 3)] = KEY_BACK, /* Volume down key */
- [KEYMAP_INDEX(0, 3)] = KEY_HOME, /* Volume up key */
+ [KEYMAP_INDEX(1, 3)] = KEY_BACK, /* Volume down key */
+ [KEYMAP_INDEX(0, 3)] = KEY_HOME, /* Volume up key */
};
static struct qwerty_keypad_info qwerty_keypad = {
- .keymap = qwerty_keymap,
- .old_keys = qwerty_keys_old,
- .rec_keys = qwerty_keys_new,
- .rows = 6,
- .columns = 5,
- .num_of_reads = 6,
- .rd_func = &pa1_ssbi2_read_bytes,
- .wr_func = &pa1_ssbi2_write_bytes,
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
+ .keymap = qwerty_keymap,
+ .old_keys = qwerty_keys_old,
+ .rec_keys = qwerty_keys_new,
+ .rows = 6,
+ .columns = 5,
+ .num_of_reads = 6,
+ .rd_func = &pa1_ssbi2_read_bytes,
+ .wr_func = &pa1_ssbi2_write_bytes,
+ .settle_time = 5 /* msec */ ,
+ .poll_time = 20 /* msec */ ,
};
void keypad_init(void)
{
- unsigned int mach_id;
+ unsigned int mach_id;
- mach_id = board_machtype();
+ mach_id = board_machtype();
- if(mach_id == LINUX_MACHTYPE_8660_QT)
- ssbi_keypad_init(&qt_keypad);
- else
- ssbi_keypad_init(&qwerty_keypad);
+ if (mach_id == LINUX_MACHTYPE_8660_QT)
+ ssbi_keypad_init(&qt_keypad);
+ else
+ ssbi_keypad_init(&qwerty_keypad);
}
diff --git a/target/msm8660_surf/rules.mk b/target/msm8660_surf/rules.mk
old mode 100755
new mode 100644
diff --git a/target/msm8660_surf/tools/makefile b/target/msm8660_surf/tools/makefile
old mode 100755
new mode 100644
diff --git a/target/msm8660_surf/tools/mkheader.c b/target/msm8660_surf/tools/mkheader.c
old mode 100755
new mode 100644
index fda8b67..4ebdde9
--- a/target/msm8660_surf/tools/mkheader.c
+++ b/target/msm8660_surf/tools/mkheader.c
@@ -39,35 +39,46 @@
#include <sys/stat.h>
-int print_usage(){
- fprintf(stderr,"usage: mkheader <bin> <hdr> <none|unified-boot>\n");
- fprintf(stderr," mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
- fprintf(stderr,"bin: Input raw appsbl binary\n");
- fprintf(stderr,"hdr: Output of appsbl header location\n");
- fprintf(stderr,"outbin: Output of the signed or unsigned apps boot location\n");
- fprintf(stderr,"maxsize: Maximum size for certificate chain\n");
- fprintf(stderr,"certchain: Output of the certchain location\n");
- fprintf(stderr,"files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
- fprintf(stderr,"certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <unsecure-boot> <outbin>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize>\n");
+ fprintf(stderr,
+ " mkheader <bin> <hdr> <secure-boot> <outbin> <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate chain\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature> <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order to create the certificate chain\n\n");
return -1;
}
-int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size){
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
unsigned bytes_left = size;
char buf[buff_size];
int ret = 0;
- while(bytes_left){
+ while (bytes_left) {
fread(buf, sizeof(char), buff_size, in);
- if(!feof(in)){
+ if (!feof(in)) {
bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
- }else
+ } else
bytes_left = 0;
}
ret = ferror(in) | ferror(out);
- if(ret)
+ if (ret)
fprintf(stderr, "ERROR: Occured during file concatenation\n");
return ret;
}
@@ -86,43 +97,43 @@
int secure_boot = 0;
int fd;
- if(argc < 3) {
+ if (argc < 3) {
return print_usage();
}
if (argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
+ if (!strcmp("unified-boot", argv[3])) {
unified_boot = 1;
- }else if(!strcmp("secure-boot",argv[3])){
+ } else if (!strcmp("secure-boot", argv[3])) {
fprintf(stderr,
"ERROR: Missing arguments: [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
- }
- else if(!strcmp("unsecure-boot",argv[3])){
- fprintf(stderr,"ERROR: Missing arguments: outbin directory\n");
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr,
+ "ERROR: Missing arguments: outbin directory\n");
return print_usage();
}
}
if (argc > 4) {
- if(!strcmp("secure-boot",argv[3])) {
- if(argc < 9 && argc != 6){
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 6) {
fprintf(stderr,
"ERROR: Missing argument(s): [outbin maxsize] | [outbin, maxsize, certchain, signature + certifcate(s)]\n");
return print_usage();
- }
- secure_boot = 1;
- signature_size = 256; //Support SHA 256
+ }
+ secure_boot = 1;
+ signature_size = 256; //Support SHA 256
cert_chain_size = atoi(argv[5]);
- }
+ }
}
- if(stat(argv[1], &s)) {
+ if (stat(argv[1], &s)) {
perror("cannot stat binary");
return -1;
}
- if(unified_boot) {
+ if (unified_boot) {
magic = unified_boot_magic;
magic_len = sizeof(unified_boot_magic);
} else {
@@ -139,24 +150,23 @@
printf("Image Destination Pointer: 0x%x\n", base);
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000003; //Flash_partition_version /* nand */
- magic[2] = 0x00000000; //image source pointer
- magic[3] = base; //image destination pointer
- magic[4] = size + cert_chain_size + signature_size; //image size
- magic[5] = size; //code size
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
magic[6] = base + size;
magic[7] = signature_size;
magic[8] = size + base + signature_size;
magic[9] = cert_chain_size;
- if (unified_boot == 1)
- {
- magic[10] = 0x33836685; /* cookie magic number */
- magic[11] = 0x00000001; /* cookie version */
- magic[12] = 0x00000002; /* file formats */
+ if (unified_boot == 1) {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
magic[13] = 0x00000000;
- magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[14] = 0x00000000; /* not setting size for boot.img */
magic[15] = 0x00000000;
magic[16] = 0x00000000;
magic[17] = 0x00000000;
@@ -165,11 +175,11 @@
}
fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
+ if (fd < 0) {
perror("cannot open header for writing");
return -1;
}
- if(write(fd, magic, magic_len) != magic_len) {
+ if (write(fd, magic, magic_len) != magic_len) {
perror("cannot write header");
close(fd);
unlink(argv[2]);
@@ -177,9 +187,9 @@
}
close(fd);
- if (secure_boot && argc > 6){
- FILE * input_file;
- FILE * output_file;
+ if (secure_boot && argc > 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
unsigned bytes_left;
@@ -187,14 +197,14 @@
int padding_size = 0;
int i;
- if((output_file = fopen(argv[6], "wb"))==NULL){
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Certificate Chain Output File: %s\n", argv[6]);
- for (i = 8; i < argc; i++){
- if((input_file = fopen(argv[i], "rb"))==NULL){
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -210,32 +220,36 @@
memset(buf, 0xFF, sizeof(buf));
padding_size = cert_chain_size - current_cert_chain_size;
- if(padding_size <0){
- fprintf(stderr, "ERROR: Input certificate chain (Size=%d) is larger than the maximum specified (Size=%d)\n",
+ if (padding_size < 0) {
+ fprintf(stderr,
+ "ERROR: Input certificate chain (Size=%d) is larger than the maximum specified (Size=%d)\n",
current_cert_chain_size, cert_chain_size);
return -1;
}
bytes_left = (padding_size > 0) ? padding_size : 0;
- while(bytes_left){
- if(!ferror(output_file))
- bytes_left -= fwrite(buf, sizeof(buf), buff_size, output_file);
- else{
- fprintf(stderr, "ERROR: Occured during certifcate chain padding\n");
+ while (bytes_left) {
+ if (!ferror(output_file))
+ bytes_left -=
+ fwrite(buf, sizeof(buf), buff_size,
+ output_file);
+ else {
+ fprintf(stderr,
+ "ERROR: Occured during certifcate chain padding\n");
return -1;
}
}
fclose(output_file);
//Concat and combine to signed image. Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -245,51 +259,53 @@
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Signature
- if((input_file = fopen(argv[7], "rb"))==NULL){
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[7], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Certifcate Chain
- if((input_file = fopen(argv[6], "rb"))==NULL){
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
- if(cat(input_file, output_file, (current_cert_chain_size + padding_size), buff_size))
+ if (cat
+ (input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
return -1;
fclose(input_file);
fclose(output_file);
- }else if(argc == 5 || argc == 6){
- FILE * input_file;
- FILE * output_file;
+ } else if (argc == 5 || argc == 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
//Concat and combine to unsigned image. Format [HDR][RAW APPSBOOT]
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
@@ -299,12 +315,12 @@
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
fclose(output_file);
diff --git a/target/msm8960/atags.c b/target/msm8960/atags.c
index 0d5b4fb..c21634b 100644
--- a/target/msm8960/atags.c
+++ b/target/msm8960/atags.c
@@ -37,20 +37,17 @@
#define SIZE_256M (256 * SIZE_1M)
#define SIZE_512M (512 * SIZE_1M)
-unsigned* target_atag_mem(unsigned* ptr)
+unsigned *target_atag_mem(unsigned *ptr)
{
struct smem_ram_ptable ram_ptable;
uint8_t i = 0;
- if (smem_ram_ptable_init(&ram_ptable))
- {
- for (i = 0; i < ram_ptable.len; i++)
- {
+ if (smem_ram_ptable_init(&ram_ptable)) {
+ for (i = 0; i < ram_ptable.len; i++) {
/* Use only 141M from memory bank starting at 0x80000000 */
if (ram_ptable.parts[i].category == SDRAM &&
- ram_ptable.parts[i].type == SYS_MEMORY &&
- ram_ptable.parts[i].start == 0x80000000)
- {
+ ram_ptable.parts[i].type == SYS_MEMORY &&
+ ram_ptable.parts[i].start == 0x80000000) {
ASSERT(ram_ptable.parts[i].size >= SIZE_256M);
*ptr++ = 4;
@@ -58,29 +55,29 @@
*ptr++ = SIZE_141M;
*ptr++ = ram_ptable.parts[i].start + SIZE_2M;
- if (ram_ptable.parts[i].size > SIZE_256M)
- {
+ if (ram_ptable.parts[i].size > SIZE_256M) {
*ptr++ = 4;
*ptr++ = 0x54410002;
- *ptr++ = ram_ptable.parts[i].size - SIZE_256M;
- *ptr++ = ram_ptable.parts[i].start + SIZE_256M;
+ *ptr++ =
+ ram_ptable.parts[i].size -
+ SIZE_256M;
+ *ptr++ =
+ ram_ptable.parts[i].start +
+ SIZE_256M;
}
}
/* Pass along all other usable memory regions to Linux */
if (ram_ptable.parts[i].category == SDRAM &&
- ram_ptable.parts[i].type == SYS_MEMORY &&
- ram_ptable.parts[i].start != 0x80000000)
- {
+ ram_ptable.parts[i].type == SYS_MEMORY &&
+ ram_ptable.parts[i].start != 0x80000000) {
*ptr++ = 4;
*ptr++ = 0x54410002;
*ptr++ = ram_ptable.parts[i].size;
*ptr++ = ram_ptable.parts[i].start;
}
}
- }
- else
- {
+ } else {
dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
ASSERT(0);
}
@@ -90,7 +87,7 @@
void *target_get_scratch_address(void)
{
- return((void *)SCRATCH_ADDR);
+ return ((void *)SCRATCH_ADDR);
}
unsigned target_get_max_flash_size(void)
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index 0027422..8dee5ff 100644
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -71,15 +71,16 @@
extern void keypad_init(void);
extern void panel_backlight_on(void);
-static unsigned mmc_sdc_base[] = { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE};
+static unsigned mmc_sdc_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
static uint32_t platform_id;
static uint32_t target_id;
static pm8921_dev_t pmic;
-static void target_detect(void);
-static uint8_t get_uart_gsbi(void);
+static void target_detect(void);
+static uint8_t get_uart_gsbi(void);
void target_early_init(void)
{
@@ -99,7 +100,7 @@
writel(0, MSM_PSHOLD_CTL_SU);
mdelay(5000);
- dprintf (CRITICAL, "Shutdown failed.\n");
+ dprintf(CRITICAL, "Shutdown failed.\n");
}
void target_init(void)
@@ -110,8 +111,8 @@
dprintf(INFO, "target_init()\n");
/* Initialize PMIC driver */
- pmic.read = (pm8921_read_func) &pa1_ssbi2_read_bytes;
- pmic.write = (pm8921_write_func) &pa1_ssbi2_write_bytes;
+ pmic.read = (pm8921_read_func) & pa1_ssbi2_read_bytes;
+ pmic.write = (pm8921_write_func) & pa1_ssbi2_write_bytes;
pm8921_init(&pmic);
@@ -121,12 +122,11 @@
/* Display splash screen if enabled */
#if DISPLAY_SPLASH_SCREEN
- if((platform_id == MSM8960) || (platform_id == MSM8660A)
- || (platform_id == MSM8260A) || (platform_id == APQ8060A)
- || (platform_id == MSM8230) || (platform_id == MSM8630)
- || (platform_id == MSM8930) || (platform_id == APQ8030)
- || (platform_id == MSM8227) || (platform_id == MSM8627))
- {
+ if ((platform_id == MSM8960) || (platform_id == MSM8660A)
+ || (platform_id == MSM8260A) || (platform_id == APQ8060A)
+ || (platform_id == MSM8230) || (platform_id == MSM8630)
+ || (platform_id == MSM8930) || (platform_id == APQ8030)
+ || (platform_id == MSM8227) || (platform_id == MSM8627)) {
panel_backlight_on();
display_init();
dprintf(SPEW, "Diplay initialized\n");
@@ -136,14 +136,12 @@
/* Trying Slot 1 first */
slot = 1;
- base_addr = mmc_sdc_base[slot-1];
- if(mmc_boot_main(slot, base_addr))
- {
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
/* Trying Slot 3 next */
slot = 3;
- base_addr = mmc_sdc_base[slot-1];
- if(mmc_boot_main(slot, base_addr))
- {
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
}
@@ -155,7 +153,6 @@
return target_id;
}
-
void target_detect(void)
{
struct smem_board_info_v6 board_info_v6;
@@ -164,19 +161,17 @@
unsigned format = 0;
unsigned id = HW_PLATFORM_UNKNOWN;
-
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if (format == 6)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format == 6) {
board_info_len = sizeof(board_info_v6);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v6, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v6,
+ board_info_len);
+ if (!smem_status) {
id = board_info_v6.board_info_v3.hw_platform;
}
}
@@ -186,72 +181,60 @@
/* Detect the board we are running on */
if ((platform_id == MSM8960) || (platform_id == MSM8660A)
- || (platform_id == MSM8260A) || (platform_id == APQ8060A))
- {
- switch(id)
- {
- case HW_PLATFORM_SURF:
- target_id = LINUX_MACHTYPE_8960_CDP;
- break;
- case HW_PLATFORM_MTP:
- target_id = LINUX_MACHTYPE_8960_MTP;
- break;
- case HW_PLATFORM_FLUID:
- target_id = LINUX_MACHTYPE_8960_FLUID;
- break;
- case HW_PLATFORM_LIQUID:
- target_id = LINUX_MACHTYPE_8960_LIQUID;
- break;
- default:
- target_id = LINUX_MACHTYPE_8960_CDP;
+ || (platform_id == MSM8260A) || (platform_id == APQ8060A)) {
+ switch (id) {
+ case HW_PLATFORM_SURF:
+ target_id = LINUX_MACHTYPE_8960_CDP;
+ break;
+ case HW_PLATFORM_MTP:
+ target_id = LINUX_MACHTYPE_8960_MTP;
+ break;
+ case HW_PLATFORM_FLUID:
+ target_id = LINUX_MACHTYPE_8960_FLUID;
+ break;
+ case HW_PLATFORM_LIQUID:
+ target_id = LINUX_MACHTYPE_8960_LIQUID;
+ break;
+ default:
+ target_id = LINUX_MACHTYPE_8960_CDP;
}
- }
- else if ((platform_id == MSM8230) || (platform_id == MSM8630)
- || (platform_id == MSM8930) || (platform_id == APQ8030))
- {
- switch(id)
- {
- case HW_PLATFORM_SURF:
- target_id = LINUX_MACHTYPE_8930_CDP;
- break;
- case HW_PLATFORM_MTP:
- target_id = LINUX_MACHTYPE_8930_MTP;
- break;
- case HW_PLATFORM_FLUID:
- target_id = LINUX_MACHTYPE_8930_FLUID;
- break;
- default:
- target_id = LINUX_MACHTYPE_8930_CDP;
+ } else if ((platform_id == MSM8230) || (platform_id == MSM8630)
+ || (platform_id == MSM8930) || (platform_id == APQ8030)) {
+ switch (id) {
+ case HW_PLATFORM_SURF:
+ target_id = LINUX_MACHTYPE_8930_CDP;
+ break;
+ case HW_PLATFORM_MTP:
+ target_id = LINUX_MACHTYPE_8930_MTP;
+ break;
+ case HW_PLATFORM_FLUID:
+ target_id = LINUX_MACHTYPE_8930_FLUID;
+ break;
+ default:
+ target_id = LINUX_MACHTYPE_8930_CDP;
}
- }
- else if ((platform_id == MSM8227) || (platform_id == MSM8627))
- {
- switch(id)
- {
- case HW_PLATFORM_SURF:
- target_id = LINUX_MACHTYPE_8627_CDP;
- break;
- case HW_PLATFORM_MTP:
- target_id = LINUX_MACHTYPE_8627_MTP;
- break;
- default:
- target_id = LINUX_MACHTYPE_8627_CDP;
+ } else if ((platform_id == MSM8227) || (platform_id == MSM8627)) {
+ switch (id) {
+ case HW_PLATFORM_SURF:
+ target_id = LINUX_MACHTYPE_8627_CDP;
+ break;
+ case HW_PLATFORM_MTP:
+ target_id = LINUX_MACHTYPE_8627_MTP;
+ break;
+ default:
+ target_id = LINUX_MACHTYPE_8627_CDP;
}
- }
- else if (platform_id == APQ8064)
- {
- switch(id)
- {
- case HW_PLATFORM_SURF:
- target_id = LINUX_MACHTYPE_8064_SIM;
- break;
- default:
- target_id = LINUX_MACHTYPE_8064_RUMI3;
+ } else if (platform_id == APQ8064) {
+ switch (id) {
+ case HW_PLATFORM_SURF:
+ target_id = LINUX_MACHTYPE_8064_SIM;
+ break;
+ default:
+ target_id = LINUX_MACHTYPE_8064_RUMI3;
}
- }
- else
- {
- dprintf(CRITICAL, "platform_id (%d) is not identified.\n", platform_id);
+ } else {
+ dprintf(CRITICAL, "platform_id (%d) is not identified.\n",
+ platform_id);
ASSERT(0);
}
}
@@ -265,21 +248,22 @@
unsigned baseband = BASEBAND_MSM;
smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(!smem_status)
- {
- if (format >= 6)
- {
+ &format, sizeof(format), 0);
+ if (!smem_status) {
+ if (format >= 6) {
board_info_len = sizeof(board_info_v6);
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v6, board_info_len);
- if(!smem_status)
- {
+ smem_status =
+ smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
+ &board_info_v6,
+ board_info_len);
+ if (!smem_status) {
/* Check for MDM or APQ baseband variants. Default to MSM */
- if (board_info_v6.platform_subtype == HW_PLATFORM_SUBTYPE_MDM)
+ if (board_info_v6.platform_subtype ==
+ HW_PLATFORM_SUBTYPE_MDM)
baseband = BASEBAND_MDM;
- else if (board_info_v6.board_info_v3.msm_id == APQ8060)
+ else if (board_info_v6.board_info_v3.msm_id ==
+ APQ8060)
baseband = BASEBAND_APQ;
else
baseband = BASEBAND_MSM;
@@ -296,13 +280,13 @@
unsigned smem_status;
smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
- &power_on_status, status_len);
+ &power_on_status, status_len);
- if (smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for power on reason\n");
+ if (smem_status) {
+ dprintf(CRITICAL,
+ "ERROR: unable to read shared memory for power on reason\n");
}
- dprintf(INFO,"Power on reason %u\n", power_on_status);
+ dprintf(INFO, "Power on reason %u\n", power_on_status);
return power_on_status;
}
@@ -315,7 +299,7 @@
writel(0, MSM_PSHOLD_CTL_SU);
mdelay(10000);
- dprintf (CRITICAL, "PSHOLD failed, trying watchdog reset\n");
+ dprintf(CRITICAL, "PSHOLD failed, trying watchdog reset\n");
writel(1, MSM_WDT0_RST);
writel(0, MSM_WDT0_EN);
writel(0x31F3, MSM_WDT0_BT);
@@ -324,7 +308,7 @@
writel(3, MSM_TCSR_BASE + TCSR_WDOG_CFG);
mdelay(10000);
- dprintf (CRITICAL, "Rebooting failed\n");
+ dprintf(CRITICAL, "Rebooting failed\n");
}
unsigned check_reboot_mode(void)
@@ -349,10 +333,9 @@
void target_serialno(unsigned char *buf)
{
unsigned int serialno;
- if(target_is_emmc_boot())
- {
- serialno = mmc_get_psn();
- snprintf((char *) buf, 13, "%x", serialno);
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
}
}
@@ -369,38 +352,37 @@
uint8_t get_uart_gsbi(void)
{
- switch(target_id)
- {
- case LINUX_MACHTYPE_8960_SIM:
- case LINUX_MACHTYPE_8960_RUMI3:
- case LINUX_MACHTYPE_8960_CDP:
- case LINUX_MACHTYPE_8960_MTP:
- case LINUX_MACHTYPE_8960_FLUID:
- case LINUX_MACHTYPE_8960_APQ:
- case LINUX_MACHTYPE_8960_LIQUID:
+ switch (target_id) {
+ case LINUX_MACHTYPE_8960_SIM:
+ case LINUX_MACHTYPE_8960_RUMI3:
+ case LINUX_MACHTYPE_8960_CDP:
+ case LINUX_MACHTYPE_8960_MTP:
+ case LINUX_MACHTYPE_8960_FLUID:
+ case LINUX_MACHTYPE_8960_APQ:
+ case LINUX_MACHTYPE_8960_LIQUID:
- return GSBI_ID_5;
+ return GSBI_ID_5;
- case LINUX_MACHTYPE_8930_CDP:
- case LINUX_MACHTYPE_8930_MTP:
- case LINUX_MACHTYPE_8930_FLUID:
+ case LINUX_MACHTYPE_8930_CDP:
+ case LINUX_MACHTYPE_8930_MTP:
+ case LINUX_MACHTYPE_8930_FLUID:
- return GSBI_ID_5;
+ return GSBI_ID_5;
- case LINUX_MACHTYPE_8064_SIM:
- case LINUX_MACHTYPE_8064_RUMI3:
+ case LINUX_MACHTYPE_8064_SIM:
+ case LINUX_MACHTYPE_8064_RUMI3:
- return GSBI_ID_3;
+ return GSBI_ID_3;
- case LINUX_MACHTYPE_8627_CDP:
- case LINUX_MACHTYPE_8627_MTP:
+ case LINUX_MACHTYPE_8627_CDP:
+ case LINUX_MACHTYPE_8627_MTP:
- return GSBI_ID_5;
+ return GSBI_ID_5;
- default:
- dprintf(CRITICAL, "uart gsbi not defined for target: %d\n",
- target_id);
+ default:
+ dprintf(CRITICAL, "uart gsbi not defined for target: %d\n",
+ target_id);
- ASSERT(0);
+ ASSERT(0);
}
}
diff --git a/target/msm8960/keypad.c b/target/msm8960/keypad.c
old mode 100755
new mode 100644
index 5cc0b87..4015170
--- a/target/msm8960/keypad.c
+++ b/target/msm8960/keypad.c
@@ -43,22 +43,21 @@
#define KEYMAP_INDEX(row, col) (row)* BITS_IN_ELEMENT(qwerty_keys_new) + (col)
unsigned int qwerty_keymap[] = {
- [KEYMAP_INDEX(0, 0)] = KEY_VOLUMEUP, /* Volume key on the device/CDP */
- [KEYMAP_INDEX(0, 1)] = KEY_VOLUMEDOWN, /* Volume key on the device/CDP */
+ [KEYMAP_INDEX(0, 0)] = KEY_VOLUMEUP, /* Volume key on the device/CDP */
+ [KEYMAP_INDEX(0, 1)] = KEY_VOLUMEDOWN, /* Volume key on the device/CDP */
};
-
struct qwerty_keypad_info qwerty_keypad = {
- .keymap = qwerty_keymap,
- .old_keys = qwerty_keys_old,
- .rec_keys = qwerty_keys_new,
- .rows = NUM_OF_ROWS,
- .columns = NUM_OF_COLS,
- .num_of_reads = NUM_OF_ROWS,
- .rd_func = &pa1_ssbi2_read_bytes,
- .wr_func = &pa1_ssbi2_write_bytes,
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
+ .keymap = qwerty_keymap,
+ .old_keys = qwerty_keys_old,
+ .rec_keys = qwerty_keys_new,
+ .rows = NUM_OF_ROWS,
+ .columns = NUM_OF_COLS,
+ .num_of_reads = NUM_OF_ROWS,
+ .rd_func = &pa1_ssbi2_read_bytes,
+ .wr_func = &pa1_ssbi2_write_bytes,
+ .settle_time = 5 /* msec */ ,
+ .poll_time = 20 /* msec */ ,
};
void keypad_init(void)
diff --git a/target/msm8960/panel.c b/target/msm8960/panel.c
index 6f8128c..924b310 100644
--- a/target/msm8960/panel.c
+++ b/target/msm8960/panel.c
@@ -37,240 +37,261 @@
void panel_backlight_on(void)
{
- struct pm8921_gpio backlight_pwm = {
- .direction = PM_GPIO_DIR_OUT,
- .output_buffer = 0,
- .output_value = 0,
- .pull = PM_GPIO_PULL_NO,
- .vin_sel = 2,
- .out_strength = PM_GPIO_STRENGTH_HIGH,
- .function = PM_GPIO_FUNC_1,
- .inv_int_pol = 0,
- };
+ struct pm8921_gpio backlight_pwm = {
+ .direction = PM_GPIO_DIR_OUT,
+ .output_buffer = 0,
+ .output_value = 0,
+ .pull = PM_GPIO_PULL_NO,
+ .vin_sel = 2,
+ .out_strength = PM_GPIO_STRENGTH_HIGH,
+ .function = PM_GPIO_FUNC_1,
+ .inv_int_pol = 0,
+ };
- int rc = pm8921_gpio_config(PM_GPIO(24), &backlight_pwm);
- if (rc) {
- dprintf(CRITICAL, "FAIL pm8921_gpio_config(): rc=%d.\n", rc);
- }
+ int rc = pm8921_gpio_config(PM_GPIO(24), &backlight_pwm);
+ if (rc) {
+ dprintf(CRITICAL, "FAIL pm8921_gpio_config(): rc=%d.\n", rc);
+ }
}
/* Pull DISP_RST_N high to get panel out of reset */
-void mipi_panel_reset(void){
+void mipi_panel_reset(void)
+{
- struct pm8921_gpio gpio43_param = {
- .direction = PM_GPIO_DIR_OUT,
- .output_buffer = 0,
- .output_value = 1,
- .pull = PM_GPIO_PULL_UP_30,
- .vin_sel = 2,
- .out_strength = PM_GPIO_STRENGTH_HIGH,
- .function = PM_GPIO_FUNC_PAIRED,
- .inv_int_pol = 0,
- .disable_pin = 0,
- };
- pm8921_gpio_config(PM_GPIO(43), &gpio43_param);
+ struct pm8921_gpio gpio43_param = {
+ .direction = PM_GPIO_DIR_OUT,
+ .output_buffer = 0,
+ .output_value = 1,
+ .pull = PM_GPIO_PULL_UP_30,
+ .vin_sel = 2,
+ .out_strength = PM_GPIO_STRENGTH_HIGH,
+ .function = PM_GPIO_FUNC_PAIRED,
+ .inv_int_pol = 0,
+ .disable_pin = 0,
+ };
+ pm8921_gpio_config(PM_GPIO(43), &gpio43_param);
}
-void mipi_dsi_panel_power_on(void){
+void mipi_dsi_panel_power_on(void)
+{
- /* Turn on LDO8 for lcd1 mipi vdd */
- pm8921_ldo_set_voltage(LDO_8, LDO_VOLTAGE_3_0V);
+ /* Turn on LDO8 for lcd1 mipi vdd */
+ pm8921_ldo_set_voltage(LDO_8, LDO_VOLTAGE_3_0V);
- /* Turn on LDO23 for lcd1 mipi vddio */
- pm8921_ldo_set_voltage(LDO_23, LDO_VOLTAGE_1_8V);
+ /* Turn on LDO23 for lcd1 mipi vddio */
+ pm8921_ldo_set_voltage(LDO_23, LDO_VOLTAGE_1_8V);
- /* Turn on LDO2 for vdda_mipi_dsi */
- pm8921_ldo_set_voltage(LDO_2, LDO_VOLTAGE_1_2V);
+ /* Turn on LDO2 for vdda_mipi_dsi */
+ pm8921_ldo_set_voltage(LDO_2, LDO_VOLTAGE_1_2V);
}
static void mipi_dsi_calibration(void)
{
- uint32_t i = 0;
- uint32_t term_cnt = 5000;
- int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ uint32_t i = 0;
+ uint32_t term_cnt = 5000;
+ int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550);
- /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */
- writel(0x01, MIPI_DSI_BASE + 0x0518);
+ /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */
+ writel(0x01, MIPI_DSI_BASE + 0x0518);
- /* DSI1_DSIPHY_CAL_SW_CFG2 */
- writel(0x0, MIPI_DSI_BASE + 0x0534);
- /* DSI1_DSIPHY_CAL_HW_CFG1 */
- writel(0x5a, MIPI_DSI_BASE + 0x053c);
- /* DSI1_DSIPHY_CAL_HW_CFG3 */
- writel(0x10, MIPI_DSI_BASE + 0x0544);
- /* DSI1_DSIPHY_CAL_HW_CFG4 */
- writel(0x01, MIPI_DSI_BASE + 0x0548);
- /* DSI1_DSIPHY_CAL_HW_CFG0 */
- writel(0x01, MIPI_DSI_BASE + 0x0538);
+ /* DSI1_DSIPHY_CAL_SW_CFG2 */
+ writel(0x0, MIPI_DSI_BASE + 0x0534);
+ /* DSI1_DSIPHY_CAL_HW_CFG1 */
+ writel(0x5a, MIPI_DSI_BASE + 0x053c);
+ /* DSI1_DSIPHY_CAL_HW_CFG3 */
+ writel(0x10, MIPI_DSI_BASE + 0x0544);
+ /* DSI1_DSIPHY_CAL_HW_CFG4 */
+ writel(0x01, MIPI_DSI_BASE + 0x0548);
+ /* DSI1_DSIPHY_CAL_HW_CFG0 */
+ writel(0x01, MIPI_DSI_BASE + 0x0538);
- /* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x01, MIPI_DSI_BASE + 0x0528);
+ /* DSI1_DSIPHY_CAL_HW_TRIGGER */
+ writel(0x01, MIPI_DSI_BASE + 0x0528);
- /* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x00, MIPI_DSI_BASE + 0x0528);
+ /* DSI1_DSIPHY_CAL_HW_TRIGGER */
+ writel(0x00, MIPI_DSI_BASE + 0x0528);
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
- while (cal_busy & 0x10) {
- i++;
- if (i > term_cnt) {
- dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY,"
- "exceeded polling TIMEOUT!\n");
- break;
- }
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
- }
+ cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ while (cal_busy & 0x10) {
+ i++;
+ if (i > term_cnt) {
+ dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY,"
+ "exceeded polling TIMEOUT!\n");
+ break;
+ }
+ cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ }
}
-int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo){
- struct mipi_dsi_phy_ctrl *pd;
- uint32_t i, off = 0;
+int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
+{
+ struct mipi_dsi_phy_ctrl *pd;
+ uint32_t i, off = 0;
- writel(0x0001, MIPI_DSI_BASE + 0x128);/* start phy sw reset */
- writel(0x0000, MIPI_DSI_BASE + 0x128);/* end phy w reset */
- writel(0x0003, MIPI_DSI_BASE + 0x500);/* regulator_ctrl_0 */
- writel(0x0001, MIPI_DSI_BASE + 0x504);/* regulator_ctrl_1 */
- writel(0x0001, MIPI_DSI_BASE + 0x508);/* regulator_ctrl_2 */
- writel(0x0000, MIPI_DSI_BASE + 0x50c);/* regulator_ctrl_3 */
- writel(0x0100, MIPI_DSI_BASE + 0x510);/* regulator_ctrl_4 */
+ writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */
+ writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */
+ writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */
+ writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */
+ writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */
+ writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */
+ writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */
- pd = (pinfo->dsi_phy_config);
+ pd = (pinfo->dsi_phy_config);
- off = 0x0480; /* strength 0 - 2 */
- for (i = 0; i < 3; i++) {
- writel(pd->strength[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0480; /* strength 0 - 2 */
+ for (i = 0; i < 3; i++) {
+ writel(pd->strength[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- off = 0x0470; /* ctrl 0 - 3 */
- for (i = 0; i < 4; i++) {
- writel(pd->ctrl[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0470; /* ctrl 0 - 3 */
+ for (i = 0; i < 4; i++) {
+ writel(pd->ctrl[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- off = 0x0500; /* regulator ctrl 0 - 4 */
- for (i = 0; i < 5; i++) {
- writel(pd->regulator[i], MIPI_DSI_BASE + off);
- off += 4;
- }
- mipi_dsi_calibration();
+ off = 0x0500; /* regulator ctrl 0 - 4 */
+ for (i = 0; i < 5; i++) {
+ writel(pd->regulator[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
+ mipi_dsi_calibration();
- off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
- for (i = 1; i < 20; i++) {
- writel(pd->pll[i], MIPI_DSI_BASE + off);
- off += 4;
- }
+ off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
+ for (i = 1; i < 20; i++) {
+ writel(pd->pll[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
- /* pll ctrl 0 */
- writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
- writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
+ /* pll ctrl 0 */
+ writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
+ writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
- /* Check that PHY is ready */
- while(!(readl(DSIPHY_PLL_RDY) & 0x01));
+ /* Check that PHY is ready */
+ while (!(readl(DSIPHY_PLL_RDY) & 0x01)) ;
- writel(0x202D, DSI_CLKOUT_TIMING_CTRL);
+ writel(0x202D, DSI_CLKOUT_TIMING_CTRL);
- off = 0x0440; /* phy timing ctrl 0 - 11 */
- for (i = 0; i < 12; i++) {
- writel(pd->timing[i], MIPI_DSI_BASE + off);
- off += 4;
- }
- return 0;
+ off = 0x0440; /* phy timing ctrl 0 - 11 */
+ for (i = 0; i < 12; i++) {
+ writel(pd->timing[i], MIPI_DSI_BASE + off);
+ off += 4;
+ }
+ return 0;
}
/* Calculations specific for the Toshiba MDT61 Panel */
-void mdp_setup_mdt61_video_dsi_config(void){
- unsigned long hsync_period;
- unsigned long vsync_period;
+void mdp_setup_mdt61_video_dsi_config(void)
+{
+ unsigned long hsync_period;
+ unsigned long vsync_period;
- /* For MDT61 display width is 200 more than image width */
- hsync_period = TSH_MDT61_DISPLAY_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK
- + MIPI_HSYNC_FRONT_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH;
+ /* For MDT61 display width is 200 more than image width */
+ hsync_period = TSH_MDT61_DISPLAY_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK
+ + MIPI_HSYNC_FRONT_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH;
- vsync_period = (TSH_MDT61_MIPI_FB_HEIGHT + MIPI_VSYNC_BACK_PORCH_LINES
- + MIPI_VSYNC_FRONT_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH) * hsync_period;
+ vsync_period = (TSH_MDT61_MIPI_FB_HEIGHT + MIPI_VSYNC_BACK_PORCH_LINES
+ + MIPI_VSYNC_FRONT_PORCH_LINES +
+ MIPI_VSYNC_PULSE_WIDTH) * hsync_period;
- writel(hsync_period<<16 | MIPI_HSYNC_PULSE_WIDTH<<0, MDP_DSI_VIDEO_HSYNC_CTL);
- writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
- writel(MIPI_VSYNC_PULSE_WIDTH * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- writel((MIPI_HSYNC_BACK_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH + TSH_MDT61_DISPLAY_WIDTH - 1)<<16 |
- (MIPI_HSYNC_BACK_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH), MDP_DSI_VIDEO_DISPLAY_HCTL);
- writel(hsync_period * (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH),
- MDP_DSI_VIDEO_DISPLAY_V_START);
- writel(hsync_period *
- (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH + TSH_MDT61_MIPI_FB_HEIGHT) - 1,
- MDP_DSI_VIDEO_DISPLAY_V_END);
+ writel(hsync_period << 16 | MIPI_HSYNC_PULSE_WIDTH << 0,
+ MDP_DSI_VIDEO_HSYNC_CTL);
+ writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
+ writel(MIPI_VSYNC_PULSE_WIDTH * hsync_period,
+ MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
+ writel((MIPI_HSYNC_BACK_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH +
+ TSH_MDT61_DISPLAY_WIDTH -
+ 1) << 16 | (MIPI_HSYNC_BACK_PORCH_DCLK +
+ MIPI_HSYNC_PULSE_WIDTH),
+ MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel(hsync_period *
+ (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH),
+ MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel(hsync_period *
+ (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH +
+ TSH_MDT61_MIPI_FB_HEIGHT) - 1, MDP_DSI_VIDEO_DISPLAY_V_END);
- /* Special Case for Toshiba 4in Panel */
- writel((1<<31) |
- (MIPI_HSYNC_BACK_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH + TSH_MDT61_MIPI_FB_WIDTH - 1)<<16 |
- MIPI_HSYNC_PULSE_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK, MDP_DSI_VIDEO_ACTIVE_HCTL);
- writel(1<<31 | hsync_period * (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH),
- MDP_DSI_VIDEO_DISPLAY_V_START);
- writel((TSH_MDT61_MIPI_FB_HEIGHT + MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH) *
- hsync_period - 1, MDP_DSI_VIDEO_DISPLAY_V_END);
+ /* Special Case for Toshiba 4in Panel */
+ writel((1 << 31) |
+ (MIPI_HSYNC_BACK_PORCH_DCLK + MIPI_HSYNC_PULSE_WIDTH +
+ TSH_MDT61_MIPI_FB_WIDTH - 1) << 16 | MIPI_HSYNC_PULSE_WIDTH +
+ MIPI_HSYNC_BACK_PORCH_DCLK, MDP_DSI_VIDEO_ACTIVE_HCTL);
+ writel(1 << 31 | hsync_period *
+ (MIPI_VSYNC_BACK_PORCH_LINES + MIPI_VSYNC_PULSE_WIDTH),
+ MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel((TSH_MDT61_MIPI_FB_HEIGHT + MIPI_VSYNC_BACK_PORCH_LINES +
+ MIPI_VSYNC_PULSE_WIDTH) * hsync_period - 1,
+ MDP_DSI_VIDEO_DISPLAY_V_END);
- writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
+ writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
}
void config_mdt61_dsi_video_mode(void)
{
- unsigned char dst_format = 3; /* RGB888 */
- unsigned char traffic_mode = 1; /* non burst mode with sync start events */
- unsigned char lane_en = 7; /* 3 Lanes -- Enables Data Lane0, 1, 2 */
- unsigned long low_pwr_stop_mode = 0;
- unsigned char eof_bllp_pwr = 0x8; /* Needed or else will have blank line at top of display */
- unsigned char interleav = 0;
+ unsigned char dst_format = 3; /* RGB888 */
+ unsigned char traffic_mode = 1; /* non burst mode with sync start events */
+ unsigned char lane_en = 7; /* 3 Lanes -- Enables Data Lane0, 1, 2 */
+ unsigned long low_pwr_stop_mode = 0;
+ unsigned char eof_bllp_pwr = 0x8; /* Needed or else will have blank line at top of display */
+ unsigned char interleav = 0;
- dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n");
- dprintf(SPEW, "Data Lane: 3 lane\n");
- dprintf(SPEW, "Traffic mode: non burst mode with sync start events\n");
+ dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB888\n");
+ dprintf(SPEW, "Data Lane: 3 lane\n");
+ dprintf(SPEW, "Traffic mode: non burst mode with sync start events\n");
- writel(0x00000000, MDP_DSI_VIDEO_EN);
+ writel(0x00000000, MDP_DSI_VIDEO_EN);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000002, DSI_CLK_CTRL);
- writel(0x00000006, DSI_CLK_CTRL);
- writel(0x0000000e, DSI_CLK_CTRL);
- writel(0x0000001e, DSI_CLK_CTRL);
- writel(0x0000003e, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000000, DSI_CLK_CTRL);
+ writel(0x00000002, DSI_CLK_CTRL);
+ writel(0x00000006, DSI_CLK_CTRL);
+ writel(0x0000000e, DSI_CLK_CTRL);
+ writel(0x0000001e, DSI_CLK_CTRL);
+ writel(0x0000003e, DSI_CLK_CTRL);
- writel(0, DSI_CTRL);
+ writel(0, DSI_CTRL);
- writel(0, DSI_ERR_INT_MASK0);
+ writel(0, DSI_ERR_INT_MASK0);
- writel(0x02020202, DSI_INT_CTRL);
+ writel(0x02020202, DSI_INT_CTRL);
- writel((MIPI_HSYNC_PULSE_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK + TSH_MDT61_DISPLAY_WIDTH)<<16 |
- (MIPI_HSYNC_PULSE_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK), DSI_VIDEO_MODE_ACTIVE_H);
+ writel((MIPI_HSYNC_PULSE_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK +
+ TSH_MDT61_DISPLAY_WIDTH) << 16 | (MIPI_HSYNC_PULSE_WIDTH +
+ MIPI_HSYNC_BACK_PORCH_DCLK),
+ DSI_VIDEO_MODE_ACTIVE_H);
- writel((MIPI_VSYNC_PULSE_WIDTH + MIPI_VSYNC_BACK_PORCH_LINES + TSH_MDT61_MIPI_FB_HEIGHT)<<16 |
- (MIPI_VSYNC_PULSE_WIDTH + MIPI_VSYNC_BACK_PORCH_LINES), DSI_VIDEO_MODE_ACTIVE_V);
+ writel((MIPI_VSYNC_PULSE_WIDTH + MIPI_VSYNC_BACK_PORCH_LINES +
+ TSH_MDT61_MIPI_FB_HEIGHT) << 16 | (MIPI_VSYNC_PULSE_WIDTH +
+ MIPI_VSYNC_BACK_PORCH_LINES),
+ DSI_VIDEO_MODE_ACTIVE_V);
- writel((MIPI_VSYNC_PULSE_WIDTH + MIPI_VSYNC_BACK_PORCH_LINES + TSH_MDT61_MIPI_FB_HEIGHT +
- MIPI_VSYNC_FRONT_PORCH_LINES - 1)<<16 |
- (MIPI_HSYNC_PULSE_WIDTH + MIPI_HSYNC_BACK_PORCH_DCLK + TSH_MDT61_DISPLAY_WIDTH +
- MIPI_HSYNC_FRONT_PORCH_DCLK - 1), DSI_VIDEO_MODE_TOTAL);
+ writel((MIPI_VSYNC_PULSE_WIDTH + MIPI_VSYNC_BACK_PORCH_LINES +
+ TSH_MDT61_MIPI_FB_HEIGHT + MIPI_VSYNC_FRONT_PORCH_LINES -
+ 1) << 16 | (MIPI_HSYNC_PULSE_WIDTH +
+ MIPI_HSYNC_BACK_PORCH_DCLK +
+ TSH_MDT61_DISPLAY_WIDTH +
+ MIPI_HSYNC_FRONT_PORCH_DCLK - 1),
+ DSI_VIDEO_MODE_TOTAL);
- writel((MIPI_HSYNC_PULSE_WIDTH)<<16 | 0, DSI_VIDEO_MODE_HSYNC);
+ writel((MIPI_HSYNC_PULSE_WIDTH) << 16 | 0, DSI_VIDEO_MODE_HSYNC);
- writel(0<<16 | 0, DSI_VIDEO_MODE_VSYNC);
+ writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
- writel(MIPI_VSYNC_PULSE_WIDTH<<16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
+ writel(MIPI_VSYNC_PULSE_WIDTH << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
- writel(1, DSI_EOT_PACKET_CTRL);
+ writel(1, DSI_EOT_PACKET_CTRL);
- writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | traffic_mode << 8
- | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
+ writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | traffic_mode << 8
+ | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
- writel(0x00010100, DSI_INT_CTRL);
- writel(0x02010202, DSI_INT_CTRL);
- writel(0x02030303, DSI_INT_CTRL);
+ writel(0x00010100, DSI_INT_CTRL);
+ writel(0x02010202, DSI_INT_CTRL);
+ writel(0x02030303, DSI_INT_CTRL);
- writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
- | 0x103, DSI_CTRL);
+ writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
+ | 0x103, DSI_CTRL);
}
diff --git a/target/msm8960/tools/mkheader.c b/target/msm8960/tools/mkheader.c
index cd11810..8c29f9c 100644
--- a/target/msm8960/tools/mkheader.c
+++ b/target/msm8960/tools/mkheader.c
@@ -39,43 +39,49 @@
#include <sys/stat.h>
-int print_usage(){
- fprintf(stderr,"usage: mkheader <bin> <hdr> <none|unified-boot>\n");
- fprintf(stderr," mkheader <bin> <hdr> <unsecure-boot>"
- " <outbin>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin>"
- " <maxsize>\n");
- fprintf(stderr," mkheader <bin> <hdr> <secure-boot> <outbin>"
- " <maxsize> <certchain> <files...>\n\n");
- fprintf(stderr,"bin: Input raw appsbl binary\n");
- fprintf(stderr,"hdr: Output of appsbl header location\n");
- fprintf(stderr,"outbin: Output of the signed or unsigned"
- " apps boot location\n");
- fprintf(stderr,"maxsize: Maximum size for certificate"
- " chain\n");
- fprintf(stderr,"certchain: Output of the certchain location\n");
- fprintf(stderr,"files: Input format <bin signature>"
- " <certifcate file(s) for certificate chain>...\n");
- fprintf(stderr,"certificate chain: Files will be concatenated in order"
- " to create the certificate chain\n\n");
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <unsecure-boot>"
+ " <outbin>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned"
+ " apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate" " chain\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature>"
+ " <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order"
+ " to create the certificate chain\n\n");
return -1;
}
-int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size){
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
unsigned bytes_left = size;
char buf[buff_size];
int ret = 0;
- while(bytes_left){
+ while (bytes_left) {
fread(buf, sizeof(char), buff_size, in);
- if(!feof(in)){
+ if (!feof(in)) {
bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
- }
- else
+ } else
bytes_left = 0;
}
ret = ferror(in) | ferror(out);
- if(ret)
+ if (ret)
fprintf(stderr, "ERROR: Occured during file concatenation\n");
return ret;
}
@@ -94,31 +100,29 @@
int secure_boot = 0;
int fd;
- if(argc < 3) {
+ if (argc < 3) {
return print_usage();
}
- if(argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
+ if (argc == 4) {
+ if (!strcmp("unified-boot", argv[3])) {
unified_boot = 1;
- }
- else if(!strcmp("secure-boot",argv[3])){
+ } else if (!strcmp("secure-boot", argv[3])) {
fprintf(stderr,
"ERROR: Missing arguments: [outbin maxsize] |"
" [outbin, maxsize, certchain,"
" signature + certifcate(s)]\n");
return print_usage();
- }
- else if(!strcmp("unsecure-boot",argv[3])){
- fprintf(stderr,"ERROR: Missing arguments:"
- " outbin directory\n");
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr, "ERROR: Missing arguments:"
+ " outbin directory\n");
return print_usage();
}
}
- if(argc > 4) {
- if(!strcmp("secure-boot",argv[3])) {
- if(argc < 9 && argc != 6){
+ if (argc > 4) {
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 6) {
fprintf(stderr,
"ERROR: Missing argument(s):"
" [outbin maxsize] | [outbin, maxsize,"
@@ -127,21 +131,20 @@
return print_usage();
}
secure_boot = 1;
- signature_size = 256; //Support SHA 256
+ signature_size = 256; //Support SHA 256
cert_chain_size = atoi(argv[5]);
}
}
- if(stat(argv[1], &s)) {
+ if (stat(argv[1], &s)) {
perror("cannot stat binary");
return -1;
}
- if(unified_boot) {
+ if (unified_boot) {
magic = unified_boot_magic;
magic_len = sizeof(unified_boot_magic);
- }
- else {
+ } else {
magic = non_unified_boot_magic;
magic_len = sizeof(non_unified_boot_magic);
}
@@ -155,19 +158,18 @@
printf("Image Destination Pointer: 0x%x\n", base);
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000003; //Flash_partition_version /* nand */
- magic[2] = 0x00000000; //image source pointer
- magic[3] = base; //image destination pointer
- magic[4] = size + cert_chain_size + signature_size; //image size
- magic[5] = size; //code size
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
magic[6] = base + size;
magic[7] = signature_size;
magic[8] = size + base + signature_size;
magic[9] = cert_chain_size;
- if(unified_boot == 1)
- {
+ if (unified_boot == 1) {
magic[10] = 0x33836685; /* cookie magic number */
magic[11] = 0x00000001; /* cookie version */
magic[12] = 0x00000002; /* file formats */
@@ -181,11 +183,11 @@
}
fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
+ if (fd < 0) {
perror("cannot open header for writing");
return -1;
}
- if(write(fd, magic, magic_len) != magic_len) {
+ if (write(fd, magic, magic_len) != magic_len) {
perror("cannot write header");
close(fd);
unlink(argv[2]);
@@ -193,9 +195,9 @@
}
close(fd);
- if(secure_boot && argc > 6){
- FILE * input_file;
- FILE * output_file;
+ if (secure_boot && argc > 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
unsigned bytes_left;
@@ -203,21 +205,21 @@
int padding_size = 0;
int i;
- if((output_file = fopen(argv[6], "wb"))==NULL){
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Certificate Chain Output File: %s\n", argv[6]);
- for(i = 8; i < argc; i++){
- if((input_file = fopen(argv[i], "rb"))==NULL){
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[i], &s);
bytes_left = s.st_size;
current_cert_chain_size += bytes_left;
- if(cat(input_file, output_file, bytes_left, buff_size))
+ if (cat(input_file, output_file, bytes_left, buff_size))
return -1;
fclose(input_file);
}
@@ -226,24 +228,23 @@
memset(buf, 0xFF, sizeof(buf));
padding_size = cert_chain_size - current_cert_chain_size;
- if(padding_size <0){
+ if (padding_size < 0) {
fprintf(stderr, "ERROR: Input certificate chain"
- " (Size=%d) is larger than the maximum"
- " specified (Size=%d)\n",
+ " (Size=%d) is larger than the maximum"
+ " specified (Size=%d)\n",
current_cert_chain_size, cert_chain_size);
return -1;
}
bytes_left = (padding_size > 0) ? padding_size : 0;
- while(bytes_left){
- if(!ferror(output_file))
+ while (bytes_left) {
+ if (!ferror(output_file))
bytes_left -= fwrite(buf,
sizeof(buf),
- buff_size,
- output_file);
- else{
+ buff_size, output_file);
+ else {
fprintf(stderr, "ERROR: Occured during"
- " certifcate chain padding\n");
+ " certifcate chain padding\n");
return -1;
}
}
@@ -252,87 +253,86 @@
/* Concat and combine to signed image.
* Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
*/
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[2], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Signature
- if((input_file = fopen(argv[7], "rb"))==NULL){
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[7], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Certifcate Chain
- if((input_file = fopen(argv[6], "rb"))==NULL){
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
- if(cat(input_file, output_file,
- (current_cert_chain_size + padding_size), buff_size))
+ if (cat(input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
return -1;
fclose(input_file);
fclose(output_file);
- }
- else if(argc == 5 || argc == 6){
- FILE * input_file;
- FILE * output_file;
+ } else if (argc == 5 || argc == 6) {
+ FILE *input_file;
+ FILE *output_file;
unsigned buff_size = 1;
char buf[buff_size];
/* Concat and combine to unsigned image.
* Format [HDR][RAW APPSBOOT]
*/
- if((output_file = fopen(argv[4], "wb"))==NULL){
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
printf("Image Output File: %s\n", argv[4]);
//Header
- if((input_file = fopen(argv[2], "rb"))==NULL){
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[2], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
//Raw Appsbl
- if((input_file = fopen(argv[1], "rb"))==NULL){
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
perror("ERROR: Occured during fopen");
return -1;
}
stat(argv[1], &s);
- if(cat(input_file, output_file, s.st_size, buff_size))
+ if (cat(input_file, output_file, s.st_size, buff_size))
return -1;
fclose(input_file);
fclose(output_file);