lk: msm: Fix files to have uniform coding style
No functional changes, just style code formatting style changes here.
Change-Id: Id3f1995ef97765b393c5c26259011c9ce1321106
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 3fbf2fc..21fad3d 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -33,155 +33,158 @@
#include <platform/timer.h>
#include <platform/iomap.h>
-void mdp_setup_dma_p_video_config(unsigned short pack_pattern,
- unsigned short img_width,
- unsigned short img_height,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned char ystride){
- dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
+void
+mdp_setup_dma_p_video_config(unsigned short pack_pattern,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned char ystride)
+{
+ dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
- // ----- programming MDP_AXI_RDMASTER_CONFIG --------
- /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
- the only port connected */
- //TODO: Seems to still work without this
- writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ // ----- programming MDP_AXI_RDMASTER_CONFIG --------
+ /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
+ the only port connected */
+ //TODO: Seems to still work without this
+ writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
- writel(0x00000049, MDP_DISP_INTF_SEL);
+ /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
+ writel(0x00000049, MDP_DISP_INTF_SEL);
- /* DMA P */
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ /* DMA P */
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- /* RGB 888 */
- writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
+ /* RGB 888 */
+ writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
- writel(0x0, MDP_DMA_P_OUT_XY);
+ writel(0x0, MDP_DMA_P_OUT_XY);
- writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
+ writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
}
-int mdp_setup_dma_p_video_mode(unsigned short disp_width,
- unsigned short disp_height,
- unsigned short img_width,
- unsigned short img_height,
- unsigned short hsync_porch0_fp,
- unsigned short hsync_porch0_bp,
- unsigned short vsync_porch0_fp,
- unsigned short vsync_porch0_bp,
- unsigned short hsync_width,
- unsigned short vsync_width,
- unsigned long input_img_addr,
- unsigned short img_width_full_size,
- unsigned short pack_pattern,
- unsigned char ystride)
+int
+mdp_setup_dma_p_video_mode(unsigned short disp_width,
+ unsigned short disp_height,
+ unsigned short img_width,
+ unsigned short img_height,
+ unsigned short hsync_porch0_fp,
+ unsigned short hsync_porch0_bp,
+ unsigned short vsync_porch0_fp,
+ unsigned short vsync_porch0_bp,
+ unsigned short hsync_width,
+ unsigned short vsync_width,
+ unsigned long input_img_addr,
+ unsigned short img_width_full_size,
+ unsigned short pack_pattern, unsigned char ystride)
{
- // unsigned long mdp_intr_status;
- int status = FAIL;
- unsigned long hsync_period;
- unsigned long vsync_period;
- unsigned long vsync_period_intmd;
+ // unsigned long mdp_intr_status;
+ int status = FAIL;
+ unsigned long hsync_period;
+ unsigned long vsync_period;
+ unsigned long vsync_period_intmd;
- dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
+ dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
- hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
- vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
- vsync_period = vsync_period_intmd * hsync_period;
+ hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
+ vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
+ vsync_period = vsync_period_intmd * hsync_period;
- // ----- programming MDP_AXI_RDMASTER_CONFIG --------
- /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
- the only port connected */
- writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL*/
- writel(0x00000049, MDP_DISP_INTF_SEL);
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ // ----- programming MDP_AXI_RDMASTER_CONFIG --------
+ /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
+ the only port connected */
+ writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */
+ writel(0x00000049, MDP_DISP_INTF_SEL);
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- // ------------- programming MDP_DMA_P_CONFIG ---------------------
- writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
+ // ------------- programming MDP_DMA_P_CONFIG ---------------------
+ writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
- writel(0x00000000, MDP_DMA_P_OUT_XY);
- writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
- writel(0x00ff0000, MDP_DMA_P_OP_MODE);
- writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
- writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
- writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
- writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
- MDP_DSI_VIDEO_DISPLAY_HCTL);
- writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
- writel((img_height + vsync_porch0_bp) * hsync_period,
- MDP_DSI_VIDEO_DISPLAY_V_END);
- writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
- writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
- writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
- // end of cmd mdp
+ writel(0x00000000, MDP_DMA_P_OUT_XY);
+ writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(0x00ff0000, MDP_DMA_P_OP_MODE);
+ writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
+ writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
+ writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
+ writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
+ MDP_DSI_VIDEO_DISPLAY_HCTL);
+ writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
+ writel((img_height + vsync_porch0_bp) * hsync_period,
+ MDP_DSI_VIDEO_DISPLAY_V_END);
+ writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
+ writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
+ writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
+ // end of cmd mdp
- writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
+ writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
- status = PASS;
- return status;
+ status = PASS;
+ return status;
}
-
-int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, unsigned short num_of_lanes)
+int
+mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
+ unsigned short num_of_lanes)
{
- int status = 0;
- unsigned long input_img_addr = MIPI_FB_ADDR;
- unsigned short image_wd = mipi_fb_cfg.width;
- unsigned short image_ht = mipi_fb_cfg.height;
- unsigned short pack_pattern = 0x12;
- unsigned char ystride = 3;
+ int status = 0;
+ unsigned long input_img_addr = MIPI_FB_ADDR;
+ unsigned short image_wd = mipi_fb_cfg.width;
+ unsigned short image_ht = mipi_fb_cfg.height;
+ unsigned short pack_pattern = 0x12;
+ unsigned char ystride = 3;
- writel(0x03ffffff, MDP_INTR_ENABLE);
- writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+ writel(0x03ffffff, MDP_INTR_ENABLE);
+ writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
- // ------------- programming MDP_DMA_P_CONFIG ---------------------
- writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
+ // ------------- programming MDP_DMA_P_CONFIG ---------------------
+ writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
- writel(0x00000000, MDP_DMA_P_OUT_XY);
- writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
- writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+ writel(0x00000000, MDP_DMA_P_OUT_XY);
+ writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
+ writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
- writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+ writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
- writel(0x00000000, MDP_DMA_P_OP_MODE);
+ writel(0x00000000, MDP_DMA_P_OP_MODE);
- writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
- writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
+ writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
+ writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
- writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
- writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
- writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
- writel(0x8a, MDP_DISP_INTF_SEL);
+ writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
+ writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+ writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+ writel(0x8a, MDP_DISP_INTF_SEL);
- return status;
+ return status;
}
void mdp_disable(void)
{
- writel(0x00000000, MDP_DSI_VIDEO_EN);
+ writel(0x00000000, MDP_DSI_VIDEO_EN);
}
void mdp_shutdown(void)
{
- mdp_disable();
- mdelay(60);
- writel(0x00000000, MDP_INTR_ENABLE);
- writel(0x00000003, MDP_OVERLAYPROC0_CFG);
+ mdp_disable();
+ mdelay(60);
+ writel(0x00000000, MDP_INTR_ENABLE);
+ writel(0x00000003, MDP_OVERLAYPROC0_CFG);
}
void mdp_start_dma(void)
{
- writel(0x00000001, MDP_DMA_P_START);
+ writel(0x00000001, MDP_DMA_P_START);
}