Merge "dev: gcdb: Add GCDB based nt35521 wxga driver for SKUT1"
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 38ba3b4..e2e497f 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -43,7 +43,10 @@
uint32_t width = pinfo->xres;
if (pinfo->mipi.dual_dsi)
- width = pinfo->xres / 2;
+ width /= 2;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
+ width /= pinfo->fbc.comp_ratio;
h_period = width + pinfo->lcdc.h_back_porch +
pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width +
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 1a328f5..c21383e 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -178,4 +178,24 @@
char *bl_pmic_model;
};
+typedef struct fb_compression {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
#endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
old mode 100644
new mode 100755
index 427a548..9734574
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -153,6 +153,27 @@
pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger;
pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger;
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ if (pinfo->fbc.enabled) {
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ pinfo->fbc.comp_ratio= pstruct->fbcinfo.comp_ratio;
+ pinfo->fbc.comp_mode = pstruct->fbcinfo.comp_mode;
+ pinfo->fbc.qerr_enable = pstruct->fbcinfo.qerr_enable;
+ pinfo->fbc.cd_bias = pstruct->fbcinfo.cd_bias;
+ pinfo->fbc.pat_enable = pstruct->fbcinfo.pat_enable;
+ pinfo->fbc.vlc_enable = pstruct->fbcinfo.vlc_enable;
+ pinfo->fbc.bflc_enable = pstruct->fbcinfo.bflc_enable;
+ pinfo->fbc.line_x_budget = pstruct->fbcinfo.line_x_budget;
+ pinfo->fbc.block_x_budget = pstruct->fbcinfo.block_x_budget;
+ pinfo->fbc.block_budget = pstruct->fbcinfo.block_budget;
+ pinfo->fbc.lossless_mode_thd = pstruct->fbcinfo.lossless_mode_thd;
+ pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
+ pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
+ pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+ } else {
+ pinfo->fbc.comp_ratio = 1;
+ }
+
pinfo->pre_on = dsi_panel_pre_on;
pinfo->pre_off = dsi_panel_pre_off;
pinfo->on = dsi_panel_post_on;
@@ -211,6 +232,9 @@
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
+ uint32_t final_xres, final_yres, final_width;
+ uint32_t final_height, final_hbp, final_hfp,final_vbp;
+ uint32_t final_vfp, final_hpw, final_vpw;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -224,16 +248,29 @@
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
- ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
+ final_xres = panel_width;
+ final_width = panel_width + pinfo->lcdc.xres_pad;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+ final_xres /= pinfo->fbc.comp_ratio;
+ final_width /= pinfo->fbc.comp_ratio;
+ dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
+ final_width);
+ }
+ final_yres = pinfo->yres;
+ final_height = pinfo->yres + pinfo->lcdc.yres_pad;
+ final_hbp = pinfo->lcdc.h_back_porch;
+ final_hfp = pinfo->lcdc.h_front_porch;
+ final_vbp = pinfo->lcdc.v_back_porch;
+ final_vfp = pinfo->lcdc.v_front_porch;
+ final_hpw = pinfo->lcdc.h_pulse_width;
+ final_vpw = pinfo->lcdc.v_pulse_width;
+
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
@@ -243,24 +280,18 @@
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
- ret = mdss_dsi_video_mode_config(
- (panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
- pinfo->mipi.dst_format,
- pinfo->mipi.traffic_mode,
- lane_enable,
- pinfo->mipi.hsa_power_stop,
- pinfo->mipi.eof_bllp_power,
- pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
+ pinfo->mipi.dst_format,
+ pinfo->mipi.traffic_mode,
+ lane_enable,
+ pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.eof_bllp_power,
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI1_BASE);
return ret;
}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index a6843ce..dcc5631 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -47,6 +47,7 @@
#define DST_SPLIT_FLAG 0x10
#define MAX_PANEL_ID_LEN 64
+#include "panel.h"
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
@@ -61,6 +62,7 @@
struct panel_timing *paneltiminginfo;
struct panel_reset_sequence *panelresetseq;
struct backlight *backlightinfo;
+ struct fb_compression fbcinfo;
};
struct panel_list {
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index c8a7991..67a6f5b 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -259,6 +259,16 @@
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x12F00)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x13000)
+
#define DMA_CMD_OFFSET 0x048
#define DMA_CMD_LENGTH 0x04C
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 9596622..c815bd0 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -43,9 +43,14 @@
#define SDRAM_START_ADDR 0x80000000
#define MSM_SHARED_BASE 0x86300000
-
#define APPS_SS_BASE 0x0B000000
+#define DDR_START get_ddr_start()
+#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
+#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
+#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
+#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
+
#define MSM_GIC_DIST_BASE APPS_SS_BASE
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index 4deaa1b..7e583c6 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -52,7 +52,7 @@
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* IMEM memory - cacheable, write through */
-#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
static mmu_section_t mmu_section_table[] = {
@@ -60,7 +60,10 @@
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
{ MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
{ A53_SS_BASE, A53_SS_BASE, A53_SS_SIZE, IOMAP_MEMORY},
- { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
+ { BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
};
static struct smem_ram_ptable ram_ptable;
@@ -114,39 +117,6 @@
uint32_t i;
uint32_t sections;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- ram_partition ptn_entry;
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
@@ -216,3 +186,30 @@
else
return MSM_SHARED_BASE;
}
+uint32_t get_ddr_start()
+{
+ uint32_t i;
+ ram_partition ptn_entry;
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Determine the Start addr of the DDR RAM */
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+ return ptn_entry.start;
+ }
+ }
+ }
+ ASSERT("DDR Start Mem Not found\n");
+}
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index c0b2880..341c0a6 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -243,6 +243,17 @@
#define MDP_BASE (0xfd900000)
+
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x71000)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x71800)
+
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
#define MDP_INTR_EN REG_MDP(0x1010)
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index fdc8553..fbbe62b 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -150,11 +150,11 @@
}
/* HLOS subtype
- * bit no |31 16 | 15 8 | 7 0|
- * board.platform_hlos_subtype = |reserved | DDR detection | subtype|
- * | bits | bits | |
+ * bit no |31 20 | 19 16| 15 8 | 7 0|
+ * board.platform_hlos_subtype = |reserved | Boot device | DDR detection | subtype|
+ * | bits | | bits |
*/
- board.platform_hlos_subtype = board_get_ddr_subtype() << 8;
+ board.platform_hlos_subtype = (board_get_ddr_subtype() << 8) | (platform_get_boot_dev() << 16);
}
else
{
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 670d344..2571763 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -151,6 +151,51 @@
return ret;
}
+int dme_set_fpoweronwpen(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ uint32_t try_again = DME_FPOWERONWPEN_RETRIES;
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fPowerOnWPEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+
+
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+
+ if (*result == 1)
+ goto utp_set_fpoweronwpen_done;
+
+ do
+ {
+ try_again--;
+ dprintf(CRITICAL, "Power on Write Protect request failed. Retrying again.\n");
+
+ if (dme_send_query_upiu(dev, &set_query))
+ return -UFS_FAILURE;
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ if (*result == 1)
+ break;
+ } while (try_again);
+
+utp_set_fpoweronwpen_done:
+ dprintf(INFO,"Power on Write Protect status: %u\n", *result);
+ return UFS_SUCCESS;
+}
+
int dme_set_fdeviceinit(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 31be6c5..c9ac677 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,7 @@
/* Retry value for commands. */
#define DME_NOP_NUM_RETRIES 20
#define DME_FDEVICEINIT_RETRIES 20
+#define DME_FPOWERONWPEN_RETRIES 20
/* Timeout value for commands. */
#define DME_NOP_QUERY_TIMEOUT 10
@@ -221,6 +222,7 @@
struct upiu_req_build_type *upiu_data);
int dme_send_nop_query(struct ufs_dev *dev);
int dme_set_fdeviceinit(struct ufs_dev *dev);
+int dme_set_fpoweronwpen(struct ufs_dev *dev);
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index dd5132f..8e17def 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -103,6 +103,9 @@
#define MDP_CTL_0_BASE REG_MDP(0x600)
#define MDP_CTL_1_BASE REG_MDP(0x700)
+#define MDP_PP_0_BASE REG_MDP(0x12D00)
+#define MDP_PP_1_BASE REG_MDP(0x12E00)
+
#define CTL_LAYER_0 0x00
#define CTL_LAYER_1 0x04
#define CTL_TOP 0x14
@@ -181,6 +184,10 @@
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0x24074)
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0x240A8)
+#define MDSS_MDP_REG_PP_FBC_MODE 0x034
+#define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038
+#define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C
+
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index c3497a8..651cc53 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -114,6 +114,45 @@
uint8_t dst_split;
};
+struct fbc_panel_info {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
+/* intf timing settings */
+struct intf_timing_params {
+ uint32_t width;
+ uint32_t height;
+ uint32_t xres;
+ uint32_t yres;
+
+ uint32_t h_back_porch;
+ uint32_t h_front_porch;
+ uint32_t v_back_porch;
+ uint32_t v_front_porch;
+ uint32_t hsync_pulse_width;
+ uint32_t vsync_pulse_width;
+
+ uint32_t border_clr;
+ uint32_t underflow_clr;
+ uint32_t hsync_skew;
+};
+
struct mipi_panel_info {
char mode; /* video/cmd */
char interleave_mode;
@@ -204,6 +243,7 @@
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
+ struct fbc_panel_info fbc;
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
struct hdmi_panel_info hdmi;
diff --git a/platform/msm_shared/include/ufs.h b/platform/msm_shared/include/ufs.h
index bbe9a40..b5c76fc 100644
--- a/platform/msm_shared/include/ufs.h
+++ b/platform/msm_shared/include/ufs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -120,5 +120,6 @@
uint32_t ufs_get_serial_num(struct ufs_dev* dev);
uint8_t ufs_get_num_of_luns(struct ufs_dev* dev);
uint32_t ufs_get_erase_blk_size(struct ufs_dev* dev);
+void ufs_dump_is_register(struct ufs_dev* dev);
void ufs_dump_hc_registers(struct ufs_dev* dev);
#endif
diff --git a/platform/msm_shared/include/utp.h b/platform/msm_shared/include/utp.h
index 042c002..e7a6df9 100644
--- a/platform/msm_shared/include/utp.h
+++ b/platform/msm_shared/include/utp.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -145,5 +145,5 @@
int utp_enqueue_upiu(struct ufs_dev *dev, struct upiu_req_build_type *upiu_data);
void utp_process_req_completion(struct ufs_req_irq_type *irq);
-
+int utp_poll_utrd_complete(struct ufs_dev *dev);
#endif
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
old mode 100644
new mode 100755
index dd32038..08ebafb
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -363,11 +363,12 @@
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
- uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
+ uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
+ struct intf_timing_params itp = {0};
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -391,41 +392,58 @@
writel(BIT(5), MDP_REG_PPB0_CNTL);
}
+ if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
+ pinfo->fbc.comp_ratio = 1;
+
+ itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
+ itp.yres = pinfo->yres;
+ itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
+ itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
+ itp.h_back_porch = pinfo->lcdc.h_back_porch;
+ itp.h_front_porch = pinfo->lcdc.h_front_porch;
+ itp.v_back_porch = pinfo->lcdc.v_back_porch;
+ itp.v_front_porch = pinfo->lcdc.v_front_porch;
+ itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
+ itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
+
+ itp.border_clr = pinfo->lcdc.border_clr;
+ itp.underflow_clr = pinfo->lcdc.underflow_clr;
+ itp.hsync_skew = pinfo->lcdc.hsync_skew;
+
+
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
- hsync_period = lcdc->h_pulse_width +
- lcdc->h_back_porch +
- adjust_xres + lcdc->xres_pad + lcdc->h_front_porch;
- vsync_period = (lcdc->v_pulse_width +
- lcdc->v_back_porch +
- pinfo->yres + lcdc->yres_pad +
- lcdc->v_front_porch);
+ hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
+ itp.width + itp.h_front_porch;
+
+ vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
+ itp.height + itp.v_front_porch;
hsync_start_x =
- lcdc->h_pulse_width +
- lcdc->h_back_porch;
+ itp.hsync_pulse_width +
+ itp.h_back_porch;
hsync_end_x =
- hsync_period - lcdc->h_front_porch - 1;
+ hsync_period - itp.h_front_porch - 1;
- display_vstart = (lcdc->v_pulse_width +
- lcdc->v_back_porch)
- * hsync_period + lcdc->hsync_skew;
- display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
- +lcdc->hsync_skew - 1;
+ display_vstart = (itp.vsync_pulse_width +
+ itp.v_back_porch)
+ * hsync_period + itp.hsync_skew;
+ display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ + itp.hsync_skew - 1;
if (intf_base == MDP_INTF_0_BASE) { /* eDP */
- display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
- display_vend -= lcdc->h_front_porch;
+ display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
+ display_vend -= itp.h_front_porch;
}
- hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
+ hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
- writel(lcdc->v_pulse_width*hsync_period,
+ writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
@@ -571,6 +589,57 @@
}
}
+void mdss_fbc_cfg(struct msm_panel_info *pinfo)
+{
+ uint32_t mode = 0;
+ uint32_t budget_ctl = 0;
+ uint32_t lossy_mode = 0;
+ uint32_t xres;
+ struct fbc_panel_info *fbc;
+ uint32_t enc_mode;
+
+ fbc = &pinfo->fbc;
+ xres = pinfo->xres;
+
+ if (!pinfo->fbc.enabled)
+ return;
+
+ if (pinfo->mipi.dual_dsi)
+ xres /= 2;
+
+ /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
+ enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
+
+ mode = ((xres) << 16) | (enc_mode) << 9 | ((fbc->comp_mode) << 8) |
+ ((fbc->qerr_enable) << 7) | ((fbc->cd_bias) << 4) |
+ ((fbc->pat_enable) << 3) | ((fbc->vlc_enable) << 2) |
+ ((fbc->bflc_enable) << 1) | 1;
+
+ dprintf(SPEW, "xres = %d, comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
+ xres, fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
+ dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
+ fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
+
+ budget_ctl = ((fbc->line_x_budget) << 12) |
+ ((fbc->block_x_budget) << 8) | fbc->block_budget;
+
+ lossy_mode = ((fbc->lossless_mode_thd) << 16) |
+ ((fbc->lossy_mode_thd) << 8) |
+ ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
+
+ writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+
+ if (pinfo->mipi.dual_dsi) {
+ writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+ }
+}
+
void mdss_qos_remapper_setup(void)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
@@ -698,6 +767,8 @@
/*If dst_split is enabled only intf 2 needs to be enabled.
CTL_1 path should not be set since CTL_0 itself is going
to split after DSPP block*/
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
if (!pinfo->lcdc.dst_split) {
@@ -842,6 +913,9 @@
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
+
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 276840b..c660a5f 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -357,6 +357,15 @@
blk_addr += unaligned_blks;
blk_count -= unaligned_blks;
+
+ head_unit = blk_addr / erase_unit_sz;
+ tail_unit = (blk_addr + blk_count - 1) / erase_unit_sz;
+
+ if (tail_unit - head_unit <= 1)
+ {
+ dprintf(INFO, "SDHCI unit erase not required\n");
+ return mmc_zero_out(dev, blk_addr, blk_count);
+ }
}
unaligned_blks = blk_count % erase_unit_sz;
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
index 8244576..1897735 100644
--- a/platform/msm_shared/ufs.c
+++ b/platform/msm_shared/ufs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -81,7 +81,7 @@
writel(1, UFS_UTRLRSR(dev->base));
/* Enable the required irqs. */
- val = UFS_IE_UTRCE | UFS_IE_UEE | UFS_IE_UTMRCE | UFS_IE_UCCE ;
+ val = UFS_IE_UEE | UFS_IE_UCCE ;
ufs_irq_enable(dev, val);
}
@@ -266,6 +266,12 @@
return ret;
}
+void ufs_dump_is_register(struct ufs_dev *dev)
+{
+ uint32_t base = dev->base;
+ dprintf(CRITICAL,"UFS_IS 0x%x\n",readl(UFS_IS(base)));
+}
+
void ufs_dump_hc_registers(struct ufs_dev *dev)
{
uint32_t base = dev->base;
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index ccaa3b5..d8858b9 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -456,6 +456,7 @@
for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
{
dwc_ep_t *ep = &dev->ep[ep_index];
+ ASSERT(ep != NULL);
DBG("\n RESET on EP = %d while state = %s", ep_index,
ep_state_lookup[ep->state]);
@@ -489,7 +490,7 @@
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -573,7 +574,11 @@
uint8_t status = 0;
uint8_t trb_updated = 0;
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
+
dwc_trb_t *trb = ep->trb;
uint32_t num_of_trb = ep->trb_queued;
uint32_t bytes_remaining = 0;
@@ -641,7 +646,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -756,7 +761,7 @@
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -930,6 +935,8 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1011,7 +1018,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1085,7 +1092,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1164,7 +1171,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1239,7 +1246,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1289,7 +1296,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1373,7 +1380,7 @@
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
#endif
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1433,6 +1440,7 @@
*/
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index)
{
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
uint8_t ep_phy_num = dev->ep[index].phy_num;
dwc_ep_cmd_set_config(dev, index, SET_CONFIG_ACTION_INIT);
@@ -1455,6 +1463,7 @@
/* Control OUT */
index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dev->ep[index].number = 0;
dev->ep[index].dir = DWC_EP_DIRECTION_OUT;
@@ -1525,7 +1534,9 @@
/* entry function into inactive state for data transfer fsm */
static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
/* queue request to receive the first setup pkt from host */
ep->req.data = NULL;
@@ -1605,7 +1616,9 @@
{
uint8_t index = DWC_EP_INDEX(new_ep->number, new_ep->dir);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
memset(ep, 0, sizeof(ep));
@@ -1691,7 +1704,9 @@
uint8_t ep_phy_num,
dwc_request_t *req)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
dwc_trb_t *trb = ep->trb;
uint8_t *data_ptr = req->data;
diff --git a/platform/msm_shared/utp.c b/platform/msm_shared/utp.c
index c7d30ff..0c0e14b 100644
--- a/platform/msm_shared/utp.c
+++ b/platform/msm_shared/utp.c
Binary files differ
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 1984ab2..5f51f80 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -25,11 +25,6 @@
DEFINES += BAM_V170=1
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
-DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
-DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
-DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
-
#Enable the feature of long press power on
DEFINES += LONG_PRESS_POWER_ON=1
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 0780268..961b5a4 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -182,6 +182,26 @@
{
}
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
diff --git a/target/msmzirc/keypad.c b/target/msmzirc/keypad.c
index 569ea66..11ba6e8 100644
--- a/target/msmzirc/keypad.c
+++ b/target/msmzirc/keypad.c
@@ -33,7 +33,7 @@
/* GPIO that controls the button
* for FASTBOOT.
*/
-#define FASTBOOT_KEY_GPIO_ID 17
+#define FASTBOOT_KEY_GPIO_ID 92
/*
* Returns fastboot button state.
diff --git a/target/msmzirc/rules.mk b/target/msmzirc/rules.mk
index 7acd1db..7a19970 100644
--- a/target/msmzirc/rules.mk
+++ b/target/msmzirc/rules.mk
@@ -4,16 +4,16 @@
PLATFORM := msmzirc
-MEMBASE := 0x87C00000
+MEMBASE := 0x81200000
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x80000000
-SCRATCH_REGION1 := 0x81C00000
-SCRATCH_REGION1_SIZE := 0x06000000 # 97MB
+SCRATCH_REGION1 := 0x81300000
+SCRATCH_REGION1_SIZE := 0x06900000 # 105MB
SCRATCH_REGION2 := 0x88000000
SCRATCH_REGION2_SIZE := 0x08000000 # 128MB
KERNEL_REGION := 0x80000000
-KERNEL_REGION_SIZE := 0x01C00000 # 28MB
+KERNEL_REGION_SIZE := 0x01200000 # 18MB
DEFINES += NO_KEYPAD_DRIVER=1