Merge "project: msm8974: disable THUMB mode"
diff --git a/dev/panel/msm/mipi_toshiba_video_720p.c b/dev/panel/msm/mipi_toshiba_video_720p.c
index 2e02edd..5357e77 100644
--- a/dev/panel/msm/mipi_toshiba_video_720p.c
+++ b/dev/panel/msm/mipi_toshiba_video_720p.c
@@ -91,22 +91,22 @@
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 720x1280, RGB888, 4 Lane 60 fps video mode */
/* regulator */
- {0x03, 0x01, 0x01, 0x00, 0x20, 0x00, 0x01},
+ {0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
/* timing */
- {0x69, 0x29, 0x1f, 0x00, 0x55, 0x55, 0x19, 0x2a,
- 0x2a, 0x03, 0x04, 0x00},
+ {0xb0, 0x23, 0x1b, 0x00, 0x94, 0x93, 0x1e, 0x25,
+ 0x15, 0x03, 0x04, 0x00},
/* phy ctrl */
{0x5f, 0x00, 0x00, 0x10},
/* strength */
- {0x77, 0x06},
+ {0xff, 0x06},
/* bist control */
{0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
/* lanes config */
- {0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
- 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
- 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
- 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
- 0x00, 0x02, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
};
void mipi_toshiba_video_720p_init(struct msm_panel_info *pinfo)
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index bd06767..0319233 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -215,16 +215,16 @@
goto msm_display_init_out;
}
- /* Enable clock */
- if (pdata->clk_func)
- ret = pdata->clk_func(1);
+ /* Turn on panel */
+ if (pdata->power_func)
+ ret = pdata->power_func(1);
if (ret)
goto msm_display_init_out;
- /* Turn on panel */
- if (pdata->power_func)
- ret = pdata->power_func(1);
+ /* Enable clock */
+ if (pdata->clk_func)
+ ret = pdata->clk_func(1);
if (ret)
goto msm_display_init_out;
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 60a1f97..93dd4bd 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -181,8 +181,37 @@
return 0;
}
+void mdss_dsi_phy_sw_reset(void)
+{
+ /* start phy sw reset */
+ writel(0x0001, MIPI_DSI_BASE + 0x012c);
+ udelay(1000);
+
+ /* end phy sw reset */
+ writel(0x0000, MIPI_DSI_BASE + 0x012c);
+ udelay(100);
+}
+
+void mdss_dsi_uniphy_pll_lock_detect_setting(void)
+{
+ writel(0x04, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+ udelay(100);
+ writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+ mdelay(1);
+}
+
+void mdss_dsi_uniphy_pll_sw_reset(void)
+{
+ writel(0x01, MIPI_DSI_BASE + 0x0268); /* PLL TEST CFG */
+ udelay(1);
+ writel(0x00, MIPI_DSI_BASE + 0x0268); /* PLL TEST CFG */
+ udelay(1);
+}
+
int mdss_dsi_uniphy_pll_config(void)
{
+ mdss_dsi_phy_sw_reset();
+
/* Configuring the Pll Vco clk to 424 Mhz */
/* Loop filter resistance value */
@@ -197,8 +226,8 @@
writel(0x03, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
- writel(0x06, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
- writel(0x05, MIPI_DSI_BASE + 0x0264); /* Cal CFG4 */
+ writel(0x66, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
+ writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
writel(0x0a, MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
writel(0xab, MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
@@ -209,7 +238,7 @@
writel(0x01, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
- writel(0x01, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
+ writel(0x71, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
writel(0x02, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
writel(0x00, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
@@ -222,18 +251,37 @@
writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
+ mdss_dsi_uniphy_pll_sw_reset();
writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(20);
+ mdelay(1);
writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(20);
+ mdelay(1);
writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
- while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01))
- udelay(1);
+ mdss_dsi_uniphy_pll_lock_detect_setting();
+ while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01)) {
+ mdss_dsi_uniphy_pll_sw_reset();
+ writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(2);
+ mdss_dsi_uniphy_pll_lock_detect_setting();
+ }
}
+
int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mdss_dsi_phy_ctrl *pd;
@@ -242,10 +290,11 @@
pd = (pinfo->mdss_dsi_phy_config);
/* Strength ctrl 0 */
- writel(0x07, MIPI_DSI_BASE + 0x0484);
writel(pd->strength[0], MIPI_DSI_BASE + 0x0484);
off = 0x0580; /* phy regulator ctrl settings */
+ /* Regulator ctrl 0 */
+ writel(0x00, MIPI_DSI_BASE + off + (4 * 0));
/* Regulator ctrl - CAL_PWD_CFG */
writel(pd->regulator[6], MIPI_DSI_BASE + off + (4 * 6));
/* Regulator ctrl - TEST */
@@ -262,6 +311,9 @@
writel(pd->regulator[4], MIPI_DSI_BASE + off + (4 * 4));
dmb();
+ /* Strength ctrl 0 */
+ writel(0x00, MIPI_DSI_BASE + 0x04dc);
+
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
writel(pd->timing[i], MIPI_DSI_BASE + off);
@@ -290,7 +342,7 @@
}
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x7f, MIPI_DSI_BASE + 0x0470);
+ writel(0x5f, MIPI_DSI_BASE + 0x0470);
/* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
writel(0x01, MIPI_DSI_BASE + 0x04d4);