Merge "target: msm8939: Add support for auto panel detection of hx8394d panel"
diff --git a/AndroidBoot.mk b/AndroidBoot.mk
index e93b7b4..06647a9 100644
--- a/AndroidBoot.mk
+++ b/AndroidBoot.mk
@@ -17,6 +17,17 @@
BOOTLOADER_PLATFORM := $(TARGET_BOARD_PLATFORM)
endif
+ifeq ($(PRODUCTS.$(INTERNAL_PRODUCT).PRODUCT_SUPPORTS_VERITY),true)
+ VERIFIED_BOOT := VERIFIED_BOOT=1
+else
+ VERIFIED_BOOT := VERIFEID_BOOT=0
+endif
+
+ifneq ($(TARGET_BUILD_VARIANT),user)
+ DEVICE_STATUS := DEFAULT_UNLOCK=true
+ USER_BUILD_VARIANT=true
+endif
+
ifeq ($(TARGET_BOARD_PLATFORM),msm8660)
BOOTLOADER_PLATFORM := msm8660_surf
endif
@@ -31,7 +42,7 @@
# ELF binary for ABOOT
TARGET_ABOOT_ELF := $(PRODUCT_OUT)/aboot.elf
$(TARGET_ABOOT_ELF): ABOOT_CLEAN | $(ABOOT_OUT)
- $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL) $(VERIFIED_BOOT) $(DEVICE_STATUS)
# NAND variant output
TARGET_NAND_BOOTLOADER := $(PRODUCT_OUT)/appsboot.mbn
@@ -59,8 +70,8 @@
$(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(NAND_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) $(SIGNED_KERNEL)
# Top level for eMMC variant targets
-$(TARGET_EMMC_BOOTLOADER): emmc_appsbootldr_clean | $(EMMC_BOOTLOADER_OUT)
- $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL)
+$(TARGET_EMMC_BOOTLOADER): emmc_appsbootldr_clean | $(EMMC_BOOTLOADER_OUT) $(INSTALLED_KEYSTOREIMAGE_TARGET)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL) $(VERIFIED_BOOT) $(DEVICE_STATUS)
# Keep build NAND & eMMC as default for targets still using TARGET_BOOTLOADER
TARGET_BOOTLOADER := $(PRODUCT_OUT)/EMMCBOOT.MBN
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index de8948e..25755a1 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -40,6 +40,7 @@
#include <arch/ops.h>
#include <dev/flash.h>
+#include <dev/flash-ubi.h>
#include <lib/ptable.h>
#include <dev/keys.h>
#include <dev/fbcon.h>
@@ -71,6 +72,7 @@
#include "devinfo.h"
#include "board.h"
#include "scm.h"
+#include "mdtp.h"
extern bool target_use_signed_kernel(void);
extern void platform_uninit(void);
@@ -105,6 +107,10 @@
#define MAX_TAGS_SIZE 1024
+#define RECOVERY_HARD_RESET_MODE 0x01
+#define FASTBOOT_HARD_RESET_MODE 0x02
+#define RTC_HARD_RESET_MODE 0x03
+
#define RECOVERY_MODE 0x77665502
#define FASTBOOT_MODE 0x77665500
#define ALARM_BOOT 0x77665503
@@ -113,16 +119,14 @@
#define DEFAULT_ERASE_SIZE 4096
#define MAX_PANEL_BUF_SIZE 128
-#define UBI_MAGIC "UBI#"
#define DISPLAY_DEFAULT_PREFIX "mdss_mdp"
-#define UBI_MAGIC_SIZE 0x04
#define BOOT_DEV_MAX_LEN 64
#define IS_ARM64(ptr) (ptr->magic_64 == KERNEL64_HDR_MAGIC) ? true : false
#define ADD_OF(a, b) (UINT_MAX - b > a) ? (a + b) : UINT_MAX
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
static const char *emmc_cmdline = " androidboot.bootdevice=";
#else
static const char *emmc_cmdline = " androidboot.emmc=true";
@@ -245,7 +249,7 @@
}
if (target_is_emmc_boot()) {
cmdline_len += strlen(emmc_cmdline);
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
boot_dev_buf = (char *) malloc(sizeof(char) * BOOT_DEV_MAX_LEN);
ASSERT(boot_dev_buf);
platform_boot_dev_cmdline(boot_dev_buf);
@@ -360,7 +364,7 @@
if (have_cmdline) --dst;
have_cmdline = 1;
while ((*dst++ = *src++));
-#if UFS_SUPPORT || USE_BOOTDEV_CMDLINE
+#if USE_BOOTDEV_CMDLINE
src = boot_dev_buf;
if (have_cmdline) --dst;
while ((*dst++ = *src++));
@@ -621,7 +625,7 @@
#if VERIFIED_BOOT
/* Write protect the device info */
- if (mmc_write_protect("devinfo", 1))
+ if (target_build_variant_user() && mmc_write_protect("devinfo", 1))
{
dprintf(INFO, "Failed to write protect dev info\n");
ASSERT(0);
@@ -690,11 +694,14 @@
static void verify_signed_bootimg(uint32_t bootimg_addr, uint32_t bootimg_size)
{
int ret;
+
+#if !VERIFIED_BOOT
#if IMAGE_VERIF_ALGO_SHA1
uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA1;
#else
uint32_t auth_algo = CRYPTO_AUTH_ALG_SHA256;
#endif
+#endif
/* Assume device is rooted at this time. */
device.is_tampered = 1;
@@ -893,6 +900,8 @@
return -1;
}
}
+ /* Set Lun for boot & recovery partitions */
+ mmc_set_lun(partition_get_lun(index));
if (mmc_read(ptn + offset, (uint32_t *) buf, page_size)) {
dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
@@ -1437,7 +1446,9 @@
{
struct device_info *info = (void*) info_buf;
unsigned long long ptn = 0;
+#if !VERIFIED_BOOT
unsigned long long size;
+#endif
int index = INVALID_PTN;
uint32_t blocksize;
uint8_t lun = 0;
@@ -1457,7 +1468,9 @@
lun = partition_get_lun(index);
mmc_set_lun(lun);
+#if !VERIFIED_BOOT
size = partition_get_size(index);
+#endif
memcpy(info, dev, sizeof(device_info));
@@ -1478,7 +1491,9 @@
{
struct device_info *info = (void*) info_buf;
unsigned long long ptn = 0;
+#if !VERIFIED_BOOT
unsigned long long size;
+#endif
int index = INVALID_PTN;
uint32_t blocksize;
@@ -1496,7 +1511,9 @@
mmc_set_lun(partition_get_lun(index));
+#if !VERIFIED_BOOT
size = partition_get_size(index);
+#endif
blocksize = mmc_get_device_blocksize();
@@ -1703,6 +1720,12 @@
int ret = 0;
uint8_t dtb_copied = 0;
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
#if VERIFIED_BOOT
if(!device.is_unlocked)
{
@@ -1881,24 +1904,25 @@
lun = partition_get_lun(index);
mmc_set_lun(lun);
-#if MMC_SDHCI_SUPPORT
- if (mmc_erase_card(ptn, size)) {
- fastboot_fail("failed to erase partition\n");
- return;
- }
-#else
- BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
- size = partition_get_size(index);
- if (size > DEFAULT_ERASE_SIZE)
- size = DEFAULT_ERASE_SIZE;
+ if (platform_boot_dev_isemmc())
+ {
+ if (mmc_erase_card(ptn, size)) {
+ fastboot_fail("failed to erase partition\n");
+ return;
+ }
+ } else {
+ BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
+ size = partition_get_size(index);
+ if (size > DEFAULT_ERASE_SIZE)
+ size = DEFAULT_ERASE_SIZE;
- /* Simple inefficient version of erase. Just writing
- 0 in first several blocks */
- if (mmc_write(ptn , size, (unsigned int *)out)) {
- fastboot_fail("failed to erase partition");
- return;
+ /* Simple inefficient version of erase. Just writing
+ 0 in first several blocks */
+ if (mmc_write(ptn , size, (unsigned int *)out)) {
+ fastboot_fail("failed to erase partition");
+ return;
+ }
}
-#endif
fastboot_okay("");
}
@@ -2292,19 +2316,21 @@
|| !strcmp(ptn->name, "persist")
|| !strcmp(ptn->name, "recoveryfs")
|| !strcmp(ptn->name, "modem"))
- {
- if (memcmp((void *)data, UBI_MAGIC, UBI_MAGIC_SIZE))
- extra = 1;
- else
- extra = 0;
- }
+ extra = 1;
else
sz = ROUND_TO_PAGE(sz, page_mask);
dprintf(INFO, "writing %d bytes to '%s'\n", sz, ptn->name);
- if (flash_write(ptn, extra, data, sz)) {
- fastboot_fail("flash write failure");
- return;
+ if (!memcmp((void *)data, UBI_MAGIC, UBI_MAGIC_SIZE)) {
+ if (flash_ubi_img(ptn, data, sz)) {
+ fastboot_fail("flash write failure");
+ return;
+ }
+ } else {
+ if (flash_write(ptn, extra, data, sz)) {
+ fastboot_fail("flash write failure");
+ return;
+ }
}
dprintf(INFO, "partition '%s' updated\n", ptn->name);
fastboot_okay("");
@@ -2323,6 +2349,12 @@
fastboot_okay("");
fastboot_stop();
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
if (target_is_emmc_boot())
{
boot_linux_from_mmc();
@@ -2503,6 +2535,7 @@
struct fbimage *logo = NULL;
uint32_t blocksize;
uint32_t readsize;
+ uint32_t logosize;
uint32_t ptn_size;
index = partition_get_index("splash");
@@ -2519,12 +2552,12 @@
ptn_size = partition_get_size(index);
blocksize = mmc_get_device_blocksize();
- readsize = ROUNDUP(sizeof(logo->header), blocksize);
+ logosize = ROUNDUP(sizeof(logo->header), blocksize);
- logo = (struct fbimage *)memalign(CACHE_LINE, ROUNDUP(readsize, CACHE_LINE));
+ logo = (struct fbimage *)memalign(CACHE_LINE, ROUNDUP(logosize, CACHE_LINE));
ASSERT(logo);
- if (mmc_read(ptn, (uint32_t *) logo, readsize)) {
+ if (mmc_read(ptn, (uint32_t *) logo, logosize)) {
dprintf(CRITICAL, "ERROR: Cannot read splash image header\n");
goto err;
}
@@ -2549,7 +2582,7 @@
goto err;
}
- if (mmc_read(ptn + sizeof(logo->header),(uint32_t *)base, readsize)) {
+ if (mmc_read(ptn + logosize,(uint32_t *)base, readsize)) {
fbcon_clear();
dprintf(CRITICAL, "ERROR: Cannot read splash image from partition\n");
goto err;
@@ -2700,6 +2733,7 @@
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
+ unsigned hard_reboot_mode = 0;
bool boot_into_fastboot = false;
/* Setup page size information for nv storage */
@@ -2767,11 +2801,15 @@
#endif
reboot_mode = check_reboot_mode();
- if (reboot_mode == RECOVERY_MODE) {
+ hard_reboot_mode = check_hard_reboot_mode();
+ if (reboot_mode == RECOVERY_MODE ||
+ hard_reboot_mode == RECOVERY_HARD_RESET_MODE) {
boot_into_recovery = 1;
- } else if(reboot_mode == FASTBOOT_MODE) {
+ } else if(reboot_mode == FASTBOOT_MODE ||
+ hard_reboot_mode == FASTBOOT_HARD_RESET_MODE) {
boot_into_fastboot = true;
- } else if(reboot_mode == ALARM_BOOT) {
+ } else if(reboot_mode == ALARM_BOOT ||
+ hard_reboot_mode == RTC_HARD_RESET_MODE) {
boot_reason_alarm = true;
}
@@ -2794,6 +2832,13 @@
#endif
}
}
+
+#ifdef MDTP_SUPPORT
+ /* Go through Firmware Lock verification before continue with boot process */
+ mdtp_fwlock_verify_lock();
+ fbcon_clear();
+#endif /* MDTP_SUPPORT */
+
boot_linux_from_mmc();
}
else
diff --git a/app/aboot/mdtp.c b/app/aboot/mdtp.c
new file mode 100644
index 0000000..60b97b0
--- /dev/null
+++ b/app/aboot/mdtp.c
@@ -0,0 +1,545 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <dev/fbcon.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <platform.h>
+#include <crypto_hash.h>
+#include <malloc.h>
+#include <sha.h>
+#include <string.h>
+#include <rand.h>
+#include <stdlib.h>
+#include "scm.h"
+#include "mdtp.h"
+
+#define DIP_ENCRYPT 0
+#define DIP_DECRYPT 1
+
+static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified);
+static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip);
+
+/********************************************************************************/
+
+/* Read the DIP from EMMC */
+static int read_DIP(DIP_t *dip)
+{
+ unsigned long long ptn = 0;
+ uint32_t actual_partition_size;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ int index = INVALID_PTN;
+
+ ASSERT(dip != NULL);
+
+ index = partition_get_index("dip");
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ actual_partition_size = ROUNDUP(sizeof(DIP_t), block_size);
+
+ if(mmc_read(ptn, (void *)dip, actual_partition_size))
+ {
+ dprintf(CRITICAL, "mdtp: read_DIP: ERROR, cannot read DIP info\n");
+ return -1;
+ }
+
+ dprintf(INFO, "mdtp: read_DIP: SUCCESS, read %d bytes\n", actual_partition_size);
+
+ return 0;
+}
+
+/* Store the DIP into the EMMC */
+static int write_DIP(DIP_t *dip)
+{
+ unsigned long long ptn = 0;
+ uint32_t partition_size;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ int index = INVALID_PTN;
+
+ ASSERT(dip != NULL);
+
+ index = partition_get_index("dip");
+ ptn = partition_get_offset(index);
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ partition_size = partition_get_size(index);
+
+ if(partition_size < size)
+ {
+ dprintf(CRITICAL, "mdtp: write_DIP: ERROR, DIP partition too small\n");
+ return -1;
+ }
+
+ if(mmc_write(ptn, ROUNDUP(size, block_size), (void *)dip))
+ {
+ dprintf(CRITICAL, "mdtp: write_DIP: ERROR, cannot read DIP info\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Provision the DIP by storing the default DIP into the EMMC */
+static void provision_DIP()
+{
+ DIP_t *enc_dip;
+ DIP_t *dec_dip;
+ int ret;
+
+ enc_dip = malloc(sizeof(DIP_t));
+ if (enc_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ return;
+ }
+
+ dec_dip = malloc(sizeof(DIP_t));
+ if (dec_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ free(enc_dip);
+ return;
+ }
+
+ memset(dec_dip, 0, sizeof(DIP_t));
+
+ dec_dip->status = DIP_STATUS_DEACTIVATED;
+
+ ret = mdtp_tzbsp_enc_hash_DIP(dec_dip, enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot cipher DIP\n");
+ goto out;
+ }
+
+ ret = write_DIP(enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot write DIP\n");
+ goto out;
+ }
+
+ ret = mdtp_tzbsp_set_provisioned_fuse();
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot set DIP_PROVISIONED fuse\n\n");
+ goto out;
+ }
+
+out:
+ free(enc_dip);
+ free(dec_dip);
+}
+
+/* Validate a hash calculated on entire given partition */
+static int verify_partition_single_hash(char *name, uint32_t size, DIP_hash_table_entry_t *hash_table)
+{
+ unsigned char digest[32]={0};
+ unsigned long long ptn = 0;
+ int index = INVALID_PTN;
+ unsigned char *buf = (unsigned char *)target_get_scratch_address();
+ uint32_t block_size = mmc_get_device_blocksize();
+ uint32_t actual_partition_size = ROUNDUP(size, block_size);
+
+ dprintf(INFO, "mdtp: verify_partition_single_hash: %s, %u\n", name, size);
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ index = partition_get_index(name);
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0) {
+ dprintf(CRITICAL, "mdtp: verify_partition_single_hash: %s: partition was not found\n", name);
+ return -1;
+ }
+
+ if (mmc_read(ptn, (void *)buf, actual_partition_size))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition__single_hash: %s: mmc_read() fail.\n", name);
+ return -1;
+ }
+
+ /* calculating the hash value using HW crypto */
+ target_crypto_init_params();
+ hash_find(buf, size, (unsigned char *)&digest, CRYPTO_AUTH_ALG_SHA256);
+
+ if (memcmp(&digest[0], &(hash_table->hash[0]), HASH_LEN))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_single_hash: %s: Failed partition hash verification\n", name);
+
+ return -1;
+ }
+
+ dprintf(INFO, "verify_partition_single_hash: %s: VERIFIED!\n", name);
+
+ return 0;
+}
+
+/* Validate a hash table calculated per block of a given partition */
+static int verify_partition_block_hash(char *name,
+ uint32_t size,
+ uint32_t total_num_blocks,
+ uint32_t verify_num_blocks,
+ DIP_hash_table_entry_t *hash_table,
+ uint8_t *force_verify_block)
+{
+ unsigned char digest[32]={0};
+ unsigned long long ptn = 0;
+ int index = INVALID_PTN;
+ unsigned char *buf = (unsigned char *)target_get_scratch_address();
+ uint32_t bytes_to_read;
+ uint32_t block_num = 0;
+
+ dprintf(INFO, "mdtp: verify_partition_block_hash: %s, %u\n", name, size);
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ index = partition_get_index(name);
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0) {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: partition was not found\n", name);
+ return -1;
+ }
+
+ /* initiating parameters for hash calculation using HW crypto */
+ target_crypto_init_params();
+
+ while (MDTP_FWLOCK_BLOCK_SIZE * block_num < size)
+ {
+ if (*force_verify_block == 0)
+ {
+ /* Skip validation of this block with probability of verify_num_blocks / total_num_blocks */
+ if ((rand() % total_num_blocks) >= verify_num_blocks)
+ {
+ block_num++;
+ hash_table += 1;
+ force_verify_block += 1;
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: skipped verification of block %d\n", name, block_num);
+ continue;
+ }
+ }
+
+ if ((size - (MDTP_FWLOCK_BLOCK_SIZE * block_num) < MDTP_FWLOCK_BLOCK_SIZE))
+ {
+ bytes_to_read = size - (MDTP_FWLOCK_BLOCK_SIZE * block_num);
+ } else
+ {
+ bytes_to_read = MDTP_FWLOCK_BLOCK_SIZE;
+ }
+
+ if (mmc_read(ptn + (MDTP_FWLOCK_BLOCK_SIZE * block_num), (void *)buf, bytes_to_read))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: mmc_read() fail.\n", name);
+ return -1;
+ }
+
+ /* calculating the hash value using HW */
+ hash_find(buf, bytes_to_read, (unsigned char *)&digest, CRYPTO_AUTH_ALG_SHA256);
+
+ if (memcmp(&digest[0], &(hash_table->hash[0]), HASH_LEN))
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition_block_hash: %s: Failed partition hash[%d] verification\n", name, block_num);
+ return -1;
+ }
+
+ block_num++;
+ hash_table += 1;
+ force_verify_block += 1;
+ }
+
+ dprintf(INFO, "verify_partition_block_hash: %s: VERIFIED!\n", name);
+
+ return 0;
+}
+
+/* Verify a given partitinon */
+static int verify_partition(char *name,
+ uint32_t size,
+ mdtp_fwlock_mode_t hash_mode,
+ uint32_t total_num_blocks,
+ uint32_t verify_num_blocks,
+ DIP_hash_table_entry_t *hash_table,
+ uint8_t *force_verify_block)
+{
+
+ ASSERT(name != NULL);
+ ASSERT(hash_table != NULL);
+
+ if (hash_mode == MDTP_FWLOCK_MODE_SINGLE)
+ {
+ return verify_partition_single_hash(name, size, hash_table);
+ } else if (hash_mode == MDTP_FWLOCK_MODE_BLOCK || hash_mode == MDTP_FWLOCK_MODE_FILES)
+ {
+ return verify_partition_block_hash(name, size, total_num_blocks, verify_num_blocks, hash_table, force_verify_block);
+ }
+ else
+ {
+ dprintf(CRITICAL, "mdtp: verify_partition: %s: Wrong DIP partition hash mode\n", name);
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Verify all protected partitinons according to the DIP */
+static int verify_all_partitions(DIP_t *dip, verify_result_t *verify_result)
+{
+ int i;
+ int verify_failure = 0;
+ uint32_t total_num_blocks;
+
+ ASSERT(dip != NULL);
+ ASSERT(verify_result != NULL);
+
+ *verify_result = VERIFY_FAILED;
+
+ if (dip->status == DIP_STATUS_DEACTIVATED)
+ {
+ *verify_result = VERIFY_SKIPPED;
+ return 0;
+ }
+ else if (dip->status == DIP_STATUS_ACTIVATED)
+ {
+ show_checking_msg();
+
+ for(i=0; i<MAX_PARTITIONS; i++)
+ {
+ if(dip->partition_cfg[i].lock_enabled && dip->partition_cfg[i].size)
+ {
+ total_num_blocks = ((dip->partition_cfg[i].size - 1) / MDTP_FWLOCK_BLOCK_SIZE);
+
+ verify_failure |= verify_partition(dip->partition_cfg[i].name,
+ dip->partition_cfg[i].size,
+ dip->partition_cfg[i].hash_mode,
+ total_num_blocks,
+ (dip->partition_cfg[i].verify_ratio * total_num_blocks) / 100,
+ dip->partition_cfg[i].hash_table,
+ dip->partition_cfg[i].force_verify_block);
+ }
+ }
+
+ if (verify_failure)
+ {
+ dprintf(CRITICAL, "mdtp: verify_all_partitions: Failed partition verification\n");
+ show_invalid_msg();
+ return -1;
+ }
+
+ }
+
+ *verify_result = VERIFY_OK;
+ show_OK_msg();
+ return 0;
+}
+
+/* Verify the DIP and all protected partitions */
+static void validate_DIP_and_firmware()
+{
+ int ret;
+ DIP_t *enc_dip;
+ DIP_t *dec_dip;
+ uint32_t verified = 0;
+ verify_result_t verify_result;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ enc_dip = malloc(ROUNDUP(sizeof(DIP_t), block_size));
+ if (enc_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ return;
+ }
+
+ dec_dip = malloc(ROUNDUP(sizeof(DIP_t), block_size));
+ if (dec_dip == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: provision_DIP: ERROR, cannot allocate DIP\n");
+ free(enc_dip);
+ return;
+ }
+
+ /* Read the DIP holding the MDTP Firmware Lock state from the DIP partition */
+ ret = read_DIP(enc_dip);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot read DIP\n");
+ goto out;
+ }
+
+ /* Decrypt and verify the integrity of the DIP */
+ ret = mdtp_tzbsp_dec_verify_DIP(enc_dip, dec_dip, &verified);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot verify DIP\n");
+ show_invalid_msg();
+ goto out;
+ }
+
+ /* In case DIP integrity verification fails, notify the user and halt */
+ if(!verified)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, corrupted DIP\n");
+ show_invalid_msg();
+ goto out;
+ }
+
+ /* Verify the integrity of the partitions which are protectedm, according to the content of the DIP */
+ ret = verify_all_partitions(dec_dip, &verify_result);
+ if(ret < 0)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, cannot verify firmware\n");
+ goto out;
+ }
+
+ if (verify_result == VERIFY_OK)
+ {
+ dprintf(INFO, "mdtp: validate_DIP_and_firmware: Verify OK\n");
+ }
+ else if (verify_result == VERIFY_FAILED)
+ {
+ dprintf(CRITICAL, "mdtp: validate_DIP_and_firmware: ERROR, corrupted firmware\n");
+ } else /* VERIFY_SKIPPED */
+ {
+ dprintf(INFO, "mdtp: validate_DIP_and_firmware: Verify skipped\n");
+ }
+
+out:
+ free(enc_dip);
+ free(dec_dip);
+
+ return;
+}
+
+/********************************************************************************/
+
+/** Entry point of the MDTP Firmware Lock: If needed, verify the DIP
+ * and all protected partitions **/
+
+int mdtp_fwlock_verify_lock()
+{
+ int ret;
+ bool enabled;
+
+ ret = mdtp_fuse_get_enabled(&enabled);
+ if(ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_fwlock_verify_lock: ERROR, cannot get enabled fuse\n");
+ return -1;
+ }
+
+ /* Continue with Firmware Lock verification only if enabled by eFuse */
+ if (enabled)
+ {
+ validate_DIP_and_firmware();
+ }
+
+ return 0;
+}
+
+/********************************************************************************/
+
+/* Decrypt a given DIP and verify its integrity */
+static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified)
+{
+ unsigned char *hash_p;
+ unsigned char hash[HASH_LEN];
+ SHA256_CTX sha256_ctx;
+ int ret;
+
+ ASSERT(enc_dip != NULL);
+ ASSERT(dec_dip != NULL);
+ ASSERT(verified != NULL);
+
+ ret = mdtp_cipher_dip_cmd((uint8_t*)enc_dip, sizeof(DIP_t),
+ (uint8_t*)dec_dip, sizeof(DIP_t),
+ DIP_DECRYPT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_tzbsp_dec_verify_DIP: ERROR, cannot cipher DIP\n");
+ *verified = 0;
+ return -1;
+ }
+
+ SHA256_Init(&sha256_ctx);
+ SHA256_Update(&sha256_ctx, dec_dip, sizeof(DIP_t) - HASH_LEN);
+ SHA256_Final(hash, &sha256_ctx);
+
+ hash_p = (unsigned char*)dec_dip + sizeof(DIP_t) - HASH_LEN;
+
+ if (memcmp(hash, hash_p, HASH_LEN))
+ {
+ *verified = 0;
+ }
+ else
+ {
+ *verified = 1;
+ }
+
+ return 0;
+}
+
+static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip)
+{
+ unsigned char *hash_p;
+ SHA256_CTX sha256_ctx;
+ int ret;
+
+ ASSERT(dec_dip != NULL);
+ ASSERT(enc_dip != NULL);
+
+ hash_p = (unsigned char*)dec_dip + sizeof(DIP_t) - HASH_LEN;
+
+ SHA256_Init(&sha256_ctx);
+ SHA256_Update(&sha256_ctx, dec_dip, sizeof(DIP_t) - HASH_LEN);
+ SHA256_Final(hash_p, &sha256_ctx);
+
+ ret = mdtp_cipher_dip_cmd((uint8_t*)dec_dip, sizeof(DIP_t),
+ (uint8_t*)enc_dip, sizeof(DIP_t),
+ DIP_ENCRYPT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_tzbsp_enc_hash_DIP: ERROR, cannot cipher DIP\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/app/aboot/mdtp.h b/app/aboot/mdtp.h
new file mode 100644
index 0000000..9975899
--- /dev/null
+++ b/app/aboot/mdtp.h
@@ -0,0 +1,122 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __APP_MDTP_H
+#define __APP_MDTP_H
+
+#define TOKEN_LEN 16
+#define MAX_BLOCKS 512
+#define MAX_PARTITIONS 3
+#define MAX_PARTITION_NAME_LEN 100
+#define HASH_LEN 32
+#define MDTP_MAX_PIN_LEN 8
+#define DIP_PADDING 11
+
+#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
+#define MDTP_FWLOCK_BLOCK_SIZE (1024*1024*16)
+#define MDTP_FWLOCK_MAX_FILES (100)
+#define MDTP_FWLOCK_MAX_FILE_NAME_LEN (100)
+
+#pragma pack(push, mdtp, 1)
+
+typedef enum {
+ DIP_STATUS_DEACTIVATED = 0,
+ DIP_STATUS_ACTIVATED,
+ DIP_STATUS_SIZE = 0x7FFFFFFF
+} dip_status_t;
+
+typedef enum {
+ MDTP_FWLOCK_MODE_SINGLE = 0,
+ MDTP_FWLOCK_MODE_BLOCK,
+ MDTP_FWLOCK_MODE_FILES,
+ MDTP_FWLOCK_MODE_SIZE = 0x7FFFFFFF
+} mdtp_fwlock_mode_t;
+
+typedef struct DIP_hash_table_entry {
+ unsigned char hash[HASH_LEN]; /* Hash on block */
+} DIP_hash_table_entry_t;
+
+typedef struct DIP_partition_cfg {
+ uint32_t size; /* DIP size */
+ char name[MAX_PARTITION_NAME_LEN]; /* Partition name */
+ uint8_t lock_enabled; /* Image locked? */
+ mdtp_fwlock_mode_t hash_mode; /* Hash per IMAGE or BLOCK */
+ uint8_t force_verify_block[MAX_BLOCKS]; /* Verify only given block numbers. */
+ char files_to_protect[MDTP_FWLOCK_MAX_FILES][MDTP_FWLOCK_MAX_FILE_NAME_LEN]; /* Verify given files */
+ uint32_t verify_ratio; /* Statistically verify this ratio of blocks */
+ DIP_hash_table_entry_t hash_table[MAX_BLOCKS]; /* Hash table */
+} DIP_partition_cfg_t;
+
+typedef struct mdtp_pin {
+ char mdtp_pin[MDTP_MAX_PIN_LEN+1]; /* A null terminated PIN. */
+} mdtp_pin_t;
+
+/** MDTP configuration. */
+typedef struct mdtp_cfg {
+ uint8_t enable_local_pin_authentication;/* Allow local authentication using a PIN. */
+ mdtp_pin_t mdtp_pin; /* Null terminated PIN provided by the user for local deactivation.
+ PIN length should be from MDTP_MIN_PIN_LEN to MDTP_MAX_PIN_LEN digits. */
+} mdtp_cfg_t;
+
+typedef struct DIP {
+ /* Management area of the DIP */
+ uint32_t version; /* DIP version */
+ dip_status_t status; /* DIP activated/deactivated */
+ mdtp_cfg_t mdtp_cfg; /* MDTP configuration, such as PIN */
+
+ /* Firmware Lock area of the DIP */
+ DIP_partition_cfg_t partition_cfg[MAX_PARTITIONS]; /* Config for each partition */
+
+ /* Footer area of the DIP */
+ uint8_t padding[DIP_PADDING]; /* Pad to multiple of 16 bytes */
+ unsigned char hash[HASH_LEN]; /* DIP integrity */
+} DIP_t;
+
+#pragma pack(pop, mdtp)
+typedef enum {
+ VERIFY_SKIPPED = 0,
+ VERIFY_OK,
+ VERIFY_FAILED,
+} verify_result_t;
+
+/* Start Firmware Lock verification process */
+int mdtp_fwlock_verify_lock();
+
+/* Return whether the MDTP is currently enabled or disabled in HW */
+int mdtp_fuse_get_enabled(bool *enabled);
+
+/* Display the "Firmware Valid" screen */
+void show_OK_msg();
+
+/* Display the "Firmware Invalid" screen */
+void show_invalid_msg();
+
+/* Display the "Verifying Firmware" screen */
+void show_checking_msg();
+
+#endif
diff --git a/app/aboot/mdtp_fuse.c b/app/aboot/mdtp_fuse.c
new file mode 100644
index 0000000..c4abd19
--- /dev/null
+++ b/app/aboot/mdtp_fuse.c
@@ -0,0 +1,257 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "mdtp.h"
+#include "scm.h"
+
+#define MAX_EFUSES (8)
+#define EFUSE_END (MDTP_EFUSE_START + MAX_EFUSES - 1)
+#define MAX_METADATA_SIZE (0x1000)
+#define QFPROM_ADDR_SPACE_RAW (0)
+
+/********************************************************************************/
+
+typedef union
+{
+ struct {
+ uint8_t enable1 : 1;
+ uint8_t disable1 : 1;
+ uint8_t enable2 : 1;
+ uint8_t disable2 : 1;
+ uint8_t enable3 : 1;
+ uint8_t disable3 : 1;
+ uint8_t reserved1 : 1;
+ uint8_t reserved2 : 1;
+ } bitwise;
+ uint8_t mask;
+} mdtp_eFuses_t;
+
+typedef struct metadata {
+ mdtp_eFuses_t eFuses;
+} metadata_t;
+
+/********************************************************************************/
+
+/**
+ * Checks if we are in test mode according to relevant eFuses
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int is_test_mode(void)
+{
+ static int test_mode_set = 0;
+ static int test_mode = 0;
+ int ret = 0;
+ uint32_t status_low = 0;
+ uint32_t status_high = 0;
+
+#define SECBOOT_FUSE 0x01
+#define SHK_FUSE 0x02
+#define DEBUG_FUSE 0x04
+
+ /* Make sure we only read the test mode once */
+ if (test_mode_set)
+ return test_mode;
+
+ ret = scm_svc_get_secure_state(&status_low, &status_high);
+
+ if(ret == 0)
+ {
+ /* (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE) implies that none of the fuses are blown */
+ if((status_low & (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE)) == (SECBOOT_FUSE | SHK_FUSE | DEBUG_FUSE))
+ test_mode = 1;
+ }
+ else
+ {
+ dprintf(CRITICAL, "mdtp: is_test_mode: qsee_get_secure_state returned error: %d, status.value[0]: %d", ret, status_low);
+ test_mode = 0;
+ }
+
+ test_mode_set = 1;
+ dprintf(INFO, "mdtp: is_test_mode: test mode is set to %d", test_mode);
+
+ return test_mode;
+}
+
+/**
+ * Read the Firmware Lock Metadata from EMMC
+ *
+ * @param metadata - Read a metadata block holding eFuse emulation from MDTP partition.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_metadata(metadata_t *metadata)
+{
+ unsigned long long ptn = 0;
+ uint32_t actual_size;
+ char metadata_block[MAX_METADATA_SIZE];
+ int index = INVALID_PTN;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ ptn = partition_get_offset(index);
+
+ if(ptn == 0)
+ {
+ return -1;
+ }
+
+ if (sizeof(metadata_t) > MAX_METADATA_SIZE)
+ {
+ dprintf(CRITICAL, "mdtp: read_metadata: ERROR, meta data size %d too big\n", sizeof(metadata_t));
+ return -1;
+ }
+
+ actual_size = ROUNDUP(MAX_METADATA_SIZE, block_size);
+
+ if(mmc_read(ptn, (void *)metadata_block, actual_size))
+ {
+ dprintf(CRITICAL, "mdtp: read_metadata: ERROR, cannot read mdtp info\n");
+ return -1;
+ }
+
+ memcpy(metadata, metadata_block, sizeof(metadata_t));
+
+ dprintf(INFO, "mdtp: read_metadata: SUCCESS, read %d bytes\n", actual_size);
+
+ return 0;
+}
+
+/**
+ * read_QFPROM_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_QFPROM_fuse(uint8_t *mask)
+{
+ static const uint32_t row_address = MDTP_EFUSE_ADDRESS;
+ uint32_t addr_type = QFPROM_ADDR_SPACE_RAW;
+ uint32_t row_data[2] = {0};
+ uint32_t qfprom_api_status = 0;
+
+ /* Read the current row where the eFuse is located */
+ (void) qfprom_read_row_cmd(row_address, addr_type, row_data, &qfprom_api_status);
+ if (qfprom_api_status)
+ {
+ dprintf(CRITICAL, "mdtp: write_QFPROM_fuse: qsee_fuse_read failed. qfprom_api_status=%d", qfprom_api_status);
+ return -1;
+ }
+
+ /* Shift the read data to be reflected in mask */
+ *mask = (uint8_t)(row_data[0] >> MDTP_EFUSE_START);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * read_test_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_test_fuse(uint8_t *mask)
+{
+ int status = 0;
+ metadata_t metadata;
+
+ status = read_metadata(&metadata);
+ if (status) {
+ dprintf(CRITICAL, "mdtp: read_test_fuse: Failure getting metadata");
+ return -1;
+ }
+
+ *mask = metadata.eFuses.mask;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * read_fuse
+ *
+ * @param mask[out] - MDTP efuse value represented by a bitfield.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+static int read_fuse(uint8_t *mask)
+{
+ if (is_test_mode())
+ return read_test_fuse(mask);
+ else
+ return read_QFPROM_fuse(mask);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * mdtp_fuse_get_enabled
+ *
+ * Read the Firmware Lock eFuses and return whether the Firmware
+ * Lock is currently enabled or disabled in HW.
+ *
+ * @param[out] enabled: 0 - enable, 1 - disable.
+ *
+ * @return - negative value for an error, 0 for success.
+ */
+int mdtp_fuse_get_enabled(bool *enabled)
+{
+ int status;
+ mdtp_eFuses_t eFuses;
+
+ status = read_fuse(&eFuses.mask);
+ if (status)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_fuse_get_enabled: Failure in reading fuse");
+ return -1;
+ }
+
+ if ((eFuses.bitwise.enable1 && !eFuses.bitwise.disable1) ||
+ (eFuses.bitwise.enable2 && !eFuses.bitwise.disable2) ||
+ (eFuses.bitwise.enable3 && !eFuses.bitwise.disable3))
+ {
+ *enabled = 1;
+ }
+ else
+ *enabled = 0;
+
+ return 0;
+}
+
diff --git a/app/aboot/mdtp_ui.c b/app/aboot/mdtp_ui.c
new file mode 100644
index 0000000..30d70d6
--- /dev/null
+++ b/app/aboot/mdtp_ui.c
@@ -0,0 +1,301 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <dev/fbcon.h>
+#include <target.h>
+#include <mmc.h>
+#include <partition_parser.h>
+#include <stdlib.h>
+#include "mdtp.h"
+
+#define MDTP_IMAGE_WIDTH 500
+#define MDTP_IMAGE_HEIGHT 800
+#define MDTP_UX_DELAY 1000
+#define MDTP_OK_OFFSET 0x0
+#define MDTP_CHECKING_OFFSET 0x200000
+#define MDTP_INVALID_OFFSET 0x400000
+#define MDTP_RECOVERED_OFFSET 0x600000
+
+extern uint32_t target_volume_down(void);
+extern void fbcon_putImage(struct fbimage *fbimg, bool flag);
+extern void mdelay(unsigned msecs);
+
+static struct fbimage mdtp_header;/* = {0};*/
+
+/********************************************************************************/
+
+/* Load the "Firmware Valid" image from EMMC */
+static struct fbimage* mdtp_images_mmc_OK()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Firmware Invalid" image from EMMC */
+static struct fbimage* mdtp_images_mmc_INVALID()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_INVALID_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Verifying Firmware" image from EMMC */
+static struct fbimage* mdtp_images_mmc_CHECKING()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_CHECKING_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Load the "Verifying Firmware" image from EMMC */
+static struct fbimage* mdtp_images_mmc_RECOVERED()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &mdtp_header;
+ uint32_t block_size = mmc_get_device_blocksize();
+
+ index = partition_get_index("mdtp");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: mdtp Partition invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display)
+ {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn+MDTP_RECOVERED_OFFSET, (void*)base, ROUNDUP(MDTP_IMAGE_WIDTH*MDTP_IMAGE_HEIGHT*3, block_size))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: mdtp image read failed\n");
+ return NULL;
+ }
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+/* Show the "Firmware Valid" image */
+static void display_image_on_screen_OK()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_OK();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_OK\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Firmware Invalid" image */
+static void display_image_on_screen_INVALID()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_INVALID();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_INVALID\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Verifying Firmware" image */
+static void display_image_on_screen_CHECKING()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_CHECKING();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_CHECKING\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Show the "Verifying Firmware" image */
+static void display_image_on_screen_RECOVERED()
+{
+ struct fbimage *fbimg;
+
+ fbcon_clear();
+ fbimg = mdtp_images_mmc_RECOVERED();
+ fbimg->header.width = MDTP_IMAGE_WIDTH;
+ fbimg->header.height = MDTP_IMAGE_HEIGHT;
+
+ dprintf(CRITICAL, "display_image_on_screen_RECOVERED\n");
+ fbcon_putImage(fbimg, true);
+}
+
+/* Display the "Firmware Valid" screen */
+void show_OK_msg()
+{
+ display_image_on_screen_OK();
+ mdelay(MDTP_UX_DELAY);
+
+ return;
+}
+
+/* Display the "Firmware Invalid" screen */
+void show_invalid_msg()
+{
+ display_image_on_screen_INVALID();
+
+ while (1)
+ {
+ if(target_volume_down())
+ {
+ display_image_on_screen_RECOVERED();
+ mdelay(MDTP_UX_DELAY);
+ break;
+ }
+ }
+
+ return;
+}
+
+/* Display the "Verifying Firmware" screen */
+void show_checking_msg()
+{
+ display_image_on_screen_CHECKING();
+ return;
+}
+
+/* Display the "Verifying Firmware" screen */
+void show_recovered_msg()
+{
+ display_image_on_screen_RECOVERED();
+ return;
+}
+
diff --git a/app/aboot/rules.mk b/app/aboot/rules.mk
index 5342d7a..95a8865 100644
--- a/app/aboot/rules.mk
+++ b/app/aboot/rules.mk
@@ -9,3 +9,9 @@
$(LOCAL_DIR)/fastboot.o \
$(LOCAL_DIR)/recovery.o
+ifeq ($(ENABLE_MDTP_SUPPORT),1)
+OBJS += \
+ $(LOCAL_DIR)/mdtp.o \
+ $(LOCAL_DIR)/mdtp_ui.o \
+ $(LOCAL_DIR)/mdtp_fuse.o
+endif
diff --git a/arch/arm/arch.c b/arch/arm/arch.c
index dc171b4..6b5cf72 100644
--- a/arch/arm/arch.c
+++ b/arch/arm/arch.c
@@ -25,6 +25,7 @@
#include <arch/ops.h>
#include <arch/arm.h>
#include <arch/arm/mmu.h>
+#include <arch/defines.h>
#include <platform.h>
#if ARM_CPU_CORTEX_A8
@@ -59,6 +60,8 @@
val |= (3<<22)|(3<<20);
__asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
+ isb();
+
/* set enable bit in fpexc */
__asm__ volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (val));
val |= (1<<30);
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 22d9a2b..cfcbaa4 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -328,6 +328,7 @@
/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
FUNCTION(arch_clean_invalidate_cache_range)
+ dsb
add r2, r0, r1 // Calculate the end address
bic r0,#(CACHE_LINE-1) // Align start with cache line
0:
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index e95036e..ce79a3e 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,6 +35,7 @@
#include <splash.h>
#include <platform.h>
#include <string.h>
+#include <arch/ops.h>
#include "font5x12.h"
@@ -300,6 +301,8 @@
memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
logo_base + (i * pitch * bytes_per_bpp), width * bytes_per_bpp);
}
+ /* Flush the contents to memory before giving the data to dma */
+ arch_clean_invalidate_cache_range((addr_t) config->base, (total_x * total_y * bytes_per_bpp));
}
fbcon_flush();
@@ -323,6 +326,8 @@
(header->height * bytes_per_bpp));
}
}
+ /* Flush the contents to memory before giving the data to dma */
+ arch_clean_invalidate_cache_range((addr_t) config->base, (total_x * total_y * bytes_per_bpp));
fbcon_flush();
#endif
}
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 646d575..2794203 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -56,16 +56,20 @@
pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width +
pinfo->lcdc.yres_pad;
- /* Pixel clock rate */
- pll_data.pixel_clock = h_period * v_period * pinfo->mipi.frame_rate;
-
- /* Store all bit clock form data */
+ /*
+ * If a bit clock rate is not specified, calculate it based
+ * on panel parameters
+ */
if (pinfo->mipi.bitclock == 0)
- pll_data.bit_clock = (pll_data.pixel_clock * pinfo->bpp) /
- pinfo->mipi.num_of_lanes;
+ pll_data.bit_clock = (h_period * v_period *
+ pinfo->mipi.frame_rate * pinfo->bpp) /
+ pinfo->mipi.num_of_lanes;
else
pll_data.bit_clock = pinfo->mipi.bitclock;
+ pll_data.pixel_clock = (pll_data.bit_clock * pinfo->mipi.num_of_lanes) /
+ pinfo->bpp;
+
pll_data.byte_clock = pll_data.bit_clock >> 3;
pll_data.halfbit_clock = pll_data.bit_clock >> 1;
@@ -144,7 +148,7 @@
{
uint32_t refclk = 19200000;
uint32_t vco_rate = pll_data.vco_clock;
- uint32_t tmp;
+ uint32_t tmp, mod;
vco_rate /= 2;
pll_data.dec_start = vco_rate / refclk;
@@ -157,11 +161,22 @@
pll_data.frac_start = tmp;
vco_rate *= 2; /* restore */
- tmp = vco_rate / (refclk / 1000);/* div 1000 first */
- tmp *= 1024;
- tmp /= 1000;
- tmp /= 10;
- pll_data.lock_comp = tmp - 1;
+ if (pll_data.en_vco_zero_phase) {
+ tmp = vco_rate / (refclk / 1000);/* div 1000 first */
+ tmp *= 1024;
+ tmp /= 1000;
+ tmp /= 10;
+ pll_data.lock_comp = tmp - 1;
+ } else {
+ tmp = vco_rate / refclk;
+ mod = vco_rate % refclk;
+ tmp *= 127;
+ mod *= 127;
+ mod /= refclk;
+ tmp += mod;
+ tmp /= 10;
+ pll_data.lock_comp = tmp;
+ }
dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
@@ -199,6 +214,24 @@
return NO_ERROR;
}
+#ifndef DISPLAY_EN_20NM_PLL_90_PHASE
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 300000000;
+ pll_data.vco_max = 1500000000;
+ pll_data.en_vco_zero_phase = 1;
+ dprintf(SPEW, "%s: Configured VCO for zero phase\n", __func__);
+}
+#else
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 1000000000;
+ pll_data.vco_max = 2000000000;
+ pll_data.en_vco_zero_phase = 0;
+ dprintf(SPEW, "%s: Configured VCO for 90 phase\n", __func__);
+}
+#endif
+
static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
{
uint32_t vco, dsi_clk;
@@ -231,12 +264,12 @@
hr_oclk2 = 4;
/* If bitclock is more than VCO min value */
- if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+ if (pll_data.halfbit_clock >= ((pll_data.vco_min) >> 1)) {
/* Direct Mode */
vco = pll_data.halfbit_clock << 1;
/* support vco clock to max value only */
- if (vco > VCO_MAX_CLOCK_20NM)
- vco = VCO_MAX_CLOCK_20NM;
+ if (vco > (pll_data.vco_max))
+ vco = (pll_data.vco_max);
pll_data.directpath = 0x0;
pll_data.byte_clock = vco / 2 / hr_oclk2;
@@ -245,8 +278,8 @@
hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
} else {
/* Indirect Mode */
- mod = VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
- ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+ mod = (pll_data.vco_min) % (4 * pll_data.halfbit_clock );
+ ndiv = (pll_data.vco_min) / (4 * pll_data.halfbit_clock );
if (mod)
ndiv += 1;
@@ -284,6 +317,9 @@
calculate_bitclock(pinfo);
if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+ config_20nm_pll_vco_range();
+
+ if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
else
ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index b261a34..aca4463 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,11 +43,6 @@
#define HALFBIT_CLOCK3 44000000 /* VCO min clock div by 8 */
#define HALFBIT_CLOCK4 40000000 /* VCO min clock div by 9 */
-#define VCO_MIN_CLOCK_20NM 300000000
-#define VCO_MAX_CLOCK_20NM 1500000000
-
-#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
-
#define HALFBIT_CLOCK1_20NM 500000000 /* VCO min clock div by 2 */
#define HALFBIT_CLOCK2_20NM 250000000 /* VCO min clock div by 4 */
#define HALFBIT_CLOCK3_20NM 125000000 /* VCO min clock div by 8 */
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 7d97842..4a49b1b 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,6 +39,7 @@
#include <qtimer.h>
#include <platform/gpio.h>
#include <mipi_dsi.h>
+#include <partition_parser.h>
#include "include/display_resource.h"
#include "include/panel.h"
@@ -82,12 +83,10 @@
uint32_t ret = NO_ERROR;
ret = calculate_clock_config(pinfo);
- if (ret) {
- dprintf(CRITICAL, "Clock calculation failed \n");
- /* should it stop here ? check with display team */
- }
-
- ret = target_panel_clock(enable, pinfo);
+ if (ret)
+ dprintf(CRITICAL, "Clock calculation failed\n");
+ else
+ ret = target_panel_clock(enable, pinfo);
return ret;
}
@@ -151,6 +150,172 @@
return ret;
}
+static int mdss_dsi_dfps_get_pll_codes_cal(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ uint32_t fps_bak;
+ uint32_t i;
+
+ fps_bak = pinfo->mipi.frame_rate;
+
+ for (i = 0; i < pinfo->dfps.panel_dfps.frame_rate_cnt; i++) {
+ int err;
+ pinfo->mipi.frame_rate = pinfo->dfps.panel_dfps.frame_rate[i];
+
+ err = mdss_dsi_panel_clock(1, pinfo);
+ if (!err) {
+ pinfo->dfps.codes_dfps[i].is_valid = 1;
+ pinfo->dfps.codes_dfps[i].frame_rate =
+ pinfo->mipi.frame_rate;
+ pinfo->dfps.codes_dfps[i].frame_rate =
+ pinfo->mipi.frame_rate;
+ pinfo->dfps.codes_dfps[i].clk_rate =
+ pinfo->mipi.dsi_pll_config->vco_clock;
+ pinfo->dfps.codes_dfps[i].pll_codes =
+ pinfo->mipi.pll_codes;
+
+ mdss_dsi_panel_clock(0, pinfo);
+ } else {
+ ret = err;
+ pinfo->dfps.codes_dfps[i].is_valid = 0;
+ dprintf(CRITICAL, "frame_rate=%d failed!\n",
+ pinfo->mipi.frame_rate);
+ }
+ }
+
+ pinfo->mipi.frame_rate = fps_bak;
+
+ return ret;
+}
+
+static int mdss_dsi_dfps_get_stored_pll_codes(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ int index;
+ unsigned long long ptn;
+ uint32_t blocksize;
+ struct dfps_info *dfps;
+
+ index = partition_get_index("splash");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition table not found\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition invalid offset\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ mmc_set_lun(partition_get_lun(index));
+
+ blocksize = mmc_get_device_blocksize();
+ if (blocksize == 0) {
+ dprintf(CRITICAL, "ERROR:splash Partition invalid blocksize\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ dfps = (struct dfps_info *)memalign(CACHE_LINE, ROUNDUP(PAGE_SIZE,
+ CACHE_LINE));
+ if (!dfps) {
+ dprintf(CRITICAL, "ERROR:splash Partition invalid memory\n");
+ ret = ERROR;
+ goto splash_err;
+ }
+
+ if (mmc_read(ptn, (uint32_t *) dfps, blocksize)) {
+ dprintf(CRITICAL, "mmc read splash failure%d\n", PAGE_SIZE);
+ ret = ERROR;
+ free(dfps);
+ goto splash_err;
+ }
+
+ dprintf(SPEW, "enable=%d cnt=%d\n", dfps->panel_dfps.enabled,
+ dfps->panel_dfps.frame_rate_cnt);
+
+ if (!dfps->panel_dfps.enabled || dfps->panel_dfps.frame_rate_cnt >
+ DFPS_MAX_FRAME_RATE) {
+ ret = ERROR;
+ free(dfps);
+ goto splash_err;
+ }
+
+ pinfo->dfps = *dfps;
+ free(dfps);
+
+splash_err:
+ return ret;
+}
+
+static int mdss_dsi_dfps_store_pll_codes(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ int index;
+ unsigned long long ptn;
+
+ index = partition_get_index("splash");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition table not found\n");
+ ret = ERROR;
+ goto store_err;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition invalid offset\n");
+ ret = ERROR;
+ goto store_err;
+ }
+
+ mmc_set_lun(partition_get_lun(index));
+
+ ret = mmc_write(ptn, sizeof(uint32_t), &pinfo->dfps);
+ if (ret)
+ dprintf(CRITICAL, "mmc write failed!\n");
+
+store_err:
+ return ret;
+}
+
+static int mdss_dsi_mipi_dfps_config(struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+
+ if (!pinfo)
+ return ERROR;
+
+ if (!pinfo->dfps.panel_dfps.enabled)
+ goto dfps_done;
+
+ if (!mdss_dsi_dfps_get_stored_pll_codes(pinfo)) {
+ dprintf(SPEW, "Found stored PLL codes!\n");
+ goto dfps_cal_done;
+ }
+
+ ret = mdss_dsi_dfps_get_pll_codes_cal(pinfo);
+ if (ret) {
+ dprintf(CRITICAL, "Cannot cal pll codes!\n");
+ goto dfps_done;
+ } else {
+ dprintf(SPEW, "Calibrate all pll codes!\n");
+ }
+
+ ret = mdss_dsi_dfps_store_pll_codes(pinfo);
+ if (ret)
+ dprintf(CRITICAL, "Cannot store pll codes!\n");
+
+dfps_cal_done:
+ if (pinfo->dfps.dfps_fb_base)
+ memcpy(pinfo->dfps.dfps_fb_base, &pinfo->dfps,
+ sizeof(struct dfps_info));
+dfps_done:
+ return ret;
+}
+
static int mdss_dsi_bl_enable(uint8_t enable)
{
int ret = NO_ERROR;
@@ -393,9 +558,20 @@
panel.panel_info.mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
panel.pll_clk_func = mdss_dsi_panel_clock;
+ panel.dfps_func = mdss_dsi_mipi_dfps_config;
panel.power_func = mdss_dsi_panel_power;
panel.pre_init_func = mdss_dsi_panel_pre_init;
panel.bl_func = mdss_dsi_bl_enable;
+ /*
+ * If dfps enabled, reserve fb memory to store pll
+ * codes and pass pll codes values to kernel.
+ */
+ if (panel.panel_info.dfps.panel_dfps.enabled) {
+ panel.panel_info.dfps.dfps_fb_base = base;
+ base += DFPS_PLL_CODES_SIZE;
+ dprintf(SPEW, "fb_base=0x%p!\n", base);
+ }
+
panel.fb.base = base;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 2fc904a..95e11d4 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -60,4 +60,17 @@
int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo, struct mdss_dsi_phy_ctrl *phy_db);
+static inline void set_panel_cmd_string(const char *panel_name,
+ char *cont_splash)
+{
+ char *ch = NULL;
+ ch = strchr((char *) panel_name, ':');
+ if (ch) {
+ *cont_splash = *(ch + 1);
+ *ch = '\0';
+ } else {
+ *cont_splash = '\0';
+ }
+}
+
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index e20b76a..913bafb 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -62,6 +62,7 @@
uint16_t panel_type;
char *panel_destination;
uint32_t panel_orientation;
+ /* panel_clockrate is deprecated in favor of panel_bitclock_freq */
uint32_t panel_clockrate;
uint16_t panel_framerate;
uint16_t panel_channelid;
@@ -148,6 +149,7 @@
uint8_t lane1_state;
uint8_t lane2_state;
uint8_t lane3_state;
+ uint8_t force_clk_lane_hs;
};
struct panel_timing {
diff --git a/dev/gcdb/display/include/panel_generic_720p_cmd.h b/dev/gcdb/display/include/panel_generic_720p_cmd.h
index 8320407..8e9ccd4 100644
--- a/dev/gcdb/display/include/panel_generic_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_generic_720p_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -151,7 +151,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration generic_720p_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h b/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h
index 7db42fd..b465b78 100644
--- a/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8279a_wsvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1115,7 +1115,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8279a_wsvga_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
index f4b5ff5..160a2a2 100644
--- a/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_skua_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -208,7 +208,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_fwvga_skua_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
index b11b9b4..7b43162 100755
--- a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -206,7 +206,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
index 528cb26..e96f540 100755
--- a/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -117,7 +117,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_truly_fwvga_video_lane_config = {
- 2, 0, 1, 1, 0, 0 /* 4, 0, 1, 1, 1, 1 */
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
index ff6133d..12db690 100644
--- a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -243,7 +243,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379a_wvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
index 3f9c7b3..d261148 100644
--- a/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -38,7 +38,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config hx8379c_fwvga_video_panel_data = {
"qcom,mdss_dsi_hx8379c_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 7000, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
@@ -64,13 +64,12 @@
};
static char hx8379c_fwvga_video_on_cmd1[] = {
- 0x15, 0x00, 0x39, 0xC0,
+ 0x11, 0x00, 0x39, 0xC0,
0xB1, 0x44, 0x1C, 0x1C,
0x31, 0x31, 0x50, 0xD0,
0xEE, 0x54, 0x80, 0x38,
0x38, 0xF8, 0x32, 0x22,
- 0x22, 0x00, 0x80, 0x30,
- 0x00, 0xFF, 0xFF, 0xFF,
+ 0x22, 0xFF, 0xFF, 0xFF,
};
static char hx8379c_fwvga_video_on_cmd2[] = {
@@ -88,16 +87,22 @@
};
static char hx8379c_fwvga_video_on_cmd4[] = {
- 0x02, 0x00, 0x39, 0xC0,
- 0xCC, 0x02, 0xFF, 0xFF,
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xC7, 0x00, 0x00, 0x00,
+ 0xC0, 0xFF, 0xFF, 0xFF,
};
static char hx8379c_fwvga_video_on_cmd5[] = {
0x02, 0x00, 0x39, 0xC0,
- 0xD2, 0x77, 0xFF, 0xFF,
+ 0xCC, 0x02, 0xFF, 0xFF,
};
static char hx8379c_fwvga_video_on_cmd6[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xD2, 0x77, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd7[] = {
0x1E, 0x00, 0x39, 0xC0,
0xD3, 0x00, 0x07, 0x00,
0x00, 0x00, 0x00, 0x00,
@@ -109,8 +114,8 @@
0x37, 0x09, 0xFF, 0xFF,
};
-static char hx8379c_fwvga_video_on_cmd7[] = {
- 0x21, 0x00, 0x39, 0xC0,
+static char hx8379c_fwvga_video_on_cmd8[] = {
+ 0x23, 0x00, 0x39, 0xC0,
0xD5, 0x18, 0x18, 0x19,
0x19, 0x18, 0x18, 0x20,
0x21, 0x24, 0x25, 0x18,
@@ -119,10 +124,10 @@
0x03, 0x06, 0x07, 0x18,
0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18,
- 0x18, 0xFF, 0xFF, 0xFF,
+ 0x18, 0x00, 0x00, 0xFF,
};
-static char hx8379c_fwvga_video_on_cmd8[] = {
+static char hx8379c_fwvga_video_on_cmd9[] = {
0x21, 0x00, 0x39, 0xC0,
0xD6, 0x18, 0x18, 0x18,
0x18, 0x19, 0x19, 0x25,
@@ -135,51 +140,52 @@
0x18, 0xFF, 0xFF, 0xFF,
};
-static char hx8379c_fwvga_video_on_cmd9[] = {
+static char hx8379c_fwvga_video_on_cmd10[] = {
0x2B, 0x00, 0x39, 0xC0,
- 0xE0, 0x00, 0x10, 0x16,
- 0x35, 0x39, 0x3F, 0x27,
- 0x47, 0x07, 0x0B, 0x0C,
- 0x17, 0x0E, 0x13, 0x16,
+ 0xE0, 0x00, 0x04, 0x0B,
+ 0x2F, 0x39, 0x3F, 0x21,
+ 0x46, 0x07, 0x0A, 0x0C,
+ 0x17, 0x0F, 0x13, 0x16,
0x14, 0x15, 0x07, 0x11,
- 0x13, 0x18, 0x00, 0x10,
- 0x17, 0x35, 0x3A, 0x3F,
- 0x26, 0x47, 0x06, 0x0B,
+ 0x13, 0x30, 0x00, 0x04,
+ 0x0B, 0x2F, 0x3A, 0x3F,
+ 0x21, 0x46, 0x07, 0x0A,
0x0C, 0x17, 0x0F, 0x14,
0x16, 0x14, 0x15, 0x07,
0x11, 0x13, 0x16, 0xFF,
};
-static char hx8379c_fwvga_video_on_cmd10[] = {
- 0x03, 0x00, 0x39, 0xC0,
- 0xB6, 0x4B, 0x4B, 0xFF,
-};
-
static char hx8379c_fwvga_video_on_cmd11[] = {
- 0x11, 0x00, 0x05, 0x80
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xB6, 0x4E, 0x4E, 0xFF,
};
static char hx8379c_fwvga_video_on_cmd12[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379c_fwvga_video_on_cmd13[] = {
0x29, 0x00, 0x05, 0x80
};
static struct mipi_dsi_cmd hx8379c_fwvga_video_on_command[] = {
{0x8, hx8379c_fwvga_video_on_cmd0, 0x00},
- {0x1c, hx8379c_fwvga_video_on_cmd1, 0x00},
+ {0x18, hx8379c_fwvga_video_on_cmd1, 0x00},
{0x10, hx8379c_fwvga_video_on_cmd2, 0x00},
{0x10, hx8379c_fwvga_video_on_cmd3, 0x00},
- {0x8, hx8379c_fwvga_video_on_cmd4, 0x00},
+ {0xc, hx8379c_fwvga_video_on_cmd4, 0x00},
{0x8, hx8379c_fwvga_video_on_cmd5, 0x00},
- {0x24, hx8379c_fwvga_video_on_cmd6, 0x00},
- {0x28, hx8379c_fwvga_video_on_cmd7, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd6, 0x00},
+ {0x24, hx8379c_fwvga_video_on_cmd7, 0x00},
{0x28, hx8379c_fwvga_video_on_cmd8, 0x00},
- {0x30, hx8379c_fwvga_video_on_cmd9, 0x00},
- {0x8, hx8379c_fwvga_video_on_cmd10, 0x00},
- {0x4, hx8379c_fwvga_video_on_cmd11, 0x96},
- {0x4, hx8379c_fwvga_video_on_cmd12, 0x78}
+ {0x28, hx8379c_fwvga_video_on_cmd9, 0x00},
+ {0x30, hx8379c_fwvga_video_on_cmd10, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd11, 0x00},
+ {0x4, hx8379c_fwvga_video_on_cmd12, 0x78},
+ {0x4, hx8379c_fwvga_video_on_cmd13, 0x14}
};
-#define HX8379C_FWVGA_VIDEO_ON_COMMAND 13
+#define HX8379C_FWVGA_VIDEO_ON_COMMAND 14
static char hx8379c_fwvga_videooff_cmd0[] = {
@@ -220,14 +226,14 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8379c_fwvga_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t hx8379c_fwvga_video_timings[] = {
- 0x73, 0x21, 0x1A, 0x00, 0x31, 0x2D, 0x1E, 0x23, 0x2B, 0x03, 0x04, 0x00
+ 0x7B, 0x21, 0x1A, 0x00, 0x31, 0x2D, 0x1E, 0x23, 0x2B, 0x03, 0x04, 0x00
};
static struct panel_timing hx8379c_fwvga_video_timing_info = {
@@ -238,7 +244,7 @@
/* Panel reset sequence */
/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence hx8379c_fwvga_video_reset_seq = {
- {1, 0, 1, }, {20, 20, 20, }, 2
+ {1, 0, 1, }, {20, 2, 20, }, 2
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
index 577918d..db6bfa0 100755
--- a/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
+++ b/dev/gcdb/display/include/panel_hx8389b_qhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -255,7 +255,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8389b_qhd_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
index 2bf8c69..32bb066 100644
--- a/dev/gcdb/display/include/panel_hx8394a_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -242,7 +242,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8394a_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8394d_720p_video.h b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
index c4095ae..ac4806f 100644
--- a/dev/gcdb/display/include/panel_hx8394d_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
@@ -248,7 +248,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration hx8394d_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_hx8394d_qhd_video.h b/dev/gcdb/display/include/panel_hx8394d_qhd_video.h
new file mode 100644
index 0000000..c04fccb
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8394d_qhd_video.h
@@ -0,0 +1,285 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_HX8394D_QHD_VIDEO_H_
+
+#define _PANEL_HX8394D_QHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config hx8394d_qhd_video_panel_data = {
+ "qcom,mdss_dsi_hx8394d_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8394d_qhd_video_panel_res = {
+ 540, 960, 52, 100, 24, 0, 8, 20, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8394d_qhd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char hx8394d_qhd_video_on_cmd0[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xb9, 0xff, 0x83, 0x94,
+};
+
+
+static char hx8394d_qhd_video_on_cmd1[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xba, 0x33, 0x83, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd2[] = {
+ 0x10, 0x00, 0x39, 0xC0,
+ 0xb1, 0x6c, 0x12, 0x12,
+ 0x37, 0x04, 0x11, 0xf1,
+ 0x80, 0xec, 0x94, 0x23,
+ 0x80, 0xc0, 0xd2, 0x18,
+};
+
+
+static char hx8394d_qhd_video_on_cmd3[] = {
+ 0x0c, 0x00, 0x39, 0xC0,
+ 0xb2, 0x00, 0x64, 0x0e,
+ 0x0d, 0x32, 0x23, 0x08,
+ 0x08, 0x1c, 0x4d, 0x00,
+};
+
+
+static char hx8394d_qhd_video_on_cmd4[] = {
+ 0x0d, 0x00, 0x39, 0xC0,
+ 0xb4, 0x00, 0xff, 0x03,
+ 0x50, 0x03, 0x50, 0x03,
+ 0x50, 0x01, 0x6a, 0x01,
+ 0x6a, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xbc, 0x07, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd6[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xbf, 0x41, 0x0e, 0x01,
+};
+
+
+static char hx8394d_qhd_video_on_cmd7[] = {
+ 0x1f, 0x00, 0x39, 0xC0,
+ 0xd3, 0x00, 0x07, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x32, 0x10, 0x05, 0x00,
+ 0x00, 0x32, 0x10, 0x00,
+ 0x00, 0x00, 0x32, 0x10,
+ 0x00, 0x00, 0x00, 0x36,
+ 0x03, 0x09, 0x09, 0x37,
+ 0x00, 0x00, 0x37, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd8[] = {
+ 0x2d, 0x00, 0x39, 0xC0,
+ 0xd5, 0x02, 0x03, 0x00,
+ 0x01, 0x06, 0x07, 0x04,
+ 0x05, 0x20, 0x21, 0x22,
+ 0x23, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x24,
+ 0x25, 0x18, 0x18, 0x19,
+ 0x19, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd9[] = {
+ 0x2d, 0x00, 0x39, 0xC0,
+ 0xd6, 0x05, 0x04, 0x07,
+ 0x06, 0x01, 0x00, 0x03,
+ 0x02, 0x23, 0x22, 0x21,
+ 0x20, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x58,
+ 0x58, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x25,
+ 0x24, 0x19, 0x19, 0x18,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd10[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xcc, 0x09, 0xFF, 0xFF,
+};
+
+
+static char hx8394d_qhd_video_on_cmd11[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xc0, 0x30, 0x14, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd12[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xc7, 0x00, 0xc0, 0x40,
+ 0xc0, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd13[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xb6, 0x43, 0x43, 0xFF,
+};
+
+static char hx8394d_qhd_video_on_cmd14[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8394d_qhd_video_on_cmd15[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_on_command[] = {
+ { 0x8 , hx8394d_qhd_video_on_cmd0, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd1, 0x00},
+ { 0x14 , hx8394d_qhd_video_on_cmd2, 0x00},
+ { 0x10 , hx8394d_qhd_video_on_cmd3, 0x00},
+ { 0x14 , hx8394d_qhd_video_on_cmd4, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd5, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd6, 0x00},
+ { 0x24 , hx8394d_qhd_video_on_cmd7, 0x00},
+ { 0x34 , hx8394d_qhd_video_on_cmd8, 0x00},
+ { 0x34 , hx8394d_qhd_video_on_cmd9, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd10, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd11, 0x00},
+ { 0xc , hx8394d_qhd_video_on_cmd12, 0x00},
+ { 0x8 , hx8394d_qhd_video_on_cmd13, 0x00},
+ { 0x4 , hx8394d_qhd_video_on_cmd14, 0xc8},
+ { 0x4 , hx8394d_qhd_video_on_cmd15, 0x0a}
+};
+#define HX8394D_QHD_VIDEO_ON_COMMAND 16
+
+static char hx8394d_qhd_video_off_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8394d_qhd_video_off_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_off_command[] = {
+ {0x4, hx8394d_qhd_video_off_cmd0, 0x32},
+ {0x4, hx8394d_qhd_video_off_cmd1, 0x78}
+};
+
+#define HX8394D_QHD_VIDEO_OFF_COMMAND 2
+
+static struct command_state hx8394d_qhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info hx8394d_qhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info hx8394d_qhd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration hx8394d_qhd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t hx8394d_qhd_video_timings[] = {
+ 0x79, 0x1a, 0x12, 0x00, 0x3e, 0x42, 0x16, 0x1e, 0x15, 0x03, 0x04, 0x00
+};
+
+static struct mipi_dsi_cmd hx8394d_qhd_video_rotation[] = {
+
+};
+#define HX8394D_QHD_VIDEO_ROTATION 0
+
+
+static struct panel_timing hx8394d_qhd_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+static struct panel_reset_sequence hx8394d_qhd_video_panel_reset_seq = {
+{
+ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight hx8394d_qhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define HX8394D_QHD_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_HX8394D_QHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h b/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h
index cffc982..c4941c5 100644
--- a/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_ili9806e_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -51,7 +51,7 @@
/* Panel resolution */
/*---------------------------------------------------------------------------*/
static struct panel_resolution ili9806e_fwvga_video_panel_res = {
- 480, 854, 52, 100, 24, 0, 8, 20, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 480, 854, 54, 100, 36, 0, 8, 20, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
@@ -782,18 +782,18 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration ili9806e_fwvga_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t ili9806e_fwvga_video_timings[] = {
- 0x73, 0x21, 0x1A, 0x00, 0x31, 0x30, 0x1E, 0x23, 0x2B, 0x03, 0x04, 0x00
+ 0x7D, 0x24, 0x19, 0x00, 0x34, 0x31, 0x1D, 0x26, 0x2A, 0x03, 0x04, 0x00
};
static struct panel_timing ili9806e_fwvga_video_timing_info = {
- 0, 4, 0x20, 0x2C
+ 0, 4, 0x1F, 0x2C
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_innolux_720p_video.h b/dev/gcdb/display/include/panel_innolux_720p_video.h
index 8bd4680..ca50810 100644
--- a/dev/gcdb/display/include/panel_innolux_720p_video.h
+++ b/dev/gcdb/display/include/panel_innolux_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -948,7 +948,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration innolux_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_1080p_video.h b/dev/gcdb/display/include/panel_jdi_1080p_video.h
index 2dbc2ba..add8e55 100755
--- a/dev/gcdb/display/include/panel_jdi_1080p_video.h
+++ b/dev/gcdb/display/include/panel_jdi_1080p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -141,7 +141,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_1080p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
index 8c9cbce..8cfee8e 100644
--- a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -82,14 +82,31 @@
0x29, 0x00, 0x05, 0x80
};
+static char jdi_4k_dualdsi_video_on_cmd_ip_0[] = {
+ 0xb0, 0x04, 0x23, 0x80
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_1[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xED, 0x80, 0x00, 0x34,
+ 0x5B, 0x04, 0xB0, 0xFF
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_2[] = {
+ 0xb0, 0x03, 0x23, 0x80
+};
+
static struct mipi_dsi_cmd jdi_4k_dualdsi_video_on_command[] = {
{0x4, jdi_4k_dualdsi_video_on_cmd0, 0x78},
{0x4, jdi_4k_dualdsi_video_on_cmd1, 0x78},
{0x4, jdi_4k_dualdsi_video_on_cmd2, 0x78},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_0, 0x50},
+ {0xC, jdi_4k_dualdsi_video_on_cmd_ip_1, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_2, 0x50},
{0x4, jdi_4k_dualdsi_video_on_cmd3, 0x78}
};
-#define JDI_4K_DUALDSI_VIDEO_ON_COMMAND 4
+#define JDI_4K_DUALDSI_VIDEO_ON_COMMAND 7
static char jdi_4k_dualdsi_videooff_cmd0[] = {
@@ -130,7 +147,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_4k_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h b/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h
new file mode 100755
index 0000000..6f09f38
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_a216_fhd_video.h
@@ -0,0 +1,165 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_JDI_A216_FHD_VIDEO_H_
+#define _PANEL_JDI_A216_FHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_a216_fhd_video_panel_data = {
+ "qcom,mdss_dsi_jdi_a216_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_a216_fhd_video_panel_res = {
+ 1080, 1920, 32, 20, 12, 0, 4, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_a216_fhd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char jdi_a216_fhd_video_on_cmd0[] = {
+ 0x51, 0xFF, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd1[] = {
+ 0x53, 0x0C, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd2[] = {
+ 0x55, 0x00, 0x15, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd3[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static char jdi_a216_fhd_video_on_cmd4[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_a216_fhd_video_on_command[] = {
+ {0x4, jdi_a216_fhd_video_on_cmd0, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd1, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd2, 0x0a},
+ {0x4, jdi_a216_fhd_video_on_cmd3, 0x28},
+ {0x4, jdi_a216_fhd_video_on_cmd4, 0xc8},
+};
+
+#define JDI_A216_FHD_VIDEO_ON_COMMAND 5
+
+
+static char jdi_a216_fhd_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_a216_fhd_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_a216_fhd_video_off_command[] = {
+ {0x4, jdi_a216_fhd_videooff_cmd0, 0x32},
+ {0x4, jdi_a216_fhd_videooff_cmd1, 0x78}
+};
+
+#define JDI_A216_FHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state jdi_a216_fhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_a216_fhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_a216_fhd_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_a216_fhd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_a216_fhd_video_timings[] = {
+ 0xce, 0x2e, 0x1e, 0x00, 0x5a, 0x5c, 0x24, 0x30, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing jdi_a216_fhd_video_timing_info = {
+ 0x0, 0x04, 0x0a, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_a216_fhd_video_reset_seq = {
+ {1, 0, 1, }, {20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_a216_fhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_JDI_A216_FHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_jdi_fhd_video.h b/dev/gcdb/display/include/panel_jdi_fhd_video.h
index a301056..9405223 100644
--- a/dev/gcdb/display/include/panel_jdi_fhd_video.h
+++ b/dev/gcdb/display/include/panel_jdi_fhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -184,7 +184,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_fhd_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
index 31b18f5..a0686d3 100644
--- a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -185,7 +185,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_qhd_dualdsi_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
index bd5ae6d..79acd3f 100644
--- a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -196,7 +196,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration jdi_qhd_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
index c5f9069..810fb6a 100644
--- a/dev/gcdb/display/include/panel_nt35521_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1443,7 +1443,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35521_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35521_wxga_video.h b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
index bdac711..2195176 100644
--- a/dev/gcdb/display/include/panel_nt35521_wxga_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1002,7 +1002,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35521_wxga_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 72f5a18..6894e96 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2900,7 +2900,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_720p_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index b935482..b812ef0 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2913,7 +2913,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h b/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
index 2a8b91f..a6854f8 100644
--- a/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_qvga_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2907,7 +2907,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35590_qvga_cmd_lane_config = {
- 1, 0, 1, 0, 0, 0
+ 1, 0, 1, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
index 2cd3d07..b514c96 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -2988,7 +2988,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35596_1080p_skuk_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 1
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
index 0c32667..57f6b4c 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -3236,7 +3236,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35596_1080p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
index e6fac4a..6e957be 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -206,7 +206,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35597_wqxga_cmd_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
index 7912ba8..d2f34d8 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -194,7 +194,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration nt35597_wqxga_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_otm1283a_720p_video.h b/dev/gcdb/display/include/panel_otm1283a_720p_video.h
index ec44928..a7b6c96 100755
--- a/dev/gcdb/display/include/panel_otm1283a_720p_video.h
+++ b/dev/gcdb/display/include/panel_otm1283a_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -930,7 +930,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm1283a_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
index 7fa9098..caaf38a 100755
--- a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -652,7 +652,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm8018b_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h b/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
index 235057e..c88fbc3 100755
--- a/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_otm8019a_fwvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -786,7 +786,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration otm8019a_fwvga_video_lane_config = {
- 2, 1, 1, 1, 0, 0
+ 2, 1, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_r61318_hd_video.h b/dev/gcdb/display/include/panel_r61318_hd_video.h
new file mode 100644
index 0000000..72c27c2
--- /dev/null
+++ b/dev/gcdb/display/include/panel_r61318_hd_video.h
@@ -0,0 +1,296 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_R61318_HD_VIDEO_H_
+#define _PANEL_R61318_HD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config r61318_hd_video_panel_data = {
+ "qcom,mdss_dsi_r61318_hd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution r61318_hd_video_panel_res = {
+ 720, 1280, 40, 30, 12, 0, 18, 9, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info r61318_hd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char r61318_hd_video_on_cmd0[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd1[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB3, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd2[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB6, 0x32, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd3[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x36, 0x0A, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd4[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xC0, 0x20, 0xB2, 0x0D,
+ 0x10, 0x02, 0x80, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd5[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xC1, 0x35, 0x85, 0x85,
+ 0x85, 0x10, 0x10, 0x33,
+
+};
+
+static char r61318_hd_video_on_cmd6[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC3, 0x20, 0x0F, 0x00,
+
+};
+
+static char r61318_hd_video_on_cmd7[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC4, 0xBC, 0xD2, 0x00,
+
+};
+
+static char r61318_hd_video_on_cmd8[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC5, 0x06, 0x03, 0x1D,
+
+};
+
+static char r61318_hd_video_on_cmd9[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC6, 0x21, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd10[] = {
+ 0x1D, 0x00, 0x29, 0xC0,
+ 0xC8, 0x60, 0x0E, 0x08,
+ 0x62, 0x90, 0x52, 0x95,
+ 0x54, 0x49, 0x29, 0x84,
+ 0x90, 0xA2, 0x4A, 0x29,
+ 0x45, 0x15, 0x42, 0x48,
+ 0xA9, 0xA4, 0xA4, 0xAA,
+ 0x85, 0x0c, 0x11, 0xc0,
+ 0x31, 0xFF, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd11[] = {
+ 0x1F, 0x00, 0x29, 0xC0,
+ 0xCA, 0x02, 0x0A, 0x0F,
+ 0x15, 0x1B, 0x20, 0x23,
+ 0x1F, 0x24, 0x24, 0x21,
+ 0x1A, 0x15, 0x0F, 0x01,
+ 0x02, 0x0A, 0x0F, 0x15,
+ 0x1B, 0x20, 0x23, 0x1F,
+ 0x24, 0x24, 0x21, 0x1A,
+ 0x15, 0x0F, 0x01, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd12[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCD, 0x00, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd13[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE5, 0x02, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd14[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xD0, 0x05, 0x89, 0x1A,
+};
+
+static char r61318_hd_video_on_cmd15[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD1, 0x03, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd16[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD2, 0x81, 0x1F, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd17[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD4, 0x50, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd18[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x34, 0x34, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd19[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x24, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd20[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xff, 0xFF, 0xFF,
+};
+
+static char r61318_hd_video_on_cmd21[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_video_on_cmd22[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r61318_hd_video_on_command[] = {
+ {0x8, r61318_hd_video_on_cmd0, 0x00},
+ {0x8, r61318_hd_video_on_cmd1, 0x00},
+ {0x8, r61318_hd_video_on_cmd2, 0x00},
+ {0x8, r61318_hd_video_on_cmd3, 0x00},
+ {0xc, r61318_hd_video_on_cmd4, 0x00},
+ {0xc, r61318_hd_video_on_cmd5, 0x00},
+ {0x8, r61318_hd_video_on_cmd6, 0x00},
+ {0x8, r61318_hd_video_on_cmd7, 0x00},
+ {0x8, r61318_hd_video_on_cmd8, 0x00},
+ {0x8, r61318_hd_video_on_cmd9, 0x00},
+ {0x24, r61318_hd_video_on_cmd10, 0x00},
+ {0x24, r61318_hd_video_on_cmd11, 0x00},
+ {0x8, r61318_hd_video_on_cmd12, 0x00},
+ {0x8, r61318_hd_video_on_cmd13, 0x00},
+ {0x8, r61318_hd_video_on_cmd14, 0x00},
+ {0x8, r61318_hd_video_on_cmd15, 0x00},
+ {0x8, r61318_hd_video_on_cmd16, 0x00},
+ {0x8, r61318_hd_video_on_cmd17, 0x00},
+ {0x8, r61318_hd_video_on_cmd18, 0x00},
+ {0x8, r61318_hd_video_on_cmd19, 0x00},
+ {0x8, r61318_hd_video_on_cmd20, 0x00},
+ {0x4, r61318_hd_video_on_cmd21, 0x78},
+ {0x4, r61318_hd_video_on_cmd22, 0x32}
+};
+
+#define R61318_HD_VIDEO_ON_COMMAND 23
+
+
+static char r61318_hd_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r61318_hd_video_off_command[] = {
+ {0x4, r61318_hd_videooff_cmd0, 0x32},
+ {0x4, r61318_hd_videooff_cmd1, 0x78}
+};
+
+#define R61318_HD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state r61318_hd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info r61318_hd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info r61318_hd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration r61318_hd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t r61318_hd_video_timings[] = {
+ 0xab, 0x1c, 0x14, 0x00, 0x2a, 0x27, 0x18, 0x1e, 0x21, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing r61318_hd_video_timing_info = {
+ 0, 4, 0x20, 0x2e
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence r61318_hd_video_reset_seq = {
+ {1, 0, 1, }, {20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight r61318_hd_video_backlight = {
+ 2, 1, 255, 0, 2, "bl_ctrl_dcs"
+};
+
+#endif /*_PANEL_R61318_HD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_r63417_1080p_video.h b/dev/gcdb/display/include/panel_r63417_1080p_video.h
new file mode 100644
index 0000000..dad028a
--- /dev/null
+++ b/dev/gcdb/display/include/panel_r63417_1080p_video.h
@@ -0,0 +1,313 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_R63417_1080P_VIDEO_H_
+#define _PANEL_R63417_1080P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config r63417_1080p_video_panel_data = {
+ "qcom,mdss_dsi_r63417_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution r63417_1080p_video_panel_res = {
+ 1080, 1920, 100, 12, 60, 0, 25, 6, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info r63417_1080p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char r63417_1080p_video_on_cmd0[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x11, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd1[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB0, 0x04, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd2[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB3, 0x14, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd3[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB6, 0x3A, 0xC3, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd4[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd5[] = {
+ 0x23, 0x00, 0x29, 0xC0,
+ 0xC1, 0xC4, 0x60, 0x10,
+ 0xEB, 0xFF, 0x6F, 0xCE,
+ 0xFF, 0xFF, 0x17, 0x12,
+ 0x58, 0x73, 0xAE, 0x31,
+ 0x20, 0xC6, 0xFF, 0xFF,
+ 0x1F, 0xF3, 0xFF, 0x5F,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x00, 0x62, 0x01, 0x22,
+ 0x22, 0x00, 0x01, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd6[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xC2, 0x31, 0xF7, 0x80,
+ 0x08, 0x08, 0x00, 0x00,
+};
+
+static char r63417_1080p_video_on_cmd7[] = {
+ 0x17, 0x00, 0x29, 0xC0,
+ 0xC4, 0x70, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x06, 0x05,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x05, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd8[] = {
+ 0x29, 0x00, 0x29, 0xC0,
+ 0xC6, 0xC8, 0x01, 0x69,
+ 0x01, 0x69, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x0B, 0x17,
+ 0x09, 0xC8, 0x08, 0x67,
+ 0x08, 0x67, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x16, 0x18,
+ 0x08, 0xFF, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd9[] = {
+ 0x0A, 0x00, 0x29, 0xC0,
+ 0xCB, 0x31, 0xFC, 0x3F,
+ 0x8C, 0x00, 0x00, 0x00,
+ 0x00, 0xC0, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd10[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0B, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd11[] = {
+ 0x0B, 0x00, 0x29, 0xC0,
+ 0xD0, 0x22, 0x82, 0xBB,
+ 0x19, 0x99, 0x4C, 0x19,
+ 0x19, 0x0C, 0x00, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd12[] = {
+ 0x1a, 0x00, 0x29, 0xC0,
+ 0xD3, 0x1B, 0x33, 0xBB,
+ 0xBB, 0xB3, 0x33, 0x33,
+ 0x33, 0x01, 0x01, 0x00,
+ 0xA0, 0xD8, 0xA0, 0x0D,
+ 0x55, 0x55, 0x33, 0x3B,
+ 0x37, 0x72, 0x07, 0x3D,
+ 0xBF, 0x44, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd13[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xD5, 0x06, 0x00, 0x00,
+ 0x01, 0x67, 0x01, 0x67,
+};
+
+static char r63417_1080p_video_on_cmd14[] = {
+ 0x1f, 0x00, 0x29, 0xC0,
+ 0xC7, 0x0C, 0x1B, 0x22,
+ 0x2B, 0x37, 0x43, 0x4C,
+ 0x5B, 0x3F, 0x47, 0x52,
+ 0x5F, 0x67, 0x6B, 0x6E,
+ 0x0C, 0x1B, 0x22, 0x2B,
+ 0x37, 0x43, 0x4C, 0x5B,
+ 0x3F, 0x47, 0x52, 0x5F,
+ 0x67, 0x6B, 0x6E, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd15[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xC8, 0x01, 0x00, 0x00,
+ 0x03, 0xFB, 0xFB, 0xEF,
+ 0x00, 0x00, 0x03, 0xFB,
+ 0xFB, 0xEF, 0x00, 0x00,
+ 0x03, 0xFB, 0xFB, 0xEF,
+};
+
+static char r63417_1080p_video_on_cmd16[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xFF, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd17[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x2C, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd18[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x55, 0x03, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd19[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char r63417_1080p_video_on_cmd20[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x29, 0x00, 0xFF, 0xFF,
+};
+
+static struct mipi_dsi_cmd r63417_1080p_video_on_command[] = {
+ {0x8, r63417_1080p_video_on_cmd0, 0x78},
+ {0x8, r63417_1080p_video_on_cmd1, 0x00},
+ {0xc, r63417_1080p_video_on_cmd2, 0x00},
+ {0x8, r63417_1080p_video_on_cmd3, 0x00},
+ {0x8, r63417_1080p_video_on_cmd4, 0x00},
+ {0x28, r63417_1080p_video_on_cmd5, 0x00},
+ {0xc, r63417_1080p_video_on_cmd6, 0x00},
+ {0x1c, r63417_1080p_video_on_cmd7, 0x00},
+ {0x30, r63417_1080p_video_on_cmd8, 0x00},
+ {0x10, r63417_1080p_video_on_cmd9, 0x00},
+ {0x8, r63417_1080p_video_on_cmd10, 0x00},
+ {0x10, r63417_1080p_video_on_cmd11, 0x00},
+ {0x20, r63417_1080p_video_on_cmd12, 0x00},
+ {0xc, r63417_1080p_video_on_cmd13, 0x00},
+ {0x24, r63417_1080p_video_on_cmd14, 0x00},
+ {0x18, r63417_1080p_video_on_cmd15, 0x00},
+ {0x8, r63417_1080p_video_on_cmd16, 0x00},
+ {0x8, r63417_1080p_video_on_cmd17, 0x00},
+ {0x8, r63417_1080p_video_on_cmd18, 0x00},
+ {0x8, r63417_1080p_video_on_cmd19, 0x00},
+ {0x8, r63417_1080p_video_on_cmd20, 0x64}
+};
+
+#define R63417_1080P_VIDEO_ON_COMMAND 21
+
+
+static char r63417_1080p_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char r63417_1080p_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r63417_1080p_video_off_command[] = {
+ {0x4, r63417_1080p_videooff_cmd0, 0x32},
+ {0x4, r63417_1080p_videooff_cmd1, 0x78}
+};
+
+#define R63417_1080P_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state r63417_1080p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info r63417_1080p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info r63417_1080p_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration r63417_1080p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t r63417_1080p_video_timings[] = {
+ 0xAE, 0x44, 0x37, 0x00, 0x5D, 0x55, 0x39, 0x46, 0x5B, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing r63417_1080p_video_timing_info = {
+ 0, 4, 0x1e, 0x34
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence r63417_1080p_video_reset_seq = {
+ {1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight r63417_1080p_video_backlight = {
+ 1, 1, 255, 0, 2, "bl_ctrl_dcs"
+};
+
+#endif /*_PANEL_R63417_1080P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_samsung_wxga_video.h b/dev/gcdb/display/include/panel_samsung_wxga_video.h
index 20f2714..e01b562 100644
--- a/dev/gcdb/display/include/panel_samsung_wxga_video.h
+++ b/dev/gcdb/display/include/panel_samsung_wxga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -196,7 +196,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration samsung_wxga_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_sharp_qhd_video.h b/dev/gcdb/display/include/panel_sharp_qhd_video.h
index df8c5a5..00f0147 100755
--- a/dev/gcdb/display/include/panel_sharp_qhd_video.h
+++ b/dev/gcdb/display/include/panel_sharp_qhd_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -76,38 +76,31 @@
static char sharp_qhd_video_on_cmd2[] = {
-0x53, 0x2c, 0x15, 0x80 };
+0x53, 0x0c, 0x15, 0x80 };
static char sharp_qhd_video_on_cmd3[] = {
-0x51, 0xff, 0x15, 0x80 };
-
-
-static char sharp_qhd_video_on_cmd4[] = {
0x29, 0x00, 0x05, 0x80 };
-static char sharp_qhd_video_on_cmd5[] = {
+static char sharp_qhd_video_on_cmd4[] = {
0xae, 0x03, 0x15, 0x80 };
-static char sharp_qhd_video_on_cmd6[] = {
+static char sharp_qhd_video_on_cmd5[] = {
0x3a, 0x77, 0x15, 0x80 };
-
-
static struct mipi_dsi_cmd sharp_qhd_video_on_command[] = {
{ 0x4 , sharp_qhd_video_on_cmd0},
{ 0x4 , sharp_qhd_video_on_cmd1},
{ 0x4 , sharp_qhd_video_on_cmd2},
{ 0x4 , sharp_qhd_video_on_cmd3},
{ 0x4 , sharp_qhd_video_on_cmd4},
-{ 0x4 , sharp_qhd_video_on_cmd5},
-{ 0x4 , sharp_qhd_video_on_cmd6}
+{ 0x4 , sharp_qhd_video_on_cmd5}
};
-#define SHARP_QHD_VIDEO_ON_COMMAND 7
+#define SHARP_QHD_VIDEO_ON_COMMAND 6
static char sharp_qhd_videooff_cmd0[] = {
0x28, 0x00, 0x05, 0x80 };
@@ -151,7 +144,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration sharp_qhd_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
index 68a277d..a1b57d3 100644
--- a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -119,7 +119,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration sharp_wqxga_dualdsi_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
@@ -151,6 +151,13 @@
0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
};
+/*---------------------------------------------------------------------------*/
+/* Dynamic fps supported frequencies by panel */
+/*---------------------------------------------------------------------------*/
+static const struct dfps_panel_info sharp_wqxga_dualdsi_video_dfps = {
+ 1, 8, {53, 54, 55, 56, 57, 58, 59, 60}
+};
+
#define SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE 0x210000
#endif /*_PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
index 7a1c8e5..74bfd7b 100755
--- a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -457,7 +457,7 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration ssd2080m_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_toshiba_720p_video.h b/dev/gcdb/display/include/panel_toshiba_720p_video.h
index 7b16246..12c6326 100755
--- a/dev/gcdb/display/include/panel_toshiba_720p_video.h
+++ b/dev/gcdb/display/include/panel_toshiba_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -309,7 +309,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration toshiba_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1, 0
};
diff --git a/dev/gcdb/display/include/panel_truly_wvga_cmd.h b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
index c443766..89a9994 100644
--- a/dev/gcdb/display/include/panel_truly_wvga_cmd.h
+++ b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -413,18 +413,18 @@
/* Lane configuration */
/*---------------------------------------------------------------------------*/
static struct lane_configuration truly_wvga_cmd_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t truly_wvga_cmd_timings[] = {
- 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+ 0x7B, 0x1A, 0x10, 0x00, 0x3C, 0x42, 0x14, 0x1C, 0x15, 0x3, 0x4, 0x00
};
static struct panel_timing truly_wvga_cmd_timing_info = {
- 2, 4, 0x04, 0x1b
+ 2, 4, 0x04, 0x1a
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_video.h b/dev/gcdb/display/include/panel_truly_wvga_video.h
index ee1ab28..18ee099 100644
--- a/dev/gcdb/display/include/panel_truly_wvga_video.h
+++ b/dev/gcdb/display/include/panel_truly_wvga_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -291,7 +291,7 @@
/*---------------------------------------------------------------------------*/
static struct lane_configuration truly_wvga_video_lane_config = {
- 2, 0, 1, 1, 0, 0
+ 2, 0, 1, 1, 0, 0, 0
};
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 9ae9bf6..d2675dc 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,21 +47,36 @@
#include "include/panel.h"
#include "target/display.h"
+static int dsi_platform_base_offset_adjust(uint32_t base)
+{
+ return target_display_get_base_offset(base);
+}
+
static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo,
char *panel_destination)
{
+ int base_offset = 0, base1_offset = 0;
+
+ /*
+ * Base offsets may vary for few platforms. Add the difference to get
+ * proper base offset for the respective platform.
+ */
+ base_offset = dsi_platform_base_offset_adjust(MIPI_DSI0_BASE);
+ base1_offset = dsi_platform_base_offset_adjust(MIPI_DSI1_BASE);
+ dprintf(SPEW, "base offset = %d, %x\n", base_offset, base_offset);
+
if (!strcmp(panel_destination, "DISPLAY_1")) {
pinfo->dest = DISPLAY_1;
- pinfo->mipi.ctl_base = MIPI_DSI0_BASE;
- pinfo->mipi.phy_base = DSI0_PHY_BASE;
- pinfo->mipi.sctl_base = MIPI_DSI1_BASE;
- pinfo->mipi.sphy_base = DSI1_PHY_BASE;
+ pinfo->mipi.ctl_base = MIPI_DSI0_BASE + base_offset;
+ pinfo->mipi.phy_base = DSI0_PHY_BASE + base_offset;
+ pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset;
+ pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_offset;
} else if (!strcmp(panel_destination, "DISPLAY_2")) {
pinfo->dest = DISPLAY_2;
- pinfo->mipi.ctl_base = MIPI_DSI1_BASE;
- pinfo->mipi.phy_base = DSI1_PHY_BASE;
- pinfo->mipi.sctl_base = MIPI_DSI0_BASE;
- pinfo->mipi.sphy_base = DSI0_PHY_BASE;
+ pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset;
+ pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_offset;
+ pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset;
+ pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_offset;
} else {
pinfo->dest = DISPLAY_UNKNOWN;
dprintf(CRITICAL, "%s: Unkown panel destination: %d\n",
@@ -69,9 +84,19 @@
return ERROR;
}
+ pinfo->mipi.pll_0_base = DSI0_PLL_BASE + base_offset;
+ pinfo->mipi.pll_1_base = DSI1_PLL_BASE + base1_offset;
+
+ /* Both DSI0 and DSI1 use the same regulator */
+ pinfo->mipi.reg_base = DSI0_REGULATOR_BASE + base_offset;
+ pinfo->mipi.sreg_base = DSI0_REGULATOR_BASE + base_offset;
+
dprintf(SPEW, "%s: panel dest=%s, ctl_base=0x%08x, phy_base=0x%08x\n",
__func__, panel_destination, pinfo->mipi.ctl_base,
pinfo->mipi.phy_base);
+ dprintf(SPEW, "pll_0_base=%08x, pll_1_base=0x%08x, reg_base=0x%08x, sreg_base=%08x\n",
+ pinfo->mipi.pll_0_base, pinfo->mipi.pll_1_base,
+ pinfo->mipi.reg_base, pinfo->mipi.sreg_base);
return NO_ERROR;
}
@@ -118,6 +143,7 @@
pinfo->lcdc.border_clr = pstruct->color->border_color;
pinfo->lcdc.underflow_clr = pstruct->color->underflow_color;
pinfo->mipi.rgb_swap = pstruct->color->color_order;
+ pinfo->bpp = pstruct->color->color_format;
switch (pinfo->bpp) {
case BPP_16:
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565;
@@ -143,7 +169,6 @@
} else {
pinfo->type = MIPI_VIDEO_PANEL;
}
- pinfo->bpp = pstruct->color->color_format;
pinfo->clk_rate = pstruct->paneldata->panel_clockrate;
pinfo->orientation = pstruct->paneldata->panel_orientation;
pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
@@ -155,6 +180,10 @@
pinfo->mipi.dual_dsi = 1;
pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state;
pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
+ if (pinfo->mipi.bitclock) {
+ /* panel_clockrate is depcrated in favor of bitclock_freq */
+ pinfo->clk_rate = pinfo->mipi.bitclock;
+ }
pinfo->mipi.use_enable_gpio =
pstruct->paneldata->panel_with_enable_gpio;
ret = dsi_panel_ctl_base_setup(pinfo,
@@ -188,6 +217,7 @@
pinfo->mipi.data_lane2 = pstruct->laneconfig->lane2_state;
pinfo->mipi.data_lane3 = pstruct->laneconfig->lane3_state;
pinfo->mipi.lane_swap = pstruct->laneconfig->dsi_lanemap;
+ pinfo->mipi.force_clk_lane_hs = pstruct->laneconfig->force_clk_lane_hs;
pinfo->mipi.t_clk_post = pstruct->paneltiminginfo->tclk_post;
pinfo->mipi.t_clk_pre = pstruct->paneltiminginfo->tclk_pre;
@@ -279,7 +309,7 @@
uint32_t panel_width = pinfo->xres;
uint32_t final_xres, final_yres, final_width;
uint32_t final_height, final_hbp, final_hfp,final_vbp;
- uint32_t final_vfp, final_hpw, final_vpw;
+ uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -310,6 +340,9 @@
final_vfp = pinfo->lcdc.v_front_porch;
final_hpw = pinfo->lcdc.h_pulse_width;
final_vpw = pinfo->lcdc.v_pulse_width;
+ low_pwr_stop = (pinfo->mipi.hfp_power_stop << 8) |
+ (pinfo->mipi.hbp_power_stop << 4) |
+ pinfo->mipi.hsa_power_stop;
ret = mdss_dsi_video_mode_config(final_width, final_height,
final_xres, final_yres,
@@ -319,7 +352,8 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.pulse_mode_hsa_he,
+ low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
pinfo->mipi.ctl_base);
@@ -333,7 +367,8 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.pulse_mode_hsa_he,
+ low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
pinfo->mipi.sctl_base);
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 717f09b..6e89f57 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -219,6 +219,7 @@
uint32_t pm8x41_v2_resin_status();
uint32_t pm8x41_resin_status();
void pm8x41_reset_configure(uint8_t);
+void pm8994_reset_configure(uint8_t);
void pm8x41_v2_reset_configure(uint8_t);
int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage);
int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 5886161..1784534 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -77,6 +77,24 @@
return val;
}
+/* SPMI helper function which takes slave id as the i/p */
+void pm8xxx_reg_write(uint8_t slave_id, uint32_t addr, uint8_t val)
+{
+ struct pmic_arb_cmd cmd;
+ struct pmic_arb_param param;
+
+ cmd.address = PERIPH_ID(addr);
+ cmd.offset = REG_OFFSET(addr);
+ cmd.slave_id = slave_id;
+
+ cmd.priority = 0;
+
+ param.buffer = &val;
+ param.size = 1;
+
+ pmic_arb_write_cmd(&cmd, ¶m);
+}
+
void pm8x41_reg_write(uint32_t addr, uint8_t val)
{
struct pmic_arb_cmd cmd;
@@ -333,6 +351,24 @@
return 0;
}
+void pm8994_reset_configure(uint8_t reset_type)
+{
+ /* Slave ID 14 is global slave ID for all the pmics */
+ uint8_t slave_id = 14;
+
+ /* disable PS_HOLD_RESET */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL2, 0x0);
+
+ /* Delay needed for disable to kick in. */
+ udelay(300);
+
+ /* configure reset type */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL, reset_type);
+
+ /* enable PS_HOLD_RESET */
+ pm8xxx_reg_write(slave_id, PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
+}
+
void pm8x41_v2_reset_configure(uint8_t reset_type)
{
uint8_t val;
diff --git a/dev/qpnp_led/include/qpnp_led.h b/dev/qpnp_led/include/qpnp_led.h
new file mode 100644
index 0000000..834b29d
--- /dev/null
+++ b/dev/qpnp_led/include/qpnp_led.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <board.h>
+
+#define PERPH_SUBTYPE(base) (base + 0x05)
+#define RGB_LED_PERPH_TYPE(base) (base + 0x04)
+#define RGB_LED_SRC_SEL(base) (base + 0x45)
+#define RGB_LED_EN_CTL(base) (base + 0x46)
+#define RGB_LED_ATC_CTL(base) (base + 0x47)
+#define LPG_PERPH_TYPE(base) (base + 0x04)
+#define LPG_PERPH_SUBTYPE(base) (base + 0x05)
+#define LPG_PATTERN_CONFIG(base) (base + 0x40)
+#define LPG_PWM_SIZE_CLK(base) (base + 0x41)
+#define LPG_PWM_FREQ_PREDIV_CLK(base) (base + 0x42)
+#define LPG_PWM_TYPE_CONFIG(base) (base + 0x43)
+#define PWM_VALUE_LSB(base) (base + 0x44)
+#define PWM_VALUE_MSB(base) (base + 0x45)
+#define LPG_ENABLE_CONTROL(base) (base + 0x46)
+#define PWM_SYNC(base) (base + 0x47)
+
+#define RGB_LED_ENABLE_BLUE 0x20
+#define RGB_LED_ENABLE_GREEN 0x40
+#define RGB_LED_ENABLE_RED 0x80
+#define RGB_LED_SOURCE_VPH_PWR 0x01
+#define RGB_LED_ENABLE_MASK 0xE0
+#define RGB_LED_SRC_MASK 0xfc
+#define PWM_6BIT_1KHZ_CLK 0x01
+#define PWM_FREQ 0x05
+#define RGB_LED_ENABLE_PWM 0xe4
+
+enum qpnp_led_op {
+ QPNP_LED_RED,
+ QPNP_LED_GREEN,
+ QPNP_LED_BLUE,
+};
+
+struct qpnp_led_data {
+ uint16_t base;
+ uint16_t lpg_base;
+ enum qpnp_led_op color_sel;
+};
+
+/* LED Initial Setup */
+void qpnp_led_init(enum qpnp_led_op color, uint16_t led_base_addr,
+ uint16_t lpg_base_addr);
diff --git a/dev/qpnp_led/qpnp_led.c b/dev/qpnp_led/qpnp_led.c
new file mode 100644
index 0000000..a1503a2
--- /dev/null
+++ b/dev/qpnp_led/qpnp_led.c
@@ -0,0 +1,94 @@
+ /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <qpnp_led.h>
+#include <platform/iomap.h>
+#include <pm8x41_wled.h>
+
+static void qpnp_led_config(struct qpnp_led_data *led)
+{
+ pm8x41_wled_reg_write(RGB_LED_SRC_SEL(led->base),
+ RGB_LED_SOURCE_VPH_PWR);
+ pm8x41_wled_reg_write(LPG_PATTERN_CONFIG(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(LPG_PWM_SIZE_CLK(led->lpg_base),
+ PWM_6BIT_1KHZ_CLK);
+ pm8x41_wled_reg_write(LPG_PWM_FREQ_PREDIV_CLK(led->lpg_base),
+ PWM_FREQ);
+ pm8x41_wled_reg_write(LPG_PWM_TYPE_CONFIG(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(PWM_VALUE_LSB(led->lpg_base), 0x20);
+ pm8x41_wled_reg_write(PWM_VALUE_MSB(led->lpg_base), 0x00);
+ pm8x41_wled_reg_write(PWM_SYNC(led->lpg_base), 0x01);
+ pm8x41_wled_reg_write(LPG_ENABLE_CONTROL(led->lpg_base),
+ RGB_LED_ENABLE_PWM);
+}
+
+static int qpnp_led_setup(struct qpnp_led_data *led)
+{
+ uint8_t reg = 0;
+
+ reg = pm8x41_wled_reg_read(RGB_LED_EN_CTL(led->base));
+
+ switch (led->color_sel) {
+ case QPNP_LED_RED:
+ reg |= RGB_LED_ENABLE_RED;
+ break;
+ case QPNP_LED_GREEN:
+ reg |= RGB_LED_ENABLE_GREEN;
+ break;
+ case QPNP_LED_BLUE:
+ reg |= RGB_LED_ENABLE_BLUE;
+ break;
+ default:
+ return -1;
+ };
+
+ pm8x41_wled_reg_write(RGB_LED_EN_CTL(led->base), reg);
+
+ return 0;
+}
+
+void qpnp_led_init(enum qpnp_led_op color, uint16_t led_base_addr,
+ uint16_t lpg_base_addr)
+{
+ int rc;
+ struct qpnp_led_data led;
+
+ led.base = led_base_addr;
+ led.lpg_base = lpg_base_addr;
+ led.color_sel = color;
+
+ rc = qpnp_led_setup(&led);
+ if (rc) {
+ dprintf(INFO, "%s : failed\n", __func__);
+ return;
+ }
+
+ qpnp_led_config(&led);
+}
+
diff --git a/dev/qpnp_led/rules.mk b/dev/qpnp_led/rules.mk
new file mode 100644
index 0000000..b35e459
--- /dev/null
+++ b/dev/qpnp_led/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+ $(LOCAL_DIR)/qpnp_led.o
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
index 3584a32..a04680d 100644
--- a/dev/qpnp_wled/include/qpnp_wled.h
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -168,6 +168,8 @@
#define QPNP_WLED_MIN_MSLEEP 20
#define QPNP_WLED_MAX_BR_LEVEL 1638
+#define PWRDN_DLY2_MASK 0x3
+
/* output feedback mode */
enum qpnp_wled_fdbk_op {
QPNP_WLED_FDBK_AUTO,
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
index b96150c..2f4b196 100644
--- a/dev/qpnp_wled/qpnp_wled.c
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -1,4 +1,4 @@
- /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -408,6 +408,10 @@
temp = wled->ibb_pwrup_dly_ms;
reg &= QPNP_WLED_IBB_PWRUP_DLY_MASK;
reg |= (temp << QPNP_WLED_IBB_PWRUP_DLY_SHIFT);
+ /* Power down delay bits could already be set, clear them before
+ * or'ing new values
+ */
+ reg &= ~(PWRDN_DLY2_MASK);
reg |= wled->ibb_pwrdn_dly_ms;
reg |= (wled->ibb_discharge_en << 2);
diff --git a/include/dev/flash-ubi.h b/include/dev/flash-ubi.h
new file mode 100644
index 0000000..50577cc
--- /dev/null
+++ b/include/dev/flash-ubi.h
@@ -0,0 +1,158 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FLASH_UBI_H_
+#define _FLASH_UBI_H_
+
+#include <sys/types.h>
+#include <lib/ptable.h>
+#include <stdint.h>
+
+struct __attribute__ ((packed)) ubifs_ch {
+ uint32_t magic;
+ uint32_t crc;
+ uint64_t sqnum;
+ uint32_t len;
+#define UBIFS_SB_NODE 6
+ uint8_t node_type;
+ uint8_t group_type;
+ uint8_t padding[2];
+};
+
+/* UBIFS superblock node */
+struct __attribute__ ((packed)) ubifs_sb_node {
+ struct ubifs_ch ch;
+ uint8_t padding[2];
+ uint8_t key_hash;
+ uint8_t key_fmt;
+#define UBIFS_FLG_SPACE_FIXUP 0x04
+ uint32_t flags;
+ uint32_t min_io_size;
+ uint32_t leb_size;
+ uint32_t leb_cnt;
+ uint32_t max_leb_cnt;
+ uint64_t max_bud_bytes;
+ uint32_t log_lebs;
+ uint32_t lpt_lebs;
+ uint32_t orph_lebs;
+ uint32_t jhead_cnt;
+ uint32_t fanout;
+ uint32_t lsave_cnt;
+ uint32_t fmt_version;
+ uint16_t default_compr;
+ uint8_t padding1[2];
+ uint32_t rp_uid;
+ uint32_t rp_gid;
+ uint64_t rp_size;
+ uint32_t time_gran;
+ uint8_t uuid[16];
+ uint32_t ro_compat_version;
+ uint8_t padding2[3968];
+};
+
+/* Erase counter header magic number (ASCII "UBI#") */
+#define UBI_EC_HDR_MAGIC 0x55424923
+
+#define UBI_MAGIC "UBI#"
+#define UBI_MAGIC_SIZE 0x04
+
+#define UBI_VERSION 1
+#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF
+#define UBI_IMAGE_SEQ_BASE 0x12345678
+#define UBI_DEF_ERACE_COUNTER 0
+#define UBI_CRC32_INIT 0xFFFFFFFFU
+#define UBIFS_CRC32_INIT 0xFFFFFFFFU
+
+/* Erase counter header fields */
+struct __attribute__ ((packed)) ubi_ec_hdr {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t padding1[3];
+ uint64_t ec; /* Warning: the current limit is 31-bit anyway! */
+ uint32_t vid_hdr_offset;
+ uint32_t data_offset;
+ uint32_t image_seq;
+ uint8_t padding2[32];
+ uint32_t hdr_crc;
+};
+
+/* Volume identifier header fields */
+struct __attribute__ ((packed)) ubi_vid_hdr {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t vol_type;
+ uint8_t copy_flag;
+ uint8_t compat;
+ uint32_t vol_id;
+ uint32_t lnum;
+ uint8_t padding1[4];
+ uint32_t data_size;
+ uint32_t used_ebs;
+ uint32_t data_pad;
+ uint32_t data_crc;
+ uint8_t padding2[4];
+ uint64_t sqnum;
+ uint8_t padding3[12];
+ uint32_t hdr_crc;
+};
+
+#define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr)
+#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr)
+#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(uint32_t))
+#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(uint32_t))
+
+#define UBI_MAX_VOLUMES 128
+#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096)
+#define UBI_LAYOUT_VOLUME_ID UBI_INTERNAL_VOL_START
+#define UBI_FM_SB_VOLUME_ID (UBI_INTERNAL_VOL_START + 1)
+
+/**
+ * struct ubi_scan_info - UBI scanning information.
+ * @ec: erase counters or eraseblock status for all eraseblocks
+ * @mean_ec: mean erase counter
+ * @bad_cnt: count of bad eraseblocks
+ * @good_cnt: count of non-bad eraseblocks
+ * @empty_cnt: count of empty eraseblocks
+ * @vid_hdr_offs: volume ID header offset from the found EC headers (%-1 means
+ * undefined)
+ * @data_offs: data offset from the found EC headers (%-1 means undefined)
+ * @image_seq: image sequence
+ */
+struct ubi_scan_info {
+ uint64_t *ec;
+ uint64_t mean_ec;
+ int bad_cnt;
+ int good_cnt;
+ int empty_cnt;
+ unsigned vid_hdr_offs;
+ unsigned data_offs;
+ uint32_t image_seq;
+};
+
+int flash_ubi_img(struct ptentry *ptn, void *data, unsigned size);
+#endif
diff --git a/include/dev/flash.h b/include/dev/flash.h
index f2b10db..9c41561 100644
--- a/include/dev/flash.h
+++ b/include/dev/flash.h
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
@@ -40,6 +41,7 @@
struct flash_info {
unsigned id;
+ unsigned id2;
unsigned type;
unsigned vendor;
unsigned device;
diff --git a/include/platform.h b/include/platform.h
index a239567..e71c407 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -53,6 +53,7 @@
unsigned board_machtype(void);
unsigned board_platform_id(void);
unsigned check_reboot_mode(void);
+unsigned check_hard_reboot_mode(void);
void platform_uninit_timer(void);
void reboot_device(unsigned);
int set_download_mode(enum dload_mode mode);
@@ -61,6 +62,7 @@
void clock_config_cdc(uint32_t interface);
int platform_is_msm8939();
int platform_is_msm8909();
+int platform_is_msm8992();
int boot_device_mask(int);
uint32_t platform_detect_panel();
#endif
diff --git a/include/string.h b/include/string.h
index 661e746..593ecf2 100644
--- a/include/string.h
+++ b/include/string.h
@@ -33,6 +33,8 @@
void *memchr (void const *, int, size_t) __PURE;
int memcmp (void const *, const void *, size_t) __PURE;
void *memcpy (void *, void const *, size_t);
+/* secure memcpy, does not copy beyong size of dest buffer*/
+size_t memscpy (void *, size_t, void const *, size_t);
void *memmove(void *, void const *, size_t);
void *memset (void *, int, size_t);
diff --git a/include/target.h b/include/target.h
index 4a2891c..772afdf 100644
--- a/include/target.h
+++ b/include/target.h
@@ -85,4 +85,5 @@
void ulpi_write(unsigned val, unsigned reg);
void target_crypto_init_params(void);
int target_cont_splash_screen(void);
+bool target_build_variant_user();
#endif
diff --git a/lib/libc/string/memscpy.c b/lib/libc/string/memscpy.c
new file mode 100644
index 0000000..3dd4d6b
--- /dev/null
+++ b/lib/libc/string/memscpy.c
@@ -0,0 +1,37 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Fundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <string.h>
+
+size_t memscpy(void *dest, size_t dst_size, const void *src, size_t src_size)
+{
+ size_t copy_size = dst_size < src_size ? dst_size : src_size;
+ memcpy(dest, src, copy_size);
+ return copy_size;
+}
diff --git a/lib/libc/string/rules.mk b/lib/libc/string/rules.mk
index fc1ceb2..97a5db8 100644
--- a/lib/libc/string/rules.mk
+++ b/lib/libc/string/rules.mk
@@ -8,6 +8,7 @@
memcpy \
memmove \
memset \
+ memscpy \
strcat \
strchr \
strcmp \
diff --git a/makefile b/makefile
index 1056726..252903e 100644
--- a/makefile
+++ b/makefile
@@ -97,6 +97,14 @@
# Useful for header files that may be included by one or more source files.
SRCDEPS := $(CONFIGHEADER)
+ifeq ($(VERIFIED_BOOT),1)
+ DEFINES += VERIFIED_BOOT=1
+ DEFINES += _SIGNED_KERNEL=1
+ ifeq ($(DEFAULT_UNLOCK),true)
+ DEFINES += DEFAULT_UNLOCK=1
+ endif
+endif
+
# these need to be filled out by the project/target/platform rules.mk files
TARGET :=
PLATFORM :=
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index d1fac29..fe66038 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -228,6 +228,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
@@ -247,6 +248,8 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE (0xFD923380)
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
diff --git a/platform/fsm9010/acpuclock.c b/platform/fsm9010/acpuclock.c
index a8a8f54..289e360 100644
--- a/platform/fsm9010/acpuclock.c
+++ b/platform/fsm9010/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -149,14 +149,14 @@
}
else
{
- dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ret = 0;
ASSERT(0);
}
-
if(ret)
{
- dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
ASSERT(0);
}
@@ -170,21 +170,23 @@
void clock_config_uart_dm(uint8_t id)
{
int ret;
- char str[256];
+ char iclk[64];
+ char cclk[64];
- sprintf(str, "uart%d_iface_clk", id);
- ret = clk_get_set_enable(str, 0, 1);
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
if(ret)
{
- dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
ASSERT(0);
}
- sprintf(str, "uart%d_core_clk", id);
- ret = clk_get_set_enable(str, 7372800, 1);
+ ret = clk_get_set_enable(cclk, 7372800, 1);
if(ret)
{
- dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
ASSERT(0);
}
}
@@ -343,3 +345,66 @@
return;
}
}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret = 0;
+
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ return;
+}
+
diff --git a/platform/fsm9010/fsm9010-clock.c b/platform/fsm9010/fsm9010-clock.c
index a3d03e4..6bff69f 100644
--- a/platform/fsm9010/fsm9010-clock.c
+++ b/platform/fsm9010/fsm9010-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -49,6 +49,11 @@
/* Clock Operations */
+static struct clk_ops clk_ops_rst =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -357,6 +362,160 @@
},
};
+/* USB30 Clocks */
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "sys_noc_usb30_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb2b_phy_sleep_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB2A_PHY_SLEEP_CBCR,
+ .bcr_reg = (uint32_t *) GCC_USB2A_PHY_BCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
+ F( 125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
+ .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
+ .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_master_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) GCC_USB30_BCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = {
+ F( 1200000, cxo, 16, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_phy_aux_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_USB3_PHY_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB3_PHY_AUX_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_phy_aux_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB3_PHY_AUX_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_phy_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) GCC_USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) GCC_USB3_PHY_PIPE_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_pipe_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t ) GCC_USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_rst,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = {
+ .cbcr_reg = (uint32_t *) GCC_USB_HS_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* CE Clocks */
static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
F( 50000000, gpll0, 12, 0, 0),
@@ -481,6 +640,17 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+
+ CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+
CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c),
CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c),
CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
diff --git a/platform/fsm9010/gpio.c b/platform/fsm9010/gpio.c
index e4d38c3..538831f 100644
--- a/platform/fsm9010/gpio.c
+++ b/platform/fsm9010/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -57,23 +57,24 @@
static struct {
unsigned int gpio_tx;
unsigned int gpio_rx;
+ unsigned int function;
} gpio_table[] = {
- { 12, 13 },
- { 4, 5 },
- { 8, 6 },
- { 10, 11 },
+ { 8, 6, 3 },
+ { 4, 5, 2 },
+ { 12, 13, 2 },
+ { 10, 11, 1 },
};
if (id >= ARRAY_SIZE(gpio_table))
return;
/* configure rx gpio */
- gpio_tlmm_config(gpio_table[id].gpio_rx, 2, GPIO_INPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(gpio_table[id].gpio_rx, gpio_table[id].function,
+ GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
- gpio_tlmm_config(gpio_table[id].gpio_tx, 2, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(gpio_table[id].gpio_tx, gpio_table[id].function,
+ GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
}
void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
diff --git a/platform/fsm9010/include/platform/clock.h b/platform/fsm9010/include/platform/clock.h
index 2690f53..fdb68d2 100644
--- a/platform/fsm9010/include/platform/clock.h
+++ b/platform/fsm9010/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_lib2.h>
-#define UART_DM_CLK_RX_TX_BIT_RATE 0x99
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xcc
void platform_clock_init(void);
@@ -43,5 +43,6 @@
void clock_config_ce(uint8_t instance);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
#endif
diff --git a/platform/fsm9010/include/platform/iomap.h b/platform/fsm9010/include/platform/iomap.h
index fca1800..68ebd32 100644
--- a/platform/fsm9010/include/platform/iomap.h
+++ b/platform/fsm9010/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -67,6 +67,7 @@
#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00200000)
+#define TCSR_PHSS_USB2_PHY_SEL 0xFD4AB000
#define CLK_CTL_BASE 0xFC400000
@@ -176,4 +177,60 @@
#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* USB 3.0 clocks */
+#define GCC_USB30_MASTER_CBCR (CLK_CTL_BASE + 0x0240)
+#define GCC_USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x0244)
+#define GCC_USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x0248)
+#define GCC_USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x024C)
+#define GCC_USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x0250)
+#define GCC_USB30_MASTER_M (CLK_CTL_BASE + 0x0254)
+#define GCC_USB30_MASTER_N (CLK_CTL_BASE + 0x0258)
+#define GCC_USB30_MASTER_D (CLK_CTL_BASE + 0x025C)
+#define GCC_USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x0260)
+#define GCC_USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x0264)
+
+/* USB Phy */
+#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x280)
+#define GCC_USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x284)
+#define GCC_USB3_PHY_AUX_CBCR (CLK_CTL_BASE + 0x288)
+#define GCC_USB3_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x28C)
+#define GCC_USB3_PHY_PIPE_MISC (CLK_CTL_BASE + 0x290)
+#define GCC_USB3_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x294)
+#define GCC_USB3_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x298)
+
+#define GCC_USB30_BCR (CLK_CTL_BASE + 0x274)
+#define GCC_SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x278)
+
+/* USB Misc */
+#define GCC_USB_HS_HSIC_BCR (CLK_CTL_BASE + 0x3C0)
+#define GCC_USB_HS_HSIC_GDSCR (CLK_CTL_BASE + 0x3C4)
+#define GCC_USB_BOOT_CLOCK_CTL (CLK_CTL_BASE + 0x1A00)
+#define GCC_USB_HS_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3EC0)
+#define GCC_USB_SS_PHY_LDO_EN (CLK_CTL_BASE + 0x3F00)
+
+/* USB HS */
+#define GCC_USB_HS_BCR (CLK_CTL_BASE + 0x480)
+#define GCC_USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define GCC_USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define GCC_USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define GCC_USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+#define GCC_USB2A_PHY_BCR (CLK_CTL_BASE + 0x4A8)
+#define GCC_USB2A_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x4AC)
+#define GCC_USB2_HS_PHY_ONLY_BCR (CLK_CTL_BASE + 0x4B0)
+
+#define GCC_QUSB2_PHY_BCR GCC_USB2A_PHY_BCR
+
+/* USB30 base */
+#define MSM_USB30_BASE 0xF9200000
+#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
+
+/* USB PHY */
+#define CM_DWC_USB2_CM_DWC_USB2_BASE 0xFCA00000
+#define CM_DWC_USB3_CM_DWC_USB3_BASE 0xFCA10000
+#define AHB2PHY_AHB2PHY_BASE 0xFCA06000
+
+#define QMP_PHY_BASE 0xF9B38000
+#define PLATFORM_QMP_OFFSET 0x8
+
#endif
diff --git a/platform/fsm9010/include/platform/irqs.h b/platform/fsm9010/include/platform/irqs.h
index 6b4900f..cba9a03 100644
--- a/platform/fsm9010/include/platform/irqs.h
+++ b/platform/fsm9010/include/platform/irqs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -45,9 +45,11 @@
#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
-#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
-#define USB1_IRQ (GIC_SPI_START + 142)
+#define USB30_EE1_IRQ (GIC_SPI_START + 224)
+#define USB30_EE2_IRQ (GIC_SPI_START + 225)
+#define USB30_POWER_EVENT_IRQ (GIC_SPI_START + 226)
+#define USB30_HS_PHY_IRQ (GIC_SPI_START + 227)
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/init.c b/platform/init.c
index aeb4f20..34c5726 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -140,3 +140,8 @@
{
return 0;
}
+
+__WEAK uint32_t use_hsonly_mode()
+{
+ return 0;
+}
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index fec3f86..4efca64 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -176,6 +176,8 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
@@ -200,6 +202,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 65f5dc6..4605314 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
@@ -183,6 +183,7 @@
#define ERR_INT_MASK0 0x108
#define RDBK_DATA0 0x068
+#define LANE_CTL 0x0A8
#define LANE_SWAP_CTL 0x0AC
#define TIMING_CTL 0x0C0
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index 18ae9e1..e2a66fe 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -187,6 +187,8 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0x1AC8300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define DSI0_REGULATOR_BASE (0x1AC8780)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
/* MDP */
#define MDP_BASE 0x1A00000
@@ -198,6 +200,14 @@
#define MDP_DMA_P_BUF_ADDR REG_MDP(0x90008)
#define MDP_DMA_P_BUF_Y_STRIDE REG_MDP(0x9000C)
+#define MDP_DMA_P_QOS_REMAPPER REG_MDP(0x90090)
+#define MDP_DMA_P_WATERMARK_0 REG_MDP(0x90094)
+#define MDP_DMA_P_WATERMARK_1 REG_MDP(0x90098)
+#define MDP_DMA_P_WATERMARK_2 REG_MDP(0x9009C)
+#define MDP_PANIC_ROBUST_CTRL REG_MDP(0x900A0)
+#define MDP_PANIC_LUT0 REG_MDP(0x900A4)
+#define MDP_ROBUST_LUT REG_MDP(0x900AC)
+
#define MDP_DSI_VIDEO_EN REG_MDP(0xF0000)
#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xF0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xF0008)
@@ -237,6 +247,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8909/platform.c b/platform/msm8909/platform.c
index 83f9060..97c6838 100644
--- a/platform/msm8909/platform.c
+++ b/platform/msm8909/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -195,6 +195,7 @@
case MSM8209:
case MSM8208:
case APQ8009:
+ case MSM8609:
ret = 1;
break;
default:
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index 0cdc26f..663a6ce 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -205,7 +205,7 @@
ASSERT(0);
}
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
ret = clk_get_set_enable("mdss_mdp_clk_src", 307200000, 1);
else
/* Set MDP clock to 320MHz */
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index e58525f..fd56c0e 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -159,6 +159,8 @@
#define DSI1_PHY_BASE (0x1AA0500)
#define DSI0_PLL_BASE (0x1A98300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define DSI0_REGULATOR_BASE (0x1A98780)
+#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
#define MDP_BASE (0x1A00000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
@@ -239,6 +241,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8916/msm8916-clock.c b/platform/msm8916/msm8916-clock.c
index d2b7215..c2ec604 100644
--- a/platform/msm8916/msm8916-clock.c
+++ b/platform/msm8916/msm8916-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -602,7 +602,7 @@
void platform_clock_init(void)
{
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
msm8939_clock_override();
clk_init(msm_clocks_8916, ARRAY_SIZE(msm_clocks_8916));
}
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index a367985..4b646fe 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -44,7 +44,7 @@
#define A53_SS_SIZE ((A53_SS_END - A53_SS_BASE)/MB)
/* LK memory - cacheable, write through */
-#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
@@ -55,6 +55,9 @@
#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
static mmu_section_t mmu_section_table[] = {
/* Physical addr, Virtual addr, Size (in MB), Flags */
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
@@ -63,12 +66,13 @@
{ SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
{ BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
- { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, SCRATCH_MEMORY},
{ BASE_ADDR_1, BASE_ADDR_1, 1024, COMMON_MEMORY},
};
int platform_is_msm8939();
+int platform_is_msm8929();
void platform_early_init(void)
{
@@ -81,7 +85,7 @@
int qtmr_irq()
{
- if (platform_is_msm8939())
+ if (platform_is_msm8939() || platform_is_msm8929())
return INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP_8x39;
else
return INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP_8x16;
@@ -171,6 +175,26 @@
return ret;
}
+int platform_is_msm8929()
+{
+ uint32_t platform = board_platform_id();
+ uint32_t ret = 0;
+
+ switch(platform)
+ {
+ case MSM8929:
+ case MSM8629:
+ case MSM8229:
+ case APQ8029:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
/* DYNAMIC SMEM REGION feature enables LK to dynamically
* read the SMEM addr info from TCSR_TZ_WONCE register.
* The first word read, if indicates a MAGIC number, then
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 0b1e4cf..ccb086f 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -224,6 +224,8 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
+#define DSI0_REGULATOR_BASE (0xFD922D80)
+#define DSI1_REGULATOR_BASE (0xFD923380)
#define EDP_BASE (0xFD923400)
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
@@ -249,6 +251,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index ab64e78..bb9709f 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -240,6 +240,11 @@
#define DSI1_PHY_BASE (0xFD9A0500)
#define DSI0_PLL_BASE (0xFD998300)
#define DSI1_PLL_BASE (0xFD9A0300)
+#define DSI0_REGULATOR_BASE (0xFD998780)
+#define DSI1_REGULATOR_BASE (0xFD9A0780)
+
+#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
+#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
#define MDP_BASE (0xfd900000)
@@ -540,6 +545,7 @@
#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
+#define LANE_CTL 0x0AC
#define LANE_SWAP_CTL 0x0B0
#define TIMING_CTL 0x0C4
@@ -550,4 +556,9 @@
#define VIDEO_MODE_VSYNC 0x034
#define VIDEO_MODE_VSYNC_VPOS 0x038
+#define QPNP_LED_CTRL_BASE 0xD000
+#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
+#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
+#define QPNP_RED_LPG_CTRL_BASE 0xB300
+
#endif
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 560a021..507158b 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -173,6 +173,23 @@
return 0;
}
+int platform_is_msm8992()
+{
+ int ret;
+
+ uint32_t platform = board_platform_id();
+ switch (platform) {
+ case MSM8992:
+ case APQ8092:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ }
+
+ return ret;
+}
+
addr_t get_bs_info_addr()
{
if (platform_is_msm8994())
diff --git a/platform/msm_shared/boot_verifier.c b/platform/msm_shared/boot_verifier.c
index 79accbf..0457ee3 100644
--- a/platform/msm_shared/boot_verifier.c
+++ b/platform/msm_shared/boot_verifier.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -26,6 +26,7 @@
*/
#include <stdlib.h>
+#include <stdint.h>
#include <crypto_hash.h>
#include <boot_verifier.h>
#include <image_verify.h>
@@ -36,6 +37,7 @@
#include <partition_parser.h>
#include <rsa.h>
#include <string.h>
+#include <openssl/err.h>
static KEYSTORE *oem_keystore;
static KEYSTORE *user_keystore;
@@ -43,7 +45,7 @@
BUF_DMA_ALIGN(keystore_buf, 4096);
char KEYSTORE_PTN_NAME[] = "keystore";
-static char *VERIFIED_FLASH_ALLOWED_PTN[] = {
+static const char *VERIFIED_FLASH_ALLOWED_PTN[] = {
"aboot",
"boot",
"recovery",
@@ -138,7 +140,7 @@
return ret;
}
- sig = d2i_X509_SIG(NULL, &input, len);
+ sig = d2i_X509_SIG(NULL, (const unsigned char **) &input, len);
if(sig == NULL)
{
dprintf(CRITICAL, "boot_verifier: Reading digest failed\n");
@@ -221,7 +223,7 @@
/* Verify target name */
if(strncmp((char*)(sig->auth_attr->target->data), pname,
sig->auth_attr->target->length) ||
- (strlen(pname) != sig->auth_attr->target->length))
+ (strlen(pname) != (unsigned long) sig->auth_attr->target->length))
{
dprintf(CRITICAL,
"boot_verifier: verification failure due to target name mismatch\n");
@@ -308,19 +310,19 @@
{
KEYSTORE *ks = NULL;
uint32_t len = 0;
- unsigned char *input = OEM_KEYSTORE;
+ const unsigned char *input = OEM_KEYSTORE;
if(oem_keystore != NULL)
return;
- len = read_der_message_length(input);
+ len = read_der_message_length((unsigned char *)input);
if(!len)
{
dprintf(CRITICAL, "boot_verifier: oem keystore length is invalid.\n");
return;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **) &input, len);
if(ks != NULL)
{
oem_keystore = ks;
@@ -358,7 +360,7 @@
return;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **)&input, len);
if(ks != NULL)
{
if(verify_keystore(user_addr, ks) == false)
@@ -407,7 +409,7 @@
goto verify_image_error;
}
- if((sig = d2i_VERIFIED_BOOT_SIG(NULL, &sig_addr, sig_len)) == NULL)
+ if((sig = d2i_VERIFIED_BOOT_SIG(NULL, (const unsigned char **) &sig_addr, sig_len)) == NULL)
{
dprintf(CRITICAL,
"boot_verifier: verification failure due to target name mismatch\n");
@@ -485,7 +487,7 @@
return ret;
}
- ks = d2i_KEYSTORE(NULL, &input, len);
+ ks = d2i_KEYSTORE(NULL, (const unsigned char **)&input, len);
if(ks != NULL)
{
ret = true;
@@ -493,9 +495,8 @@
return ret;
}
-static bool check_list(char**list, char* entry)
+static bool check_list(const char **list, const char* entry)
{
- int i = 0;
if(list == NULL || entry == NULL)
return false;
@@ -510,7 +511,7 @@
return false;
}
-bool boot_verify_flash_allowed(char * entry)
+bool boot_verify_flash_allowed(const char * entry)
{
return check_list(VERIFIED_FLASH_ALLOWED_PTN, entry);
}
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 0f592f9..8caad79 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -139,6 +139,8 @@
#else
ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE);
+ arch_clean_invalidate_cache_range((addr_t)&cmd_list_ptr, sizeof(struct cmd_element));
+
/* Enqueue the desc for the above command */
ret = bam_add_one_desc(bam_core,
CRYPTO_WRITE_PIPE_INDEX,
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index ce49916..ecffcc4 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -283,6 +283,9 @@
if (ret)
goto msm_display_init_out;
+ if (pdata->dfps_func)
+ ret = pdata->dfps_func(&(panel->panel_info));
+
/* Enable clock */
if (pdata->clk_func)
ret = pdata->clk_func(1, &(panel->panel_info));
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 61efb47..e128453 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -101,6 +101,7 @@
switch (resp_upiu->opcode)
{
+ case UPIU_QUERY_OP_READ_ATTRIBUTE:
case UPIU_QUERY_OP_READ_FLAG:
case UPIU_QUERY_OP_SET_FLAG:
if (buf_len < sizeof(uint32_t))
@@ -137,7 +138,7 @@
req_upiu.idn = query->idn;
req_upiu.trans_type = UPIU_TYPE_QUERY_REQ;
req_upiu.dd = UTRD_NO_DATA_TRANSFER;
- req_upiu.resp_ptr = (struct upiu_basic_hdr *) &resp_upiu;
+ req_upiu.resp_ptr = (struct upiu_basic_resp_hdr *) &resp_upiu;
req_upiu.resp_len = sizeof(resp_upiu);
req_upiu.resp_data_ptr = query->buf;
req_upiu.timeout_msecs = UTP_GENERIC_CMD_TIMEOUT;
@@ -159,6 +160,79 @@
return ret;
}
+int dme_set_fpurgeenable(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ STACKBUF_DMA_ALIGN(status, sizeof(uint32_t));
+ uint32_t try_again = DME_BPURGESTATUS_RETRIES;
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fPurgeEn,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_ATTRIBUTE,
+ UFS_IDX_bPurgeStatus,
+ 0,
+ 0,
+ (addr_t)status,
+ sizeof(uint32_t)};
+
+ if (dme_send_query_upiu(dev, &set_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Purge Enable failed\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+ dprintf(INFO, "%s:%d Purge enable status: %u\n", __func__,__LINE__, *result);
+
+ do {
+ *status = 0;
+ arch_invalidate_cache_range((addr_t) status, sizeof(uint32_t));
+ if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Purge Status Read failed\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+
+ switch (*status)
+ {
+
+ case 0x0:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation returning to ufs_erase. Purge Status 0x0\n", __func__, __LINE__);
+#endif
+ return UFS_SUCCESS;
+ case 0x3:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation has completed. Purge Status:0x3\n", __func__, __LINE__);
+#endif
+ // next read of status will move to 0
+ continue;
+ case 0x1:
+#ifdef DEBUG_UFS
+ dprintf(INFO, "%s:%d Purge operation is still in progress.. Retrying\n", __func__, __LINE__);
+#endif
+ try_again--;
+ continue;
+ case 0x2:
+ dprintf(CRITICAL, "%s:%d Purge operation stopped prematurely\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ case 0x4:
+ dprintf(CRITICAL, "%s:%d Purge operation failed due to logical unit queue not empty\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ case 0x5:
+ dprintf(CRITICAL, "%s:%d Purge operation general failure\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+ } while((*status == 0x1 || *status == 0x3) && try_again);
+
+ // should not come here
+ dprintf(CRITICAL, "%s:%d Purge operation timed out after checking status %d times\n", __func__, __LINE__, DME_BPURGESTATUS_RETRIES);
+ return -UFS_FAILURE;
+}
+
int dme_set_fpoweronwpen(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
@@ -430,7 +504,7 @@
int dme_send_nop_query(struct ufs_dev *dev)
{
struct upiu_req_build_type req_upiu;
- struct upiu_basic_hdr resp_upiu;
+ struct upiu_basic_resp_hdr resp_upiu;
int ret;
unsigned try_again;
@@ -491,6 +565,7 @@
switch (upiu_data->opcode)
{
case UPIU_QUERY_OP_READ_FLAG:
+ case UPIU_QUERY_OP_READ_ATTRIBUTE:
case UPIU_QUERY_OP_READ_DESCRIPTOR:
req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_READ_REQ;
break;
diff --git a/platform/msm_shared/flash-ubi.c b/platform/msm_shared/flash-ubi.c
new file mode 100644
index 0000000..0051a3a
--- /dev/null
+++ b/platform/msm_shared/flash-ubi.c
@@ -0,0 +1,615 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <dev/flash-ubi.h>
+#include <dev/flash.h>
+#include <qpic_nand.h>
+#include <rand.h>
+
+static
+const uint32_t crc32_table[256] = {
+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+ 0x2d02ef8dL
+};
+
+static uint32_t mtd_crc32(uint32_t crc, const void *buf, size_t size)
+{
+ const uint8_t *p = buf;
+
+ while (size--)
+ crc = crc32_table[(crc ^ *p++) & 0xff] ^ (crc >> 8);
+ return crc;
+}
+
+/**
+ * check_pattern - check if buffer contains only a certain byte pattern.
+ * @buf: buffer to check
+ * @patt: the pattern to check
+ * @size: buffer size in bytes
+ *
+ * This function returns %1 if there are only @patt bytes in @buf, and %0 if
+ * something else was also found.
+ */
+int check_pattern(const void *buf, uint8_t patt, int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ if (((const uint8_t *)buf)[i] != patt)
+ return 0;
+ return 1;
+}
+
+/**
+ * read_ec_hdr - read and check an erase counter header.
+ * @peb: number of the physical erase block to read the header for
+ * @ec_hdr: a &struct ubi_ec_hdr object where to store the read erase counter
+ * header
+ *
+ * This function reads erase counter header from physical eraseblock @peb and
+ * stores it in @ec_hdr. This function also checks the validity of the read
+ * header.
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - if PEB was found valid
+ * 1 - if PEB is empty
+ */
+static int read_ec_hdr(uint32_t peb, struct ubi_ec_hdr *ec_hdr)
+{
+ unsigned char *spare, *tmp_buf;
+ int ret = -1;
+ uint32_t crc;
+ int page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size()/page_size;
+
+ spare = (unsigned char *)malloc(flash_spare_size());
+ if (!spare)
+ {
+ dprintf(CRITICAL, "read_ec_hdr: Mem allocation failed\n");
+ return ret;
+ }
+
+ tmp_buf = (unsigned char *)malloc(page_size);
+ if (!tmp_buf)
+ {
+ dprintf(CRITICAL, "read_ec_hdr: Mem allocation failed\n");
+ goto out_tmp_buf;
+ }
+
+ if (qpic_nand_block_isbad(peb * num_pages_per_blk)) {
+ dprintf(CRITICAL, "read_ec_hdr: Bad block @ %d\n", peb);
+ goto out;
+ }
+
+ if (qpic_nand_read(peb * num_pages_per_blk, 1, tmp_buf, spare)) {
+ dprintf(CRITICAL, "read_ec_hdr: Read %d failed \n", peb);
+ goto out;
+ }
+ memcpy(ec_hdr, tmp_buf, UBI_EC_HDR_SIZE);
+
+ if (check_pattern((void *)ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+
+ /* Make sure we read a valid UBI EC_HEADER */
+ if (BE32(ec_hdr->magic) != (uint32_t)UBI_EC_HDR_MAGIC) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong magic at peb-%d Expected: %d, received %d\n",
+ peb, UBI_EC_HDR_MAGIC, BE32(ec_hdr->magic));
+ goto out;
+ }
+
+ if (ec_hdr->version != UBI_VERSION) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong version at peb-%d Expected: %d, received %d\n",
+ peb, UBI_VERSION, ec_hdr->version);
+ goto out;
+ }
+
+ if (BE64(ec_hdr->ec) > UBI_MAX_ERASECOUNTER) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong ec at peb-%d: %lld \n",
+ peb, BE64(ec_hdr->ec));
+ goto out;
+ }
+
+ crc = mtd_crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC);
+ if (BE32(ec_hdr->hdr_crc) != crc) {
+ dprintf(CRITICAL,
+ "read_ec_hdr: Wrong crc at peb-%d: calculated %d, recived %d\n",
+ peb,crc, BE32(ec_hdr->hdr_crc));
+ goto out;
+ }
+
+ ret = 0;
+out:
+ free(tmp_buf);
+out_tmp_buf:
+ free(spare);
+ return ret;
+}
+
+/**
+ * write_ec_header() - Write provided ec_header for given PEB
+ * @peb: number of the physical erase block to write the header to
+ * @new_ech: the ec_header to write
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - on success
+ */
+static int write_ec_header(uint32_t peb, struct ubi_ec_hdr *new_ech)
+{
+ unsigned page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size()/page_size;
+ unsigned char *buf;
+ int ret = 0;
+
+ buf = malloc(sizeof(uint8_t) * page_size);
+ if (!buf) {
+ dprintf(CRITICAL, "write_ec_header: Mem allocation failed\n");
+ return -1;
+ }
+
+ memset(buf, 0, page_size);
+ ASSERT(page_size > sizeof(*new_ech));
+ memcpy(buf, new_ech, UBI_EC_HDR_SIZE);
+ ret = qpic_nand_write(peb * num_pages_per_blk, 1, buf, 0);
+ if (ret) {
+ dprintf(CRITICAL,
+ "write_ec_header: qpic_nand_write failed with %d\n", ret);
+ ret = -1;
+ goto out;
+ }
+
+out:
+ free(buf);
+ return ret;
+}
+
+/**
+ * scan_partition() - Collect the ec_headers info of a given partition
+ * @ptn: partition to read the headers of
+ *
+ * Returns allocated and filled struct ubi_scan_info (si).
+ * Note: si should be released by caller.
+ */
+static struct ubi_scan_info *scan_partition(struct ptentry *ptn)
+{
+ struct ubi_scan_info *si;
+ struct ubi_ec_hdr *ec_hdr;
+ unsigned i, curr_peb;
+ unsigned long long sum = 0;
+ int page_size = flash_page_size();
+ int ret;
+
+ si = malloc(sizeof(*si));
+ if (!si) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ return NULL;
+ }
+
+ memset((void *)si, 0, sizeof(*si));
+ si->ec = malloc(ptn->length * sizeof(uint64_t));
+ if (!si->ec) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ goto out_failed_ec;
+ }
+ memset((void *)si->ec, 0, ptn->length * sizeof(uint64_t));
+
+ ec_hdr = malloc(UBI_EC_HDR_SIZE);
+ if (!ec_hdr) {
+ dprintf(CRITICAL,"scan_partition: (%s) Memory allocation failed\n",
+ ptn->name);
+ goto out_failed;
+ }
+
+ curr_peb = ptn->start;
+ si->vid_hdr_offs = 0;
+ si->image_seq = rand() & UBI_IMAGE_SEQ_BASE;
+
+ for (i = 0; i < ptn->length; i++){
+ ret = read_ec_hdr(curr_peb + i, ec_hdr);
+ switch (ret) {
+ case 1:
+ si->empty_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ break;
+ case 0:
+ if (!si->vid_hdr_offs) {
+ si->vid_hdr_offs = BE32(ec_hdr->vid_hdr_offset);
+ si->data_offs = BE32(ec_hdr->data_offset);
+ if (!si->vid_hdr_offs || !si->data_offs ||
+ si->vid_hdr_offs % page_size ||
+ si->data_offs % page_size) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ si->vid_hdr_offs = 0;
+ continue;
+ }
+ if (BE32(ec_hdr->vid_hdr_offset) != si->vid_hdr_offs) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ continue;
+ }
+ if (BE32(ec_hdr->data_offset) != si->data_offs) {
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ continue;
+ }
+ }
+ si->good_cnt++;
+ si->ec[i] = BE64(ec_hdr->ec);
+ break;
+ case -1:
+ default:
+ si->bad_cnt++;
+ si->ec[i] = UBI_MAX_ERASECOUNTER;
+ break;
+ }
+ }
+
+ /*
+ * If less then 95% of the PEBs were "bad" (didn't have valid
+ * ec header), then set mean_ec = UBI_DEF_ERACE_COUNTER.
+ */
+ sum = 0;
+ if (si->good_cnt && (double)(si->good_cnt / ptn->length) * 100 > 95) {
+ for (i = 0; i < ptn->length; i++) {
+ if (si->ec[i] == UBI_MAX_ERASECOUNTER)
+ continue;
+ sum += si->ec[i];
+ }
+ si->mean_ec = sum / si->good_cnt;
+ } else {
+ si->mean_ec = UBI_DEF_ERACE_COUNTER;
+ }
+ free(ec_hdr);
+ return si;
+
+out_failed:
+ free(si->ec);
+out_failed_ec:
+ free(si);
+ return NULL;
+}
+
+/**
+ * update_ec_header() - Update provided ec_header
+ * @si: pointer to struct ubi_scan_info, holding the collected
+ * ec_headers information of the partition
+ * @index: index in si->ec[] of this peb. Relative to ptn->start
+ * @new_header: False if this is an update of an existing header.
+ * True if new header needs to be filled in
+ */
+static void update_ec_header(struct ubi_ec_hdr *old_ech,
+ const struct ubi_scan_info *si,
+ int index, bool new_header)
+{
+ uint32_t crc;
+
+ if (si->ec[index] < UBI_MAX_ERASECOUNTER)
+ old_ech->ec = BE64(si->ec[index] + 1);
+ else
+ old_ech->ec = BE64(si->mean_ec);
+
+ if (new_header) {
+ old_ech->vid_hdr_offset = BE32(si->vid_hdr_offs);
+ old_ech->data_offset = BE32(si->data_offs);
+ old_ech->magic = BE32(UBI_EC_HDR_MAGIC);
+ old_ech->version = UBI_VERSION;
+ }
+ old_ech->image_seq = BE32(si->image_seq);
+ crc = mtd_crc32(UBI_CRC32_INIT,
+ (const void *)old_ech, UBI_EC_HDR_SIZE_CRC);
+ old_ech->hdr_crc = BE32(crc);
+}
+
+/**
+ * calc_data_len - calculate how much real data is stored in the buffer
+ * @page_size: min I/O of the device
+ * @buf: a buffer with the contents of the physical eraseblock
+ * @len: the buffer length
+ *
+ * This function calculates how much "real data" is stored in @buf and
+ * returns the length (in number of pages). Continuous 0xFF bytes at the end
+ * of the buffer are not considered as "real data".
+ */
+static int calc_data_len(int page_size, const void *buf, int len)
+{
+ int i;
+
+ for (i = len - 1; i >= 0; i--)
+ if (((const uint8_t *)buf)[i] != 0xFF)
+ break;
+
+ /* The resulting length must be aligned to the minimum flash I/O size */
+ len = i + 1;
+ len = (len + page_size - 1) / page_size;
+ return len;
+}
+
+/**
+ * fastmap_present - returns true if Fastmap superblock is found
+ * @data: raw data to test
+ *
+ * This function returns 1 if the provided PEB data contains
+ * Fastmap superblock, 0 otherwise
+ */
+static int fastmap_present(const void *data){
+ struct ubi_ec_hdr *ec_hdr = (struct ubi_ec_hdr *)(data);
+ struct ubi_vid_hdr *vid_hdr;
+
+ vid_hdr = (struct ubi_vid_hdr *)(data + BE32(ec_hdr->vid_hdr_offset));
+ if (BE32(vid_hdr->vol_id) == UBI_FM_SB_VOLUME_ID)
+ return 1;
+ else
+ return 0;
+}
+
+/**
+ * ubi_erase_peb - Erase PEB and update EC header
+ * @peb_num: number of the PEB to erase
+ * @need_erase: if true PEB will be erased
+ * @si: UBI scan information
+ * @ptn_start: first PEB of the flashed partition
+ *
+ * This function erases the given PEB (if required) and writes a new EC
+ * header for it.
+ *
+ * Returns: -1 on error
+ * 0 on success
+ */
+static int ubi_erase_peb(int peb_num, int need_erase,
+ struct ubi_scan_info *si, int ptn_start)
+{
+ struct ubi_ec_hdr new_ech;
+ int page_size = flash_page_size();
+ int num_pages_per_blk = flash_block_size() / page_size;
+ int ret;
+
+ if (need_erase && qpic_nand_blk_erase(peb_num * num_pages_per_blk)) {
+ dprintf(INFO, "flash_ubi_img: erase of %d failed\n", peb_num);
+ return -1;
+ }
+ memset(&new_ech, 0xff, sizeof(new_ech));
+ update_ec_header(&new_ech, si, peb_num - ptn_start, true);
+
+ /* Write new ec_header */
+ ret = write_ec_header(peb_num, &new_ech);
+ if (ret) {
+ dprintf(CRITICAL, "flash_ubi_img: write ec_header to %d failed\n",
+ peb_num);
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * remove_F_flag() - Turn off space-fixup flag in the ubifs superblock
+ * @data: pointer to the peb to check in the flashed image
+ *
+ * The UBIFS Superblock will be located at LEB 0 of the image. LEB 0 will be
+ * mapped as follows:
+ * If the image contains Fastmap superblock:
+ * - LEB 0 will be at PEB3
+ * else:
+ * - LEB 0 will be at PEB2
+ */
+static void remove_F_flag(const void *leb_data)
+{
+ struct ubifs_ch *ch;
+ struct ubifs_sb_node *ubifs_sb;
+ struct ubi_ec_hdr *ech;
+ struct ubi_vid_hdr *vidh;
+ int vol_id;
+
+ ech = (struct ubi_ec_hdr *)leb_data;
+ vidh = (struct ubi_vid_hdr *)(leb_data + BE32(ech->vid_hdr_offset));
+ vol_id = BE32(vidh->vol_id);
+
+ if (vol_id > UBI_MAX_VOLUMES &&
+ vol_id != UBI_LAYOUT_VOLUME_ID &&
+ vol_id != UBI_FM_SB_VOLUME_ID)
+ return;
+
+ ubifs_sb = (struct ubifs_sb_node *)(leb_data + BE32(ech->data_offset));
+ ch = (struct ubifs_ch *)ubifs_sb;
+ if (ch->node_type != UBIFS_SB_NODE)
+ return;
+ if (ubifs_sb->flags & UBIFS_FLG_SPACE_FIXUP) {
+ ubifs_sb->flags &= (~UBIFS_FLG_SPACE_FIXUP);
+ ch->crc = mtd_crc32(UBIFS_CRC32_INIT, (void *)ubifs_sb + 8,
+ sizeof(struct ubifs_sb_node) - 8);
+ }
+}
+
+/**
+ * flash_ubi_img() - Write the provided (UBI) image to given partition
+ * @ptn: partition to write the image to
+ * @data: the image to write
+ * @size: size of the image to write
+ *
+ * Return codes:
+ * -1 - in case of error
+ * 0 - on success
+ */
+int flash_ubi_img(struct ptentry *ptn, void *data, unsigned size)
+{
+ struct ubi_scan_info *si;
+ struct ubi_ec_hdr *old_ech;
+ uint32_t curr_peb = ptn->start;
+ void *img_peb;
+ unsigned page_size = flash_page_size();
+ unsigned block_size = flash_block_size();
+ int num_pages_per_blk = block_size / page_size;
+ int num_pages;
+ int ret, need_erase;
+ int bad_blocks_cnt = 0;
+ int fmsb_peb = 0;
+
+ si = scan_partition(ptn);
+ if (!si) {
+ dprintf(CRITICAL, "flash_ubi_img: scan_partition failed\n");
+ return -1;
+ }
+
+ /*
+ * In case si->vid_hdr_offs is still -1 (non UBI image was
+ * flashed on device, get the value from the image to flush
+ */
+ if (!si->vid_hdr_offs){
+ struct ubi_ec_hdr *echd = (struct ubi_ec_hdr *)data;
+ si->vid_hdr_offs = BE32(echd->vid_hdr_offset);
+ si->data_offs = BE32(echd->data_offset);
+ }
+
+ need_erase = (si->empty_cnt == (int)ptn->length ? 0 : 1);
+ /* Update the "to be" flashed image and flash it */
+ img_peb = data;
+ while (size && curr_peb < ptn->start + ptn->length) {
+ if (need_erase && qpic_nand_blk_erase(curr_peb * num_pages_per_blk)) {
+ dprintf(CRITICAL, "flash_ubi_img: erase of %d failed\n",
+ curr_peb);
+ bad_blocks_cnt++;
+ curr_peb++;
+ continue;
+ }
+ remove_F_flag(img_peb);
+ /* Update the ec_header in the image */
+ old_ech = (struct ubi_ec_hdr *)img_peb;
+ update_ec_header(old_ech, si, curr_peb - ptn->start, false);
+ if (size < block_size)
+ num_pages = size / page_size;
+ else
+ num_pages = calc_data_len(page_size, img_peb, block_size);
+ /* Write one block from image */
+ ret = qpic_nand_write(curr_peb * num_pages_per_blk,
+ num_pages, img_peb, 0);
+ if (ret) {
+ dprintf(CRITICAL, "flash_ubi_img: writing to peb-%d failed\n",
+ curr_peb);
+ bad_blocks_cnt++;
+ curr_peb++;
+ continue;
+ }
+ if (size < block_size)
+ size = 0;
+ else
+ size -= block_size;
+
+ if (fastmap_present(img_peb))
+ fmsb_peb = curr_peb;
+ img_peb += flash_block_size();
+ curr_peb++;
+ }
+
+ if (size) {
+ dprintf(CRITICAL,
+ "flash_ubi_img: Not enough good blocks to flash image!");
+ ret = -1;
+ goto out;
+ }
+
+ /* Erase and write ec_header for the rest of the blocks */
+ for (; curr_peb < ptn->start + ptn->length; curr_peb++)
+ if (ubi_erase_peb(curr_peb, need_erase, si, ptn->start))
+ bad_blocks_cnt++;
+
+ ret = 0;
+ /*
+ * If flashed image contains fastmap data and bad blocks were found
+ * we need to invalidate the flashed fastmap since it isn't accurate
+ * anymore.
+ */
+ if (bad_blocks_cnt && fmsb_peb) {
+ dprintf(CRITICAL, "flash_ubi_img: invalidate fmsb\n");
+ ret = ubi_erase_peb(ptn->start + 2, 1, si, ptn->start);
+ }
+
+out:
+ free(si->ec);
+ free(si);
+ return ret;
+}
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index 839f301..0967cd1 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -183,6 +183,11 @@
ept->next = ept_list;
ept_list = ept;
+ arch_clean_invalidate_cache_range((addr_t) ept,
+ sizeof(struct udc_endpoint));
+ arch_clean_invalidate_cache_range((addr_t) ept->head,
+ sizeof(struct ept_queue_head));
+
DBG("ept%d %s @%p/%p max=%d bit=%x\n",
num, in ? "in" : "out", ept, ept->head, max_pkt, ept->bit);
@@ -525,6 +530,7 @@
DBG("setup_tx %p %d\n", buf, len);
memcpy(ep0req->buf, buf, len);
ep0req->buf = (void *)PA((addr_t)ep0req->buf);
+ arch_clean_invalidate_cache_range((addr_t)ep0req->buf, len);
ep0req->complete = ep0in_complete;
ep0req->length = len;
udc_request_queue(ep0in, ep0req);
@@ -541,6 +547,7 @@
arch_clean_invalidate_cache_range((addr_t) ept->head->setup_data,
sizeof(struct ept_queue_head));
memcpy(&s, ept->head->setup_data, sizeof(s));
+ arch_clean_invalidate_cache_range((addr_t)&s, sizeof(s));
writel(ept->bit, USB_ENDPTSETUPSTAT);
DBG("handle_setup type=0x%02x req=0x%02x val=%d idx=%d len=%d (%s)\n",
diff --git a/platform/msm_shared/include/boot_verifier.h b/platform/msm_shared/include/boot_verifier.h
index 616f23c..972086d 100644
--- a/platform/msm_shared/include/boot_verifier.h
+++ b/platform/msm_shared/include/boot_verifier.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -156,5 +156,5 @@
/* Function to validate keystore */
bool boot_verify_validate_keystore(unsigned char * user_addr);
/* Function to check if partition is allowed to flash in verified mode */
-bool boot_verify_flash_allowed(char * entry);
+bool boot_verify_flash_allowed(const char * entry);
#endif
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 0bc2b3d..aa11c54 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -51,6 +51,7 @@
#define DME_NOP_NUM_RETRIES 20
#define DME_FDEVICEINIT_RETRIES 20
#define DME_FPOWERONWPEN_RETRIES 20
+#define DME_BPURGESTATUS_RETRIES 500000
/* Timeout value for commands. */
#define DME_NOP_QUERY_TIMEOUT 10
@@ -72,6 +73,7 @@
#define UFS_IDX_bBootLunEn 0x00
#define UFS_IDX_bCurrentPowerMode 0x01
#define UFS_IDX_bActiveICCLevel 0x03
+#define UFS_IDX_bPurgeStatus 0x06
#define UFS_IDX_bRefClkFreq 0x0a
#define UFS_IDX_bConfigDescrLock 0x0b
@@ -84,6 +86,7 @@
/* Flags definitions */
#define UFS_IDX_fDeviceInit 0x01
#define UFS_IDX_fPowerOnWPEn 0x03
+#define UFS_IDX_fPurgeEn 0x06
enum utp_query_response_upiu_type
{
@@ -246,6 +249,9 @@
*/
int dme_set_fpoweronwpen(struct ufs_dev *dev);
+/* Purge is used to securely erase blocks that are unmapped in ufs */
+int dme_set_fpurgeenable(struct ufs_dev *dev);
+
/* Unit descriptor gives the characteristics and capabilities of
* logical units.
*/
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 6c293af..9515354 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -82,6 +82,7 @@
#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
+#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDSS_MAX_LINE_BUF_WIDTH 2048
@@ -117,9 +118,6 @@
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x3F8)
#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x4F0)
-#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
-#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
-
#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
#define MDP_INTF_2_BASE REG_MDP(0x12900)
@@ -164,7 +162,6 @@
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x02E0)
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x02E4)
-#define VBIF_VBIF_QOS_REMAP_00 REG_MDP(0xC8020)
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0x24004)
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0x240D8)
#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0x240F0)
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 2ec9398..c2ddd9b 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -162,6 +162,9 @@
uint32_t halfbit_clock;
uint32_t vco_clock;
uint32_t vco_delay;
+ uint32_t vco_min;
+ uint32_t vco_max;
+ uint32_t en_vco_zero_phase;
uint8_t directpath;
uint8_t posdiv1;
uint8_t posdiv3;
@@ -211,8 +214,7 @@
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
void mdss_dsi_phy_sw_reset(uint32_t ctl_base);
-int mdss_dsi_phy_init(struct mipi_panel_info *mipi,
- uint32_t ctl_base, uint32_t phy_base);
+int mdss_dsi_phy_init(struct mipi_panel_info *mipi);
void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi,
uint32_t phy_base);
int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo);
@@ -230,7 +232,8 @@
uint16_t dst_format,
uint16_t traffic_mode,
uint8_t lane_en,
- uint16_t low_pwr_stop_mode,
+ uint8_t pulse_mode_hsa_he,
+ uint32_t low_pwr_stop_mode,
uint8_t eof_bllp_pwr,
uint8_t interleav,
uint32_t ctl_base);
@@ -253,8 +256,8 @@
int rdbk_len);
int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
struct mdss_dsi_pll_config *pd);
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd);
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ struct mdss_dsi_pll_config *pd);
void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index dbf02b5..4b09f69 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -36,6 +36,9 @@
#define TRUE 1
#define FALSE 0
+#define DFPS_MAX_FRAME_RATE 10
+#define DFPS_PLL_CODES_SIZE 0x1000 /* One page */
+
/* panel type list */
#define NO_PANEL 0xffff /* No Panel */
#define MDDI_PANEL 1 /* MDDI */
@@ -143,6 +146,30 @@
uint32_t max_pred_err;
};
+
+struct dfps_panel_info {
+ uint32_t enabled;
+ uint32_t frame_rate_cnt;
+ uint32_t frame_rate[DFPS_MAX_FRAME_RATE];
+};
+
+struct dfps_pll_codes {
+ uint32_t codes[2];
+};
+
+struct dfps_codes_info {
+ uint32_t is_valid;
+ uint32_t frame_rate;
+ uint32_t clk_rate;
+ struct dfps_pll_codes pll_codes;
+};
+
+struct dfps_info {
+ struct dfps_panel_info panel_dfps;
+ struct dfps_codes_info codes_dfps[DFPS_MAX_FRAME_RATE];
+ void *dfps_fb_base;
+};
+
/* intf timing settings */
struct intf_timing_params {
uint32_t width;
@@ -226,6 +253,12 @@
uint32_t phy_base;
uint32_t sctl_base;
uint32_t sphy_base;
+ uint32_t reg_base;
+ uint32_t sreg_base;
+ uint32_t pll_0_base;
+ uint32_t pll_1_base;
+
+ struct dfps_pll_codes pll_codes;
};
struct edp_panel_info {
@@ -282,6 +315,8 @@
struct hdmi_panel_info hdmi;
struct edp_panel_info edp;
+ struct dfps_info dfps;
+
struct labibb_desc *labibb;
int (*on) (void);
@@ -305,6 +340,7 @@
uint32_t (*clk_func) (uint8_t enable, struct msm_panel_info *pinfo);
int (*bl_func) (uint8_t enable);
uint32_t (*pll_clk_func) (uint8_t enable, struct msm_panel_info *);
+ int (*dfps_func)(struct msm_panel_info *);
int (*post_power_func)(int enable);
int (*pre_init_func)(void);
};
diff --git a/platform/msm_shared/include/qmp_phy.h b/platform/msm_shared/include/qmp_phy.h
index c112919..4558abe 100644
--- a/platform/msm_shared/include/qmp_phy.h
+++ b/platform/msm_shared/include/qmp_phy.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,6 +30,12 @@
#include <platform/iomap.h>
+struct qmp_reg
+{
+ uint32_t off;
+ uint32_t val;
+};
+
/* QMP register offsets */
#define QSERDES_COM_DEC_START1 (PLATFORM_QMP_OFFSET + 0xA4)
#define QSERDES_COM_DEC_START2 (PLATFORM_QMP_OFFSET + 0x104)
@@ -81,5 +87,6 @@
void usb30_qmp_phy_reset(void);
void usb30_qmp_phy_init(void);
+bool use_hsonly_mode();
#endif
diff --git a/platform/msm_shared/include/qpic_nand.h b/platform/msm_shared/include/qpic_nand.h
index f640cf8..14282ec 100644
--- a/platform/msm_shared/include/qpic_nand.h
+++ b/platform/msm_shared/include/qpic_nand.h
@@ -52,6 +52,7 @@
#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
#define NAND_READ_ID NAND_REG(0x0040)
#define NAND_READ_STATUS NAND_REG(0x0044)
+#define NAND_READ_ID2 NAND_REG(0x0048)
#define NAND_CONFIG_DATA NAND_REG(0x0050)
#define NAND_CONFIG NAND_REG(0x0054)
#define NAND_CONFIG_MODE NAND_REG(0x0058)
@@ -310,7 +311,9 @@
struct flash_id
{
unsigned flash_id;
+ unsigned flash_id2;
unsigned mask;
+ unsigned mask2;
unsigned density;
unsigned widebus;
unsigned pagesize;
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 1614a95..283f1cc 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -123,6 +123,23 @@
} feature_version_rsp;
typedef struct{
+ uint32 *status_ptr;
+ uint32 status_len;
+} get_secure_state_req;
+
+typedef struct{
+ uint32 status_low;
+ uint32 status_high;
+} get_secure_state_rsp;
+
+typedef struct{
+ uint32 row_address;
+ uint32 addr_type;
+ uint32 *row_data;
+ uint32 *qfprom_api_status;
+} qfprom_read_row_req;
+
+typedef struct{
uint32 *keystore_ptr;
uint32 keystore_len;
} ssd_protect_keystore_req;
@@ -154,6 +171,14 @@
uint32_t out_buf_size;
}__PACKED;
+typedef struct {
+ uint8_t *in_buf;
+ uint32_t in_buf_size;
+ uint8_t *out_buf;
+ uint32_t out_buf_size;
+ uint32_t direction;
+} mdtp_cipher_dip_req;
+
/* SCM support as per ARM spec */
/*
* Structure to define the argument for scm call
@@ -227,12 +252,13 @@
#define IOMMU_SECURE_CFG 0x02
#define TZ_INFO_GET_FEATURE_ID 0x03
+#define TZ_INFO_GET_SECURE_STATE 0x04
#define PRNG_CMD_ID 0x01
#define IS_CALL_AVAIL_CMD 0x01
/* Download Mode specific arguments to be passed to TZ */
-#define SCM_EDLOAD_MODE 0x02
+#define SCM_EDLOAD_MODE 0x01
#define SCM_DLOAD_MODE 0x10
/* SSD parsing status messages from TZ */
@@ -272,11 +298,30 @@
int decrypt_scm_v2(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int encrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int scm_svc_version(uint32 * major, uint32 * minor);
+
+/**
+ * Check security status on the device. Returns the security check result.
+ * Bit value 0 means the check passing, and bit value 1 means the check failing.
+ *
+ * @state_low[out] : lower 32 bits of the state:
+ * Bit 0: secboot enabling check failed
+ * Bit 1: Sec HW key is not programmed
+ * Bit 2: debug disable check failed
+ * Bit 3: Anti-rollback check failed
+ * Bit 4: fuse config check failed
+ * Bit 5: rpmb fuse check failed
+ * @state_high[out] : highr 32 bits of the state.
+ *
+ * Returns 0 on success, negative on failure.
+ */
+int scm_svc_get_secure_state(uint32_t *state_low, uint32_t *state_high);
+
int scm_protect_keystore(uint32_t * img_ptr, uint32_t img_len);
#define SCM_SVC_FUSE 0x08
#define SCM_BLOW_SW_FUSE_ID 0x01
#define SCM_IS_SW_FUSE_BLOWN_ID 0x02
+#define SCM_QFPROM_READ_ROW_ID 0x05
#define HLOS_IMG_TAMPER_FUSE 0
@@ -287,6 +332,9 @@
#define SCM_SVC_ES 0x10
#define SCM_SAVE_PARTITION_HASH_ID 0x01
+#define SCM_SVC_MDTP 0x12
+#define SCM_MDTP_CIPHER_DIP 0x01
+
#define SCM_SVC_PWR 0x9
#define SCM_IO_DISABLE_PMIC_ARBITER 0x1
@@ -303,9 +351,37 @@
uint8_t switch_ce_chn_cmd(enum ap_ce_channel_type channel);
+/**
+ * Encrypt or Decrypt a Data Integrity Partition (DIP) structure using a
+ * HW derived key. The DIP is used for storing integrity information for
+ * Mobile Device Theft Protection (MDTP) service.
+ *
+ * @in_buf[in] : Pointer to plain text buffer.
+ * @in_buf_size[in] : Plain text buffer size.
+ * @out_buf[in] : Pointer to encrypted buffer.
+ * @out_buf_size[in] : Encrypted buffer size.
+ * @direction[in] : 0 for ENCRYPTION, 1 for DECRYPTION.
+ *
+ * Returns 0 on success, negative on failure.
+ */
+int mdtp_cipher_dip_cmd(uint8_t *in_buf, uint32_t in_buf_size, uint8_t *out_buf,
+ uint32_t out_buf_size, uint32_t direction);
void set_tamper_fuse_cmd();
+/**
+ * Reads the row data of the specified QFPROM row address.
+ *
+ * @row_address[in] : Row address in the QFPROM region to read.
+ * @addr_type[in] : Raw or corrected address.
+ * @row_data[in] : Pointer to the data to be read.
+ * @qfprom_api_status[out] : Status of the read operation.
+ *
+ * Returns Any errors while reading data from the specified
+ * Returns 0 on success, negative on failure.
+ */
+int qfprom_read_row_cmd(uint32_t row_address, uint32_t addr_type, uint32_t *row_data, uint32_t *qfprom_api_status);
+
int scm_halt_pmic_arbiter();
int scm_call_atomic2(uint32_t svc, uint32_t cmd, uint32_t arg1, uint32_t arg2);
int restore_secure_cfg(uint32_t id);
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index 0cdfe2f..d3bc7f5 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -76,7 +76,9 @@
#define SDCC_DLL_EN BIT(16)
#define SDCC_DLL_CDR_EN BIT(17)
#define SDCC_DLL_CLK_OUT_EN BIT(18)
+#define SDCC_FLL_CYCLE_CNT BIT(18)
#define SDCC_DLL_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_CLOCK_DISABLE BIT(21)
#define SDCC_DLL_PDN_EN BIT(29)
#define SDCC_DLL_RESET_EN BIT(30)
#define SDCC_DLL_CONFIG_MCLK_START 0x18
@@ -124,6 +126,8 @@
#define SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0 0x11C
+#define TCXO_FREQ 19200000
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
diff --git a/platform/msm_shared/include/ucs.h b/platform/msm_shared/include/ucs.h
index 094946e..48c50db 100644
--- a/platform/msm_shared/include/ucs.h
+++ b/platform/msm_shared/include/ucs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -175,4 +175,6 @@
int ucs_do_scsi_rpmb_read(struct ufs_dev *dev, uint32_t *req_buf, uint32_t blk_cnt,
uint32_t *resp_buffer, uint32_t *response_length);
+/* This function parses the first byte of the sense data and returns the sense key */
+int parse_sense_key(uint32_t sense_data);
#endif
diff --git a/platform/msm_shared/include/upiu.h b/platform/msm_shared/include/upiu.h
index 1c9968d..e081909 100644
--- a/platform/msm_shared/include/upiu.h
+++ b/platform/msm_shared/include/upiu.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -44,6 +44,27 @@
uint16_t data_seg_len;
} __PACKED;
+
+struct upiu_basic_resp_hdr
+{
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ uint8_t task_tag;
+ uint8_t cmd_set_type;
+ uint8_t query_task_mgmt_func;
+ uint8_t response;
+ uint8_t status;
+ uint8_t total_ehs_len;
+ uint8_t device_info;
+ uint16_t data_seg_len;
+ uint32_t residual_transfer_count;
+ uint32_t reserved[4];
+ uint16_t sense_length;
+ uint16_t sense_response_code;
+ uint32_t sense_data[4];
+} __PACKED;
+
struct upiu_trans_mgmt_query_hdr
{
struct upiu_basic_hdr basic_hdr;
@@ -149,7 +170,7 @@
uint8_t idn;
uint8_t index;
uint8_t selector;
- struct upiu_basic_hdr *resp_ptr;
+ struct upiu_basic_resp_hdr *resp_ptr;
uint64_t resp_len;
uint16_t resp_data_len;
addr_t resp_data_ptr;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index cd7e5a4..ddda7ee 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -73,6 +73,32 @@
return mdss_mdp_intf_off;
}
+static uint32_t mdss_mdp_get_ppb_offset()
+{
+ uint32_t mdss_mdp_ppb_off = 0;
+ uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
+
+ /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_108)
+ mdss_mdp_ppb_off = 0x1420;
+ else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
+ mdss_mdp_ppb_off = 0x1334;
+ else
+ dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n");
+
+ return mdss_mdp_ppb_off;
+}
+
+static uint32_t mdss_mdp_vbif_qos_remap_get_offset()
+{
+ uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
+
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
+ return 0xB0020;
+ else
+ return 0xC8020;
+}
+
void mdp_clk_gating_ctrl(void)
{
writel(0x40000000, MDP_CLK_CTRL0);
@@ -118,6 +144,9 @@
else
*ctl0_reg_val = 0x22048;
*ctl1_reg_val = 0x24090;
+
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(4);
break;
case MDSS_MDP_PIPE_TYPE_DMA:
if (dual_pipe_single_ctl)
@@ -125,6 +154,8 @@
else
*ctl0_reg_val = 0x22840;
*ctl1_reg_val = 0x25080;
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(12);
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
@@ -133,6 +164,8 @@
else
*ctl0_reg_val = 0x22041;
*ctl1_reg_val = 0x24082;
+ if (pinfo->lcdc.dst_split)
+ *ctl0_reg_val |= BIT(1);
break;
}
/* For targets from MDP v1.5, MDP INTF registers are double buffered */
@@ -146,7 +179,8 @@
*ctl1_reg_val |= BIT(31);
}
} else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
- (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) {
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_109) ||
+ (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) {
if (pinfo->dest == DISPLAY_2) {
*ctl0_reg_val |= BIT(29);
*ctl1_reg_val |= BIT(30);
@@ -423,8 +457,9 @@
}
if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) {
- writel(BIT(16), MDP_REG_PPB0_CONFIG);
- writel(BIT(5), MDP_REG_PPB0_CNTL);
+ uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
+ writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
+ writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
@@ -505,6 +540,7 @@
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
uint32_t adjust_xres = 0;
+ uint32_t fetch_enable = BIT(31);
struct lcdc_panel_info *lcdc = NULL;
@@ -549,8 +585,11 @@
fetch_start = (v_total - fetch_lines) * h_total + 1;
- writel(fetch_start, MDP_PROG_FETCH_START + intf_base);
- writel(BIT(31), MDP_INTF_CONFIG + intf_base);
+ if (pinfo->dfps.panel_dfps.enabled)
+ fetch_enable |= BIT(23);
+
+ writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base);
+ writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base);
}
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
@@ -562,7 +601,7 @@
height = fb->height;
width = fb->width;
- if (pinfo->lcdc.dual_pipe)
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
width /= 2;
/* write active region size*/
@@ -595,10 +634,17 @@
break;
}
+ /*
+ * When ping-pong split is enabled and two pipes are used,
+ * both the pipes need to be staged on the same layer mixer.
+ */
+ if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split)
+ left_staging_level |= right_staging_level;
+
/* Base layer for layer mixer 0 */
writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0);
- if (pinfo->lcdc.dual_pipe) {
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) {
writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE);
writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP);
@@ -696,7 +742,9 @@
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_105) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_109))
+ MDSS_MDP_HW_REV_109) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_110))
map = 0xA4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_103))
@@ -713,6 +761,7 @@
uint32_t left_pipe_xin_id, right_pipe_xin_id;
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t vbif_qos[4] = {0, 0, 0, 0};
+ uint32_t vbif_offset;
mdp_select_pipe_xin_id(pinfo,
&left_pipe_xin_id, &right_pipe_xin_id);
@@ -724,7 +773,8 @@
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
- MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) {
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) {
vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
@@ -733,8 +783,11 @@
return;
}
+ vbif_offset = mdss_mdp_vbif_qos_remap_get_offset();
+
for (i = 0; i < 4; i++) {
- reg_val = readl(VBIF_VBIF_QOS_REMAP_00 + i*4);
+ /* VBIF_VBIF_QOS_REMAP_00 */
+ reg_val = readl(REG_MDP(vbif_offset) + i*4);
mask = 0x3 << (left_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2);
@@ -744,7 +797,7 @@
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2);
}
- writel(reg_val, VBIF_VBIF_QOS_REMAP_00 + i*4);
+ writel(reg_val, REG_MDP(vbif_offset) + i*4);
}
}
@@ -943,6 +996,8 @@
if (pinfo->lcdc.split_display) {
reg = BIT(1); /* Command mode */
+ if (pinfo->lcdc.dst_split)
+ reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */
if (pinfo->lcdc.pipe_swap)
reg |= BIT(4); /* Use intf2 as trigger */
else
@@ -953,8 +1008,9 @@
}
if (pinfo->lcdc.dst_split) {
- writel(BIT(16), MDP_REG_PPB0_CONFIG);
- writel(BIT(5), MDP_REG_PPB0_CNTL);
+ uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
+ writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
+ writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
mdp_clk_gating_ctrl();
@@ -1002,7 +1058,8 @@
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
if (pinfo->dest == DISPLAY_1)
timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
@@ -1054,7 +1111,9 @@
uint32_t ctl0_reg_val, ctl1_reg_val;
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
- writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+ if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
+ writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
+
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 9a6e21e..f8ff3bb 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -41,6 +41,7 @@
#include <platform/timer.h>
#include <err.h>
#include <msm_panel.h>
+#include <arch/ops.h>
extern void mdp_disable(void);
extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
@@ -218,6 +219,7 @@
size = 4 - size;
size += cm->size;
memcpy((uint8_t *)off, (cm->payload), size);
+ arch_clean_invalidate_cache_range((addr_t)(off), size);
writel(off, ctl_base + DMA_CMD_OFFSET);
writel(size, ctl_base + DMA_CMD_LENGTH);
if (dual_dsi) {
@@ -374,12 +376,20 @@
mipi->sctl_base + COMMAND_MODE_DMA_CTRL);
/* for 8939 hw dsi1 has Lane_map as 3210 */
- if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1)
+ if (readl(mipi->ctl_base) == DSI_HW_REV_103_1)
lane_swap_dsi1 = 0x7;
else
lane_swap_dsi1 = lane_swap;
writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->sctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->sctl_base + LANE_CTL);
+ }
}
writel(0x0001, mipi->ctl_base + SOFT_RESET);
@@ -396,6 +406,14 @@
writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->ctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->ctl_base + LANE_CTL);
+ }
#endif
return 0;
@@ -490,7 +508,8 @@
uint16_t dst_format,
uint16_t traffic_mode,
uint8_t lane_en,
- uint16_t low_pwr_stop_mode,
+ uint8_t pulse_mode_hsa_he,
+ uint32_t low_pwr_stop_mode,
uint8_t eof_bllp_pwr,
uint8_t interleav,
uint32_t ctl_base)
@@ -498,6 +517,12 @@
int status = 0;
#if (DISPLAY_TYPE_MDSS == 1)
+ int last_line_interleave_en = 0;
+
+ /*Check if EOF_BLLP_PWR_MODE bit is set*/
+ if(eof_bllp_pwr & 0x8)
+ last_line_interleave_en = 1;
+
/* disable mdp first */
mdp_disable();
@@ -557,9 +582,10 @@
writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) {
- writel(low_pwr_stop_mode << 16 |
- eof_bllp_pwr << 12 | traffic_mode << 8
- | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL);
+ writel(last_line_interleave_en << 31 | pulse_mode_hsa_he << 28 |
+ low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 |
+ traffic_mode << 8 | dst_format << 4 | 0x0,
+ ctl_base + VIDEO_MODE_CTRL);
} else {
writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
eof_bllp_pwr << 12 | traffic_mode << 8
@@ -596,9 +622,7 @@
dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,
mipi->phy_base);
- mdss_dsi_phy_init(mipi, mipi->ctl_base, mipi->phy_base);
- if (mipi->dual_dsi)
- mdss_dsi_phy_init(mipi, mipi->sctl_base, mipi->sphy_base);
+ mdss_dsi_phy_init(mipi);
ret = mdss_dsi_host_init(mipi, mipi->dual_dsi,
mipi->broadcast);
@@ -802,6 +826,7 @@
goto mipi_cmds_error;
memcpy((void *)off, (cm->payload), cm->size);
+ arch_clean_invalidate_cache_range((addr_t)(off), size);
writel(off, DSI_DMA_CMD_OFFSET);
writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
dsb();
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 780b56e..da0551e 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -156,12 +156,16 @@
return status;
}
-static void mdss_dsi_pll_20nm_config_common_block(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_common_block_1(uint32_t pll_base)
{
writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
writel(0x2a, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x2b, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void mdss_dsi_pll_20nm_config_common_block_2(uint32_t pll_base)
+{
writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
@@ -191,12 +195,6 @@
writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
}
-static void mdss_dsi_pll_20nm_phy_config(uint32_t pll_base)
-{
- mdss_dsi_pll_20nm_config_common_block(pll_base);
- mdss_dsi_pll_20nm_config_loop_bw(pll_base);
-}
-
static void mdss_dsi_pll_20nm_config_vco_rate(uint32_t pll_base, struct mdss_dsi_pll_config *pd)
{
@@ -233,8 +231,10 @@
writel(((pd->lock_comp >> 16) & 0xff),
pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
- writel(0x01, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
-
+ if (pd->en_vco_zero_phase)
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
+ else
+ writel(0x0d, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
dprintf(SPEW, "div frac1=0x%x, div frac2 = 0x%x, div frac3=0x%x\n",
readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1),
@@ -270,32 +270,33 @@
writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
}
-static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_powerdown(uint32_t pll_base)
{
- dprintf(SPEW, "Disabling DSI PHY PLL \n");
- writel(0x02, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
- writel(0x06, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ dprintf(SPEW, "Powerdown DSI PHY PLL \n");
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
+ writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
dmb();
}
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd)
+
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ struct mdss_dsi_pll_config *pd)
{
-
- mdss_dsi_pll_20nm_phy_config(pll_base);
-
/*
* For 20nm PHY, DSI PLL 1 drains some current in its reset state.
* Need to turn off the DSI1 PLL explicitly.
*/
- if (ctl_base == MIPI_DSI0_BASE) {
- dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
- mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
- }
+ mdss_dsi_pll_20nm_config_common_block_1(pll_1_base);
+ mdss_dsi_pll_20nm_config_powerdown(pll_1_base);
+ mdss_dsi_pll_20nm_config_common_block_1(pll_base);
+ mdss_dsi_pll_20nm_config_common_block_2(pll_base);
+ mdss_dsi_pll_20nm_config_loop_bw(pll_base);
mdss_dsi_pll_20nm_config_vco_rate(pll_base, pd);
-
mdss_dsi_pll_20nm_config_resetsm(pll_base);
mdss_dsi_pll_20nm_config_vco_start(pll_base);
+
udelay(1000);
}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index da0634f..32ed968 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -48,6 +48,12 @@
#define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188
#define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4
#define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_0 0x00
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_1 0x04
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_2 0x08
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_3 0x0c
+#define MDSS_DSI_DSIPHY_REGULATOR_CTRL_4 0x10
+#define MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x18
#define MMSS_DSI_PHY_LDO_CTRL 0x01dc
#define TOTAL_TIMING_CTRL_CONFIG 12
@@ -219,29 +225,28 @@
udelay(100);
}
-static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
+static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
+ uint32_t phy_base, uint32_t reg_base)
{
/* DSI0 and DSI1 have a common regulator */
- uint32_t off = 0x0280; /* phy regulator ctrl settings */
-
if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
/* LDO ctrl */
- writel(0x1d, DSI0_PHY_BASE + MMSS_DSI_PHY_LDO_CTRL);
+ writel(0x1d, phy_base + MMSS_DSI_PHY_LDO_CTRL);
} else {
/* Regulator ctrl 1 */
- writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1));
+ writel(pd->regulator[1], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_1);
/* Regulator ctrl 2 */
- writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2));
+ writel(pd->regulator[2], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_2);
/* Regulator ctrl 3 */
- writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3));
+ writel(pd->regulator[3], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_3);
/* Regulator ctrl 4 */
- writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
+ writel(pd->regulator[4], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_4);
/* Regulator ctrl - CAL_PWR_CFG */
- writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6));
+ writel(pd->regulator[6], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG);
/* LDO ctrl */
- writel(0x00, phy_base + 0x01dc);
+ writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL);
/* Regulator ctrl 0 */
- writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0));
+ writel(pd->regulator[0], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_0);
dmb();
}
}
@@ -398,7 +403,7 @@
/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
if (phy_base == DSI0_PHY_BASE ||
- (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1))
+ (readl(mipi->ctl_base) == DSI_HW_REV_103_1))
writel(0x01, phy_base + 0x01d4);
else
writel(0x00, phy_base + 0x01d4);
@@ -434,12 +439,12 @@
}
static int mdss_dsi_phy_20nm_init(struct mipi_panel_info *mipi,
- uint32_t ctl_base, uint32_t phy_base)
+ uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base)
{
struct mdss_dsi_phy_ctrl *pd = mipi->mdss_dsi_phy_db;
uint32_t i, off = 0, ln, offset;
- mdss_dsi_20nm_phy_regulator_init(pd, phy_base);
+ mdss_dsi_20nm_phy_regulator_init(pd, phy_base, reg_base);
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
@@ -468,15 +473,23 @@
return 0;
}
-int mdss_dsi_phy_init (struct mipi_panel_info *mipi,
- uint32_t ctl_base, uint32_t phy_base)
+int mdss_dsi_phy_init(struct mipi_panel_info *mipi)
{
int ret;
- if (mipi->mdss_dsi_phy_db->is_pll_20nm)
- ret = mdss_dsi_phy_20nm_init(mipi, ctl_base, phy_base);
- else
- ret = mdss_dsi_phy_28nm_init(mipi, ctl_base, phy_base);
+ if (mipi->mdss_dsi_phy_db->is_pll_20nm) {
+ ret = mdss_dsi_phy_20nm_init(mipi, mipi->ctl_base,
+ mipi->phy_base, mipi->reg_base);
+ if (mipi->dual_dsi)
+ ret = mdss_dsi_phy_20nm_init(mipi, mipi->sctl_base,
+ mipi->sphy_base, mipi->reg_base);
+ } else {
+ ret = mdss_dsi_phy_28nm_init(mipi,
+ mipi->ctl_base, mipi->phy_base);
+ if (mipi->dual_dsi)
+ ret = mdss_dsi_phy_28nm_init(mipi, mipi->sctl_base,
+ mipi->sphy_base);
+ }
return ret;
}
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index bcec0ad..82f9662 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -614,7 +614,8 @@
return 1;
}
- size = partition_get_size(index);
+ /* Convert the size to blocks */
+ size = partition_get_size(index) / block_size;
/*
* For read only partitions the minimum size allocated on the disk is
@@ -623,6 +624,7 @@
*/
if (partition_read_only(index) && size < card->wp_grp_size)
{
+ /* Write protect api takes the size in bytes, convert size to bytes */
size = card->wp_grp_size * block_size;
}
/* Set the power on WP bit */
diff --git a/platform/msm_shared/partial_goods.c b/platform/msm_shared/partial_goods.c
index 6ca8324..d2c3ab6 100644
--- a/platform/msm_shared/partial_goods.c
+++ b/platform/msm_shared/partial_goods.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -40,10 +40,16 @@
int ret = 0;
int prop_len = 0;
uint32_t reg = readl(QFPROM_PTE_PART_ADDR);
- uint32_t prop_type;
+ uint32_t prop_type = 0;
struct subnode_list *subnode_lst = NULL;
const struct fdt_property *prop = NULL;
- const char *replace_str;
+ const char *replace_str = NULL;
+
+ /*
+ * The PTE register bits 23 to 27 have the partial goods
+ * info, extract the partial goods value before using
+ */
+ reg = (reg & 0x0f800000) >> 23;
/* If none of the DTB needs update */
if (!reg)
@@ -112,7 +118,7 @@
case STATUS_TYPE:
if (prop_len == sizeof("ok"))
replace_str = "no";
- else if (prop_len = sizeof("okay"))
+ else if (prop_len == sizeof("okay"))
replace_str = "dsbl";
else
{
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 38b2a80..2338060 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -872,10 +872,8 @@
return INVALID_PTN;
}
for (n = 0; n < partition_count; n++) {
- if (!memcmp
- (name, &partition_entries[n].name, input_string_length)
- && input_string_length ==
- strlen((const char *)&partition_entries[n].name)) {
+ if ((input_string_length == strlen((const char *)&partition_entries[n].name))
+ && !memcmp(name, &partition_entries[n].name, input_string_length)) {
return n;
}
}
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index dbd5f1d..a2c21cf 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -45,12 +45,87 @@
#define QMP_PHY_MAX_TIMEOUT 1000
#define PHYSTATUS BIT(6)
+static bool hsonly_mode;
+
+struct qmp_reg qmp_settings[] =
+{
+ {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+ {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+ {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+ {0xb4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+ {0xb8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+ {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+ {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x178, 0x01}, /* QSERDES_COM_HSCLK_SEL */
+ {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+ {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+ {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x10c, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x124, 0x1c}, /* QSERDES_COM_VCO_TUNE_CTRL */
+ {0x12c, 0x3f}, /* QSERDES_COM_VCO_TUNE1_MODE0 */
+ {0x130, 0x01}, /* QSERDES_COM_VCO_TUNE2_MODE0 */
+ {0x184, 0x0a}, /* QSERDES_COM_CORECLK_DIV */
+ {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0xc8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+ {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+ {0xc4, 0x15}, /*QSERDES_COM_RESCODE_DIV_NUM */
+ {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+ {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+ {0xc, 0x0a}, /* QSERDES_COM_BG_TIMER */
+ {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+ {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+ {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+ {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+ {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+ {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+ {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4d8, 0x03}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x70, 0xf}, /* QSERDES_COM_BG_TRIM */
+ {0x48, 0xf}, /* QSERDES_COM_PLL_IVCO */
+ {0x4e0, 0xb8}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x514, 0x04}, /* QSERDES_RX_SIGDET_CNTRL */
+ {0x518, 0x1b}, /* QSERDES_RX_SIGDET_LVL */
+ {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+ {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x6c4, 0x03}, /* USB3_PHY_FLL_CNTRL2 */
+ {0x6c0, 0x02}, /* USB3_PHY_FLL_CNTRL1 */
+ {0x6c8, 0x09}, /* USB3_PHY_FLL_CNT_VAL_L */
+ {0x6cc, 0x42}, /* USB3_PHY_FLL_CNT_VAL_H_TOL */
+ {0x6d0, 0x85}, /* USB3_PHY_FLL_MAN_CODE */
+ {0x294, 0x02}, /* QSERDES_TX_LANE_MODE */
+ {0x680, 0xd1}, /* USB3_PHY_LOCK_DETECT_CONFIG1 */
+ {0x684, 0x1f}, /* USB3_PHY_LOCK_DETECT_CONFIG2 */
+ {0x688, 0x47}, /* USB3_PHY_LOCK_DETECT_CONFIG3 */
+ {0x664, 0x08}, /* USB3_PHY_POWER_STATE_CONFIG2 */
+ {0x600, 0x00}, /* USB3_PHY_SW_RESET */
+ {0x608, 0x03}, /* USB3_PHY_START_CONTROL */
+};
+
__WEAK uint32_t target_override_pll()
{
return 0;
}
-static void qmp_phy_qmp_reset()
+__WEAK uint32_t platform_get_qmp_rev()
+{
+ return 0x10000000;
+}
+
+/* USB3.0 QMP phy reset */
+static void qmp_phy_qmp_reset(void)
{
int ret = 0;
uint32_t val;
@@ -154,75 +229,101 @@
void usb30_qmp_phy_init()
{
int timeout = QMP_PHY_MAX_TIMEOUT;
+ uint32_t rev_id = 0;
+ uint32_t phy_status = 0;
+ uint32_t qmp_reg_size;
+ uint32_t i;
+
+ rev_id = platform_get_qmp_rev();
/* Sequence as per HPG */
-
writel(0x01, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_DOWN_CONTROL);
- writel(0x08, QMP_PHY_BASE + QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
- if (target_override_pll())
- writel(0xE1, QMP_PHY_BASE + QSERDES_COM_PLL_VCOTAIL_EN);
-
- writel(0x82, QMP_PHY_BASE + QSERDES_COM_DEC_START1);
- writel(0x03, QMP_PHY_BASE + QSERDES_COM_DEC_START2);
- writel(0xD5, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START1);
- writel(0xAA, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START2);
- writel(0x4D, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START3);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP_EN);
- writel(0x2B, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP1);
- writel(0x68, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP2);
- writel(0x7C, QMP_PHY_BASE + QSERDES_COM_PLL_CRCTRL);
- writel(0x02, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETI);
- writel(0x1F, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETP);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETP);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETI);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IE_TRIM);
- writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IP_TRIM);
- writel(0x46, QMP_PHY_BASE + QSERDES_COM_PLL_CNTRL);
-
- /* CDR Settings */
- writel(0xDA, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL1);
- writel(0x42, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL2);
-
- /* Calibration Settings */
- writel(0x90, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL);
- if (target_override_pll())
- writel(0x07, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ if (rev_id >= 0x20000000)
+ {
+ qmp_reg_size = sizeof(qmp_settings) / sizeof(struct qmp_reg);
+ for (i = 0 ; i < qmp_reg_size; i++)
+ writel(qmp_settings[i].val, QMP_PHY_BASE + qmp_settings[i].off);
+ }
else
- writel(0x05, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ {
+ writel(0x08, QMP_PHY_BASE + QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
- writel(0x20, QMP_PHY_BASE + QSERDES_COM_RES_CODE_START_SEG1);
- writel(0x77, QMP_PHY_BASE + QSERDES_COM_RES_CODE_CAL_CSR);
- writel(0x15, QMP_PHY_BASE + QSERDES_COM_RES_TRIM_CONTROL);
- writel(0x03, QMP_PHY_BASE + QSERDES_TX_RCV_DETECT_LVL);
- writel(0x02, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2);
- writel(0x6C, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
- writel(0xC7, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
- writel(0x40, QMP_PHY_BASE + QSERDES_RX_SIGDET_ENABLES);
- writel(0x73, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
- writel(0x06, QMP_PHY_BASE + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
- writel(0x48, QMP_PHY_BASE + PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_EN_CENTER);
- writel(0x02, QMP_PHY_BASE + QSERDES_COM_SSC_ADJ_PER1);
- writel(0x31, QMP_PHY_BASE + QSERDES_COM_SSC_PER1);
- writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_PER2);
- writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE1);
- writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE2);
- writel(0x08, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_STATE_CONFIG2);
+ if (target_override_pll())
+ writel(0xE1, QMP_PHY_BASE + QSERDES_COM_PLL_VCOTAIL_EN);
- writel(0x00, QMP_PHY_BASE + PCIE_USB3_PHY_SW_RESET);
- writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
+ writel(0x82, QMP_PHY_BASE + QSERDES_COM_DEC_START1);
+ writel(0x03, QMP_PHY_BASE + QSERDES_COM_DEC_START2);
+ writel(0xD5, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START1);
+ writel(0xAA, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START2);
+ writel(0x4D, QMP_PHY_BASE + QSERDES_COM_DIV_FRAC_START3);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP_EN);
+ writel(0x2B, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP1);
+ writel(0x68, QMP_PHY_BASE + QSERDES_COM_PLLLOCK_CMP2);
+ writel(0x7C, QMP_PHY_BASE + QSERDES_COM_PLL_CRCTRL);
+ writel(0x02, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETI);
+ writel(0x1F, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETP);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_PLL_CP_SETP);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_PLL_IP_SETI);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IE_TRIM);
+ writel(0x0F, QMP_PHY_BASE + QSERDES_COM_IP_TRIM);
+ writel(0x46, QMP_PHY_BASE + QSERDES_COM_PLL_CNTRL);
- clock_bumpup_pipe3_clk();
+ /* CDR Settings */
+ writel(0xDA, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL1);
+ writel(0x42, QMP_PHY_BASE + QSERDES_RX_CDR_CONTROL2);
- while ((readl(QMP_PHY_BASE + PCIE_USB3_PHY_PCS_STATUS) & PHYSTATUS))
+ /* Calibration Settings */
+ writel(0x90, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL);
+ if (target_override_pll())
+ writel(0x07, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+ else
+ writel(0x05, QMP_PHY_BASE + QSERDES_COM_RESETSM_CNTRL2);
+
+ writel(0x20, QMP_PHY_BASE + QSERDES_COM_RES_CODE_START_SEG1);
+ writel(0x77, QMP_PHY_BASE + QSERDES_COM_RES_CODE_CAL_CSR);
+ writel(0x15, QMP_PHY_BASE + QSERDES_COM_RES_TRIM_CONTROL);
+ writel(0x03, QMP_PHY_BASE + QSERDES_TX_RCV_DETECT_LVL);
+ writel(0x02, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2);
+ writel(0x6C, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
+ writel(0xC7, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
+ writel(0x40, QMP_PHY_BASE + QSERDES_RX_SIGDET_ENABLES);
+ writel(0x73, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
+ writel(0x06, QMP_PHY_BASE + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
+ writel(0x48, QMP_PHY_BASE + PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_EN_CENTER);
+ writel(0x02, QMP_PHY_BASE + QSERDES_COM_SSC_ADJ_PER1);
+ writel(0x31, QMP_PHY_BASE + QSERDES_COM_SSC_PER1);
+ writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_PER2);
+ writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE1);
+ writel(0x19, QMP_PHY_BASE + QSERDES_COM_SSC_STEP_SIZE2);
+ writel(0x08, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_STATE_CONFIG2);
+
+ writel(0x00, QMP_PHY_BASE + PCIE_USB3_PHY_SW_RESET);
+ writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
+ }
+
+ if (rev_id >= 0x20000000)
+ phy_status = 0x77c;
+ else
+ phy_status = 0x728;
+
+ while ((readl(QMP_PHY_BASE + phy_status) & PHYSTATUS))
{
udelay(1);
timeout--;
if (!timeout)
{
- dprintf(CRITICAL, "QMP phy initialization failed\n");
+ dprintf(CRITICAL, "QMP phy initialization failed, fallback to HighSpeed only mode\n");
+ hsonly_mode = true;
return;
}
}
+
+ clock_bumpup_pipe3_clk();
+}
+
+bool use_hsonly_mode()
+{
+ return hsonly_mode;
}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index 2608ee6..ae1cba0 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -33,6 +33,7 @@
#include <debug.h>
#include <string.h>
#include <malloc.h>
+#include <bits.h>
#include <sys/types.h>
#include <platform.h>
#include <platform/clock.h>
@@ -63,13 +64,14 @@
static uint8_t* rdwr_buf;
static struct flash_id supported_flash[] = {
- /* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
- {0x1590AC2C, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
- {0x1590AA2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1},
- {0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
- {0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
- {0x9590DC2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
- {0x1590aa98, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
+ /* Flash ID Flash ID2 ID Mask ID Mask2 Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
+ {0x1590AC2C, 0x56, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590AC2C, 0x57, 0xFFFFFFFF, 0xFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 1},
+ {0x1590AA2C, 0x06, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1},
+ {0x2690AC2C, 0x54, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
+ {0x1590ACAD, 0, 0xFFFFFFFF, 0x0, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
+ {0x9590DC2C, 0x56, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590aa98, 0x76, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
@@ -201,8 +203,8 @@
struct cmd_element *cmd_list_ptr_start = ce_array;
int num_desc = 0;
uint32_t status;
- uint32_t id;
- uint32_t flash_cmd = NAND_CMD_FETCH_ID;
+ uint32_t id, id2;
+ uint32_t flash_cmd = NAND_CMD_FETCH_ID | BIT(19); //bit 19 needs to be set to get extended NAND ID
uint32_t exec_cmd = 1;
int nand_ret = NANDC_RESULT_SUCCESS;
@@ -241,9 +243,11 @@
}
/* Read the id */
- id = qpic_nand_read_reg(NAND_READ_ID, BAM_DESC_UNLOCK_FLAG);
+ id = qpic_nand_read_reg(NAND_READ_ID, 0);
+ id2 = qpic_nand_read_reg(NAND_READ_ID2, BAM_DESC_UNLOCK_FLAG);
flash->id = id;
+ flash->id2 = id2;
flash->vendor = id & 0xff;
flash->device = (id >> 8) & 0xff;
flash->dev_cfg = (id >> 24) & 0xFF;
@@ -1221,8 +1225,10 @@
/* Check if we support the device */
for (index = 0; index < (ARRAY_SIZE(supported_flash)); index++)
{
- if ((flash->id & supported_flash[index].mask) ==
- (supported_flash[index].flash_id & (supported_flash[index].mask)))
+ if (((flash->id & supported_flash[index].mask) ==
+ (supported_flash[index].flash_id & (supported_flash[index].mask))) &&
+ ((flash->id2 & supported_flash[index].mask2) ==
+ (supported_flash[index].flash_id2 & (supported_flash[index].mask2))))
{
dev_found = 1;
break;
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 834e883..793b88c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -38,7 +38,7 @@
$(LOCAL_DIR)/mmc.o
endif
-ifeq ($(ENABLE_VERIFIED_BOOT),1)
+ifeq ($(VERIFIED_BOOT),1)
OBJS += \
$(LOCAL_DIR)/boot_verifier.o
endif
@@ -241,12 +241,6 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/ufs.o \
- $(LOCAL_DIR)/utp.o \
- $(LOCAL_DIR)/uic.o \
- $(LOCAL_DIR)/ucs.o \
- $(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
$(LOCAL_DIR)/crypto_hash.o \
@@ -336,6 +330,7 @@
$(LOCAL_DIR)/board.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/flash-ubi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/dev_tree.o \
@@ -358,6 +353,7 @@
$(LOCAL_DIR)/board.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/flash-ubi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/clock.o \
@@ -419,6 +415,7 @@
$(LOCAL_DIR)/crypto5_wrapper.o \
$(LOCAL_DIR)/i2c_qup.o \
$(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
$(LOCAL_DIR)/dload_util.o
endif
@@ -439,12 +436,6 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/ufs.o \
- $(LOCAL_DIR)/utp.o \
- $(LOCAL_DIR)/uic.o \
- $(LOCAL_DIR)/ucs.o \
- $(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
$(LOCAL_DIR)/qmp_usb30_phy.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
@@ -507,14 +498,23 @@
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o
+endif
+
+ifeq ($(ENABLE_UFS_SUPPORT), 1)
+ OBJS += \
$(LOCAL_DIR)/ufs.o \
$(LOCAL_DIR)/utp.o \
$(LOCAL_DIR)/uic.o \
$(LOCAL_DIR)/ucs.o \
$(LOCAL_DIR)/ufs_hci.o \
- $(LOCAL_DIR)/dme.o \
- $(LOCAL_DIR)/qmp_usb30_phy.o \
- $(LOCAL_DIR)/qusb2_phy.o
+ $(LOCAL_DIR)/dme.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 03b61c9..b45fd3d 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -333,7 +333,7 @@
else
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD,SSD_ENCRYPT_ID);
- scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = (uint32_t) cmd.img_ptr;
scm_arg.x3 = (uint32_t) cmd.img_len_ptr;
@@ -424,6 +424,7 @@
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = parse_req.md_len;
scm_arg.x3 = (uint32_t) parse_req.md;
+ scm_arg.atomic = true;
ret = scm_call2(&scm_arg, &scm_ret);
parse_rsp.status = scm_ret.x1;
@@ -583,6 +584,48 @@
return ret;
}
+int scm_svc_get_secure_state(uint32_t *state_low, uint32_t *state_high)
+{
+ get_secure_state_req req;
+ get_secure_state_rsp rsp;
+
+ int ret = 0;
+
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ if (!scm_arm_support)
+ {
+ req.status_ptr = (uint32_t*)&rsp;
+ req.status_len = sizeof(rsp);
+
+ ret = scm_call(TZBSP_SVC_INFO,
+ TZ_INFO_GET_SECURE_STATE,
+ &req,
+ sizeof(req),
+ NULL,
+ 0);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, TZ_INFO_GET_SECURE_STATE);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x0);
+
+ ret = scm_call2(&scm_arg, &scm_ret);
+
+ rsp.status_low = scm_ret.x1;
+ rsp.status_high = scm_ret.x2;
+ }
+
+ if(!ret)
+ {
+ *state_low = rsp.status_low;
+ *state_high = rsp.status_high;
+ }
+
+ return ret;
+}
+
int scm_protect_keystore(uint32_t * img_ptr, uint32_t img_len)
{
int ret=0;
@@ -759,6 +802,119 @@
}
}
+int mdtp_cipher_dip_cmd(uint8_t *in_buf, uint32_t in_buf_size, uint8_t *out_buf,
+ uint32_t out_buf_size, uint32_t direction)
+{
+ uint32_t svc_id;
+ uint32_t cmd_id;
+ void *cmd_buf;
+ void *rsp_buf;
+ size_t cmd_len;
+ size_t rsp_len;
+ mdtp_cipher_dip_req req;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ ASSERT(in_buf != NULL);
+ ASSERT(out_buf != NULL);
+
+ req.in_buf = in_buf;
+ req.in_buf_size = in_buf_size;
+ req.out_buf = out_buf;
+ req.out_buf_size = out_buf_size;
+ req.direction = direction;
+
+ if (!scm_arm_support)
+ {
+ svc_id = SCM_SVC_MDTP;
+ cmd_id = SCM_MDTP_CIPHER_DIP;
+ cmd_buf = (void *)&req;
+ cmd_len = sizeof(req);
+ rsp_buf = NULL;
+ rsp_len = 0;
+
+ if (scm_call(svc_id, cmd_id, cmd_buf, cmd_len, rsp_buf, rsp_len))
+ {
+ dprintf(CRITICAL, "Failed to call Cipher DIP SCM\n");
+ return -1;
+ }
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_MDTP, SCM_MDTP_CIPHER_DIP);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x5, SMC_PARAM_TYPE_BUFFER_READ, SMC_PARAM_TYPE_VALUE,
+ SMC_PARAM_TYPE_BUFFER_READWRITE, SMC_PARAM_TYPE_VALUE, SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = (uint32_t)req.in_buf;
+ scm_arg.x3 = req.in_buf_size;
+ scm_arg.x4 = (uint32_t)req.out_buf;
+ scm_arg.x5[0] = req.out_buf_size;
+ scm_arg.x5[1] = req.direction;
+
+ if (scm_call2(&scm_arg, &scm_ret))
+ {
+ dprintf(CRITICAL, "Failed in Cipher DIP SCM call\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+int qfprom_read_row_cmd(uint32_t row_address,
+ uint32_t addr_type,
+ uint32_t *row_data,
+ uint32_t *qfprom_api_status)
+{
+ uint32_t svc_id;
+ uint32_t cmd_id;
+ void *cmd_buf;
+ void *rsp_buf;
+ size_t cmd_len;
+ size_t rsp_len;
+ qfprom_read_row_req req;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
+
+ req.row_address = row_address;
+ req.addr_type = addr_type;
+ req.row_data = row_data;
+ req.qfprom_api_status = qfprom_api_status;
+
+ if (!scm_arm_support)
+ {
+ svc_id = SCM_SVC_FUSE;
+ cmd_id = SCM_QFPROM_READ_ROW_ID;
+ cmd_buf = (void *)&req;
+ cmd_len = sizeof(req);
+ rsp_buf = NULL;
+ rsp_len = 0;
+
+ if (scm_call(svc_id, cmd_id, cmd_buf, cmd_len, rsp_buf, rsp_len))
+ {
+ dprintf(CRITICAL, "Failed to call SCM_SVC_FUSE.SCM_QFPROM_READ_ROW_ID SCM\n");
+ return -1;
+ }
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_QFPROM_READ_ROW_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x4, SMC_PARAM_TYPE_VALUE, SMC_PARAM_TYPE_VALUE,
+ SMC_PARAM_TYPE_BUFFER_READWRITE, SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = req.row_address;
+ scm_arg.x3 = req.addr_type;
+ scm_arg.x4 = (uint32_t)req.row_data;
+ scm_arg.x5[0] = (uint32_t)req.qfprom_api_status;
+
+ if (scm_call2(&scm_arg, &scm_ret))
+ {
+ dprintf(CRITICAL, "Failed to call SCM_SVC_FUSE.SCM_QFPROM_READ_ROW_ID SCM\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
/*
* Switches the CE1 channel between ADM and register usage.
* channel : AP_CE_REGISTER_USE, CE1 uses register interface
@@ -996,7 +1152,7 @@
arg->x0 = arg->atomic ? (arg->x0 | SCM_ATOMIC_BIT) : arg->x0;
x5 = arg->x5[0];
- if ((arg->x1 & 0xF) > SCM_MAX_ARG_LEN)
+ if ((arg->x1 & 0xF) > SCM_MAX_ARG_LEN - 1)
{
indir_arg = memalign(CACHE_LINE, (SCM_INDIR_MAX_LEN * sizeof(uint32_t)));
ASSERT(indir_arg);
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 5ffbb88..c898a81 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -504,7 +504,13 @@
trans_complete = 1;
break;
}
- else if (int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress)
+ /*
+ * Some controllers set the data timout first on issuing an erase & take time
+ * to set data complete interrupt. We need to wait hoping the controller would
+ * set data complete
+ */
+ else if (int_status & SDHCI_ERR_INT_STAT_MASK && !host->tuning_in_progress &&
+ !((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK)))
goto err;
/*
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index ba63845..4e83a55 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -294,14 +294,36 @@
REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val);
}
+static void sdhci_dll_clk_enable(struct sdhci_host *host, int enable)
+{
+ if (enable)
+ {
+ REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~SDCC_DLL_CLOCK_DISABLE), SDCC_HC_REG_DLL_CONFIG_2);
+ }
+ else
+ {
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+ REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | SDCC_DLL_CLOCK_DISABLE), SDCC_HC_REG_DLL_CONFIG_2);
+ }
+}
+
/* Initialize DLL (Programmable Delay Line) */
static uint32_t sdhci_msm_init_dll(struct sdhci_host *host)
{
uint32_t pwr_save = 0;
uint32_t timeout = SDHCI_DLL_TIMEOUT;
+ uint32_t dll_cfg2;
+ uint32_t mclk_clk_freq = 0;
pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN;
+ /* Dll sequence needs additional steps for sdcc core version 42 */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ /* Disable DLL clock before configuring */
+ sdhci_dll_clk_enable(host, 0);
+ }
+
/* PWR SAVE to 0 */
if (pwr_save)
REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & ~SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
@@ -313,10 +335,33 @@
/* Set frequency field in DLL_CONFIG */
msm_set_dll_freq(host);
+ /* Configure the mclk freq based on the current clock rate
+ * and fll cycle count as per hpg section 15.2.2
+ */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ dll_cfg2 = REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2);
+ if (dll_cfg2 & SDCC_FLL_CYCLE_CNT)
+ mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 8;
+ else
+ mclk_clk_freq = (host->cur_clk_rate / TCXO_FREQ) * 4;
+
+ REG_WRITE32(host, ((REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) & ~(0xFF << 10)) | (mclk_clk_freq << 10)), SDCC_HC_REG_DLL_CONFIG_2);
+
+ udelay(5);
+ }
+
/* Write 0 to DLL_RST */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
/* Write 0 to DLL_PDN */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Set the mclk clock and enable the dll clock */
+ if (host->major == 1 && host->minor >= 0x42)
+ {
+ msm_set_dll_freq(host);
+ sdhci_dll_clk_enable(host, 1);
+ }
/* Write 1 to DLL_EN */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), SDCC_DLL_CONFIG_REG);
/* Write 1 to CLK_OUT_EN */
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 9c9cf61..db186d4 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -400,6 +400,14 @@
MDM9609 = 262,
MSM8239 = 263,
APQ8009 = 265,
+ MSMTELLURIUM = 264,
+ MSMTERBIUM = 266,
+ MSM8929 = 268,
+ MSM8629 = 269,
+ MSM8229 = 270,
+ APQ8029 = 271,
+ MSM8609 = 275,
+ FSM9916 = 276,
};
enum platform {
diff --git a/platform/msm_shared/ucs.c b/platform/msm_shared/ucs.c
index 49ecf1b..3e7563a 100644
--- a/platform/msm_shared/ucs.c
+++ b/platform/msm_shared/ucs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,8 +37,7 @@
int ucs_do_scsi_cmd(struct ufs_dev *dev, struct scsi_req_build_type *req)
{
struct upiu_req_build_type req_upiu;
- struct upiu_basic_hdr resp_upiu;
- int ret;
+ struct upiu_basic_resp_hdr resp_upiu;
memset(&req_upiu, 0 , sizeof(struct upiu_req_build_type));
@@ -68,9 +67,14 @@
{
if (resp_upiu.status == SCSI_STATUS_CHK_COND && (*((uint8_t *)(req->cdb)) != SCSI_CMD_SENSE_REQ))
{
- ret = ucs_do_request_sense(dev);
- if (ret)
- dprintf(CRITICAL, "SCSI request sense failed.\n");
+ dprintf(CRITICAL, "Data segment length: %x\n", BE16(resp_upiu.data_seg_len));
+ if (BE16(resp_upiu.data_seg_len))
+ {
+ dprintf(CRITICAL, "SCSI Request failed and we have sense data\n");
+ dprintf(CRITICAL, "Sense Data Length/Response Code: 0x%x/0x%x\n", BE16(resp_upiu.sense_length), BE16(resp_upiu.sense_response_code));
+ parse_sense_key(resp_upiu.sense_data[0]);
+ dprintf(CRITICAL, "Sense Buffer (HEX): 0x%x 0x%x 0x%x 0x%x\n", BE32(resp_upiu.sense_data[0]), BE32(resp_upiu.sense_data[1]), BE32(resp_upiu.sense_data[2]), BE32(resp_upiu.sense_data[3]));
+ }
}
dprintf(CRITICAL, "ucs_do_scsi_cmd failed status = %x\n", resp_upiu.status);
@@ -80,6 +84,57 @@
return UFS_SUCCESS;
}
+int parse_sense_key(uint32_t sense_data)
+{
+ uint32_t key = BE32(sense_data) >> 24;
+ dprintf(CRITICAL, "Sense Key: 0x%x\n", key);
+ switch(key)
+ {
+ case 0x0:
+ dprintf(INFO, "NO SENSE: No information available to be reported\n");
+ break;
+ case 0x1:
+ dprintf(INFO, "RECOVERED ERROR: Additional sense buffer bytes indicate further details\n");
+ break;
+ case 0x2:
+ dprintf(INFO, "NOT READY: Logical Unit Not Ready and cannot be accessed at this time\n");
+ break;
+ case 0x3:
+ dprintf(INFO, "MEDIUM ERROR: Last command unsuccessful due to non-recoverable error condition\n");
+ break;
+ case 0x4:
+ dprintf(INFO, "HARDWARE ERROR: Target detected a non-recoverable hardware error\n");
+ break;
+ case 0x5:
+ dprintf(INFO, "ILLEGAL REQUEST: Illegal parameter in the command descriptor block in the command sent\n");
+ break;
+ case 0x6:
+ dprintf(INFO, "UNIT ATTENTION: Unit has been reset/unexpectedly power on/removable media has changed\n");
+ break;
+ case 0x7:
+ dprintf(INFO, "DATA PROTECT: Read/Write operation attempted on a block that is protected from this operation\n");
+ break;
+ case 0x8:
+ dprintf(INFO, "BLANK CHECK: Target encountered blank or unformatted media while reading or writing\n");
+ break;
+ case 0x9:
+ dprintf(INFO, "VENDOR SPECIFIC: Vendor specific error or exceptional conditions\n");
+ break;
+ case 0xB:
+ dprintf(INFO, "ABORTED COMMAND: Target aborted the execution of the command\n");
+ break;
+ case 0xD:
+ dprintf(INFO, "VOLUME OVERFLOW: Buffered peripheral device has reached the end of partition\n");
+ break;
+ case 0xE:
+ dprintf(INFO, "MISCOMPARE: Source data did not match the data read from the media\n");
+ break;
+ default:
+ dprintf(INFO, "INVALID sense key\n");
+ }
+ return key;
+}
+
int ucs_do_scsi_rpmb_read(struct ufs_dev *dev, uint32_t *req_buf, uint32_t blk_cnt,
uint32_t *resp_buf, uint32_t *resp_len)
{
@@ -316,7 +371,9 @@
struct unmap_blk_desc *blk_desc;
param_list = (struct unmap_param_list *)param;
- param_list->data_len = (sizeof(struct unmap_param_list) - 1) << 0x8; /* n-1 */
+
+ // data length = size of unmap block descriptor struct (n-1) - size of data length field.
+ param_list->data_len = ((sizeof(struct unmap_param_list) - 1) - 1) << 0x8;
param_list->blk_desc_data_len = sizeof(struct unmap_blk_desc) << 0x8;
@@ -337,6 +394,7 @@
/* Flush cdb to memory. */
dsb();
arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+ arch_invalidate_cache_range((addr_t) param, sizeof(struct unmap_param_list));
memset((void*)&req_upiu, 0 , sizeof(struct scsi_req_build_type));
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index a6324a4..6f419cd 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -1583,6 +1583,7 @@
/* enable device event generation */
dwc_event_device_enable(dev, BIT(DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT) |
BIT(DWC_EVENT_DEVICE_EVENT_ID_USB_RESET) |
+ BIT(DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY) |
BIT(DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE));
/* 18.e initialize control end point
diff --git a/platform/msm_shared/usb30_dwc_hw.c b/platform/msm_shared/usb30_dwc_hw.c
index 3327bca..7b69bbb 100644
--- a/platform/msm_shared/usb30_dwc_hw.c
+++ b/platform/msm_shared/usb30_dwc_hw.c
@@ -41,6 +41,7 @@
#include <usb30_dwc_hw.h>
#include <smem.h>
#include <board.h>
+#include <qmp_phy.h>
extern char* ss_link_state_lookup[20];
extern char* hs_link_state_lookup[20];
@@ -512,17 +513,15 @@
void dwc_phy_digital_reset(dwc_dev_t *dev)
{
REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 1);
-#ifndef USE_HSONLY_MODE
- REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 1);
-#endif
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 1);
/* per HPG */
udelay(100);
REG_WRITE_FIELDI(dev, GUSB2PHYCFG, 0, PHYSOFTRST, 0);
-#ifndef USE_HSONLY_MODE
- REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 0);
-#endif
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELDI(dev, GUSB3PIPECTL, 0, PHYSOFTRST, 0);
/* per HPG */
udelay(100);
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index 0e47c81..0e5e1b0 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -46,6 +46,7 @@
#include <smem.h>
#include <board.h>
#include <platform/timer.h>
+#include <qmp_phy.h>
//#define DEBUG_USB
@@ -232,10 +233,6 @@
/* 2. Put controller in reset */
dwc_reset(dwc, 1);
- /* HS only mode support */
-#ifdef USE_HSONLY_MODE
- usb_wrapper_hsonly_mode(wrapper);
-#endif
/* Steps 3 - 7 must be done while dwc is in reset condition */
@@ -243,9 +240,8 @@
phy_reset(wrapper, dev_info);
/* 4. SS phy config */
-#ifndef USE_HSONLY_MODE
- usb_wrapper_ss_phy_configure(wrapper);
-#endif
+ if (!use_hsonly_mode())
+ usb_wrapper_ss_phy_configure(wrapper);
/* 5. HS phy init */
usb_wrapper_hs_phy_init(wrapper);
@@ -266,6 +262,10 @@
if (dev_info->t_usb_if->phy_init)
dev_info->t_usb_if->phy_init();
+ /* HS only mode support */
+ if (use_hsonly_mode())
+ usb_wrapper_hsonly_mode(wrapper);
+
/* 10. */
usb_wrapper_workaround_10(wrapper);
diff --git a/platform/msm_shared/usb30_wrapper.c b/platform/msm_shared/usb30_wrapper.c
index 6cec193..b6ca7ea 100644
--- a/platform/msm_shared/usb30_wrapper.c
+++ b/platform/msm_shared/usb30_wrapper.c
@@ -49,6 +49,7 @@
#include <platform/clock.h>
#include <usb30_wrapper.h>
#include <usb30_wrapper_hwio.h>
+#include <qmp_phy.h>
/* Configure DBM mode: by-pass or DBM */
@@ -166,9 +167,8 @@
REG_WRITE_FIELD(dev, HS_PHY_CTRL, SW_SESSVLD_SEL, 0x1);
/* Indicate power present to SS phy */
-#ifndef USE_HSONLY_MODE
- REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
-#endif
+ if (!use_hsonly_mode())
+ REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
}
/* API to read SS PHY registers */
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
index 3b76b91..e2ee7d5 100644
--- a/platform/thulium/acpuclock.c
+++ b/platform/thulium/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -70,12 +70,16 @@
}
else if(freq == MMC_CLK_96MHZ)
{
- ret = clk_get_set_enable(clk_name, 100000000, true);
+ ret = clk_get_set_enable(clk_name, 96000000, true);
}
else if(freq == MMC_CLK_192MHZ)
{
ret = clk_get_set_enable(clk_name, 192000000, true);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
@@ -168,13 +172,20 @@
clock_usb30_gdsc_enable();
- ret = clk_get_set_enable("usb30_master_clk", 125000000, true);
+ ret = clk_get_set_enable("usb30_master_clk", 150000000, true);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
ASSERT(0);
}
+ ret = clk_get_set_enable("gcc_aggre2_usb3_axi_clk", 150000000, true);
+ if (ret)
+ {
+ dprintf(CRITICAL, "failed to set aggre2_usb3_axi_clk, ret = %d\n", ret);
+ ASSERT(0);
+ }
+
ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true);
if(ret)
{
@@ -202,8 +213,6 @@
dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
ASSERT(0);
}
-
- pm8x41_lnbb_clock_ctrl(1);
}
void clock_bumpup_pipe3_clk()
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
index 8108fd6..276841d 100644
--- a/platform/thulium/include/platform/iomap.h
+++ b/platform/thulium/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -38,6 +38,7 @@
#define MSM_SHARED_IMEM_BASE 0x066BF000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
@@ -45,6 +46,12 @@
#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
+#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
+
+#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
+
#define PERIPH_SS_BASE 0x07400000
#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
@@ -87,8 +94,8 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
/* UART Clocks */
-#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x29004)
-#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29008)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
@@ -97,26 +104,27 @@
/* USB3 clocks */
#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
-#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF014)
-#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF018)
-#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
-#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
-#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
+#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
@@ -157,7 +165,7 @@
#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
/* DRV strength for sdcc */
-#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000)
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
/* SDHCI - power control registers */
#define SDCC_MCI_HC_MODE (0x00000078)
@@ -171,7 +179,13 @@
#define BOOT_CONFIG_OFFSET 0x00006044
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
-/* Fix This */
-#define PLATFORM_QMP_OFFSET 0x8
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
+
+/* Dummy macro needed for compilation only */
+#define PLATFORM_QMP_OFFSET 0x0
#endif
diff --git a/platform/thulium/include/platform/irqs.h b/platform/thulium/include/platform/irqs.h
index dd0f31a..696c83f 100644
--- a/platform/thulium/include/platform/irqs.h
+++ b/platform/thulium/include/platform/irqs.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,8 @@
#define USB30_EE1_IRQ (GIC_SPI_START + 131)
+#define GLINK_IPC_IRQ (GIC_SPI_START + 168)
+
/* Retrofit universal macro names */
#define INT_USB_HS USB30_EE1_IRQ
diff --git a/platform/thulium/include/platform/partial_goods.h b/platform/thulium/include/platform/partial_goods.h
index eea9c8b..03c16ec 100644
--- a/platform/thulium/include/platform/partial_goods.h
+++ b/platform/thulium/include/platform/partial_goods.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -33,14 +33,14 @@
/* Look up table for partial goods */
struct partial_goods table[] =
{
- {0x00001, "/cpus", {{"cpu@100", "device_type"},}},
- {0x00010, "/cpus", {{"cpu@101", "device_type"},}},
- {0x00011, "/cpus", {{"cpu@100", "device_type"},
+ {0x1, "/cpus", {{"cpu@100", "device_type"},}},
+ {0x2, "/cpus", {{"cpu@101", "device_type"},}},
+ {0x3, "/cpus", {{"cpu@100", "device_type"},
{"cpu@101","device_type"},}},
- {0x00100, "/cpus", {{"cpu@100", "device_type"},
+ {0x4, "/cpus", {{"cpu@100", "device_type"},
{"cpu@101", "device_type"},
{"cpu@1", "device_type"},}},
- {0x10000, "/soc", {{"qcom,kgsl-3d0", "status"},}},
- {0x10010, "/soc", {{"qcom,msm-adsp-loader", "status"},}},
- {0x10001, "/soc", {{"qcom,vidc", "status"},}},
+ {0x10, "/soc", {{"qcom,kgsl-3d0", "status"},}},
+ {0x11, "/soc", {{"qcom,vidc", "status"},}},
+ {0x12, "/soc", {{"qcom,msm-adsp-loader", "status"},}},
};
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
index 1dad8cc..be0678c 100644
--- a/platform/thulium/platform.c
+++ b/platform/thulium/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -130,3 +130,14 @@
{
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+
+addr_t get_bs_info_addr()
+{
+ return BS_INFO_ADDR;
+}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
index ae1d0de..d0a23ed 100644
--- a/platform/thulium/thulium-clock.c
+++ b/platform/thulium/thulium-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -185,13 +185,13 @@
},
};
-static struct vote_clk gcc_blsp1_ahb_clk = {
- .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
- .en_mask = BIT(17),
+ .en_mask = BIT(15),
.c = {
- .dbg_name = "gcc_blsp1_ahb_clk",
+ .dbg_name = "gcc_blsp2_ahb_clk",
.ops = &clk_ops_vote,
},
};
@@ -204,9 +204,9 @@
F( 20000000, gpll0, 15, 1, 2),
F( 25000000, gpll0, 12, 1, 2),
F( 50000000, gpll0, 12, 0, 0),
- F( 96000000, gpll4, 16, 0, 0),
- F(192000000, gpll4, 8, 0, 0),
- F(384000000, gpll4, 4, 0, 0),
+ F( 96000000, gpll4, 4, 0, 0),
+ F(192000000, gpll4, 2, 0, 0),
+ F(384000000, gpll4, 1, 0, 0),
F_END
};
@@ -261,7 +261,9 @@
};
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
- F( 125000000, gpll0, 1, 5, 24),
+ F( 19200000, cxo, 1, 0, 0),
+ F( 120000000, gpll0, 5, 0, 0),
+ F( 150000000, gpll0, 4, 0, 0),
F_END
};
@@ -293,6 +295,16 @@
},
};
+static struct branch_clk gcc_aggre2_usb3_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_AGGRE2_USB3_AXI_CBCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_aggre2_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
F( 60000000, gpll0, 10, 0, 0),
F_END
@@ -398,11 +410,12 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart8_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c),
CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c),
/* USB30 clocks */
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("gcc_aggre2_usb3_axi_clk", gcc_aggre2_usb3_axi_clk.c),
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
diff --git a/project/apq8084.mk b/project/apq8084.mk
index fb61eea..4ca01bd 100644
--- a/project/apq8084.mk
+++ b/project/apq8084.mk
@@ -32,6 +32,8 @@
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
+DEFINES += USE_BOOTDEV_CMDLINE=1
+
ifeq ($(EMMC_BOOT),1)
DEFINES += _EMMC_BOOT=1
endif
diff --git a/project/fsm9010.mk b/project/fsm9010.mk
index bd48cd7..7759f73 100644
--- a/project/fsm9010.mk
+++ b/project/fsm9010.mk
@@ -13,7 +13,8 @@
endif
EMMC_BOOT := 1
-ENABLE_SDHCI_SUPPORT := 0
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_USB30_SUPPORT := 1
DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -33,3 +34,7 @@
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
diff --git a/project/msm8909.mk b/project/msm8909.mk
index 007499a..afc40f6 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -20,7 +20,7 @@
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_LOG_BUF=1
-DEFINES += WITH_DEBUG_UART=1
+DEFINES += WITH_DEBUG_UART=0
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
diff --git a/project/msm8994.mk b/project/msm8994.mk
index bef93ce..f797e77 100644
--- a/project/msm8994.mk
+++ b/project/msm8994.mk
@@ -34,6 +34,7 @@
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
DEFINES += ENABLE_XPU_VIOLATION=1
+DEFINES += USE_BOOTDEV_CMDLINE=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -62,5 +63,11 @@
DEFINES += SMD_SUPPORT=1
endif
+ifeq ($(ENABLE_MDTP_SUPPORT),1)
+DEFINES += MDTP_SUPPORT=1
+DEFINES += MDTP_EFUSE_ADDRESS=0xFC4B81F8 # QFPROM_RAW_SPARE_REG19_LSB
+DEFINES += MDTP_EFUSE_START=17
+endif
+
# Turn on Werror
CFLAGS += -Werror
diff --git a/project/thulium.mk b/project/thulium.mk
index 824b2dd..05e764f 100644
--- a/project/thulium.mk
+++ b/project/thulium.mk
@@ -30,11 +30,12 @@
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82200000
DEFINES += ABOOT_FORCE_TAGS_ADDR=0x82000000
DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
DEFINES += USB_RESET_FROM_CLK=1
+DEFINES += USE_BOOTDEV_CMDLINE=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -55,4 +56,8 @@
DEFINES += USB30_SUPPORT=1
endif
+ifeq ($(ENABLE_PARTIAL_GOODS_SUPPORT),1)
+DEFINES += ENABLE_PARTIAL_GOODS_SUPPORT=1
+endif
+
CFLAGS += -Werror
diff --git a/scripts/buildall b/scripts/buildall
index 906ee0c..c355387 100755
--- a/scripts/buildall
+++ b/scripts/buildall
@@ -1,6 +1,6 @@
#!/bin/sh
-PROJECTS="armemu-test sam7ex256-test osk5912-test qemu-arm-test beagle-test surf-test"
+PROJECTS="msm8226 msm8974 apq8084 msm8994 mdm9630 mdm9640 msm8610 msm8916 thulium"
FAILED=""
for p in $PROJECTS; do
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 6aa3b33..543951e 100755
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -285,13 +285,17 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
target_sdc_init();
- else
+#endif
+#ifdef UFS_SUPPORT
+ if(!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
+#endif
/* Storage initialization is complete, read the partition table info */
if (partition_read_table())
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index b077038..b46ef08 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,6 +44,7 @@
#include <target/display.h>
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 12
@@ -177,9 +178,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
@@ -506,7 +507,9 @@
void target_display_init(const char *panel_name)
{
uint32_t ret = 0;
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -528,6 +531,11 @@
target_force_cont_splash_disable(true);
msm_display_off();
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/fsm9010/init.c b/target/fsm9010/init.c
index 8f3da01..e5c50bb 100644
--- a/target/fsm9010/init.c
+++ b/target/fsm9010/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,8 @@
#include <platform/gpio.h>
#include <platform/timer.h>
#include <stdlib.h>
+#include <string.h>
+#include <sdhci_msm.h>
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl();
@@ -91,7 +93,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART2_BASE);
+ uart_dm_init(3, 0, BLSP1_UART3_BASE);
#endif
}
@@ -155,31 +157,39 @@
}
#if MMC_SDHCI_SUPPORT
+
static void target_mmc_sdhci_init()
{
- struct mmc_config_data config = {0};
+ static uint32_t mmc_clks[] = {
+ MMC_CLK_200MHZ, MMC_CLK_96MHZ, MMC_CLK_50MHZ };
+ struct mmc_config_data config;
+ unsigned int i;
+
+ memset(&config, 0, sizeof config);
config.bus_width = DATA_BUS_WIDTH_8BIT;
- config.max_clk_rate = MMC_CLK_96MHZ;
/* Trying Slot 1*/
config.slot = 1;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
- if (!(dev = mmc_init(&config))) {
+ for (i = 0; i < ARRAY_SIZE(mmc_clks); ++i) {
+ config.max_clk_rate = mmc_clks[i];
+ dprintf(INFO, "SDHC Running at %u MHz\n",
+ config.max_clk_rate / 1000000);
+ dev = mmc_init(&config);
+ if (dev && partition_read_table() == 0)
+ return;
+ }
+
+ if (dev == NULL)
dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
-
- /*
- * MMC initialization is complete, read the partition table info
- */
- if (partition_read_table()) {
+ else
dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
+ ASSERT(0);
}
void *target_mmc_device()
@@ -278,7 +288,10 @@
};
switch (platform) {
+ case FSM9008:
case FSM9010:
+ case FSM9016:
+ case FSM9055:
board->baseband = BASEBAND_MSM;
break;
default:
@@ -347,34 +360,6 @@
return 0;
}
-/* Check if MSM needs VBUS mimic for USB */
-static int target_needs_vbus_mimic()
-{
- return 1;
-}
-
-/* Do target specific usb initialization */
-void target_usb_init(void)
-{
- uint32_t val;
-
- extern void ulpi_write(unsigned val, unsigned reg);
-
- if (target_needs_vbus_mimic()) {
- /* Select and enable external configuration with USB PHY */
- ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
-
- /* Enable sess_vld */
- val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
- writel(val, USB_GENCONFIG_2);
-
- /* Enable external vbus configuration in the LINK */
- val = readl(USB_USBCMD);
- val |= SESS_VLD_CTRL;
- writel(val, USB_USBCMD);
- }
-}
-
/* Returns 1 if target supports continuous splash screen. */
int target_cont_splash_screen()
{
@@ -390,6 +375,7 @@
{
#if MMC_SDHCI_SUPPORT
mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
#else
mmc_put_card_to_sleep();
#endif
@@ -412,17 +398,41 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ {
+ off: SDC1_CLK_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
+ {
+ off: SDC1_CMD_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
+ {
+ off: SDC1_DATA_HDRV_CTL_OFF,
+ val: TLMM_CUR_VAL_10MA,
+ mask: TLMM_HDRV_MASK
+ },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
- { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
- { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
- { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ {
+ off: SDC1_CLK_PULL_CTL_OFF,
+ val: TLMM_NO_PULL,
+ mask: TLMM_PULL_MASK
+ },
+ {
+ off: SDC1_CMD_PULL_CTL_OFF,
+ val: TLMM_PULL_UP,
+ mask: TLMM_PULL_MASK
+ },
+ {
+ off: SDC1_DATA_PULL_CTL_OFF,
+ val: TLMM_PULL_UP,
+ mask: TLMM_PULL_MASK
+ },
};
/* Set the drive strength & pull control values */
@@ -437,6 +447,92 @@
return _emmc_recovery_init();
}
+#define USB30_QSCRATCH_GENERAL_CFG (MSM_USB30_QSCRATCH_BASE + 0x08)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL (1 << 0)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW (1 << 3)
+#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS (1 << 8)
+
+#define CM_DWC_USB2_USB_PHY_UTMI_CTRL5 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x74)
+#define CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x78)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x98)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x9c)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa0)
+#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa4)
+#define CM_DWC_USB2_USB_PHY_REFCLK_CTRL (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xe8)
+
+void target_usb_phy_mux_configure(void)
+{
+}
+
+void target_usb_phy_init(void)
+{
+ uint32_t val;
+
+ /* Disable clock */
+ val = readl(USB30_QSCRATCH_GENERAL_CFG);
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ mdelay(1);
+
+ /* Select UTMI instead of PIPE3 */
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ val |= USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+ mdelay(1);
+
+ /* Enable clock */
+ val &= ~USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
+ writel(val, USB30_QSCRATCH_GENERAL_CFG);
+
+ /* Initialize HS PICO PHY */
+ writel(0xc4, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0);
+ writel(0x88, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1);
+ writel(0x11, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2);
+ writel(0x03, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3);
+
+ writel(0x02, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
+ mdelay(1);
+ writel(0x00, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
+
+ val = readl(CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
+ val &= ~(7 << 1);
+ val |= (6 << 1);
+ writel(val, CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
+
+ val = readl(CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
+ val &= ~(7 << 4);
+ val |= (7 << 4);
+ writel(val, CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
+}
+
+void target_usb_phy_reset(void)
+{
+}
+
+target_usb_iface_t* target_usb30_init()
+{
+ target_usb_iface_t *t_usb_iface;
+
+ t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ ASSERT(t_usb_iface);
+
+ t_usb_iface->mux_config = target_usb_phy_mux_configure;
+ t_usb_iface->phy_init = target_usb_phy_init;
+ t_usb_iface->phy_reset = target_usb_phy_reset;
+ t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->vbus_override = 1;
+
+ return t_usb_iface;
+}
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+ return "dwc";
+}
+
+/* configure hs phy mux if using dwc controller */
void target_usb_stop(void)
{
}
diff --git a/target/fsm9010/meminfo.c b/target/fsm9010/meminfo.c
index c6dd53e..fa0f96a 100644
--- a/target/fsm9010/meminfo.c
+++ b/target/fsm9010/meminfo.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -90,6 +90,6 @@
unsigned target_get_max_flash_size(void)
{
- return (512 * 1024 * 1024);
+ return (86 * 1024 * 1024);
}
#endif /* DEVICE_TREE */
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
index 36cdc57..17a1b1d 100644
--- a/target/fsm9010/rules.mk
+++ b/target/fsm9010/rules.mk
@@ -4,7 +4,7 @@
PLATFORM := fsm9010
-MEMBASE := 0x0F900000 # SDRAM
+MEMBASE := 0x18a00000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x0b600000
@@ -12,12 +12,13 @@
TAGS_ADDR := BASE_ADDR+0x01e00000
KERNEL_ADDR := BASE_ADDR+0x00008000
RAMDISK_ADDR := BASE_ADDR+0x02000000
-SCRATCH_ADDR := 0x0ff00000
+SCRATCH_ADDR := 0x0e000000
MODULES += \
dev/keys \
- lib/ptable \
- lib/libfdt
+ lib/ptable \
+ lib/libfdt \
+ dev/pmic/pm8x41
DEFINES += \
MEMSIZE=$(MEMSIZE) \
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
index aff6aa6..cc06e0e 100644
--- a/target/fsm9900/init.c
+++ b/target/fsm9900/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -342,6 +342,7 @@
case FSM9915:
case FSM9950:
case FSM9955:
+ case FSM9916:
board->baseband = BASEBAND_MSM;
break;
default:
@@ -369,7 +370,7 @@
uint32_t restart_reason = 0;
uint32_t restart_reason_addr;
- restart_reason_addr = RESTART_REASON_ADDR;
+ restart_reason_addr = RESTART_REASON_ADDR_V2;
/* Read reboot reason and scrub it */
restart_reason = readl(restart_reason_addr);
@@ -381,7 +382,7 @@
void reboot_device(unsigned reboot_reason)
{
/* Write the reboot reason */
- writel(reboot_reason, RESTART_REASON_ADDR);
+ writel(reboot_reason, RESTART_REASON_ADDR_V2);
/* Disable Watchdog Debug.
* Required becuase of a H/W bug which causes the system to
diff --git a/target/init.c b/target/init.c
index 79e0466..97809cc 100644
--- a/target/init.c
+++ b/target/init.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -52,6 +54,11 @@
return (120 * 1024 * 1024);
}
+__WEAK int flash_ubi_img(void)
+{
+ return 0;
+}
+
__WEAK int target_is_emmc_boot(void)
{
#if _EMMC_BOOT
@@ -66,6 +73,11 @@
return 0;
}
+__WEAK unsigned check_hard_reboot_mode(void)
+{
+ return 0;
+}
+
__WEAK void reboot_device(unsigned reboot_reason)
{
}
@@ -204,3 +216,13 @@
{
return DDR_CONFIG_VAL;
}
+
+/* Return Build variant */
+__WEAK bool target_build_variant_user()
+{
+#if USER_BUILD_VARIANT
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index 442d117..91c61ef 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -83,7 +83,7 @@
#define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF
-#define EXT4_CMDLINE " rootfstype=ext4 root=/dev/mmcblk0p"
+#define EXT4_CMDLINE " rootwait rootfstype=ext4 root=/dev/mmcblk0p"
#define UBI_CMDLINE " rootfstype=ubifs rootflags=bulk_read ubi.fm_autoconvert=1"
struct qpic_nand_init_config config;
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index ca4623c..4ac9b37 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 8
@@ -305,9 +306,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
@@ -397,6 +398,9 @@
uint32_t panel_loop = 0;
uint32_t ret = 0;
uint32_t fb_addr = MIPI_FB_ADDR;
+ char cont_splash = '\0';
+
+ set_panel_cmd_string(panel_name, &cont_splash);
if (!strcmp(panel_name, NO_PANEL_CONFIG)
|| !strcmp(panel_name, SIM_VIDEO_PANEL)
@@ -420,6 +424,10 @@
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 573a585..f87b2ed 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -192,6 +192,9 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
+
+ set_panel_cmd_string(panel_name, &cont_splash);
if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
dprintf(INFO, "Skip panel configuration\n");
@@ -210,6 +213,10 @@
}
} while (++panel_loop <= (uint32_t)oem_panel_max_auto_detect_panels());
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 56c25c2..96232fe 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -240,7 +240,7 @@
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
};
/* Pull configs for sdc pins */
@@ -471,6 +471,7 @@
case MSM8909:
case MSM8209:
case MSM8208:
+ case MSM8609:
board->baseband = BASEBAND_MSM;
break;
@@ -511,6 +512,7 @@
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
case HW_PLATFORM_QRD:
+ case HW_PLATFORM_RCM:
splash_screen = 1;
break;
default:
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
index 440f08c..f7b5717 100644
--- a/target/msm8909/oem_panel.c
+++ b/target/msm8909/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -40,10 +40,13 @@
#include "include/panel_hx8394d_720p_video.h"
#include "include/panel_hx8379a_fwvga_skua_video.h"
#include "include/panel_sharp_qhd_video.h"
+#include "include/panel_truly_wvga_cmd.h"
#include "include/panel_ili9806e_fwvga_video.h"
#include "include/panel_hx8379c_fwvga_video.h"
+#include "include/panel_hx8394d_qhd_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 0
+#define ILI9806E_FWVGA_VIDEO_PANEL_POST_INIT_DELAY 68
enum {
QRD_SKUA = 0x00,
@@ -60,8 +63,10 @@
HX8394D_720P_VIDEO_PANEL,
HX8379A_FWVGA_SKUA_VIDEO_PANEL,
SHARP_QHD_VIDEO_PANEL,
+ TRULY_WVGA_CMD_PANEL,
ILI9806E_FWVGA_VIDEO_PANEL,
HX8379C_FWVGA_VIDEO_PANEL,
+ HX8394D_QHD_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -73,8 +78,10 @@
{"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
{"hx8379a_fwvga_skua_video", HX8379A_FWVGA_SKUA_VIDEO_PANEL},
{"sharp_qhd_video", SHARP_QHD_VIDEO_PANEL},
+ {"truly_wvga_cmd", TRULY_WVGA_CMD_PANEL},
{"ili9806e_fwvga_video",ILI9806E_FWVGA_VIDEO_PANEL},
{"hx8379c_fwvga_video",HX8379C_FWVGA_VIDEO_PANEL},
+ {"hx8394d_qhd_video", HX8394D_QHD_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -90,6 +97,9 @@
* OEM can keep there panel specific on instructions in this
* function
*/
+ if (panel_id == ILI9806E_FWVGA_VIDEO_PANEL)
+ mdelay(ILI9806E_FWVGA_VIDEO_PANEL_POST_INIT_DELAY);
+
return NO_ERROR;
}
@@ -182,6 +192,30 @@
= SHARP_QHD_VIDEO_OFF_COMMAND;
memcpy(phy_db->timing, sharp_qhd_video_timings, TIMING_SIZE);
break;
+ case TRULY_WVGA_CMD_PANEL:
+ panelstruct->paneldata = &truly_wvga_cmd_panel_data;
+ panelstruct->panelres = &truly_wvga_cmd_panel_res;
+ panelstruct->color = &truly_wvga_cmd_color;
+ panelstruct->videopanel = &truly_wvga_cmd_video_panel;
+ panelstruct->commandpanel = &truly_wvga_cmd_command_panel;
+ panelstruct->state = &truly_wvga_cmd_state;
+ panelstruct->laneconfig = &truly_wvga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_cmd_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = truly_wvga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = TRULY_WVGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = truly_wvga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = TRULY_WVGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_cmd_timings, TIMING_SIZE);
+ break;
case ILI9806E_FWVGA_VIDEO_PANEL:
panelstruct->paneldata = &ili9806e_fwvga_video_panel_data;
panelstruct->panelres = &ili9806e_fwvga_video_panel_res;
@@ -232,6 +266,31 @@
hx8379c_fwvga_video_timings, TIMING_SIZE);
pinfo->mipi.signature = HX8379C_FWVGA_VIDEO_SIGNATURE;
break;
+ case HX8394D_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394d_qhd_video_panel_data;
+ panelstruct->panelres = &hx8394d_qhd_video_panel_res;
+ panelstruct->color = &hx8394d_qhd_video_color;
+ panelstruct->videopanel = &hx8394d_qhd_video_video_panel;
+ panelstruct->commandpanel = &hx8394d_qhd_video_command_panel;
+ panelstruct->state = &hx8394d_qhd_video_state;
+ panelstruct->laneconfig = &hx8394d_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394d_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394d_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &hx8394d_qhd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8394d_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8394D_QHD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8394d_qhd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8394D_QHD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394d_qhd_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394D_QHD_VIDEO_SIGNATURE;
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -281,6 +340,7 @@
switch (hw_id) {
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
+ case HW_PLATFORM_RCM:
panel_id = HX8394D_720P_VIDEO_PANEL;
break;
case HW_PLATFORM_QRD:
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index c7c8c2d..7b7aea7 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define VCO_DELAY_USEC 1000
#define GPIO_STATE_LOW 0
@@ -50,6 +51,7 @@
#define RESET_GPIO_SEQ_LEN 3
#define PWM_DUTY_US 13
#define PWM_PERIOD_US 27
+#define PM8916_VER 0x20000
static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
{
@@ -93,12 +95,19 @@
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_mpp mpp;
+ uint32_t hw_id = board_hardware_id();
+ struct board_pmic_data pmic_info;
int rc;
if (bl->bl_interface_type == BL_DCS)
return 0;
- mpp.base = PM8x41_MMP2_BASE;
+ board_pmic_info(&pmic_info, 1);
+ if (pmic_info.pmic_version == PM8916_VER)
+ mpp.base = PM8x41_MMP4_BASE;
+ else
+ mpp.base = PM8x41_MMP2_BASE;
+
mpp.vin = MPP_VIN0;
if (enable) {
pm_pwm_enable(false);
@@ -116,6 +125,14 @@
pm8x41_enable_mpp(&mpp, MPP_DISABLE);
}
mdelay(20);
+
+ if (enable) {
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ bkl_gpio.pin_direction, bkl_gpio.pin_pull,
+ bkl_gpio.pin_strength, bkl_gpio.pin_state);
+ gpio_set(bkl_gpio.pin_id, 2);
+ }
+
return 0;
}
@@ -149,9 +166,9 @@
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- if (!dsi_pll_enable_seq_8909(DSI0_PLL_BASE))
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_0_base))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
@@ -183,14 +200,6 @@
gpio_set(enable_gpio.pin_id, 2);
}
- if (hw_id == HW_PLATFORM_SURF || (hw_id == HW_PLATFORM_MTP)) {
- /* configure backlight gpio for CDP and MTP */
- gpio_tlmm_config(bkl_gpio.pin_id, 0,
- bkl_gpio.pin_direction, bkl_gpio.pin_pull,
- bkl_gpio.pin_strength, bkl_gpio.pin_state);
- gpio_set(bkl_gpio.pin_id, 2);
- }
-
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
@@ -214,7 +223,7 @@
return ret;
}
-int target_ldo_ctrl(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
if (enable)
regulator_enable(); /* L2, L6, and L17 */
@@ -231,9 +240,16 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
- if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
- dprintf(INFO, "Skip panel configuration\n");
+ set_panel_cmd_string(panel_name, &cont_splash);
+
+ panel_name += strspn(panel_name, " ");
+ if (!strcmp(panel_name, NO_PANEL_CONFIG)
+ || !strcmp(panel_name, SIM_VIDEO_PANEL)
+ || !strcmp(panel_name, SIM_CMD_PANEL)) {
+ dprintf(INFO, "Selected %s: Skip panel configuration\n",
+ panel_name);
return;
}
@@ -247,6 +263,11 @@
msm_display_off();
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
index 366b1f7..27b4a5d 100644
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -41,6 +41,10 @@
"msmgpio", 25, 3, 1, 0, 1
};
+static struct gpio_pin ts_reset_gpio = {
+ "msmgpio", 12, 3, 1, 0, 1
+};
+
static struct gpio_pin enable_gpio = {
"msmgpio", 97, 3, 1, 0, 1
};
@@ -148,6 +152,7 @@
{
HW_PLATFORM_SUBTYPE_DEFAULT = 0,
HW_PLATFORM_SUBTYPE_CDP_1 = 1,
+ HW_PLATFORM_SUBTYPE_CDP_2 = 2,
HW_PLATFORM_SUBTYPE_MTP_3 = 3,
HW_PLATFORM_SUBTYPE_SKUH = 4,
HW_PLATFORM_SUBTYPE_SKUI = 5, /* msm8916 */
@@ -171,6 +176,9 @@
NT35521_WXGA_VIDEO_PANEL,
SAMSUNG_WXGA_VIDEO_PANEL,
HX8279A_WSVGA_VIDEO_PANEL,
+ R61318_HD_VIDEO_PANEL,
+ R63417_1080P_VIDEO_PANEL,
+ JDI_A216_FHD_VIDEO_PANEL,
UNKNOWN_PANEL
};
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index 0289973..fbc45e4 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -66,6 +66,7 @@
#endif
#define FASTBOOT_MODE 0x77665500
+#define PON_SOFT_RB_SPARE 0x88F
#define CE1_INSTANCE 1
#define CE_EE 1
@@ -241,6 +242,21 @@
return restart_reason;
}
+unsigned check_hard_reboot_mode(void)
+{
+ uint8_t hard_restart_reason = 0;
+ uint8_t value = 0;
+
+ /* Read reboot reason and scrub it
+ * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason
+ */
+ value = pm8x41_reg_read(PON_SOFT_RB_SPARE);
+ hard_restart_reason = value >> 5;
+ pm8x41_reg_write(PON_SOFT_RB_SPARE, value & 0x1f);
+
+ return hard_restart_reason;
+}
+
static int scm_dload_mode(int mode)
{
int ret = 0;
@@ -341,11 +357,15 @@
case MSM8636:
case MSM8936:
case MSM8239:
+ case MSM8929:
+ case MSM8629:
+ case MSM8229:
board->baseband = BASEBAND_MSM;
break;
case APQ8016:
case APQ8039:
case APQ8036:
+ case APQ8029:
board->baseband = BASEBAND_APQ;
break;
default:
@@ -411,6 +431,7 @@
switch(board_hardware_id()) {
case HW_PLATFORM_SURF:
+ case HW_PLATFORM_MTP:
ret = 1;
break;
default:
@@ -460,7 +481,7 @@
if (is_cold_boot &&
(!(pon_reason & HARD_RST)) &&
(!(pon_reason & KPDPWR_N)) &&
- ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
return 1;
else
return 0;
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 154bd4c..9e4349d 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -55,6 +55,9 @@
#include "include/panel_nt35521_wxga_video.h"
#include "include/panel_samsung_wxga_video.h"
#include "include/panel_hx8279a_wsvga_video.h"
+#include "include/panel_r61318_hd_video.h"
+#include "include/panel_r63417_1080p_video.h"
+#include "include/panel_jdi_a216_fhd_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -88,7 +91,10 @@
{"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
{"nt35521_wxga_video", NT35521_WXGA_VIDEO_PANEL},
{"samsung_wxga_video", SAMSUNG_WXGA_VIDEO_PANEL},
- {"hx8279a_wsvga_video", HX8279A_WSVGA_VIDEO_PANEL}
+ {"hx8279a_wsvga_video", HX8279A_WSVGA_VIDEO_PANEL},
+ {"r61318_hd_video", R61318_HD_VIDEO_PANEL},
+ {"r63417_1080p_video", R63417_1080P_VIDEO_PANEL},
+ {"jdi_a216_fhd_video", JDI_A216_FHD_VIDEO_PANEL},
};
static uint32_t panel_id;
@@ -474,6 +480,78 @@
memcpy(phy_db->timing,
hx8279a_wsvga_video_timings, TIMING_SIZE);
break;
+ case R61318_HD_VIDEO_PANEL:
+ panelstruct->paneldata = & r61318_hd_video_panel_data;
+ panelstruct->panelres = & r61318_hd_video_panel_res;
+ panelstruct->color = & r61318_hd_video_color;
+ panelstruct->videopanel = & r61318_hd_video_video_panel;
+ panelstruct->commandpanel = & r61318_hd_video_command_panel;
+ panelstruct->state = & r61318_hd_video_state;
+ panelstruct->laneconfig = & r61318_hd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = & r61318_hd_video_timing_info;
+ panelstruct->panelresetseq
+ = & r61318_hd_video_reset_seq;
+ panelstruct->backlightinfo = & r61318_hd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = r61318_hd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = R61318_HD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = r61318_hd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = R61318_HD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ r61318_hd_video_timings, TIMING_SIZE);
+ break;
+ case R63417_1080P_VIDEO_PANEL:
+ panelstruct->paneldata = & r63417_1080p_video_panel_data;
+ panelstruct->panelres = & r63417_1080p_video_panel_res;
+ panelstruct->color = & r63417_1080p_video_color;
+ panelstruct->videopanel = & r63417_1080p_video_video_panel;
+ panelstruct->commandpanel = & r63417_1080p_video_command_panel;
+ panelstruct->state = & r63417_1080p_video_state;
+ panelstruct->laneconfig = & r63417_1080p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = & r63417_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = & r63417_1080p_video_reset_seq;
+ panelstruct->backlightinfo = & r63417_1080p_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = r63417_1080p_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = R63417_1080P_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = r63417_1080p_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = R63417_1080P_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ r63417_1080p_video_timings, TIMING_SIZE);
+ break;
+ case JDI_A216_FHD_VIDEO_PANEL:
+ panelstruct->paneldata = &jdi_a216_fhd_video_panel_data;
+ panelstruct->panelres = &jdi_a216_fhd_video_panel_res;
+ panelstruct->color = &jdi_a216_fhd_video_color;
+ panelstruct->videopanel = &jdi_a216_fhd_video_video_panel;
+ panelstruct->commandpanel = &jdi_a216_fhd_video_command_panel;
+ panelstruct->state = &jdi_a216_fhd_video_state;
+ panelstruct->laneconfig = &jdi_a216_fhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_a216_fhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_a216_fhd_video_reset_seq;
+ panelstruct->backlightinfo = &jdi_a216_fhd_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = jdi_a216_fhd_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = JDI_A216_FHD_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = jdi_a216_fhd_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = JDI_A216_FHD_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_a216_fhd_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -524,13 +602,31 @@
switch (hw_id) {
case HW_PLATFORM_MTP:
- panel_id = JDI_1080P_VIDEO_PANEL;
- if (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3)
+ if (platform_is_msm8939() &&
+ hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3) {
panel_id = JDI_FHD_VIDEO_PANEL;
+ } else {
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ switch (auto_pan_loop) {
+ case 0:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ break;
+ case 1:
+ panel_id = HX8394D_720P_VIDEO_PANEL;
+ break;
+ default:
+ panel_id = UNKNOWN_PANEL;
+ dprintf(CRITICAL, "Unknown panel\n");
+ return PANEL_TYPE_UNKNOWN;
+ }
+ auto_pan_loop++;
+ }
break;
case HW_PLATFORM_SURF:
if (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1) {
panel_id = JDI_FHD_VIDEO_PANEL;
+ } else if (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_2) {
+ panel_id = JDI_A216_FHD_VIDEO_PANEL;
} else {
panel_id = JDI_1080P_VIDEO_PANEL;
switch (auto_pan_loop) {
@@ -555,10 +651,15 @@
target_id = board_target_id();
plat_hw_ver_major = ((target_id >> 16) & 0xFF);
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
switch (hw_subtype) {
case HW_PLATFORM_SUBTYPE_SKUK:
- panel_id = NT35596_1080P_VIDEO_PANEL;
+ if ((plat_hw_ver_major >> 4) == 0x1)
+ panel_id = R61318_HD_VIDEO_PANEL;
+ else if ((plat_hw_ver_major >> 4) == 0x2)
+ panel_id = R63417_1080P_VIDEO_PANEL;
+ else
+ panel_id = NT35596_1080P_VIDEO_PANEL;
break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
@@ -610,7 +711,7 @@
* Update all data structures after 'panel_init' label. Only panel
* selection is supposed to happen before that.
*/
- if (platform_is_msm8939() || (hw_id == HW_PLATFORM_QRD)) {
+ if (platform_is_msm8939() || platform_is_msm8929() || (hw_id == HW_PLATFORM_QRD)) {
phy_db->regulator_mode = DSI_PHY_REGULATOR_LDO_MODE;
memcpy(panel_regulator_settings,
ldo_regulator_settings, REGULATOR_SIZE);
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index a3e5bad..0ddaec1 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +45,7 @@
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define VCO_DELAY_USEC 1000
#define GPIO_STATE_LOW 0
@@ -145,9 +146,9 @@
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE);
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE))
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_0_base))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
pll_data->pclk_n,
@@ -310,6 +311,18 @@
}
}
+int target_panel_reset_jdi_a216(uint8_t enable)
+{
+ if (enable) {
+ gpio_tlmm_config(ts_reset_gpio.pin_id, 0,
+ ts_reset_gpio.pin_direction, ts_reset_gpio.pin_pull,
+ ts_reset_gpio.pin_strength, ts_reset_gpio.pin_state);
+ gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_HIGH);
+ } else {
+ gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_LOW);
+ }
+}
+
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
@@ -338,13 +351,18 @@
gpio_set_dir(enable_gpio.pin_id, 2);
}
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
target_panel_reset_skuk(enable);
- if ((hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1) ||
- (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3))
+ if (((hw_id == HW_PLATFORM_SURF) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1)) ||
+ ((hw_id == HW_PLATFORM_MTP) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3)))
target_panel_reset_incell(enable);
+ if ((hw_id == HW_PLATFORM_SURF) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_2))
+ target_panel_reset_jdi_a216(enable);
} else { /* msm8916 */
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUH))
@@ -378,7 +396,7 @@
if (pinfo->mipi.use_enable_gpio)
gpio_set_dir(enable_gpio.pin_id, 0);
- if (platform_is_msm8939()) {
+ if (platform_is_msm8939() || platform_is_msm8929()) {
if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
target_panel_reset_skuk(enable);
@@ -410,7 +428,9 @@
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -431,6 +451,11 @@
msm_display_off();
}
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 289675c..6224f31 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -247,9 +247,9 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(DSI0_PLL_BASE);
+ mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.ctl_base, pll_data);
+ dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
@@ -413,10 +413,12 @@
uint32_t hw_id = board_hardware_id();
uint32_t panel_loop = 0;
int ret = 0;
+ char cont_splash = '\0';
if (target_hw_interposer())
return;
+ set_panel_cmd_string(panel_name, &cont_splash);
panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
@@ -431,6 +433,7 @@
dprintf(INFO, "%s: HDMI is primary\n", __func__);
return;
}
+
switch (hw_id) {
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
@@ -461,6 +464,11 @@
} while (++panel_loop <= (uint32_t)oem_panel_max_auto_detect_panels());
break;
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
index 0bbc751..c426ee2 100644
--- a/target/msm8994/include/target/display.h
+++ b/target/msm8994/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -49,15 +49,15 @@
};
static const uint32_t panel_regulator_settings[] = {
- 0x03, 0x02, 0x03, 0x00, 0x10, 0x07, 0x01
+ 0x03, 0x03, 0x03, 0x00, 0x20, 0x07, 0x01
};
static const char panel_lane_config[] = {
-0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x88,
-0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x88,
-0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x88
+0x02, 0xa0, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x46,
+0x02, 0xa0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x46,
+0x00, 0xa0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x46
};
static const uint32_t panel_physical_ctrl[] = {
@@ -81,6 +81,9 @@
#define PWM_BL_LPG_CHAN_ID 4 /* lpg_out<3> */
+#define HDMI_PANEL_NAME "hdmi"
+#define HDMI_CONTROLLER_STRING "hdmi:0"
+
#endif
/*---------------------------------------------------------------------------*/
@@ -91,6 +94,7 @@
int target_display_post_on();
int target_display_post_off();
int target_cont_splash_screen();
+int target_display_get_base_offset(uint32_t base);
void target_force_cont_splash_disable(uint8_t override);
uint8_t target_panel_auto_detect_enabled();
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 4990ea0..5df2874 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -58,6 +58,8 @@
#include <qusb2_phy.h>
#include <rpm-smd.h>
#include <sdhci_msm.h>
+#include <pm8x41_wled.h>
+#include <qpnp_led.h>
#include "target/display.h"
@@ -75,7 +77,7 @@
#define FASTBOOT_MODE 0x77665500
-#define PMIC_WLED_SLAVE_ID 3
+#define PMIC_LED_SLAVE_ID 3
#define DDR_CFG_DLY_VAL 0x80040870
void target_crypto_init_params(void);
@@ -320,20 +322,31 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
- else
+#endif
+#ifdef UFS_SUPPORT
+ if(!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
-
+#endif
/* Storage initialization is complete, read the partition table info */
mmc_read_partition_table(0);
rpm_smd_init();
+
+ /* QPNP LED init for boot process notification */
+ if (board_hardware_id() == HW_PLATFORM_LIQUID){
+ pm8x41_wled_config_slave_id(PMIC_LED_SLAVE_ID);
+ qpnp_led_init(QPNP_LED_BLUE, QPNP_LED_CTRL_BASE,
+ QPNP_BLUE_LPG_CTRL_BASE);
+ }
+
}
unsigned board_machtype(void)
@@ -442,7 +455,7 @@
else
reset_type = PON_PSHOLD_HARD_RESET;
- pm8x41_reset_configure(reset_type);
+ pm8994_reset_configure(reset_type);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
@@ -543,7 +556,7 @@
dprintf(CRITICAL, "Going down for shutdown.\n");
/* Configure PMIC for shutdown. */
- pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+ pm8994_reset_configure(PON_PSHOLD_SHUTDOWN);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index fca02c9..de292b5 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,6 +35,7 @@
#include <board.h>
#include <mipi_dsi.h>
#include <qtimer.h>
+#include <platform.h>
#include "include/panel.h"
#include "panel_display.h"
@@ -124,6 +125,14 @@
panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data;
panelstruct->paneldata->panel_operating_mode = 11;
panelstruct->paneldata->panel_with_enable_gpio = 0;
+
+ /*
+ * Even though this panel can be supported with a single pipe,
+ * enable ping-pong split and use two pipes for simplicity sake.
+ */
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &sharp_wqxga_dualdsi_video_panel_res;
panelstruct->color = &sharp_wqxga_dualdsi_video_color;
panelstruct->videopanel = &sharp_wqxga_dualdsi_video_video_panel;
@@ -148,11 +157,16 @@
= SHARP_WQXGA_DUALDSI_VIDEO_OFF_COMMAND;
memcpy(phy_db->timing,
sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+ pinfo->dfps.panel_dfps = sharp_wqxga_dualdsi_video_dfps;
break;
case JDI_QHD_DUALDSI_VIDEO_PANEL:
pan_type = PANEL_TYPE_DSI;
pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_video_color;
panelstruct->videopanel = &jdi_qhd_dualdsi_video_video_panel;
@@ -179,6 +193,10 @@
pan_type = PANEL_TYPE_DSI;
pinfo->lcd_reg_en = 1;
panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
@@ -206,6 +224,10 @@
pinfo->lcd_reg_en = 1;
pinfo->mipi.cmds_post_tg = 1;
panelstruct->paneldata = &jdi_4k_dualdsi_video_panel_data;
+
+ if (platform_is_msm8992())
+ panelstruct->paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
panelstruct->panelres = &jdi_4k_dualdsi_video_panel_res;
panelstruct->color = &jdi_4k_dualdsi_video_color;
panelstruct->videopanel = &jdi_4k_dualdsi_video_video_panel;
diff --git a/target/msm8994/regulator.c b/target/msm8994/regulator.c
index 8a8d1e1..c28afa2 100644
--- a/target/msm8994/regulator.c
+++ b/target/msm8994/regulator.c
@@ -35,15 +35,15 @@
{
LDOA_RES_TYPE, 2,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 2,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1250000,
+ KEY_CURRENT, 4, 16,
},
};
@@ -52,15 +52,15 @@
{
LDOA_RES_TYPE, 12,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 12,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 11,
},
};
@@ -69,32 +69,32 @@
{
LDOA_RES_TYPE, 14,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 14,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 52,
},
};
-static uint32_t ldo28[][11]=
+static uint32_t ldo28[][14]=
{
{
LDOA_RES_TYPE, 28,
KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
},
{
LDOA_RES_TYPE, 28,
KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
- KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
KEY_MICRO_VOLT, 4, 1000000,
+ KEY_CURRENT, 4, 72,
},
};
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index ec35e53..9c02201 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -16,10 +16,13 @@
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
+DEFINES += DISPLAY_EN_20NM_PLL_90_PHASE
+
MODULES += \
dev/keys \
dev/pmic/pm8x41 \
dev/qpnp_wled \
+ dev/qpnp_led \
lib/ptable \
dev/gcdb/display \
lib/libfdt
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 1ac0895..6cf3653 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -62,6 +62,9 @@
#define PMIC_WLED_SLAVE_ID 3
#define PMIC_MPP_SLAVE_ID 2
+#define DSI0_BASE_ADJUST -0x4000
+#define DSI1_BASE_ADJUST -0xA000
+
/*---------------------------------------------------------------------------*/
/* GPIO configuration */
/*---------------------------------------------------------------------------*/
@@ -253,9 +256,10 @@
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t ret;
+ uint32_t ret = NO_ERROR;
struct mdss_dsi_pll_config *pll_data;
uint32_t flags;
+ struct dfps_pll_codes *pll_codes = &pinfo->mipi.pll_codes;
if (pinfo->dest == DISPLAY_2) {
flags = MMSS_DSI_CLKS_FLAG_DSI1;
@@ -268,36 +272,53 @@
}
pll_data = pinfo->mipi.dsi_pll_config;
- if (enable) {
- mdp_gdsc_ctrl(enable);
- mmss_bus_clock_enable();
- mdp_clock_enable();
- ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
- if (ret) {
- dprintf(CRITICAL,
- "%s: Failed to restore MDP security configs",
- __func__);
- mdp_clock_disable();
- mmss_bus_clock_disable();
- mdp_gdsc_ctrl(0);
- return ret;
- }
- mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
- MIPI_DSI0_BASE, pll_data);
- dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
- mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
- pll_data->pclk_m,
- pll_data->pclk_n,
- pll_data->pclk_d);
- } else if(!target_cont_splash_screen()) {
- /* Disable clocks if continuous splash off */
+
+ if (!enable) {
mmss_dsi_clock_disable(flags);
- mdp_clock_disable();
- mmss_bus_clock_disable();
- mdp_gdsc_ctrl(enable);
+ goto clks_disable;
}
+ mdp_gdsc_ctrl(enable);
+ mmss_bus_clock_enable();
+ mdp_clock_enable();
+
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ goto clks_disable;
+ }
+
+ mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_0_base,
+ pinfo->mipi.pll_1_base, pll_data);
+
+ if (!dsi_pll_20nm_enable_seq(pinfo->mipi.pll_0_base)) {
+ ret = ERROR;
+ dprintf(CRITICAL, "PLL failed to lock!\n");
+ goto clks_disable;
+ }
+
+ pll_codes->codes[0] = readl_relaxed(pinfo->mipi.pll_0_base +
+ MMSS_DSI_PHY_PLL_CORE_KVCO_CODE);
+ pll_codes->codes[1] = readl_relaxed(pinfo->mipi.pll_0_base +
+ MMSS_DSI_PHY_PLL_CORE_VCO_TUNE);
+ dprintf(SPEW, "codes %d %d\n", pll_codes->codes[0],
+ pll_codes->codes[1]);
+
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+
return NO_ERROR;
+
+clks_disable:
+ mdp_clock_disable();
+ mmss_bus_clock_disable();
+ mdp_gdsc_ctrl(0);
+
+ return ret;
}
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
@@ -417,16 +438,50 @@
return NO_ERROR;
}
+int target_display_get_base_offset(uint32_t base)
+{
+ if(platform_is_msm8992()) {
+ if (base == MIPI_DSI0_BASE)
+ return DSI0_BASE_ADJUST;
+ else if (base == MIPI_DSI1_BASE)
+ return DSI1_BASE_ADJUST;
+ }
+
+ return 0;
+}
+
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+ int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ bool ret = true;
+ panel_name += strspn(panel_name, " ");
+
+ if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
+ strlen(HDMI_CONTROLLER_STRING))) {
+ dprintf(CRITICAL, "command line argument is greater than buffer size\n");
+ return false;
+ }
+
+ strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+ buf_size -= prefix_string_len;
+ strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size);
+ buf_size -= LK_OVERRIDE_PANEL_LEN;
+ strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
+ } else {
+ ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+ }
+
+ return ret;
}
void target_display_init(const char *panel_name)
{
- panel_name += strspn(panel_name, " ");
+ char cont_splash = '\0';
+ set_panel_cmd_string(panel_name, &cont_splash);
+ panel_name += strspn(panel_name, " ");
if (!strcmp(panel_name, NO_PANEL_CONFIG)
|| !strcmp(panel_name, SIM_VIDEO_PANEL)
|| !strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)
@@ -435,11 +490,19 @@
dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
panel_name);
return;
+ } else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+ return;
}
+
if (gcdb_display_init(panel_name, MDP_REV_50, (void *)MIPI_FB_ADDR)) {
target_force_cont_splash_disable(true);
msm_display_off();
}
+
+ if (cont_splash == '0') {
+ dprintf(INFO, "Forcing continuous splash disable\n");
+ target_force_cont_splash_disable(true);
+ }
}
void target_display_shutdown(void)
diff --git a/target/target_display.c b/target/target_display.c
index a16a46e..ae014e1 100644
--- a/target/target_display.c
+++ b/target/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -64,6 +64,10 @@
{
return 0;
}
+__WEAK int target_display_get_base_offset(uint32_t base)
+{
+ return 0;
+}
__WEAK int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
return 0;
diff --git a/target/thulium/init.c b/target/thulium/init.c
index 6be1df5..28c6b2c 100644
--- a/target/thulium/init.c
+++ b/target/thulium/init.c
@@ -56,6 +56,15 @@
#include <sdhci_msm.h>
#include <qusb2_phy.h>
+#define CE_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
+
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
@@ -72,8 +81,6 @@
struct mmc_device *dev;
struct ufs_dev ufs_device;
-extern void ulpi_write(unsigned val, unsigned reg);
-
void target_early_init(void)
{
#if WITH_DEBUG_UART
@@ -99,7 +106,7 @@
thread_sleep(1);
/* Get status of P_GPIO_5 */
- pm8x41_gpio_get(3, &status);
+ pm8x41_gpio_get(2, &status);
return !status; /* active low */
}
@@ -169,6 +176,7 @@
config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_192MHZ;
+ config.hs400_support = 1;
/* Try slot 1*/
config.slot = 1;
@@ -214,22 +222,22 @@
platform_read_boot_config();
+#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
- else
+#endif
+#ifdef UFS_SUPPORT
+ if (!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
+#endif
/* Storage initialization is complete, read the partition table info */
- if (partition_read_table())
- {
- dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
+ mmc_read_partition_table(0);
}
unsigned board_machtype(void)
@@ -252,7 +260,10 @@
switch(platform) {
case MSMTHULIUM:
- board->baseband = BASEBAND_MSM;
+ if (board->platform_version == 0x10000)
+ board->baseband = BASEBAND_APQ;
+ else
+ board->baseband = BASEBAND_MSM;
break;
default:
dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
@@ -316,9 +327,7 @@
void target_usb_phy_reset()
{
-#ifndef USE_HSONLY_MODE
usb30_qmp_phy_reset();
-#endif
qusb2_phy_reset();
}
@@ -329,10 +338,7 @@
t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
ASSERT(t_usb_iface);
-#ifndef USE_HSONLY_MODE
t_usb_iface->phy_init = usb30_qmp_phy_init;
-#endif
-
t_usb_iface->phy_reset = target_usb_phy_reset;
t_usb_iface->clock_init = clock_usb30_init;
t_usb_iface->vbus_override = 1;
@@ -351,8 +357,38 @@
return 1;
}
-void target_fastboot_init(void)
+crypto_engine_type board_ce_type(void)
{
- /* We are entering fastboot mode, so read partition table */
- mmc_read_partition_table(1);
+ return CRYPTO_ENGINE_TYPE_SW;
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE_INSTANCE;
+ ce_params.crypto_base = MSM_CE_BASE;
+ ce_params.bam_base = MSM_CE_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
}