Merge "platform: msm8226: Add MMU and cache configurations."
diff --git a/platform/msm8226/platform.c b/platform/msm8226/platform.c
index ecec907..3a44db4 100644
--- a/platform/msm8226/platform.c
+++ b/platform/msm8226/platform.c
@@ -29,9 +29,33 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
-#include <platform/clock.h>
#include <qgic.h>
#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+};
+
+static struct smem_ram_ptable ram_ptable;
void platform_early_init(void)
{
@@ -50,3 +74,55 @@
{
qtimer_uninit();
}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+ ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < ram_ptable.len; i++)
+ {
+ if(ram_ptable.parts[i].type == SYS_MEMORY)
+ {
+ if((ram_ptable.parts[i].category == SDRAM) ||
+ (ram_ptable.parts[i].category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ram_ptable.parts[i].start & 0xFFFFF) == 0);
+
+ sections = (ram_ptable.parts[i].size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ram_ptable.parts[i].start +
+ sections * MB,
+ ram_ptable.parts[i].start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}