msm7627a/msm8x25: Fix AHB source clock divider
Set the ratio of acpu clock & ahb clock to 1:8
Change-Id: I64bb6affb7963a7bcfed923936f1d1845ef24d68
diff --git a/platform/msm7x27a/acpuclock.c b/platform/msm7x27a/acpuclock.c
index ba0b939..3cf9386 100644
--- a/platform/msm7x27a/acpuclock.c
+++ b/platform/msm7x27a/acpuclock.c
@@ -77,7 +77,7 @@
#define MIN_AXI_HZ 120000000
#define ACPU_800MHZ 41
-#define A11S_CLK_SEL_MASK 0x7 /* bits 2:0 */
+#define A11S_CLK_SEL_MASK 0x1 /* bits 2:0 */
/* The stepping frequencies have been choosen to make sure the step
* is <= 256 MHz for both 7x27a and 7x25a targets. The
@@ -256,6 +256,10 @@
/* Jump into table and set every entry. */
for (; i < size; i++) {
+ val = readl(A11S_CLK_SEL_ADDR);
+ val |= BIT(1) | BIT(2);
+ writel(val, A11S_CLK_SEL_ADDR);
+
val = readl(A11S_CLK_CNTL_ADDR);
/* Make sure not to disturb already used src */