Merge "target: mdm9640: Change to enable QMP Phy for sdx20 targets."
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index 97e55ec..487e7d8 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -512,12 +512,7 @@
ASSERT(t_usb_iface);
t_usb_iface->mux_config = NULL;
- if (platform_is_sdx20()){
- t_usb_iface->mux_config = target_mux_configure;
- t_usb_iface->phy_init = NULL;
- }
- else
- t_usb_iface->phy_init = usb30_qmp_phy_init;
+ t_usb_iface->phy_init = usb30_qmp_phy_init;
t_usb_iface->phy_reset = target_usb_phy_reset;
t_usb_iface->clock_init = clock_usb30_init;
t_usb_iface->vbus_override = 1;
@@ -632,18 +627,140 @@
{0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
};
+/* QMP settings are different for sdx20 when compared to v2.0/v1.0 hardware.
+ * Use the QMP settings from target code to keep the common driver clean
+ */
+struct qmp_reg qmp_settings_sdx20[] =
+{
+ {0x804, 0x01}, /* USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+ {0x048, 0x07}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+ {0x080, 0x1A}, /* USB3PHY_QSERDES_COM_SYSCLK_EN_SEL */
+ {0x034, 0x04}, /* USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x138, 0x30}, /* USB3PHY_QSERDES_COM_CLK_SELECT */
+ {0x03C, 0x02}, /* USB3PHY_QSERDES_COM_SYS_CLK_CTRL */
+ {0x08C, 0x08}, /* USB3PHY_QSERDES_COM_RESETSM_CNTRL2 */
+ {0x15C, 0x06}, /* USB3PHY_QSERDES_COM_CMN_CONFIG */
+ {0x164, 0x01}, /* USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x13C, 0x80}, /* USB3PHY_QSERDES_COM_HSCLK_SEL */
+ {0x0B0, 0x82}, /* USB3PHY_QSERDES_COM_DEC_START_MODE0 */
+ {0x0B8, 0xAB}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0x0BC, 0xEA}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0x0C0, 0x02}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x060, 0x06}, /* USB3PHY_QSERDES_COM_CP_CTRL_MODE0 */
+ {0x068, 0x16}, /* USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x070, 0x36}, /* USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x0DC, 0x00}, /* USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x0D8, 0x3F}, /* USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x0F8, 0x01}, /* USB3PHY_QSERDES_COM_VCO_TUNE2_MODE0 */
+ {0x0F4, 0xC9}, /* USB3PHY_QSERDES_COM_VCO_TUNE1_MODE0 */
+ {0x148, 0x0A}, /* USB3PHY_QSERDES_COM_CORECLK_DIV_MODE0 */
+ {0x0A0, 0x00}, /* USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0x09C, 0x34}, /* USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x098, 0x15}, /* USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x154, 0x00}, /* USB3PHY_QSERDES_COM_CORE_CLK_EN */
+ {0x094, 0x00}, /* USB3PHY_QSERDES_COM_LOCK_CMP_CFG */
+ {0x0F0, 0x00}, /* USB3PHY_QSERDES_COM_VCO_TUNE_MAP */
+ {0x00C, 0x0A}, /* USB3PHY_QSERDES_COM_BG_TIMER */
+ {0x010, 0x01}, /* USB3PHY_QSERDES_COM_SSC_EN_CENTER */
+ {0x01C, 0x31}, /* USB3PHY_QSERDES_COM_SSC_PER1 */
+ {0x020, 0x01}, /* USB3PHY_QSERDES_COM_SSC_PER2 */
+ {0x014, 0x00}, /* USB3PHY_QSERDES_COM_SSC_ADJ_PER1 */
+ {0x018, 0x00}, /* USB3PHY_QSERDES_COM_SSC_ADJ_PER2 */
+ {0x024, 0x85}, /* USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x028, 0x07}, /* USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 */
+
+ /* Rx Settings */
+ {0x4C0, 0x0C}, /* USB3PHY_QSERDES_RX_VGA_CAL_CNTRL2 */
+ {0x564, 0x59}, /* USB3PHY_QSERDES_RX_RX_MODE_00 */
+ {0x430, 0x0B}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4D4, 0x0E}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4D8, 0x4E}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x4DC, 0x18}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x4F8, 0x77}, /* USB3PHY_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x4FC, 0x80}, /* USB3PHY_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x504, 0x03}, /* USB3PHY_QSERDES_RX_SIGDET_CNTRL */
+ {0x50C, 0x1A}, /* USB3PHY_QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x50C, 0x1A}, /* USB3PHY_QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x260, 0x10}, /* USB3PHY_QSERDES_TX_HIGHZ_DRVR_EN */
+ {0x2A4, 0x12}, /* USB3PHY_QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x28C, 0xC6}, /* USB3PHY_QSERDES_TX_LANE_MODE_1 */
+ {0x8C8, 0x83}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNTRL2 */
+ {0x8CC, 0x09}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_L */
+ {0x8D0, 0xA2}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
+ {0x8D0, 0xA2}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
+ {0x8D4, 0x40}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_MAN_CODE */
+ {0x8C4, 0x02}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNTRL1 */
+ {0x880, 0xD1}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
+ {0x884, 0x1F}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
+ {0x888, 0x47}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
+ {0x864, 0x1B}, /* USB3PHY_PCIE_USB3_UNI_PCS_POWER_STATE_CONFIG2 */
+ {0x0D0, 0x80}, /* USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL */
+ {0x434, 0x75}, /* USB3PHY_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+ {0x43C, 0x00}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+ {0x440, 0x00}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+ {0x444, 0x80}, /* USB3PHY_QSERDES_RX_UCDR_PI_CONTROLS */
+ {0x408, 0x0A}, /* USB3PHY_QSERDES_RX_UCDR_FO_GAIN */
+ {0x414, 0x06}, /* USB3PHY_QSERDES_RX_UCDR_SO_GAIN */
+ {0x500, 0x00}, /* USB3PHY_QSERDES_RX_SIGDET_ENABLES */
+ {0x244, 0x0D}, /* USB3PHY_QSERDES_TX_RES_CODE_LANE_OFFSET_TX */
+ {0x248, 0x09}, /* USB3PHY_QSERDES_TX_RES_CODE_LANE_OFFSET_RX */
+ {0x80C, 0x9F}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V0 */
+ {0x810, 0x9F}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V1 */
+ {0x814, 0xB5}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V2 */
+ {0x818, 0x4C}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V3 */
+ {0x81C, 0x64}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V4 */
+ {0x820, 0x6A}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_LS */
+ {0x824, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */
+ {0x828, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */
+ {0x82C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */
+ {0x830, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */
+ {0x834, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */
+ {0x838, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */
+ {0x83C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */
+ {0x840, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */
+ {0x844, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */
+ {0x848, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */
+ {0x84C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_LS */
+ {0x850, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */
+ {0x85C, 0x02}, /* USB3PHY_PCIE_USB3_UNI_PCS_RATE_SLEW_CNTRL */
+ {0x8B8, 0x75}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_WAIT_TIME */
+ {0x8BC, 0x7A}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_RUN_TIME */
+ {0x8B0, 0x86}, /* USB3PHY_PCIE_USB3_UNI_PCS_LFPS_TX_ECSTART_EQTLOCK */
+ {0x8A0, 0x04}, /* USB3PHY_PCIE_USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+ {0x88C, 0x44}, /* USB3PHY_PCIE_USB3_UNI_PCS_TSYNC_RSYNC_TIME */
+ {0x880, 0xD1}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
+ {0x884, 0x1F}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
+ {0x888, 0x47}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
+ {0x870, 0xF1}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
+ {0x874, 0x01}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
+ {0x878, 0x40}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */
+ {0x87C, 0x00}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */
+// {0x9DB, 0xBA}, /* USB3PHY_PCIE_USB3_UNI_PCS_RX_SIGDET_LVL */
+ {0x8B8, 0x75}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_WAIT_TIME */
+ {0x8B0, 0x86}, /* USB3PHY_PCIE_USB3_UNI_PCS_LFPS_TX_ECSTART_EQTLOCK */
+ {0x8BC, 0x13}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_RUN_TIME */
+ {0xA0C, 0x21}, /* USB3PHY_PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
+ {0xA10, 0x60}, /* USB3PHY_PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
+ {0x800, 0x00}, /* USB3PHY_PCIE_USB3_UNI_PCS_SW_RESET */
+ {0x808, 0x03}, /* USB3PHY_PCIE_USB3_UNI_PCS_START_CONTROL */
+};
+
struct qmp_reg *target_get_qmp_settings()
{
- if (platform_is_mdm9650() || platform_is_sdx20())
+ if (platform_is_mdm9650())
return qmp_settings;
+ else if(platform_is_sdx20())
+ return qmp_settings_sdx20;
else
return NULL;
}
int target_get_qmp_regsize()
{
- if (platform_is_mdm9650() || platform_is_sdx20())
+ if (platform_is_mdm9650())
return ARRAY_SIZE(qmp_settings);
+ else if(platform_is_sdx20())
+ return ARRAY_SIZE(qmp_settings_sdx20);
else
return 0;
}