Merge "platform: msm_shared: Enable compilation for crypto"
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index 221443c..7261b6e 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -35,6 +35,7 @@
#include <mmc.h>
#include <clock.h>
#include <platform/clock.h>
+#include <blsp_qup.h>
void hsusb_clock_init(void)
{
@@ -398,3 +399,41 @@
clock_ce_enable(instance);
}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ uint8_t ret = 0;
+ char clk_name[64];
+
+ struct clk *qup_clk;
+
+ if((blsp_id != BLSP_ID_1) || (qup_id != QUP_ID_1)) {
+ dprintf(CRITICAL, "Incorrect BLSP-%d or QUP-%d configuration\n", blsp_id, qup_id);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "blsp1_qup2_ahb_iface_clk");
+
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+ return;
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup2_i2c_apps_clk");
+
+ qup_clk = clk_get(clk_name);
+
+ if (!qup_clk) {
+ dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+ return;
+ }
+
+ ret = clk_enable(qup_clk);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+ return;
+ }
+}
diff --git a/platform/msm8916/gpio.c b/platform/msm8916/gpio.c
index 3035047..a0af57c 100644
--- a/platform/msm8916/gpio.c
+++ b/platform/msm8916/gpio.c
@@ -30,6 +30,7 @@
#include <reg.h>
#include <platform/iomap.h>
#include <platform/gpio.h>
+#include <blsp_qup.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
@@ -82,3 +83,26 @@
gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
+
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ if(blsp_id == BLSP_ID_1) {
+ switch (qup_id) {
+ case QUP_ID_1:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(6, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(7, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ default:
+ dprintf(CRITICAL, "Incorrect QUP id %d\n",qup_id);
+ ASSERT(0);
+ };
+ } else {
+ dprintf(CRITICAL, "Incorrect BLSP id %d\n",blsp_id);
+ ASSERT(0);
+ }
+}
diff --git a/platform/msm8916/include/platform/clock.h b/platform/msm8916/include/platform/clock.h
index 887c836..bcbbc2e 100644
--- a/platform/msm8916/include/platform/clock.h
+++ b/platform/msm8916/include/platform/clock.h
@@ -76,4 +76,5 @@
void mdp_gdsc_ctrl(uint8_t enable);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id);
#endif
diff --git a/platform/msm8916/include/platform/gpio.h b/platform/msm8916/include/platform/gpio.h
index 12d9fe2..5b4552b 100644
--- a/platform/msm8916/include/platform/gpio.h
+++ b/platform/msm8916/include/platform/gpio.h
@@ -70,4 +70,5 @@
uint8_t drvstr,
uint32_t enable);
void gpio_set_value(uint32_t gpio, uint32_t value);
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id);
#endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 1b2042a..1b02be6 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -93,6 +93,13 @@
#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
+
+/* I2C */
+#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)
+#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018)
+#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014)
+
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
diff --git a/platform/msm8916/include/platform/irqs.h b/platform/msm8916/include/platform/irqs.h
index 4211c77..d85dd9a 100644
--- a/platform/msm8916/include/platform/irqs.h
+++ b/platform/msm8916/include/platform/irqs.h
@@ -63,4 +63,6 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
NR_BOARD_IRQS)
+
+#define BLSP_QUP_IRQ(blsp_id, qup_id) (GIC_SPI_START + 95 + qup_id)
#endif /* __IRQS_MSM8916_H */
diff --git a/platform/msm8916/msm8916-clock.c b/platform/msm8916/msm8916-clock.c
index 267fa31..2f70737 100644
--- a/platform/msm8916/msm8916-clock.c
+++ b/platform/msm8916/msm8916-clock.c
@@ -141,6 +141,19 @@
},
};
+/* BLSP1_QUP2 Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_qup2_i2c_apps_clk_src[] =
+{
+ F( 96000, cxo, 10, 1, 2),
+ F( 4800000, cxo, 4, 0, 0),
+ F( 9600000, cxo, 2, 0, 0),
+ F( 16000000, gpll0, 10, 1, 5),
+ F( 19200000, gpll0, 1, 0, 0),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F_END
+};
+
static struct branch_clk gcc_sdcc1_apps_clk =
{
.cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
@@ -468,6 +481,30 @@
},
};
+
+static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP2_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP2_APPS_CBCR,
+ .parent = &gcc_blsp1_qup2_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
/* Clock lookup table */
static struct clk_lookup msm_clocks_8916[] =
{
@@ -494,6 +531,10 @@
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+
+ CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/msm_shared/i2c_qup.c b/platform/msm_shared/i2c_qup.c
index 4b525b6..916d865 100644
--- a/platform/msm_shared/i2c_qup.c
+++ b/platform/msm_shared/i2c_qup.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -222,7 +222,7 @@
{
unsigned retries = 0;
- dprintf(INFO, "Polling Status for state:0x%x\n", state);
+ dprintf(SPEW, "Polling Status for state:0x%x\n", state);
while (retries != 2000) {
unsigned status = readl(dev->qup_base + QUP_STATE);
@@ -241,9 +241,9 @@
qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val, unsigned addr, int rdwr)
{
if (rdwr)
- dprintf(INFO, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
+ dprintf(SPEW, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
else
- dprintf(INFO, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
+ dprintf(SPEW, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
}
#else
static inline void
@@ -501,7 +501,7 @@
dev->out_blk_sz * (2 << ((fifo_reg & 0x1C) >> 2));
dev->in_fifo_sz =
dev->in_blk_sz * (2 << ((fifo_reg & 0x380) >> 7));
- dprintf(INFO, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
+ dprintf(SPEW, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
dev->in_blk_sz, dev->in_fifo_sz, dev->out_blk_sz,
dev->out_fifo_sz);
}
@@ -613,7 +613,7 @@
ret = err;
goto out_err;
}
- dprintf(INFO, "idx:%d, rem:%d, num:%d, mode:%d\n",
+ dprintf(SPEW, "idx:%d, rem:%d, num:%d, mode:%d\n",
idx, rem, num, dev->mode);
qup_print_status(dev);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 85c4039..c4e4eae 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -182,7 +182,8 @@
$(LOCAL_DIR)/image_verify.o \
$(LOCAL_DIR)/crypto_hash.o \
$(LOCAL_DIR)/crypto5_eng.o \
- $(LOCAL_DIR)/crypto5_wrapper.o
+ $(LOCAL_DIR)/crypto5_wrapper.o \
+ $(LOCAL_DIR)/i2c_qup.o
endif
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 6abdeac..12a777c 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -363,6 +363,10 @@
APQ8039 = 241,
MSM8236 = 242,
MSM8636 = 243,
+ APQ8016 = 247,
+ MSM8216 = 248,
+ MSM8116 = 249,
+ MSM8616 = 250,
};
enum platform {
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index ccc5b8f..a8fc06b 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -317,11 +317,15 @@
switch(platform)
{
case MSM8916:
+ case MSM8116:
+ case MSM8216:
+ case MSM8616:
case MSM8939:
case MSM8236:
case MSM8636:
board->baseband = BASEBAND_MSM;
break;
+ case APQ8016:
case APQ8039:
case APQ8036:
board->baseband = BASEBAND_APQ;
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
old mode 100644
new mode 100755
index dbf1ed8..b548cf5
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -40,6 +40,8 @@
#include <platform/gpio.h>
#include <platform/iomap.h>
#include <target/display.h>
+#include <i2c_qup.h>
+#include <blsp_qup.h>
#include "include/panel.h"
#include "include/display_resource.h"
@@ -163,6 +165,50 @@
return 0;
}
+#define QRD_LCD_I2C_ADDRESS 0x3E
+#define QRD_LCD_VPOS_ADDRESS 0x00
+#define QRD_LCD_VNEG_ADDRESS 0x01
+#define QRD_LCD_DIS_ADDRESS 0x03
+#define QRD_LCD_CONTROL_ADDRESS 0xFF
+
+static struct qup_i2c_dev *i2c_dev;
+static int qrd_lcd_i2c_read(uint8_t addr)
+{
+ int ret = 0;
+ /* Create a i2c_msg buffer, that is used to put the controller into read
+ mode and then to read some data. */
+ struct i2c_msg msg_buf[] = {
+ {QRD_LCD_I2C_ADDRESS, I2C_M_WR, 1, &addr},
+ {QRD_LCD_I2C_ADDRESS, I2C_M_RD, 1, &ret}
+ };
+
+ ret = qup_i2c_xfer(i2c_dev, msg_buf, 2);
+ if(ret < 0) {
+ dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int qrd_lcd_i2c_write(uint8_t addr, uint8_t val)
+{
+ int ret = 0;
+ uint8_t data_buf[] = { addr, val };
+
+ /* Create a i2c_msg buffer, that is used to put the controller into write
+ mode and then to write some data. */
+ struct i2c_msg msg_buf[] = { {QRD_LCD_I2C_ADDRESS,
+ I2C_M_WR, 2, data_buf}
+ };
+
+ ret = qup_i2c_xfer(i2c_dev, msg_buf, 1);
+ if(ret < 0) {
+ dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
@@ -182,19 +228,45 @@
if (hw_id == HW_PLATFORM_QRD &&
hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) {
- /* for tps65132 ENP */
+ /* for tps65132 chip ENP */
gpio_tlmm_config(enp_gpio.pin_id, 0,
enp_gpio.pin_direction, enp_gpio.pin_pull,
enp_gpio.pin_strength,
enp_gpio.pin_state);
gpio_set_dir(enp_gpio.pin_id, 2);
- /* for tps65132 ENN */
+ /* for tps65132 chip ENN */
gpio_tlmm_config(enn_gpio.pin_id, 0,
enn_gpio.pin_direction, enn_gpio.pin_pull,
enn_gpio.pin_strength,
enn_gpio.pin_state);
gpio_set_dir(enn_gpio.pin_id, 2);
+
+ i2c_dev = qup_blsp_i2c_init(BLSP_ID_1, QUP_ID_1, 100000, 19200000);
+ if(!i2c_dev) {
+ dprintf(CRITICAL, "qup_blsp_i2c_init failed \n");
+ ASSERT(0);
+ }
+
+ ret = qrd_lcd_i2c_write(QRD_LCD_VPOS_ADDRESS, 0x0E); /* 5.4V */
+ if (ret) {
+ dprintf(CRITICAL, "VPOS Register: I2C Write failure\n");
+ }
+
+ ret = qrd_lcd_i2c_write(QRD_LCD_VNEG_ADDRESS, 0x0E); /* -5.4V */
+ if (ret) {
+ dprintf(CRITICAL, "VNEG Register: I2C write failure\n");
+ }
+
+ ret = qrd_lcd_i2c_write(QRD_LCD_DIS_ADDRESS, 0x0F);
+ if (ret) {
+ dprintf(CRITICAL, "Apps freq DIS Register: I2C write failure\n");
+ }
+
+ ret = qrd_lcd_i2c_write(QRD_LCD_CONTROL_ADDRESS, 0xF0);
+ if (ret) {
+ dprintf(CRITICAL, "Control Register: I2C write failure\n");
+ }
}
if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) {