arch: arm: Flush the cache after mmu tables are updated
Update the TTBCR bits with cache aatributes of mmu page tables memory.
MMU page table updates would not take affect if the page table mapping
and TTBCR bits for TTBR0 have different cache attributes. Make sure to
flush the page table memory after its updated and align the page table
address to cacheline
Change-Id: I864f7b97ec068d62203080c2bda2011b764d259c
diff --git a/arch/arm/mmu_lpae.c b/arch/arm/mmu_lpae.c
index ddf66fd..e4f9c27 100644
--- a/arch/arm/mmu_lpae.c
+++ b/arch/arm/mmu_lpae.c
@@ -31,10 +31,12 @@
#include <compiler.h>
#include <arch.h>
#include <arch/arm.h>
+#include <arch/ops.h>
#include <arch/defines.h>
#include <arch/arm/mmu.h>
#include <mmu.h>
#include <platform.h>
+#include <stdlib.h>
#if ARM_WITH_MMU
@@ -51,8 +53,8 @@
#define L2_PT_MASK 0xFFFFE00000
#define L2_INDEX_MASK 0x3FE00000
-uint64_t mmu_l1_pagetable[L1_PT_SZ] __attribute__ ((aligned(4096))); /* Max is 8 */
-uint64_t mmu_l2_pagetable[L2_PT_SZ*MMU_L2_PT_SIZE] __attribute__ ((aligned(4096))); /* Macro from target code * 512 */
+uint64_t mmu_l1_pagetable[ROUNDUP(L1_PT_SZ, CACHE_LINE)] __attribute__ ((aligned(4096))); /* Max is 8 */
+uint64_t mmu_l2_pagetable[ROUNDUP(L2_PT_SZ*MMU_L2_PT_SIZE, CACHE_LINE)] __attribute__ ((aligned(4096))); /* Macro from target code * 512 */
uint64_t avail_l2_pt = L2_PT_SZ;
uint64_t *empty_l2_pt = mmu_l2_pagetable;
@@ -101,6 +103,7 @@
/* Advance pointer to next empty l2 page table */
empty_l2_pt += MMU_L2_PT_SIZE;
avail_l2_pt--;
+ arch_clean_invalidate_cache_range((addr_t) mmu_l1_pagetable, L1_PT_SZ);
}
else
{
@@ -134,6 +137,7 @@
p_addr += SIZE_2MB;
arm_invalidate_tlb();
}
+ arch_clean_invalidate_cache_range((addr_t) mmu_l2_pagetable, (L2_PT_SZ*MMU_L2_PT_SIZE));
}
/************************************************************/
@@ -171,6 +175,7 @@
address_start++;
arm_invalidate_tlb();
}
+ arch_clean_invalidate_cache_range((addr_t) mmu_l1_pagetable, L1_PT_SZ);
}
void arm_mmu_map_entry(mmu_section_t *entry)
@@ -201,8 +206,8 @@
arm_write_mair0(MAIR0);
arm_write_mair1(MAIR1);
- /* TTBCR.EAE = 1 */
- arm_write_ttbcr(0x80000000);
+ /* TTBCR.EAE = 1 & IRGN0 [9:8], ORNG0 bits [11:10]: 01 */
+ arm_write_ttbcr(0x80000500);
/* Enable TRE */
arm_write_cr1(arm_read_cr1() | (1<<28));