commit c3311934214d77ce7ee0b8811af9a3f62f66bb3c
author Linux Build Service Account <lnxbuild@localhost> Sat May 30 16:23:15 2015 -0700
committer Gerrit - the friendly Code Review server <code-review@localhost> Sat May 30 16:23:15 2015 -0700
tree 992ddcfbfe2ba55b6fc9b666f96b1f966d223731
parent 162394dab0ad1b43c8d7f98cbc059393afaf8044
parent 9586be6b2c4513b227fe97d954db61e2c4c4a91c

Merge "target: msm8996: set the correct parent for DSI RCG clocks"

platform/msm8996/acpuclock.c

diff --git a/platform/msm8996/acpuclock.c b/platform/msm8996/acpuclock.c
index 63dd958..9b1a23b 100644
--- a/platform/msm8996/acpuclock.c
+++ b/platform/msm8996/acpuclock.c
@@ -495,18 +495,18 @@
 	clk_disable(clk_get("mmss_mmagic_axi_clk"));
 }
 
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags)
+void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags)
 {
 	int ret;
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
 		/* Enable DSI0 branch clocks */
 
-		writel(0x100, DSI_BYTE0_CFG_RCGR);
+		writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR);
 		writel(0x1, DSI_BYTE0_CMD_RCGR);
 		writel(0x1, DSI_BYTE0_CBCR);
 
-		writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+		writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
 		writel(0x1, DSI_PIXEL0_CMD_RCGR);
 		writel(0x1, DSI_PIXEL0_CBCR);
 
@@ -520,11 +520,11 @@
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
 		/* Enable DSI1 branch clocks */
-		writel(0x100, DSI_BYTE1_CFG_RCGR);
+		writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR);
 		writel(0x1, DSI_BYTE1_CMD_RCGR);
 		writel(0x1, DSI_BYTE1_CBCR);
 
-		writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+		writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
 		writel(0x1, DSI_PIXEL1_CMD_RCGR);
 		writel(0x1, DSI_PIXEL1_CBCR);
 

platform/msm8996/include/platform/clock.h

diff --git a/platform/msm8996/include/platform/clock.h b/platform/msm8996/include/platform/clock.h
index f740bd0..4ad790f 100644
--- a/platform/msm8996/include/platform/clock.h
+++ b/platform/msm8996/include/platform/clock.h
@@ -82,6 +82,7 @@
 #define DSI_PIXEL0_D                    REG_MM(0x2010)
 
 #define DSI0_PHY_PLL_OUT                BIT(8)
+#define DSI1_PHY_PLL_OUT                BIT(9)
 #define PIXEL_SRC_DIV_1_5               BIT(1)
 
 #define DSI_BYTE1_CMD_RCGR              REG_MM(0x2140)
@@ -112,7 +113,7 @@
 void clock_usb30_init(void);
 void clock_reset_usb_phy();
 
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi);
+void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t dual_dsi);
 void mmss_dsi_clock_disable(uint32_t dual_dsi);
 void mmss_bus_clock_enable(void);
 void mmss_bus_clock_disable(void);

target/msm8996/target_display.c

diff --git a/target/msm8996/target_display.c b/target/msm8996/target_display.c
index f9f3a5b..283720c 100644
--- a/target/msm8996/target_display.c
+++ b/target/msm8996/target_display.c
@@ -275,7 +275,7 @@
 
 int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
 {
-	uint32_t flags;
+	uint32_t flags, dsi_phy_pll_out;
 	uint32_t ret = NO_ERROR;
 	uint32_t board_version = board_soc_version();
 
@@ -311,7 +311,13 @@
 		dprintf(CRITICAL, "PLL failed to lock!\n");
 		goto clks_disable;
 	}
-	mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags);
+
+	if (pinfo->mipi.use_dsi1_pll)
+		dsi_phy_pll_out = DSI1_PHY_PLL_OUT;
+	else
+		dsi_phy_pll_out = DSI0_PHY_PLL_OUT;
+	mmss_dsi_clock_enable(dsi_phy_pll_out, flags);
+
 	return NO_ERROR;
 
 clks_disable: