msm_shared: gsbi cleanup
Clean up gsbi and gsbi based uart, i2c code.
Change-Id: I900d204c0a736aa6617d40646ed8a4dd70e78bcb
CRs-Fixed: 293016
diff --git a/platform/msm8960/acpuclock.c b/platform/msm8960/acpuclock.c
old mode 100755
new mode 100644
index f3484d5..b2e63bb
--- a/platform/msm8960/acpuclock.c
+++ b/platform/msm8960/acpuclock.c
@@ -29,17 +29,13 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
-
-/* NS/MD value for USB XCVR */
-#define MSM_BOOT_USB_XCVR_NS_VAL 0x00E400C3
-#define MSM_BOOT_USB_XCVR_MD_VAL 0x000500DF
+#include <platform/clock.h>
+#include <uart_dm.h>
+#include <gsbi.h>
/* Set rate and enable the clock */
-void clock_config(uint32_t ns,
- uint32_t md,
- uint32_t ns_addr,
- uint32_t md_addr)
+void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
{
unsigned int val = 0;
@@ -96,8 +92,45 @@
/* Setup USB AHB clock */
/* Setup XCVR clock */
- clock_config(MSM_BOOT_USB_XCVR_NS_VAL,
- MSM_BOOT_USB_XCVR_MD_VAL,
+ clock_config(USB_XCVR_CLK_NS,
+ USB_XCVR_CLK_MD,
USB_HS1_XCVR_FS_CLK_NS,
USB_HS1_XCVR_FS_CLK_MD);
}
+
+/* Configure UART clock - based on the gsbi id */
+void clock_config_uart_dm(uint8_t id)
+{
+ /* Enable gsbi_uart_clk */
+ clock_config(UART_DM_CLK_NS_115200,
+ UART_DM_CLK_MD_115200,
+ GSBIn_UART_APPS_NS(id),
+ GSBIn_UART_APPS_MD(id));
+
+
+ /* Enable gsbi_pclk */
+ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
+}
+
+/* Configure i2c clock */
+void clock_config_i2c(uint8_t id, uint32_t freq)
+{
+ uint32_t ns;
+ uint32_t md;
+
+ switch (freq)
+ {
+ case 24000000:
+ ns = I2C_CLK_NS_24MHz;
+ md = I2C_CLK_MD_24MHz;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id));
+
+ /* Enable the GSBI HCLK */
+ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
+}
+
diff --git a/platform/msm8960/gpio.c b/platform/msm8960/gpio.c
index 6a88915..b9aa637 100644
--- a/platform/msm8960/gpio.c
+++ b/platform/msm8960/gpio.c
@@ -29,7 +29,8 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
-#include <platform/gpio_hw.h>
+#include <platform/gpio.h>
+#include <gsbi.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
@@ -51,3 +52,22 @@
writel(dir, addr);
return;
}
+
+/* Configure gpio for uart - based on gsbi id */
+void gpio_config_uart_dm(uint8_t id)
+{
+ switch (id)
+ {
+ case GSBI_ID_5:
+ /* configure rx gpio */
+ gpio_tlmm_config(23, 1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(22, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
diff --git a/platform/msm8x60/include/platform/gpio_hw.h b/platform/msm8960/include/platform/clock.h
similarity index 62%
rename from platform/msm8x60/include/platform/gpio_hw.h
rename to platform/msm8960/include/platform/clock.h
index 97c2b17..3650340 100644
--- a/platform/msm8x60/include/platform/gpio_hw.h
+++ b/platform/msm8960/include/platform/clock.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/*
+ * * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -26,37 +27,27 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLATFORM_MSM8X60_GPIO_HW_H
-#define __PLATFORM_MSM8X60_GPIO_HW_H
+#ifndef __PLATFORM_MSM8960_CLOCK_H
+#define __PLATFORM_MSM8960_CLOCK_H
-#define TLMM_BASE_ADDR (0x800000)
-#define GPIO_CONFIG (0x1000)
-#define GPIO_IN_OUT (0x1004)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + GPIO_CONFIG + (x)*0x10)
-#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + GPIO_IN_OUT + (x)*0x10)
+/* GSBI/I2C QUP APPS CLK definitions */
+#define I2C_CLK_MD_24MHz 0x000100FB
+#define I2C_CLK_NS_24MHz 0x00FC005B
-/* GPIO TLMM: Direction */
-#define GPIO_INPUT 0
-#define GPIO_OUTPUT 1
+/* NS/MD value for USB XCVR */
+#define USB_XCVR_CLK_NS 0x00E400C3
+#define USB_XCVR_CLK_MD 0x000500DF
-/* GPIO TLMM: Pullup/Pulldown */
-#define GPIO_NO_PULL 0
-#define GPIO_PULL_DOWN 1
-#define GPIO_KEEPER 2
-#define GPIO_PULL_UP 3
+/* NS/MD value for UART */
+#define UART_DM_CLK_NS_115200 0xFFE40040
+#define UART_DM_CLK_MD_115200 0x0002FFE2
-/* GPIO TLMM: Drive Strength */
-#define GPIO_2MA 0
-#define GPIO_4MA 1
-#define GPIO_6MA 2
-#define GPIO_8MA 3
-#define GPIO_10MA 4
-#define GPIO_12MA 5
-#define GPIO_14MA 6
-#define GPIO_16MA 7
-/* GPIO TLMM: Status */
-#define GPIO_ENABLE 0
-#define GPIO_DISABLE 1
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+
+
+void hsusb_clock_init(void);
+void clock_config_uart_dm(uint8_t id);
+void clock_config_i2c(uint8_t id, uint32_t freq);
#endif
diff --git a/platform/msm8960/include/platform/gpio_hw.h b/platform/msm8960/include/platform/gpio.h
similarity index 87%
rename from platform/msm8960/include/platform/gpio_hw.h
rename to platform/msm8960/include/platform/gpio.h
index 5376069..178fde2 100644
--- a/platform/msm8960/include/platform/gpio_hw.h
+++ b/platform/msm8960/include/platform/gpio.h
@@ -26,15 +26,8 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLATFORM_MSM8960_GPIO_HW_H
-#define __PLATFORM_MSM8960_GPIO_HW_H
-
-#include <platform/iomap.h>
-
-#define GPIO_CONFIG (0x1000)
-#define GPIO_IN_OUT (0x1004)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + GPIO_CONFIG + (x)*0x10)
-#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + GPIO_IN_OUT + (x)*0x10)
+#ifndef __PLATFORM_MSM8960_GPIO_H
+#define __PLATFORM_MSM8960_GPIO_H
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
@@ -60,4 +53,7 @@
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
+void gpio_config_i2c(uint8_t gsbi_id);
+void gpio_config_uart_dm(uint8_t id);
+
#endif
diff --git a/platform/msm8960/include/platform/iomap.h b/platform/msm8960/include/platform/iomap.h
index 46ae235..864b950 100644
--- a/platform/msm8960/include/platform/iomap.h
+++ b/platform/msm8960/include/platform/iomap.h
@@ -35,22 +35,18 @@
#define MSM_SHARED_IMEM_BASE 0x2A03F000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define MSM_SHARED_BASE 0x80000000
#define MSM_TCSR_BASE 0x1A400000
#define MSM_GIC_DIST_BASE 0x02000000
#define MSM_TMR_BASE 0x0200A000
+#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
+
#define MSM_GIC_CPU_BASE 0x02002000
#define MSM_VIC_BASE 0x02080000
#define MSM_USB_BASE 0x12500000
-#define MSM_UART3_BASE 0xA9C00000
#define TLMM_BASE_ADDR 0x00800000
-#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
-#define MSM_CSR_BASE 0x02081000
-#define MSM_GCC_BASE 0x02082000
-#define MSM_ACC0_BASE 0x02041000
-#define MSM_ACC1_BASE 0x02051000
-
#define TCSR_WDOG_CFG 0x30
#define MSM_WDT0_RST (MSM_TMR_BASE + 0x38)
#define MSM_WDT0_EN (MSM_TMR_BASE + 0x40)
@@ -62,61 +58,14 @@
#define MSM_SDC3_BASE 0x12180000
#define MSM_SDC4_BASE 0x121C0000
-#define MSM_SHARED_BASE 0x80000000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
-#define GPIO_CFG133_ADDR 0x00801850
-#define GPIO_CFG135_ADDR 0x00801870
-#define GPIO_CFG136_ADDR 0x00801880
-#define GPIO_CFG137_ADDR 0x00801890
-#define GPIO_CFG138_ADDR 0x008018A0
-#define GPIO_CFG139_ADDR 0x008018B0
-#define GPIO_CFG140_ADDR 0x008018C0
-#define GPIO_CFG141_ADDR 0x008018D0
-#define GPIO_CFG142_ADDR 0x008018E0
-#define GPIO_CFG143_ADDR 0x008018F0
-#define GPIO_CFG144_ADDR 0x00801900
-#define GPIO_CFG145_ADDR 0x00801910
-#define GPIO_CFG146_ADDR 0x00801920
-#define GPIO_CFG147_ADDR 0x00801930
-#define GPIO_CFG148_ADDR 0x00801940
-#define GPIO_CFG149_ADDR 0x00801950
-#define GPIO_CFG150_ADDR 0x00801960
-#define GPIO_CFG151_ADDR 0x00801970
-#define GPIO_CFG152_ADDR 0x00801980
-#define GPIO_CFG153_ADDR 0x00801990
-#define GPIO_CFG154_ADDR 0x008019A0
-#define GPIO_CFG155_ADDR 0x008019B0
-#define GPIO_CFG156_ADDR 0x008019C0
-#define GPIO_CFG157_ADDR 0x008019D0
-#define GPIO_CFG158_ADDR 0x008019E0
+#define GSBI_BASE(id) ((id) <= 7 ? (0x16000000 + (((id)-1) << 20)) : \
+ (0x1A000000 + (((id)-8) << 20)))
+#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
+#define QUP_BASE(id) (GSBI_BASE(id) + 0x80000)
-#define GSBI1_BASE 0x16000000
-#define GSBI2_BASE 0x16100000
-#define GSBI3_BASE 0x16200000
-#define GSBI4_BASE 0x16300000
-#define GSBI5_BASE 0x16400000
-#define GSBI6_BASE 0x16500000
-#define GSBI7_BASE 0x16600000
-#define GSBI8_BASE 0x19800000
-#define GSBI9_BASE 0x19900000
-#define GSBI10_BASE 0x19A00000
-#define GSBI11_BASE 0x19B00000
-#define GSBI12_BASE 0x19C00000
-
-#define GSBI1_QUP_BASE (GSBI1_BASE + 0x80000)
-#define GSBI2_QUP_BASE (GSBI2_BASE + 0x80000)
-#define GSBI3_QUP_BASE (GSBI3_BASE + 0x80000)
-#define GSBI4_QUP_BASE (GSBI4_BASE + 0x80000)
-#define GSBI5_QUP_BASE (GSBI5_BASE + 0x80000)
-#define GSBI6_QUP_BASE (GSBI6_BASE + 0x80000)
-#define GSBI7_QUP_BASE (GSBI7_BASE + 0x80000)
-#define GSBI8_QUP_BASE (GSBI8_BASE + 0x80000)
-#define GSBI9_QUP_BASE (GSBI9_BASE + 0x80000)
-#define GSBI10_QUP_BASE (GSBI10_BASE + 0x80000)
-#define GSBI11_QUP_BASE (GSBI11_BASE + 0x80000)
-#define GSBI12_QUP_BASE (GSBI12_BASE + 0x80000)
-
-#define GSBI_CTL_PROTOCOL_CODE_I2C (0x20)
#define EBI2_CHIP_SELECT_CFG0 0x1A100000
#define EBI2_XMEM_CS3_CFG1 0x1A110034
@@ -129,8 +78,10 @@
#define USB_HS1_XCVR_FS_CLK_NS (CLK_CTL_BASE + 0x290C)
#define GSBIn_HCLK_CTL(n) (CLK_CTL_BASE + 0x29C0 + (32 * ((n) - 1)))
#define GSBIn_HCLK_FS(n) (CLK_CTL_BASE + 0x29C4 + (32 * ((n) - 1)))
-#define GSBIn_QUP_APPS_MD(n) (CLK_CTL_BASE + 0x29D0 + (32 * ((n) - 1)))
-#define GSBIn_QUP_APPS_NS(n) (CLK_CTL_BASE + 0x29D4 + (32 * ((n) - 1)))
+#define GSBIn_QUP_APPS_MD(n) (CLK_CTL_BASE + 0x29C8 + (32 * ((n) - 1)))
+#define GSBIn_QUP_APPS_NS(n) (CLK_CTL_BASE + 0x29CC + (32 * ((n) - 1)))
+#define GSBIn_UART_APPS_MD(n) (CLK_CTL_BASE + 0x29D0 + (32 * ((n) - 1)))
+#define GSBIn_UART_APPS_NS(n) (CLK_CTL_BASE + 0x29D4 + (32 * ((n) - 1)))
#define MSM_BOOT_PLL8_STATUS (CLK_CTL_BASE + 0x3158)
#define MSM_BOOT_PLL_ENABLE_SC0 (CLK_CTL_BASE + 0x34C0)
diff --git a/platform/msm8960/include/platform/irqs.h b/platform/msm8960/include/platform/irqs.h
index e118752..033d790 100644
--- a/platform/msm8960/include/platform/irqs.h
+++ b/platform/msm8960/include/platform/irqs.h
@@ -39,35 +39,16 @@
#define GIC_PPI_START 16
#define GIC_SPI_START 32
-#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
+#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
-#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
-#define USB1_HS_IRQ (GIC_SPI_START + 100)
-#define USB2_IRQ (GIC_SPI_START + 141)
-#define USB1_IRQ (GIC_SPI_START + 142)
-#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
-#define GSBI2_UART_IRQ (GIC_SPI_START + 148)
-#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
-#define GSBI3_UART_IRQ (GIC_SPI_START + 150)
-#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
-#define GSBI4_UART_IRQ (GIC_SPI_START + 152)
-#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
-#define GSBI5_UART_IRQ (GIC_SPI_START + 154)
-#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
-#define GSBI6_UART_IRQ (GIC_SPI_START + 156)
-#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
-#define GSBI7_UART_IRQ (GIC_SPI_START + 158)
-#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
-#define GSBI8_UART_IRQ (GIC_SPI_START + 160)
-#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
-#define GSBI9_UART_IRQ (GIC_SPI_START + 189)
-#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
-#define GSBI10_UART_IRQ (GIC_SPI_START + 191)
-#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
-#define GSBI11_UART_IRQ (GIC_SPI_START + 193)
-#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
-#define GSBI12_UART_IRQ (GIC_SPI_START + 195)
-#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
+#define USB1_HS_IRQ (GIC_SPI_START + 100)
+#define USB2_IRQ (GIC_SPI_START + 141)
+#define USB1_IRQ (GIC_SPI_START + 142)
+
+#define GSBI_QUP_IRQ(id) ((id) <= 8 ? (GIC_SPI_START + 145 + 2*((id))) : \
+ (GIC_SPI_START + 187 + 2*((id)-8)))
+
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/msm8960/platform.c b/platform/msm8960/platform.c
index 34d3af8..309b98e 100644
--- a/platform/msm8960/platform.c
+++ b/platform/msm8960/platform.c
@@ -31,15 +31,15 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
+#include <uart_dm.h>
-extern void uart_init(void);
extern void platform_init_timer(void);
extern void platform_init_interrupts(void);
void platform_early_init(void)
{
- uart_init();
+ uart_init(target_uart_gsbi());
platform_init_interrupts();
platform_init_timer();
}
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
old mode 100755
new mode 100644
index a1213cf..a2158fb
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,13 @@
#include <stdint.h>
#include <debug.h>
+#include <reg.h>
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <platform/clock.h>
#include <platform/scm-io.h>
-#include <reg.h>
+#include <uart_dm.h>
+#include <gsbi.h>
/* Read, modify, then write-back a register. */
static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask)
@@ -289,3 +291,42 @@
writel((1<<4), CE2_HCLK_CTL);
return;
}
+
+/* Configure UART clock - based on the gsbi id */
+void clock_config_uart_dm(uint8_t id)
+{
+ uint32_t ns = UART_DM_CLK_NS_115200;
+ uint32_t md = UART_DM_CLK_MD_115200;
+
+ /* Enable PLL8 */
+ pll8_enable();
+
+ /* Enable gsbi_uart_clk */
+ clock_config(ns, md, GSBIn_UART_APPS_NS(id), GSBIn_UART_APPS_MD(id));
+
+ /* Enable the GSBI HCLK */
+ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
+}
+
+/* Configure i2c clock */
+void clock_config_i2c(uint8_t id, uint32_t freq)
+{
+ uint32_t ns;
+ uint32_t md;
+
+ switch (freq)
+ {
+ case 24000000:
+ ns = I2C_CLK_NS_24MHz;
+ md = I2C_CLK_MD_24MHz;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id));
+
+ /* Enable the GSBI HCLK */
+ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
+}
+
diff --git a/platform/msm8x60/gpio.c b/platform/msm8x60/gpio.c
index 966bbeb..b57d893 100644
--- a/platform/msm8x60/gpio.c
+++ b/platform/msm8x60/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -29,9 +29,8 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
-#include <dev/gpio.h>
-
-#include <platform/gpio_hw.h>
+#include <platform/gpio.h>
+#include <gsbi.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
@@ -53,3 +52,38 @@
writel(dir, addr);
return;
}
+
+/* Configure gpio for uart - based on gsbi id */
+void gpio_config_uart_dm(uint8_t id)
+{
+ switch (id)
+ {
+ case GSBI_ID_12:
+ /* configure rx gpio */
+ gpio_tlmm_config(117, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ /* configure tx gpio */
+ gpio_tlmm_config(118, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
+/* Configure gpio for i2c - based on gsbi id */
+void gpio_config_i2c(uint8_t id)
+{
+ switch (id)
+ {
+ case GSBI_ID_8:
+ gpio_tlmm_config(64, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_2MA, GPIO_DISABLE);
+ gpio_tlmm_config(65, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_2MA, GPIO_DISABLE);
+ break;
+ default:
+ ASSERT(0);
+ }
+}
+
diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
index 59b42ca..1dab781 100644
--- a/platform/msm8x60/include/platform/clock.h
+++ b/platform/msm8x60/include/platform/clock.h
@@ -1,5 +1,5 @@
/*
- * * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -87,6 +87,16 @@
#define BB_PLL8_N_VAL_REG (MSM_CLK_CTL_BASE + 0x314C)
#define CE2_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2740)
+/* NS/MD value for UART */
+#define UART_DM_CLK_NS_115200 0xFD940043
+#define UART_DM_CLK_MD_115200 0x0006FD8E
+
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xEE
+
+/* GSBI/I2C QUP APPS CLK definitions */
+#define I2C_CLK_MD_24MHz 0x000100FB
+#define I2C_CLK_NS_24MHz 0x00FC005B
enum clk_sources {
PLL_0 = 0,
@@ -104,4 +114,8 @@
NUM_SRC
};
+void hsusb_clock_init(void);
+void clock_config_uart_dm(uint8_t id);
+void clock_config_i2c(uint8_t id, uint32_t freq);
+
#endif
diff --git a/platform/msm8960/include/platform/gpio_hw.h b/platform/msm8x60/include/platform/gpio.h
similarity index 86%
copy from platform/msm8960/include/platform/gpio_hw.h
copy to platform/msm8x60/include/platform/gpio.h
index 5376069..9465a12 100644
--- a/platform/msm8960/include/platform/gpio_hw.h
+++ b/platform/msm8x60/include/platform/gpio.h
@@ -26,15 +26,8 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLATFORM_MSM8960_GPIO_HW_H
-#define __PLATFORM_MSM8960_GPIO_HW_H
-
-#include <platform/iomap.h>
-
-#define GPIO_CONFIG (0x1000)
-#define GPIO_IN_OUT (0x1004)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + GPIO_CONFIG + (x)*0x10)
-#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + GPIO_IN_OUT + (x)*0x10)
+#ifndef __PLATFORM_MSM8X60_GPIO_H
+#define __PLATFORM_MSM8X60_GPIO_H
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
@@ -60,4 +53,7 @@
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
+void gpio_config_i2c(uint8_t gsbi_id);
+void gpio_config_uart_dm(uint8_t id);
+
#endif
diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index 9eb873c..882f9c1 100755
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -63,6 +63,10 @@
#define SURF_DEBUG_LED_ADDR 0x1D000202
+#define TLMM_BASE_ADDR 0x00800000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
#define GPIO_CFG133_ADDR 0x00801850
#define GPIO_CFG135_ADDR 0x00801870
#define GPIO_CFG136_ADDR 0x00801880
@@ -89,33 +93,11 @@
#define GPIO_CFG157_ADDR 0x008019D0
#define GPIO_CFG158_ADDR 0x008019E0
-#define GSBI1_BASE (0x16000000)
-#define GSBI2_BASE (0x16100000)
-#define GSBI3_BASE (0x16200000)
-#define GSBI4_BASE (0x16300000)
-#define GSBI5_BASE (0x16400000)
-#define GSBI6_BASE (0x16500000)
-#define GSBI7_BASE (0x16600000)
-#define GSBI8_BASE (0x19800000)
-#define GSBI9_BASE (0x19900000)
-#define GSBI10_BASE (0x19A00000)
-#define GSBI11_BASE (0x19B00000)
-#define GSBI12_BASE (0x19C00000)
+#define GSBI_BASE(id) ((id) <= 7 ? (0x16000000 + (((id)-1) << 20)) : \
+ (0x19800000 + (((id)-8) << 20)))
+#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
+#define QUP_BASE(id) (GSBI_BASE(id) + 0x80000)
-#define GSBI1_QUP_BASE (GSBI1_BASE + 0x80000)
-#define GSBI2_QUP_BASE (GSBI2_BASE + 0x80000)
-#define GSBI3_QUP_BASE (GSBI3_BASE + 0x80000)
-#define GSBI4_QUP_BASE (GSBI4_BASE + 0x80000)
-#define GSBI5_QUP_BASE (GSBI5_BASE + 0x80000)
-#define GSBI6_QUP_BASE (GSBI6_BASE + 0x80000)
-#define GSBI7_QUP_BASE (GSBI7_BASE + 0x80000)
-#define GSBI8_QUP_BASE (GSBI8_BASE + 0x80000)
-#define GSBI9_QUP_BASE (GSBI9_BASE + 0x80000)
-#define GSBI10_QUP_BASE (GSBI10_BASE + 0x80000)
-#define GSBI11_QUP_BASE (GSBI11_BASE + 0x80000)
-#define GSBI12_QUP_BASE (GSBI12_BASE + 0x80000)
-
-#define GSBI_CTL_PROTOCOL_CODE_I2C (0x20)
#define CLK_CTL_BASE 0x00900000
#define USB_HS1_HCLK_CTL (CLK_CTL_BASE + 0x2900)
@@ -125,8 +107,10 @@
#define MSM_BOOT_PLL8_STATUS (CLK_CTL_BASE + 0x3158)
#define GSBIn_HCLK_CTL(n) (CLK_CTL_BASE + 0x29C0 + (32 * ((n) - 1)))
#define GSBIn_HCLK_FS(n) (CLK_CTL_BASE + 0x29C4 + (32 * ((n) - 1)))
-#define GSBIn_QUP_APPS_MD(n) (CLK_CTL_BASE + 0x29D0 + (32 * ((n) - 1)))
-#define GSBIn_QUP_APPS_NS(n) (CLK_CTL_BASE + 0x29D4 + (32 * ((n) - 1)))
+#define GSBIn_QUP_APPS_MD(n) (CLK_CTL_BASE + 0x29C8 + (32 * ((n) - 1)))
+#define GSBIn_QUP_APPS_NS(n) (CLK_CTL_BASE + 0x29CC + (32 * ((n) - 1)))
+#define GSBIn_UART_APPS_MD(n) (CLK_CTL_BASE + 0x29D0 + (32 * ((n) - 1)))
+#define GSBIn_UART_APPS_NS(n) (CLK_CTL_BASE + 0x29D4 + (32 * ((n) - 1)))
/* Defines for the GPIO EXPANDER chip, SX1509QIULTRT */
#define GPIO_EXPANDER_REG_OPEN_DRAIN_A (0x0B)
diff --git a/platform/msm8x60/include/platform/irqs.h b/platform/msm8x60/include/platform/irqs.h
old mode 100755
new mode 100644
index 1c6a5c1..feb3bd8
--- a/platform/msm8x60/include/platform/irqs.h
+++ b/platform/msm8x60/include/platform/irqs.h
@@ -34,35 +34,15 @@
#define GIC_PPI_START 16
#define GIC_SPI_START 32
-#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
-#define USB1_HS_IRQ (GIC_SPI_START + 100)
-#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
-#define USB2_IRQ (GIC_SPI_START + 141)
-#define USB1_IRQ (GIC_SPI_START + 142)
-#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
-#define GSBI2_UART_IRQ (GIC_SPI_START + 148)
-#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
-#define GSBI3_UART_IRQ (GIC_SPI_START + 150)
-#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
-#define GSBI4_UART_IRQ (GIC_SPI_START + 152)
-#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
-#define GSBI5_UART_IRQ (GIC_SPI_START + 154)
-#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
-#define GSBI6_UART_IRQ (GIC_SPI_START + 156)
-#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
-#define GSBI7_UART_IRQ (GIC_SPI_START + 158)
-#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
-#define GSBI8_UART_IRQ (GIC_SPI_START + 160)
-#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
-#define GSBI9_UART_IRQ (GIC_SPI_START + 189)
-#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
-#define GSBI10_UART_IRQ (GIC_SPI_START + 191)
-#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
-#define GSBI11_UART_IRQ (GIC_SPI_START + 193)
-#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
-#define GSBI12_UART_IRQ (GIC_SPI_START + 195)
-#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
+#define USB1_HS_IRQ (GIC_SPI_START + 100)
+#define USB2_IRQ (GIC_SPI_START + 141)
+#define USB1_IRQ (GIC_SPI_START + 142)
+
+#define GSBI_QUP_IRQ(id) ((id) <= 8 ? (GIC_SPI_START + 145 + 2*(id)) : \
+ (GIC_SPI_START + 187 + 2*((id)-8)))
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
diff --git a/platform/msm8x60/panel.c b/platform/msm8x60/panel.c
index 0809661..0e78ed3 100644
--- a/platform/msm8x60/panel.c
+++ b/platform/msm8x60/panel.c
@@ -31,10 +31,11 @@
#include <kernel/thread.h>
#include <i2c_qup.h>
#include <platform/iomap.h>
-#include <platform/gpio_hw.h>
+#include <platform/gpio.h>
#include <platform/clock.h>
#include <platform/pmic.h>
#include <platform/pmic_pwm.h>
+#include <gsbi.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@@ -307,7 +308,7 @@
void board_lcd_enable(void)
{
int rc = -1;
- dev = qup_i2c_init(GSBI8_BASE, 100000, 24000000);
+ dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
/* Make sure dev is created and initialized properly */
if (!dev) {
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
index 61fe1d0..bfd8ed2 100755
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -38,6 +38,8 @@
#include <platform/debug.h>
#include <platform/iomap.h>
#include <i2c_qup.h>
+#include <gsbi.h>
+#include <uart_dm.h>
#define CONVERT_ENDIAN_U32(val) \
((((uint32_t)(val) & 0x000000FF) << 24) | \
@@ -63,7 +65,6 @@
void platform_init_timer();
void uart3_clock_init(void);
-void uart_init(void);
struct fbcon_config *lcdc_init(void);
@@ -75,7 +76,7 @@
void platform_early_init(void)
{
- uart_init();
+ uart_init(target_uart_gsbi());
platform_init_interrupts();
platform_init_timer();
}
@@ -138,7 +139,7 @@
{
uint32_t id = 0;
uint16_t offset = 0;
- dev = qup_i2c_init(GSBI8_BASE, 100000, 24000000);
+ dev = qup_i2c_init(GSBI_ID_8, 100000, 24000000);
if(!dev){
return id;
}
diff --git a/platform/msm_shared/i2c_qup.c b/platform/msm_shared/i2c_qup.c
index 84e529a..78e2269 100644
--- a/platform/msm_shared/i2c_qup.c
+++ b/platform/msm_shared/i2c_qup.c
@@ -36,10 +36,12 @@
#include <reg.h>
#include <kernel/thread.h>
+#include <gsbi.h>
#include <i2c_qup.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
-#include <platform/gpio_hw.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
static struct qup_i2c_dev *dev_addr = NULL;
@@ -122,42 +124,6 @@
QUP_STATUS_ERROR_FLAGS = 0x7C,
};
-void set_i2c_clk(struct qup_i2c_dev *dev)
-{
- uint32_t md = 0;
- uint32_t ns = 0;
-
- switch (dev->src_clk_freq) {
- case 24000000:
- ns = I2C_APPS_CLK_NS_24MHz;
- md = I2C_APPS_CLK_MD_24MHz;
- break;
- default:
- return;
- }
- /* Enable the GSBI8 HCLK */
- writel((GSBI8_HCLK_CTL_CLK_ENA << GSBI8_HCLK_CTL_S),
- GSBIn_HCLK_CTL(dev->gsbi_number));
- clock_config(ns,
- md,
- GSBIn_QUP_APPS_NS(dev->gsbi_number),
- GSBIn_QUP_APPS_MD(dev->gsbi_number));
-}
-
-void i2c_gpio_cfg(uint32_t base)
-{
- switch (base) {
- case GSBI8_BASE:
- gpio_tlmm_config(64, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_2MA, GPIO_DISABLE);
- gpio_tlmm_config(65, 1, GPIO_OUTPUT, GPIO_NO_PULL,
- GPIO_2MA, GPIO_DISABLE);
- break;
- default:
- break;
- }
-}
-
#ifdef DEBUG_QUP
static void qup_print_status(struct qup_i2c_dev *dev)
{
@@ -175,8 +141,6 @@
}
#endif
-void i2c_gpio_cfg(unsigned base);
-
static irqreturn_t qup_i2c_interrupt(void)
{
struct qup_i2c_dev *dev = dev_addr;
@@ -478,7 +442,7 @@
run I2C_MASTER_CORE at. */
if (dev->clk_state == 0) {
if (dev->clk_ctl == 0) {
- set_i2c_clk(dev);
+ clock_config_i2c(dev->gsbi_number, dev->src_clk_freq);
}
}
/* Initialize QUP registers during first transfer */
@@ -488,7 +452,7 @@
unsigned fifo_reg;
/* Configure the GSBI Protocol Code for i2c */
writel((GSBI_PROTOCOL_CODE_I2C <<
- GSBI_CTRL_REG_PROTOCOL_CODE_S), dev->gsbi_base);
+ GSBI_CTRL_REG_PROTOCOL_CODE_S), GSBI_CTRL_REG(dev->gsbi_base));
fs_div = ((dev->src_clk_freq / dev->clk_freq) / 2) - 3;
hs_div = 3;
@@ -677,97 +641,7 @@
return ret;
}
-static int set_gsbi_number(struct qup_i2c_dev *dev)
-{
- switch (dev->qup_base) {
- case GSBI1_QUP_BASE:
- dev->gsbi_number = 1;
- break;
- case GSBI2_QUP_BASE:
- dev->gsbi_number = 2;
- break;
- case GSBI3_QUP_BASE:
- dev->gsbi_number = 3;
- break;
- case GSBI4_QUP_BASE:
- dev->gsbi_number = 4;
- break;
- case GSBI5_QUP_BASE:
- dev->gsbi_number = 5;
- break;
- case GSBI6_QUP_BASE:
- dev->gsbi_number = 6;
- break;
- case GSBI7_QUP_BASE:
- dev->gsbi_number = 7;
- break;
- case GSBI8_QUP_BASE:
- dev->gsbi_number = 8;
- break;
- case GSBI9_QUP_BASE:
- dev->gsbi_number = 9;
- break;
- case GSBI10_QUP_BASE:
- dev->gsbi_number = 10;
- break;
- case GSBI11_QUP_BASE:
- dev->gsbi_number = 11;
- break;
- case GSBI12_QUP_BASE:
- dev->gsbi_number = 12;
- break;
- default:
- return 1;
- }
- return 0;
-}
-
-static int set_qup_irq(struct qup_i2c_dev *dev)
-{
- switch (dev->qup_base) {
- case GSBI1_QUP_BASE:
- dev->qup_irq = GSBI1_QUP_IRQ;
- break;
- case GSBI2_QUP_BASE:
- dev->qup_irq = GSBI2_QUP_IRQ;
- break;
- case GSBI3_QUP_BASE:
- dev->qup_irq = GSBI3_QUP_IRQ;
- break;
- case GSBI4_QUP_BASE:
- dev->qup_irq = GSBI4_QUP_IRQ;
- break;
- case GSBI5_QUP_BASE:
- dev->qup_irq = GSBI5_QUP_IRQ;
- break;
- case GSBI6_QUP_BASE:
- dev->qup_irq = GSBI6_QUP_IRQ;
- break;
- case GSBI7_QUP_BASE:
- dev->qup_irq = GSBI7_QUP_IRQ;
- break;
- case GSBI8_QUP_BASE:
- dev->qup_irq = GSBI8_QUP_IRQ;
- break;
- case GSBI9_QUP_BASE:
- dev->qup_irq = GSBI9_QUP_IRQ;
- break;
- case GSBI10_QUP_BASE:
- dev->qup_irq = GSBI10_QUP_IRQ;
- break;
- case GSBI11_QUP_BASE:
- dev->qup_irq = GSBI11_QUP_IRQ;
- break;
- case GSBI12_QUP_BASE:
- dev->qup_irq = GSBI12_QUP_IRQ;
- break;
- default:
- return 1;
- }
- return 0;
-}
-
-struct qup_i2c_dev *qup_i2c_init(unsigned base,
+struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id,
unsigned clk_freq, unsigned src_clk_freq)
{
struct qup_i2c_dev *dev;
@@ -781,20 +655,21 @@
}
dev = memset(dev, 0, sizeof(struct qup_i2c_dev));
+ /* Setup base addresses and irq based on gsbi_id */
+ dev->qup_irq = GSBI_QUP_IRQ(gsbi_id);
+ dev->qup_base = QUP_BASE(gsbi_id);
+ dev->gsbi_base = GSBI_BASE(gsbi_id);
+ dev->gsbi_number = gsbi_id;
+
/* This must be done for qup_i2c_interrupt to work. */
dev_addr = dev;
/* Initialize the GPIO for GSBIn as i2c */
- i2c_gpio_cfg(base);
+ gpio_config_i2c(dev->gsbi_number);
- /* Configure GSBIn in i2c mode */
- writel(GSBI_CTL_PROTOCOL_CODE_I2C, base);
-
- /* Set the base address for GSBIn QUP The reason we add 0x80000 is to make
- the GSBIn base address be the GSBIn QUP base address, which is what the
- i2c driver wants. */
- dev->gsbi_base = base;
- dev->qup_base = base + 0x80000;
+ /* Configure the GSBI Protocol Code for i2c */
+ writel((GSBI_PROTOCOL_CODE_I2C <<
+ GSBI_CTRL_REG_PROTOCOL_CODE_S), GSBI_CTRL_REG(dev->gsbi_base));
/* Set clk_freq and src_clk_freq for i2c. */
dev->clk_freq = clk_freq;
@@ -805,23 +680,6 @@
dev->one_bit_t = USEC_PER_SEC / dev->clk_freq;
dev->clk_ctl = 0;
- /* Set the IRQ number for GSBIn_BASE address */
- if (set_qup_irq(dev)) {
- dprintf(INFO,
- "Could not find a valid QUP IRQ value based on GSBIn_BASE: %d\n",
- base);
- dprintf(INFO, "Please double check the GSBIn_BASE address.\n");
- return NULL;
- }
-
- /* Set the GSBI number based on GSBIn_BASE address */
- if (set_gsbi_number(dev)) {
- dprintf(INFO, "Could not find a valid GSBI # based on GSBIn_BASE: %d\n",
- base);
- dprintf(INFO, "Please double check the GSBIn_BASE address.\n");
- return NULL;
- }
-
/* Register the GSBIn QUP IRQ */
register_int_handler(dev->qup_irq, qup_i2c_interrupt, 0);
diff --git a/platform/msm_shared/include/gsbi.h b/platform/msm_shared/include/gsbi.h
new file mode 100644
index 0000000..4a70265
--- /dev/null
+++ b/platform/msm_shared/include/gsbi.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __GSBI_H_
+#define __GSBI_H_
+
+#include <platform/iomap.h>
+
+/* GSBI Registers */
+#define GSBI_CTRL_REG(id) (GSBI_BASE(id) + 0x0)
+
+#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4
+#define GSBI_PROTOCOL_CODE_I2C 0x2
+#define GSBI_PROTOCOL_CODE_SPI 0x3
+#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4
+#define GSBI_PROTOCOL_CODE_I2C_UART 0x6
+
+#define GSBI_HCLK_CTL_S 4
+#define GSBI_HCLK_CTL_CLK_ENA 0x1
+
+enum {
+ GSBI_ID_1 = 1,
+ GSBI_ID_2,
+ GSBI_ID_3,
+ GSBI_ID_4,
+ GSBI_ID_5,
+ GSBI_ID_6,
+ GSBI_ID_7,
+ GSBI_ID_8,
+ GSBI_ID_9,
+ GSBI_ID_10,
+ GSBI_ID_11,
+ GSBI_ID_12,
+};
+
+#endif
+
diff --git a/platform/msm_shared/include/i2c_qup.h b/platform/msm_shared/include/i2c_qup.h
index 6925f44..b143768 100644
--- a/platform/msm_shared/include/i2c_qup.h
+++ b/platform/msm_shared/include/i2c_qup.h
@@ -105,7 +105,7 @@
};
/* Function Definitions */
-struct qup_i2c_dev *qup_i2c_init(unsigned base,
+struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id,
unsigned clk_freq, unsigned src_clk_freq);
int qup_i2c_deinit(struct qup_i2c_dev *dev);
int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num);
@@ -242,14 +242,4 @@
I2C_FUNC_SMBUS_I2C_BLOCK | \
I2C_FUNC_SMBUS_PEC)
-/* GSBI/I2C QUP APPS CLK definitions */
-#define I2C_APPS_CLK_MD_24MHz 0x000100FB
-#define I2C_APPS_CLK_NS_24MHz 0x00FC005B
-
-#define GSBI8_HCLK_CTL_S (4)
-#define GSBI8_HCLK_CTL_CLK_ENA (0x1)
-
-#define GSBI_CTRL_REG_PROTOCOL_CODE_S (4)
-#define GSBI_PROTOCOL_CODE_I2C (0x2)
-
#endif /* __I2C_QUP__ */
diff --git a/platform/msm_shared/include/uart_dm.h b/platform/msm_shared/include/uart_dm.h
old mode 100755
new mode 100644
index 2f95d56..a3d0a72
--- a/platform/msm_shared/include/uart_dm.h
+++ b/platform/msm_shared/include/uart_dm.h
@@ -68,65 +68,22 @@
(MSM_BOOT_UART_DM_SBL_1 << 2) | \
(MSM_BOOT_UART_DM_8_BPS << 4))
-/* Platform specific macros for GSBI, Clocks etc. */
-#ifdef PLATFORM_MSM8960
- #define MSM_BOOT_GSBI_BASE (GSBI5_BASE)
- #define MSM_BOOT_UART_DM_GSBI_HCLK_CTL GSBIn_HCLK_CTL(5)
- #define MSM_BOOT_UART_DM_APPS_MD GSBIn_QUP_APPS_MD(5)
- #define MSM_BOOT_UART_DM_APPS_NS GSBIn_QUP_APPS_NS(5)
- #define MSM_BOOT_UART_DM_NS_VAL 0xFFE40040
- #define MSM_BOOT_UART_DM_MD_VAL 0x0002FFE2
-
- #define MSM_BOOT_UART_DM_RX_TX_BIT_RATE 0xFF
-
- /* GPIO pins - 2 wire using UART2 */
- #define MSM_BOOT_UART_DM_RX_GPIO 23
- #define MSM_BOOT_UART_DM_TX_GPIO 22
- #define MSM_BOOT_UART_DM_RX_GPIO_FUNC 1
- #define MSM_BOOT_UART_DM_TX_GPIO_FUNC 1
-
-#elif PLATFORM_MSM8X60
- #define MSM_BOOT_GSBI_BASE (GSBI12_BASE)
- #define MSM_BOOT_UART_DM_GSBI_HCLK_CTL GSBIn_HCLK_CTL(12)
- #define MSM_BOOT_UART_DM_APPS_MD GSBIn_QUP_APPS_MD(12)
- #define MSM_BOOT_UART_DM_APPS_NS GSBIn_QUP_APPS_NS(12)
- #define MSM_BOOT_UART_DM_NS_VAL 0xFD940043
- #define MSM_BOOT_UART_DM_MD_VAL 0x0006FD8E
-
- /* CSR is used to further divide fundamental frequency.
- * Using EE we are dividing gsbi_uart_clk by 2 so as to get
- * 115.2k bit rate for fundamental frequency of 3.6864 MHz
- */
- #define MSM_BOOT_UART_DM_RX_TX_BIT_RATE 0xEE
-
- /* GPIO pins - 2 wire using UART2 */
- #define MSM_BOOT_UART_DM_RX_GPIO 117
- #define MSM_BOOT_UART_DM_TX_GPIO 118
- #define MSM_BOOT_UART_DM_RX_GPIO_FUNC 2
- #define MSM_BOOT_UART_DM_TX_GPIO_FUNC 2
-#else
- #error "UART GSBI needs to be defined for the platform"
-#endif
-
-
-#define MSM_BOOT_GSBI_CTRL_REG MSM_BOOT_GSBI_BASE
-#define MSM_BOOT_UART_DM_BASE (MSM_BOOT_GSBI_BASE+0x40000)
-#define MSM_BOOT_UART_DM_REG(offset) (MSM_BOOT_UART_DM_BASE + offset)
+/* UART_DM Registers */
/* UART Operational Mode Register */
-#define MSM_BOOT_UART_DM_MR1 MSM_BOOT_UART_DM_REG(0x0000)
-#define MSM_BOOT_UART_DM_MR2 MSM_BOOT_UART_DM_REG(0x0004)
+#define MSM_BOOT_UART_DM_MR1(id) (GSBI_UART_DM_BASE(id) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(id) (GSBI_UART_DM_BASE(id) + 0x04)
#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
/* UART Clock Selection Register */
-#define MSM_BOOT_UART_DM_CSR MSM_BOOT_UART_DM_REG(0x0008)
+#define MSM_BOOT_UART_DM_CSR(id) (GSBI_UART_DM_BASE(id) + 0x08)
/* UART DM TX FIFO Registers - 4 */
-#define MSM_BOOT_UART_DM_TF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
+#define MSM_BOOT_UART_DM_TF(id, x) (GSBI_UART_DM_BASE(id) + 0x70+(4*(x)))
/* UART Command Register */
-#define MSM_BOOT_UART_DM_CR MSM_BOOT_UART_DM_REG(0x0010)
+#define MSM_BOOT_UART_DM_CR(id) (GSBI_UART_DM_BASE(id) + 0x10)
#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
@@ -168,7 +125,7 @@
#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
/* UART Interrupt Mask Register */
-#define MSM_BOOT_UART_DM_IMR MSM_BOOT_UART_DM_REG(0x0014)
+#define MSM_BOOT_UART_DM_IMR(id) (GSBI_UART_DM_BASE(id) + 0x14)
#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
@@ -189,42 +146,42 @@
MSM_BOOT_UART_DM_RXSTALE)
/* UART Interrupt Programming Register */
-#define MSM_BOOT_UART_DM_IPR MSM_BOOT_UART_DM_REG(0x0018)
+#define MSM_BOOT_UART_DM_IPR(id) (GSBI_UART_DM_BASE(id) + 0x18)
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
/* UART Transmit/Receive FIFO Watermark Register */
-#define MSM_BOOT_UART_DM_TFWR MSM_BOOT_UART_DM_REG(0x001C)
+#define MSM_BOOT_UART_DM_TFWR(id) (GSBI_UART_DM_BASE(id) + 0x1C)
/* Interrupt is generated when FIFO level is less than or equal to this value */
#define MSM_BOOT_UART_DM_TFW_VALUE 0
-#define MSM_BOOT_UART_DM_RFWR MSM_BOOT_UART_DM_REG(0x0020)
+#define MSM_BOOT_UART_DM_RFWR(id) (GSBI_UART_DM_BASE(id) + 0x20)
/*Interrupt generated when no of words in RX FIFO is greater than this value */
#define MSM_BOOT_UART_DM_RFW_VALUE 0
/* UART Hunt Character Register */
-#define MSM_BOOT_UART_DM_HCR MSM_BOOT_UART_DM_REG(0x0024)
+#define MSM_BOOT_UART_DM_HCR(id) (GSBI_UART_DM_BASE(id) + 0x24)
/* Used for RX transfer initialization */
-#define MSM_BOOT_UART_DM_DMRX MSM_BOOT_UART_DM_REG(0x0034)
+#define MSM_BOOT_UART_DM_DMRX(id) (GSBI_UART_DM_BASE(id) + 0x34)
/* Default DMRX value - any value bigger than FIFO size would be fine */
-#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
/* Register to enable IRDA function */
-#define MSM_BOOT_UART_DM_IRDA MSM_BOOT_UART_DM_REG(0x0038)
+#define MSM_BOOT_UART_DM_IRDA(id) (GSBI_UART_DM_BASE(id) + 0x38)
/* UART Data Mover Enable Register */
-#define MSM_BOOT_UART_DM_DMEN MSM_BOOT_UART_DM_REG(0x003C)
+#define MSM_BOOT_UART_DM_DMEN(id) (GSBI_UART_DM_BASE(id) + 0x3C)
/* Number of characters for Transmission */
-#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX MSM_BOOT_UART_DM_REG(0x0040)
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id) (GSBI_UART_DM_BASE(id) + 0x040)
/* UART RX FIFO Base Address */
-#define MSM_BOOT_UART_DM_BADR MSM_BOOT_UART_DM_REG(0x0044)
+#define MSM_BOOT_UART_DM_BADR(id) (GSBI_UART_DM_BASE(id) + 0x44)
/* UART Status Register */
-#define MSM_BOOT_UART_DM_SR MSM_BOOT_UART_DM_REG(0x0008)
+#define MSM_BOOT_UART_DM_SR(id) (GSBI_UART_DM_BASE(id) + 0x008)
#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
@@ -236,26 +193,26 @@
#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
/* UART Receive FIFO Registers - 4 in numbers */
-#define MSM_BOOT_UART_DM_RF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
+#define MSM_BOOT_UART_DM_RF(id, x) (GSBI_UART_DM_BASE(id) + 0x70 + (4*(x)))
/* UART Masked Interrupt Status Register */
-#define MSM_BOOT_UART_DM_MISR MSM_BOOT_UART_DM_REG(0x0010)
+#define MSM_BOOT_UART_DM_MISR(id) (GSBI_UART_DM_BASE(id) + 0x10)
/* UART Interrupt Status Register */
-#define MSM_BOOT_UART_DM_ISR MSM_BOOT_UART_DM_REG(0x0014)
+#define MSM_BOOT_UART_DM_ISR(id) (GSBI_UART_DM_BASE(id) + 0x14)
/* Number of characters received since the end of last RX transfer */
-#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP MSM_BOOT_UART_DM_REG(0x0038)
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id) (GSBI_UART_DM_BASE(id) + 0x38)
/* UART TX FIFO Status Register */
-#define MSM_BOOT_UART_DM_TXFS MSM_BOOT_UART_DM_REG(0x004C)
+#define MSM_BOOT_UART_DM_TXFS(id) (GSBI_UART_DM_BASE(id) + 0x4C)
#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
/* UART RX FIFO Status Register */
-#define MSM_BOOT_UART_DM_RXFS MSM_BOOT_UART_DM_REG(0x0050)
+#define MSM_BOOT_UART_DM_RXFS(id) (GSBI_UART_DM_BASE(id) + 0x50)
#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
@@ -271,4 +228,5 @@
#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
+void uart_init(uint8_t gsbi_id);
#endif /* __UART_DM_H__*/
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
old mode 100755
new mode 100644
index 16889a6..6fbe0d9
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -30,13 +30,14 @@
#include <stdlib.h>
#include <debug.h>
#include <reg.h>
+#include <sys/types.h>
#include <platform/iomap.h>
#include <platform/irqs.h>
#include <platform/interrupts.h>
-#include <platform/gpio_hw.h>
-#include <dev/uart.h>
-#include "uart_dm.h"
-
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <uart_dm.h>
+#include <gsbi.h>
#ifndef NULL
#define NULL 0
@@ -67,30 +68,27 @@
/* Static Function Prototype Declarations */
-static unsigned int msm_boot_uart_config_gpios(void);
-static unsigned int msm_boot_uart_dm_config_clock(void);
-static unsigned int msm_boot_uart_dm_gsbi_init(void);
+static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id);
static unsigned int msm_boot_uart_replace_lr_with_cr(char* data_in,
int num_of_chars,
char *data_out,
int *num_of_chars_out);
-static unsigned int msm_boot_uart_dm_init(void);
-static unsigned int msm_boot_uart_dm_read(unsigned int* data,
+static unsigned int msm_boot_uart_dm_init(uint8_t id);
+static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int* data,
int wait);
-static unsigned int msm_boot_uart_dm_write(char* data,
+static unsigned int msm_boot_uart_dm_write(uint8_t id, char* data,
unsigned int num_of_chars);
-static unsigned int msm_boot_uart_dm_init_rx_transfer(void);
-static unsigned int msm_boot_uart_dm_reset(void);
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id);
+static unsigned int msm_boot_uart_dm_reset(uint8_t id);
+/* TODO: Detele the patch that adds this to sys/types.h gets merged */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* Keep track of gsbi vs port mapping.
+ */
+static uint8_t gsbi_lookup[4];
/* Extern functions */
-void clock_config(unsigned int ns, unsigned int md,
- unsigned int ns_addr, unsigned int md_addr);
-
-void gpio_tlmm_config(uint32_t gpio, uint8_t func,
- uint8_t dir, uint8_t pull,
- uint8_t drvstr, uint32_t enable );
-
void udelay(unsigned usecs);
@@ -126,70 +124,30 @@
return MSM_BOOT_UART_DM_E_SUCCESS;
}
-
-static unsigned int msm_boot_uart_dm_config_gpios(void)
-{
- /* GPIO Pin: MSM_BOOT_UART_DM_RX_GPIO
- Function: MSM_BOOT_UART_DM_RX_GPIO_FUNC
- Direction: IN
- Pull: No PULL
- Drive Strength: 8 ma
- Output Enable: Disable
- */
- gpio_tlmm_config(MSM_BOOT_UART_DM_RX_GPIO, MSM_BOOT_UART_DM_RX_GPIO_FUNC,
- GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
-
- /* GPIO Pin: MSM_BOOT_UART_DM_TX_GPIO
- Function: MSM_BOOT_UART_DM_TX_GPIO_FUNC
- Direction: OUT
- Pull: No PULL
- Drive Strength: 8 ma
- Output Enable: Disable
- */
- gpio_tlmm_config(MSM_BOOT_UART_DM_TX_GPIO, MSM_BOOT_UART_DM_TX_GPIO_FUNC,
- GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-
-
-static unsigned int msm_boot_uart_dm_config_clock(void)
-{
- uart_clock_init();
-
- /* Enable gsbi_uart_clk */
- clock_config(MSM_BOOT_UART_DM_NS_VAL,
- MSM_BOOT_UART_DM_MD_VAL,
- MSM_BOOT_UART_DM_APPS_NS,
- MSM_BOOT_UART_DM_APPS_MD);
-
- /* Enable gsbi_pclk */
- writel(0x10, MSM_BOOT_UART_DM_GSBI_HCLK_CTL);
-
- return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-
-
/*
* Initialize and configure GSBI for operation
*/
-static unsigned int msm_boot_uart_dm_gsbi_init(void)
+static unsigned int msm_boot_uart_dm_gsbi_init(uint8_t id)
{
- /* Configure the clock block */
- msm_boot_uart_dm_config_clock();
+ /* Configure the uart clock */
+ clock_config_uart_dm(id);
- /* Configure TLMM/GPIO to provide connectivity between GSBI
+ /* Configure GPIO to provide connectivity between GSBI
product ports and chip pads */
- msm_boot_uart_dm_config_gpios();
-
+ gpio_config_uart_dm(id);
/* Configure Data Mover for GSBI operation.
* Currently not supported. */
/* Configure GSBI for UART_DM protocol.
* I2C on 2 ports, UART (without HS flow control) on the other 2. */
- writel(0x60, MSM_BOOT_GSBI_CTRL_REG);
+ writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,
+ GSBI_CTRL_REG(id));
+
+ /* Configure clock selection register for tx and rx rates.
+ * Selecting 115.2k for both RX and TX.
+ */
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -197,13 +155,13 @@
/*
* Reset the UART
*/
-static unsigned int msm_boot_uart_dm_reset(void)
+static unsigned int msm_boot_uart_dm_reset(uint8_t id)
{
- writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -212,47 +170,42 @@
/*
* Initialize UART_DM - configure clock and required registers.
*/
-static unsigned int msm_boot_uart_dm_init(void)
+static unsigned int msm_boot_uart_dm_init(uint8_t id)
{
- /* Configure GSB12 for uart dm */
- msm_boot_uart_dm_gsbi_init();
-
-
- /* Configure clock selection register for tx and rx rates.
- * Selecting 115.2k for both RX and TX */
- writel(MSM_BOOT_UART_DM_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR);
+ /* Configure GSBI for uart dm */
+ msm_boot_uart_dm_gsbi_init(id);
/* Configure UART mode registers MR1 and MR2 */
/* Hardware flow control isn't supported */
- writel(0x0, MSM_BOOT_UART_DM_MR1);
+ writel(0x0, MSM_BOOT_UART_DM_MR1(id));
/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
- writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2);
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(id));
/* Configure Interrupt Mask register IMR */
- writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR);
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(id));
/* Configure Tx and Rx watermarks configuration registers */
/* TX watermark value is set to 0 - interrupt is generated when
* FIFO level is less than or equal to 0 */
- writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR);
+ writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(id));
/* RX watermark value*/
- writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR);
+ writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(id));
/* Configure Interrupt Programming Register*/
/* Set initial Stale timeout value*/
- writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR);
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR(id));
/* Configure IRDA if required */
/* Disabling IRDA mode */
- writel(0x0, MSM_BOOT_UART_DM_IRDA);
+ writel(0x0, MSM_BOOT_UART_DM_IRDA(id));
/* Configure and enable sim interface if required */
/* Configure hunt character value in HCR register */
/* Keep it in reset state */
- writel(0x0, MSM_BOOT_UART_DM_HCR);
+ writel(0x0, MSM_BOOT_UART_DM_HCR(id));
/* Configure Rx FIFO base address */
/* Both TX/RX shares same SRAM and default is half-n-half.
@@ -261,19 +214,19 @@
* We have found RAM_ADDR_WIDTH = 0x7f */
/* Issue soft reset command */
- msm_boot_uart_dm_reset();
+ msm_boot_uart_dm_reset(id);
/* Enable/Disable Rx/Tx DM interfaces */
/* Data Mover not currently utilized. */
- writel(0x0, MSM_BOOT_UART_DM_DMEN);
+ writel(0x0, MSM_BOOT_UART_DM_DMEN(id));
/* Enable transmitter and receiver */
- writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR(id));
/* Initialize Receive Path */
- msm_boot_uart_dm_init_rx_transfer();
+ msm_boot_uart_dm_init_rx_transfer(id);
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -282,12 +235,12 @@
/*
* Initialize Receive Path
*/
-static unsigned int msm_boot_uart_dm_init_rx_transfer(void)
+static unsigned int msm_boot_uart_dm_init_rx_transfer(uint8_t id)
{
- writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
- writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX);
- writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX(id));
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR(id));
return MSM_BOOT_UART_DM_E_SUCCESS;
}
@@ -296,7 +249,7 @@
* UART Receive operation
* Reads a word from the RX FIFO.
*/
-static unsigned int msm_boot_uart_dm_read(unsigned int* data, int wait)
+static unsigned int msm_boot_uart_dm_read(uint8_t id, unsigned int* data, int wait)
{
static int rx_last_snap_count = 0;
static int rx_chars_read_since_last_xfer = 0;
@@ -306,10 +259,8 @@
return MSM_BOOT_UART_DM_E_INVAL;
}
-
-
/* We will be polling RXRDY status bit */
- while (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_RXRDY))
+ while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_RXRDY))
{
/* if this is not a blocking call, we'll just return */
if (!wait)
@@ -319,13 +270,13 @@
}
/* Check for Overrun error. We'll just reset Error Status */
- if (readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_UART_OVERRUN)
+ if (readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_UART_OVERRUN)
{
- writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(id));
}
/* RX FIFO is ready; read a word. */
- *data = readl(MSM_BOOT_UART_DM_RF(0));
+ *data = readl(MSM_BOOT_UART_DM_RF(id, 0));
/* increment the total count of chars we've read so far */
rx_chars_read_since_last_xfer += 4;
@@ -340,15 +291,15 @@
if (rx_last_snap_count == 0)
{
/* Check if we've received stale event */
- if (readl(MSM_BOOT_UART_DM_MISR) & MSM_BOOT_UART_DM_RXSTALE)
+ if (readl(MSM_BOOT_UART_DM_MISR(id)) & MSM_BOOT_UART_DM_RXSTALE)
{
/* Send command to reset stale interrupt */
- writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(id));
}
/* Check if we haven't read more than DMRX value */
else if ((unsigned int)rx_chars_read_since_last_xfer <
- readl(MSM_BOOT_UART_DM_DMRX))
+ readl(MSM_BOOT_UART_DM_DMRX(id)))
{
/* We can still continue reading before initializing RX transfer */
return MSM_BOOT_UART_DM_E_SUCCESS;
@@ -358,7 +309,7 @@
/* Read UART_DM_RX_TOTAL_SNAP register to know how many valid chars
* we've read so far since last transfer */
- rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP);
+ rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(id));
}
@@ -369,18 +320,17 @@
return MSM_BOOT_UART_DM_E_SUCCESS;
}
- msm_boot_uart_dm_init_rx_transfer();
+ msm_boot_uart_dm_init_rx_transfer(id);
rx_last_snap_count = 0;
rx_chars_read_since_last_xfer = 0;
return MSM_BOOT_UART_DM_E_SUCCESS;
}
-
/*
* UART transmit operation
*/
-static unsigned int msm_boot_uart_dm_write(char* data,
+static unsigned int msm_boot_uart_dm_write(uint8_t id, char* data,
unsigned int num_of_chars)
{
unsigned int tx_word_count = 0;
@@ -409,9 +359,9 @@
/* Check if transmit FIFO is empty.
* If not we'll wait for TX_READY interrupt. */
- if (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_TXEMT))
+ if (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXEMT))
{
- while (!(readl(MSM_BOOT_UART_DM_ISR) & MSM_BOOT_UART_DM_TX_READY))
+ while (!(readl(MSM_BOOT_UART_DM_ISR(id)) & MSM_BOOT_UART_DM_TX_READY))
{
udelay(1);
/* Kick watchdog? */
@@ -420,10 +370,10 @@
/* We are here. FIFO is ready to be written. */
/* Write number of characters to be written */
- writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX);
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(id));
/* Clear TX_READY interrupt */
- writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(id));
/* We use four-character word FIFO. So we need to divide data into
* four characters and write in UART_DM_TF register */
@@ -437,13 +387,13 @@
PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
/* Wait till TX FIFO has space */
- while (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_TXRDY))
+ while (!(readl(MSM_BOOT_UART_DM_SR(id)) & MSM_BOOT_UART_DM_SR_TXRDY))
{
udelay(1);
}
/* TX FIFO has space. Write the chars */
- writel(tx_word, MSM_BOOT_UART_DM_TF(0));
+ writel(tx_word, MSM_BOOT_UART_DM_TF(id, 0));
tx_char_left = num_of_chars - (i+1)*4;
tx_data = tx_data + 4;
}
@@ -451,20 +401,23 @@
return MSM_BOOT_UART_DM_E_SUCCESS;
}
-
/* Defining functions that's exposed to outside world and in coformance to
* existing uart implemention. These functions are being called to initialize
- * UART and print debug messages in bootloader. */
-
-void uart_init(void)
+ * UART and print debug messages in bootloader.
+ */
+void uart_init(uint8_t gsbi_id)
{
+ static uint8_t port = 0;
char *data = "Android Bootloader - UART_DM Initialized!!!\n";
- msm_boot_uart_dm_init();
- msm_boot_uart_dm_write(data, 44);
+ msm_boot_uart_dm_init(gsbi_id);
+ msm_boot_uart_dm_write(gsbi_id, data, 44);
+ ASSERT(port < ARRAY_SIZE(gsbi_lookup));
+ gsbi_lookup[port++] = gsbi_id;
}
+
/* UART_DM uses four character word FIFO where as UART core
* uses a character FIFO. so it's really inefficient to try
* to write single character. But that's how dprintf has been
@@ -472,8 +425,9 @@
*/
int uart_putc(int port, char c)
{
+ uint8_t gsbi_id = gsbi_lookup[port];
- msm_boot_uart_dm_write(&c, 1);
+ msm_boot_uart_dm_write(gsbi_id, &c, 1);
return 0;
}
@@ -486,12 +440,14 @@
{
int byte;
static unsigned int word = 0;
+ uint8_t gsbi_id = gsbi_lookup[port];
if (!word)
{
/* Read from FIFO only if it's a first read or all the four
* characters out of a word have been read */
- if (msm_boot_uart_dm_read( &word, wait) != MSM_BOOT_UART_DM_E_SUCCESS)
+ if (msm_boot_uart_dm_read(gsbi_id, &word, wait) !=
+ MSM_BOOT_UART_DM_E_SUCCESS)
{
return -1;
}
diff --git a/target/msm8660_surf/init.c b/target/msm8660_surf/init.c
index c51a260..3ef3e36 100644
--- a/target/msm8660_surf/init.c
+++ b/target/msm8660_surf/init.c
@@ -39,19 +39,22 @@
#include <mmc.h>
#include <platform/timer.h>
#include <platform/iomap.h>
-#include <platform/gpio_hw.h>
+#include <platform/gpio.h>
#include <baseband.h>
#include <reg.h>
#include <platform.h>
+#include <gsbi.h>
-#define LINUX_MACHTYPE_8660_SURF 2755
-#define LINUX_MACHTYPE_8660_FFA 3017
-#define LINUX_MACHTYPE_8660_FLUID 3124
-#define LINUX_MACHTYPE_8660_QT 3298
+#define LINUX_MACHTYPE_8660_SURF 2755
+#define LINUX_MACHTYPE_8660_FFA 3017
+#define LINUX_MACHTYPE_8660_FLUID 3124
+#define LINUX_MACHTYPE_8660_QT 3298
#define LINUX_MACHTYPE_8660_CHARM_SURF 3181
#define LINUX_MACHTYPE_8660_CHARM_FFA 3199
#define LINUX_MACHTYPE_8x60_DRAGON 3586
+static const uint8_t uart_gsbi_id = GSBI_ID_12;
+
void keypad_init(void);
static int emmc_boot = -1; /* set to uninitialized */
@@ -412,3 +415,8 @@
return;
}
+
+uint8_t target_uart_gsbi(void)
+{
+ return uart_gsbi_id;
+}
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index db569ab..fb218b6 100644
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -40,6 +40,7 @@
#include <dev/keys.h>
#include <dev/pm8921.h>
#include <dev/gpio_keypad.h>
+#include <gsbi.h>
#define LINUX_MACHTYPE_8960_SIM 3230
#define LINUX_MACHTYPE_8960_RUMI3 3231
@@ -55,6 +56,8 @@
static pm8921_dev_t pmic;
+static const uint8_t uart_gsbi_id = GSBI_ID_5;
+
void target_init(void)
{
unsigned base_addr;
@@ -191,3 +194,8 @@
/* Set the BOOT_DONE flag in PM8921 */
pm8921_boot_done();
}
+
+uint8_t target_uart_gsbi(void)
+{
+ return uart_gsbi_id;
+}