Merge "target/platform: msm8994: Update frequency tables"
diff --git a/AndroidBoot.mk b/AndroidBoot.mk
index b3dbf12..6ddf49d 100644
--- a/AndroidBoot.mk
+++ b/AndroidBoot.mk
@@ -1,5 +1,7 @@
#Android makefile to build lk bootloader as a part of Android Build
+CROSS_COMPILE := ../../../prebuilts/gcc/linux-x86/arm/arm-eabi-$(TARGET_GCC_VERSION)/bin/arm-eabi-
+
# Set flags if we need to include security libs
ifeq ($(TARGET_BOOTIMG_SIGNED),true)
SIGNED_KERNEL := SIGNED_KERNEL=1
@@ -23,7 +25,7 @@
# ELF binary for ABOOT
TARGET_ABOOT_ELF := $(PRODUCT_OUT)/aboot.elf
$(TARGET_ABOOT_ELF): ABOOT_CLEAN | $(ABOOT_OUT)
- $(MAKE) -C bootable/bootloader/lk BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(ABOOT_OUT) $(BOOTLOADER_PLATFORM) $(EMMC_BOOT) $(SIGNED_KERNEL)
# NAND variant output
TARGET_NAND_BOOTLOADER := $(PRODUCT_OUT)/appsboot.mbn
@@ -48,11 +50,11 @@
# Top level for NAND variant targets
$(TARGET_NAND_BOOTLOADER): appsbootldr_clean | $(NAND_BOOTLOADER_OUT)
- $(MAKE) -C bootable/bootloader/lk BOOTLOADER_OUT=../../../$(NAND_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) $(SIGNED_KERNEL)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(NAND_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) $(SIGNED_KERNEL)
# Top level for eMMC variant targets
$(TARGET_EMMC_BOOTLOADER): emmc_appsbootldr_clean | $(EMMC_BOOTLOADER_OUT)
- $(MAKE) -C bootable/bootloader/lk BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL)
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(EMMC_BOOTLOADER_OUT) $(BOOTLOADER_PLATFORM) EMMC_BOOT=1 $(SIGNED_KERNEL)
# Keep build NAND & eMMC as default for targets still using TARGET_BOOTLOADER
TARGET_BOOTLOADER := $(PRODUCT_OUT)/EMMCBOOT.MBN
@@ -73,4 +75,4 @@
$(TARGET_NANDWRITE): nandwrite_clean | $(NANDWRITE_OUT)
@echo $(BOOTLOADER_PLATFORM)_nandwrite
- $(MAKE) -C bootable/bootloader/lk BOOTLOADER_OUT=../../../$(NANDWRITE_OUT) $(BOOTLOADER_PLATFORM)_nandwrite BUILD_NANDWRITE=1
+ $(MAKE) -C bootable/bootloader/lk TOOLCHAIN_PREFIX=$(CROSS_COMPILE) BOOTLOADER_OUT=../../../$(NANDWRITE_OUT) $(BOOTLOADER_PLATFORM)_nandwrite BUILD_NANDWRITE=1
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index c30af8a..08d3e3b 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -213,21 +213,6 @@
#define BOOT_CONFIG_OFFSET 0x00006034
#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
-/* mdss */
-#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
-
-#define MIPI_DSI_BASE (0xFD922800)
-#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
-#define MIPI_DSI1_BASE (0xFD922E00)
-#define DSI0_PHY_BASE (0xFD922B00)
-#define DSI1_PHY_BASE (0xFD923100)
-#define DSI0_PLL_BASE (0xFD922A00)
-#define DSI1_PLL_BASE (0xFD923000)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-
-#define MDP_BASE (0xfd900000)
-#define REG_MDP(off) (MDP_BASE + (off))
-
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
#define TRIG_CTRL 0x084
@@ -251,6 +236,18 @@
#define VIDEO_MODE_VSYNC 0x034
#define VIDEO_MODE_VSYNC_VPOS 0x038
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
+#define MIPI_DSI_BASE (0xFD922800)
+#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE (0xFD922E00)
+#define DSI0_PHY_BASE (0xFD922B00)
+#define DSI1_PHY_BASE (0xFD923100)
+#define DSI0_PLL_BASE (0xFD922A00)
+#define DSI1_PLL_BASE (0xFD923000)
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define MDP_BASE (0xfd900000)
+#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x2200)
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index d7e5094..4429c0a 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -179,6 +179,14 @@
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x1E00)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2200)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x2A00)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x2E00)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3200)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3600)
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 681072a..b8c2af4 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -144,15 +144,17 @@
#define DSI0_PLL_BASE (0x1A98300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-
#define MDP_BASE (0x1A00000)
#define REG_MDP(off) (MDP_BASE + (off))
-
#define MDP_HW_REV REG_MDP(0x1000)
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 64f21ea..8463a77 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -215,8 +215,8 @@
(PERIPH_SS_BASE + 0x00163000 + \
(qup_id * 0x1000)))
+/* MDSS */
#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
-
#define MIPI_DSI_BASE (0xFD922800)
#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
#define MIPI_DSI1_BASE (0xFD922E00)
@@ -225,11 +225,17 @@
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-
#define EDP_BASE (0xFD923400)
-
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x1E00)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2200)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x2A00)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x2E00)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3200)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3600)
#define SOFT_RESET 0x118
#define CLK_CTRL 0x11C
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 4c77c7d..7a6559a 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -32,13 +32,6 @@
#include <msm_panel.h>
-#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
-#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
-#define MDP_VP_0_RGB_0_BASE REG_MDP(0x1E00)
-#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2200)
-#define MDP_VP_0_DMA_0_BASE REG_MDP(0x2A00)
-#define MDP_VP_0_DMA_1_BASE REG_MDP(0x2E00)
-
#define PIPE_SSPP_SRC0_ADDR 0x14
#define PIPE_SSPP_SRC_YSTRIDE 0x24
#define PIPE_SSPP_SRC_IMG_SIZE 0x04
@@ -53,9 +46,6 @@
#define REQPRIORITY_FIFO_WATERMARK1 0x54
#define REQPRIORITY_FIFO_WATERMARK2 0x58
-#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3200)
-#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3600)
-
#define LAYER_0_OUT_SIZE 0x04
#define LAYER_0_OP_MODE 0x00
#define LAYER_0_BORDER_COLOR_0 0x08
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index c8e9227..a1e73e3 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -81,6 +81,46 @@
writel(0x40000000, MDP_CLK_CTRL4);
}
+static void mdp_select_pipe_type(struct msm_panel_info *pinfo,
+ uint32_t *left_pipe, uint32_t *right_pipe)
+{
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ *left_pipe = MDP_VP_0_RGB_0_BASE;
+ *right_pipe = MDP_VP_0_RGB_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ *left_pipe = MDP_VP_0_DMA_0_BASE;
+ *right_pipe = MDP_VP_0_DMA_1_BASE;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ *left_pipe = MDP_VP_0_VIG_0_BASE;
+ *right_pipe = MDP_VP_0_VIG_1_BASE;
+ break;
+ }
+}
+
+static void mdss_mdp_set_flush(struct msm_panel_info *pinfo,
+ uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val)
+{
+ switch (pinfo->pipe_type) {
+ case MDSS_MDP_PIPE_TYPE_RGB:
+ *ctl0_reg_val = 0x22048;
+ *ctl1_reg_val = 0x24090;
+ break;
+ case MDSS_MDP_PIPE_TYPE_DMA:
+ *ctl0_reg_val = 0x22840;
+ *ctl1_reg_val = 0x25080;
+ break;
+ case MDSS_MDP_PIPE_TYPE_VIG:
+ default:
+ *ctl0_reg_val = 0x22041;
+ *ctl1_reg_val = 0x24082;
+ break;
+ }
+}
+
static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info
*pinfo, uint32_t pipe_base)
{
@@ -204,44 +244,37 @@
fixed_smp_cnt = 0;
}
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- right_sspp_client_id = 0x11; /* 17 */
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- right_sspp_client_id = 0xD; /* 13 */
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- right_sspp_client_id = 0x4; /* 4 */
- break;
- }
-
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106)) {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
left_sspp_client_id = 0x7; /* 7 */
+ right_sspp_client_id = 0x11; /* 17 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
left_sspp_client_id = 0x4; /* 4 */
+ right_sspp_client_id = 0xD; /* 13 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
left_sspp_client_id = 0x1; /* 1 */
+ right_sspp_client_id = 0x4; /* 4 */
break;
}
} else {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
left_sspp_client_id = 0x10; /* 16 */
+ right_sspp_client_id = 0x11; /* 17 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
left_sspp_client_id = 0xA; /* 10 */
+ right_sspp_client_id = 0xD; /* 13 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
left_sspp_client_id = 0x1; /* 1 */
+ right_sspp_client_id = 0x4; /* 4 */
break;
}
}
@@ -366,7 +399,7 @@
*pinfo)
{
uint32_t mdp_rgb_size, height, width;
- uint32_t reg_val;
+ uint32_t left_staging_level, right_staging_level;
height = fb->height;
width = fb->width;
@@ -388,21 +421,24 @@
writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP);
writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA);
- /* Baselayer for layer mixer 0 */
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
- reg_val = 0x0000200;
+ left_staging_level = 0x0000200;
+ right_staging_level = 0x1000;
break;
case MDSS_MDP_PIPE_TYPE_DMA:
- reg_val = 0x0040000;
+ left_staging_level = 0x0040000;
+ right_staging_level = 0x200000;
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
- reg_val = 0x1;
+ left_staging_level = 0x1;
+ right_staging_level = 0x8;
break;
}
- writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_0);
+ /* Base layer for layer mixer 0 */
+ writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0);
if (pinfo->lcdc.dual_pipe) {
writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
@@ -416,24 +452,11 @@
writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP);
writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA);
- /* Baselayer for layer mixer 1 */
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- reg_val = 0x1000;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- reg_val = 0x200000;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- reg_val = 0x8;
- break;
- }
-
+ /* Base layer for layer mixer 1 */
if (pinfo->lcdc.split_display)
- writel(reg_val, MDP_CTL_1_BASE + CTL_LAYER_1);
+ writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1);
else
- writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_1);
+ writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1);
}
}
@@ -476,22 +499,7 @@
mdp_clk_gating_ctrl();
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- left_pipe = MDP_VP_0_VIG_0_BASE;
- right_pipe = MDP_VP_0_VIG_1_BASE;
- break;
- }
-
+ mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
@@ -528,22 +536,7 @@
mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- left_pipe = MDP_VP_0_VIG_0_BASE;
- right_pipe = MDP_VP_0_VIG_1_BASE;
- break;
- }
-
+ mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdp_clk_gating_ctrl();
mdss_vbif_setup();
@@ -602,22 +595,7 @@
writel(intf_sel, MDP_DISP_INTF_SEL);
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- left_pipe = MDP_VP_0_RGB_0_BASE;
- right_pipe = MDP_VP_0_RGB_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- left_pipe = MDP_VP_0_DMA_0_BASE;
- right_pipe = MDP_VP_0_DMA_1_BASE;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- left_pipe = MDP_VP_0_VIG_0_BASE;
- right_pipe = MDP_VP_0_VIG_1_BASE;
- break;
- }
-
+ mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
mdss_qos_remapper_setup();
@@ -643,22 +621,7 @@
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- ctl0_reg_val = 0x22048;
- ctl1_reg_val = 0x24090;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- ctl0_reg_val = 0x22840;
- ctl1_reg_val = 0x25080;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- ctl0_reg_val = 0x22041;
- ctl1_reg_val = 0x24082;
- break;
- }
-
+ mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
@@ -699,22 +662,7 @@
int mdp_dma_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- ctl0_reg_val = 0x22048;
- ctl1_reg_val = 0x24090;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- ctl0_reg_val = 0x22840;
- ctl1_reg_val = 0x25080;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- ctl0_reg_val = 0x22041;
- ctl1_reg_val = 0x24082;
- break;
- }
-
+ mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_CTL_0_BASE + CTL_START);
@@ -728,20 +676,8 @@
int mdp_edp_on(struct msm_panel_info *pinfo)
{
- uint32_t ctl0_reg_val;
- switch (pinfo->pipe_type) {
- case MDSS_MDP_PIPE_TYPE_RGB:
- ctl0_reg_val = 0x22048;
- break;
- case MDSS_MDP_PIPE_TYPE_DMA:
- ctl0_reg_val = 0x22840;
- break;
- case MDSS_MDP_PIPE_TYPE_VIG:
- default:
- ctl0_reg_val = 0x22041;
- break;
- }
-
+ uint32_t ctl0_reg_val, ctl1_reg_val;
+ mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index e072754..ca92840 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -48,6 +48,7 @@
#include "include/panel_otm8019a_fwvga_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
+#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -84,6 +85,15 @@
int oem_panel_on()
{
+ /*
+ *OEM can keep there panel specific on instructions in this
+ *function
+ */
+ if (panel_id == OTM8019A_FWVGA_VIDEO_PANEL) {
+ /* needs extra delay to avoid unexpected artifacts */
+ mdelay(OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY);
+ }
+
return NO_ERROR;
}
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 4e3db96..dbf1ed8 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -180,7 +180,7 @@
gpio_set_dir(enable_gpio.pin_id, 2);
}
- if(hw_id == HW_PLATFORM_QRD &&
+ if (hw_id == HW_PLATFORM_QRD &&
hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) {
/* for tps65132 ENP */
gpio_tlmm_config(enp_gpio.pin_id, 0,
@@ -197,10 +197,13 @@
gpio_set_dir(enn_gpio.pin_id, 2);
}
- gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) {
+ /* configure backlight gpio for MTP & CDP */
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
bkl_gpio.pin_direction, bkl_gpio.pin_pull,
bkl_gpio.pin_strength, bkl_gpio.pin_state);
- gpio_set_dir(bkl_gpio.pin_id, 2);
+ gpio_set_dir(bkl_gpio.pin_id, 2);
+ }
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,