Merge "platform: msm_shared: Correct the USB function prototype to avoid compiler warning."
diff --git a/arch/arm/include/arch/defines.h b/arch/arm/include/arch/defines.h
index f1e5228..55eba02 100644
--- a/arch/arm/include/arch/defines.h
+++ b/arch/arm/include/arch/defines.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -44,8 +44,10 @@
#if ARM_ISA_ARMV7
#define dsb() __asm__ volatile ("dsb" : : : "memory");
+#define dmb() __asm__ volatile ("dmb" : : : "memory");
#elif ARM_ISA_ARMV6
#define dsb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0): "memory");
+#define dmb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0): "memory");
#endif
#define GET_CAHE_LINE_START_ADDR(addr) ROUNDDOWN(addr, CACHE_LINE)
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 33f8382..969ee40 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -217,7 +217,8 @@
dsi_id_len = strlen(dsi_id);
panel_node_len = strlen(panel_node);
- slave_panel_node_len = strlen(slave_panel_node);
+ if (slave_panel_node)
+ slave_panel_node_len = strlen(slave_panel_node);
arg_size = prefix_string_len + dsi_id_len + panel_node_len +
LK_OVERRIDE_PANEL_LEN + 1;
@@ -257,8 +258,8 @@
strlcpy(pbuf, DSI_1_STRING, buf_size);
pbuf += DSI_1_STRING_LEN;
buf_size -= DSI_1_STRING_LEN;
-
- strlcpy(pbuf, slave_panel_node, buf_size);
+ if (slave_panel_node)
+ strlcpy(pbuf, slave_panel_node, buf_size);
}
end:
return ret;
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 47ec49f..a6eb0ff 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -2935,5 +2935,6 @@
1, 1, 4095, 100, 1, "PMIC_8941"
};
+#define NT35590_720P_CMD_SIGNATURE 0x210000
#endif /*_PANEL_NT35590_720P_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index 9dff1a3..b935482 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -2948,5 +2948,6 @@
1, 1, 4095, 100, 1, "PMIC_8941"
};
+#define NT35590_720P_VIDEO_SIGNATURE 0x210000
#endif /*_PANEL_NT35590_720P_VIDEO_H_*/
diff --git a/include/platform.h b/include/platform.h
index aa63431..b427b04 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -53,5 +55,5 @@
void platform_uninit_timer(void);
void reboot_device(unsigned);
int set_download_mode(enum dload_mode mode);
-
+uint32_t platform_get_smem_base_addr();
#endif
diff --git a/include/target.h b/include/target.h
index d8a0daf..0af99e1 100644
--- a/include/target.h
+++ b/include/target.h
@@ -72,7 +72,7 @@
void target_usb_phy_reset(void);
void target_usb_phy_mux_configure(void);
target_usb_iface_t * target_usb30_init();
-
+bool target_is_cdp_qvga();
/* Boot device */
enum boot_device
{
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index cfdf646..f8d59a2 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -219,6 +219,10 @@
#define MIPI_DSI_BASE (0xFD922800)
#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
#define MIPI_DSI1_BASE (0xFD922E00)
+#define DSI0_PHY_BASE (0xFD922B00)
+#define DSI1_PHY_BASE (0xFD923100)
+#define DSI0_PLL_BASE (0xFD922A00)
+#define DSI1_PLL_BASE (0xFD923000)
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
diff --git a/platform/init.c b/platform/init.c
index 7efea46..1e39cfc 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -24,6 +26,7 @@
#include <debug.h>
#include <platform.h>
#include <boot_stats.h>
+#include <platform/iomap.h>
/*
* default implementations of these routines, if the platform code
@@ -111,3 +114,8 @@
{
return -1;
}
+
+__WEAK uint32_t platform_get_smem_base_addr()
+{
+ return (uint32_t)MSM_SHARED_BASE;
+}
diff --git a/platform/mdm9x35/include/platform/iomap.h b/platform/mdm9x35/include/platform/iomap.h
index 7a99b8a..fc459dd 100755
--- a/platform/mdm9x35/include/platform/iomap.h
+++ b/platform/mdm9x35/include/platform/iomap.h
@@ -132,11 +132,14 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
-#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
-#define GCC_USB30_PHY_COM_BCR (CLK_CTL_BASE + 0x1B88)
-#define GCC_USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x1B8C)
+/* USB Phy reset */
+#define USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
+#define USB3_PHY_COM_BCR (CLK_CTL_BASE + 0x1B88)
+#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x1B8C)
+#define USB2B_PHY_BCR (CLK_CTL_BASE + 0x04B0)
/* USB 3.0 clocks */
+#define USB2B_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x04B4)
#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x0108)
#define GCC_USB_30_BCR (CLK_CTL_BASE + 0x03C0)
#define GCC_USB_30_MISC (CLK_CTL_BASE + 0x03C4)
diff --git a/platform/mdm9x35/mdm9x35-clock.c b/platform/mdm9x35/mdm9x35-clock.c
index 4b0605f..5ba21bb 100755
--- a/platform/mdm9x35/mdm9x35-clock.c
+++ b/platform/mdm9x35/mdm9x35-clock.c
@@ -45,11 +45,17 @@
/* Clock Operations */
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
.disable = clock_lib2_branch_clk_disable,
.set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
};
static struct clk_ops clk_ops_rcg_mnd =
@@ -292,6 +298,7 @@
};
static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
.cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.parent = &usb30_pipe_clk_src.c,
.has_sibling = 0,
@@ -391,6 +398,35 @@
},
};
+static struct reset_clk gcc_usb30_phy_com_reset = {
+ .bcr_reg = (uint32_t *) USB3_PHY_COM_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_com_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t *) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct branch_clk gcc_usb2b_phy_sleep_clk = {
+ .bcr_reg = (uint32_t *) USB2B_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB2B_PHY_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup mdm_9635_clocks[] =
{
@@ -407,6 +443,10 @@
CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_phy_com_reset", gcc_usb30_phy_com_reset.c),
+
CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
};
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 5b537e8..d7e5094 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -35,6 +35,9 @@
#define SDRAM_START_ADDR 0x00000000
#define MSM_SHARED_BASE 0x0FA00000
+#define MSM_DYNAMIC_SHARED_BASE 0xFE802FF8
+
+#define SMEM_TARGET_INFO_ADDR 0xFE802FF0
#define APPS_SS_BASE 0xF9000000
@@ -169,6 +172,10 @@
#define MIPI_DSI_BASE (0xFD922800)
#define MIPI_DSI0_BASE MIPI_DSI_BASE
#define MIPI_DSI1_BASE MIPI_DSI_BASE
+#define DSI0_PHY_BASE (0xFD922B00)
+#define DSI1_PHY_BASE DSI0_PHY_BASE
+#define DSI0_PLL_BASE (0xFD922A00)
+#define DSI1_PLL_BASE DSI0_PLL_BASE
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
diff --git a/platform/msm8226/platform.c b/platform/msm8226/platform.c
index 3a25699..1d15a62 100644
--- a/platform/msm8226/platform.c
+++ b/platform/msm8226/platform.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -141,3 +141,19 @@
}
}
}
+
+/* DYNAMIC SMEM REGION feature enables LK to dynamically read the SMEM address from MSM_DYNAMIC_SHARED_BASE.
+ * If the feature is enabled(by reading the MAGIC as mentioned below) then the SMEM address is read from
+ * MSM_DYNAMIC_SHARED_BASE otherwise revert to the older way of getting SMEM address - MSM_SHARED_BASE */
+
+uint32_t platform_get_smem_base_addr()
+{
+ uint32_t smem_addr = 0;
+
+ if(readl(SMEM_TARGET_INFO_ADDR) == SMEM_TARGET_INFO_IDENTIFIER)
+ smem_addr = readl(MSM_DYNAMIC_SHARED_BASE);
+ else
+ smem_addr = MSM_SHARED_BASE;
+
+ return smem_addr;
+}
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index ce0eb26..65f5dc6 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -100,6 +100,10 @@
#define MIPI_DSI_BASE 0xFDD00000
#define MIPI_DSI0_BASE MIPI_DSI_BASE
#define MIPI_DSI1_BASE MIPI_DSI_BASE
+#define DSI0_PHY_BASE MIPI_DSI_BASE
+#define DSI1_PHY_BASE MIPI_DSI_BASE
+#define DSI0_PLL_BASE MIPI_DSI_BASE
+#define DSI1_PLL_BASE MIPI_DSI_BASE
#define REG_DSI(off) (MIPI_DSI_BASE + (off))
#define DSIPHY_REGULATOR_BASE 0x500
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index 06a2c06..7f81f9a 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -170,3 +170,125 @@
ASSERT(0);
}
}
+
+/* Control the MDSS GDSC */
+void mdp_gdsc_ctrl(uint8_t enable)
+{
+ uint32_t reg = 0;
+ reg = readl(MDP_GDSCR);
+ if (enable) {
+ if (!(reg & GDSC_POWER_ON_BIT)) {
+ reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
+ reg |= GDSC_EN_FEW_WAIT_256_MASK;
+ writel(reg, MDP_GDSCR);
+ while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)));
+ } else {
+ dprintf(SPEW, "MDP GDSC already enabled\n");
+ }
+ } else {
+ reg |= BIT(0);
+ writel(reg, MDP_GDSCR);
+ while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT));
+ }
+}
+
+/* Enable all the MDP branch clocks */
+void mdp_clock_enable(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Set MDP clock to 320MHz */
+ ret = clk_get_set_enable("mdss_mdp_clk_src", 320000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+/* Disable all the MDP branch clocks */
+void mdp_clock_disable(void)
+{
+ clk_disable(clk_get("mdss_vsync_clk"));
+ clk_disable(clk_get("mdss_mdp_clk"));
+ clk_disable(clk_get("mdss_mdp_clk_src"));
+ clk_disable(clk_get("mdp_ahb_clk"));
+}
+
+/* Disable all the bus clocks needed by MDSS */
+void mdss_bus_clocks_disable(void)
+{
+ /* Disable MDSS AXI clock */
+ clk_disable(clk_get("mdss_axi_clk"));
+}
+
+/* Enable all the bus clocks needed by MDSS */
+void mdss_bus_clocks_enable(void)
+{
+ int ret;
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+/* Disable all the branch clocks needed by the DSI controller */
+void gcc_dsi_clocks_disable(void)
+{
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_PIXEL0_CBCR);
+ writel(0x0, DSI_BYTE0_CBCR);
+}
+
+/* Configure all the branch clocks needed by the DSI controller */
+void gcc_dsi_clocks_enable(uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change becasue
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure Pixel clock */
+ writel(0x100, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
diff --git a/platform/msm8916/include/platform/clock.h b/platform/msm8916/include/platform/clock.h
index 58403da..87cb561 100644
--- a/platform/msm8916/include/platform/clock.h
+++ b/platform/msm8916/include/platform/clock.h
@@ -34,6 +34,37 @@
#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define REG_MM(off) (CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR REG_MM(0x4D078)
+#define GDSC_POWER_ON_BIT BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK BIT(19)
+
+#define VSYNC_CMD_RCGR REG_MM(0x4D02C)
+#define VSYNC_CFG_RCGR REG_MM(0x4D030)
+#define MDSS_VSYNC_CBCR REG_MM(0x4D090)
+
+#define MDP_CMD_RCGR REG_MM(0x4D014)
+#define MDP_CFG_RCGR REG_MM(0x4D018)
+#define MDP_CBCR REG_MM(0x4D088)
+#define MDP_AHB_CBCR REG_MM(0x4D07C)
+#define MDP_AXI_CBCR REG_MM(0x4D080)
+
+#define DSI_BYTE0_CMD_RCGR REG_MM(0x4D044)
+#define DSI_BYTE0_CFG_RCGR REG_MM(0x4D048)
+#define DSI_BYTE0_CBCR REG_MM(0x4D094)
+#define DSI_ESC0_CMD_RCGR REG_MM(0x4D05C)
+#define DSI_ESC0_CFG_RCGR REG_MM(0x4D060)
+#define DSI_ESC0_CBCR REG_MM(0x4D098)
+#define DSI_PIXEL0_CMD_RCGR REG_MM(0x4D000)
+#define DSI_PIXEL0_CFG_RCGR REG_MM(0x4D004)
+#define DSI_PIXEL0_CBCR REG_MM(0x4D084)
+#define DSI_PIXEL0_M REG_MM(0x4D008)
+#define DSI_PIXEL0_N REG_MM(0x4D00C)
+#define DSI_PIXEL0_D REG_MM(0x4D010)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
@@ -41,5 +72,6 @@
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
-
+void mdp_clock_init(void);
+void mdp_gdsc_ctrl(uint8_t enable);
#endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 9eaa7b9..e5a8c88 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -130,4 +130,94 @@
#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+
+/* MDSS */
+#define MIPI_DSI_BASE (0x1A98000)
+#define MIPI_DSI0_BASE MIPI_DSI_BASE
+#define MIPI_DSI1_BASE MIPI_DSI_BASE
+#define DSI0_PHY_BASE (0x1A98500)
+#define DSI1_PHY_BASE DSI0_PHY_BASE
+#define DSI0_PLL_BASE (0x1A98300)
+#define DSI1_PLL_BASE DSI0_PLL_BASE
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+
+#define MDP_BASE (0x1A00000)
+#define REG_MDP(off) (MDP_BASE + (off))
+
+#define MDP_HW_REV REG_MDP(0x1000)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
+#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
+#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
+#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
+#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
+#define MDP_CTL_0_BASE REG_MDP(0x2000)
+#define MDP_CTL_1_BASE REG_MDP(0x2200)
+#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
+#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
+#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
+#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
+#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
+#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
+
+#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
+#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
+
+#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
+
+#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
+#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
+#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
+#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
+#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
+#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
+#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
+#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
+#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
+#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
+#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
+#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
+#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
+#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
+#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
+#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
+#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
+
+#define SOFT_RESET 0x118
+#define CLK_CTRL 0x11C
+#define TRIG_CTRL 0x084
+#define CTRL 0x004
+#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
+#define ERR_INT_MASK0 0x10C
+
+#define LANE_SWAP_CTL 0x0B0
+#define TIMING_CTL 0x0C4
+
+#define VIDEO_MODE_ACTIVE_H 0x024
+#define VIDEO_MODE_ACTIVE_V 0x028
+#define VIDEO_MODE_TOTAL 0x02C
+#define VIDEO_MODE_HSYNC 0x030
+#define VIDEO_MODE_VSYNC 0x034
+#define VIDEO_MODE_VSYNC_VPOS 0x038
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
+
#endif
diff --git a/platform/msm8916/msm8916-clock.c b/platform/msm8916/msm8916-clock.c
index ca4bd4c..04e25ec 100644
--- a/platform/msm8916/msm8916-clock.c
+++ b/platform/msm8916/msm8916-clock.c
@@ -39,6 +39,8 @@
/* Mux source select values */
#define cxo_source_val 0
#define gpll0_source_val 1
+#define cxo_mm_source_val 0
+#define gpll0_mm_source_val 1
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -306,6 +308,115 @@
},
};
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+ F_MM( 80000000, gpll0, 10, 0, 0),
+ F_MM( 100000000, gpll0, 8, 0, 0),
+ F_MM( 200000000, gpll0, 4, 0, 0),
+ F_MM( 320000000, gpll0, 2.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc0_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc0_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+ .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
+ .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_vsync_clk,
+
+ .c = {
+ .dbg_name = "vsync_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_esc0_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
+ .parent = &dsi_esc0_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc0_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_axi_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdp_ahb_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdp_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdp_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_mdp_clk = {
+ .cbcr_reg = (uint32_t *) MDP_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_vsync_clk = {
+ .cbcr_reg = MDSS_VSYNC_CBCR,
+ .parent = &vsync_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_vsync_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8916[] =
{
@@ -320,6 +431,13 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
+ CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
+ CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
+ CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
+ CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
+ CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/msm8916/rules.mk b/platform/msm8916/rules.mk
index 85dff4f..86f1a47 100644
--- a/platform/msm8916/rules.mk
+++ b/platform/msm8916/rules.mk
@@ -15,6 +15,9 @@
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+DEVS += fbcon
+MODULES += dev/fbcon
+
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 91eb0db..730147d 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -178,6 +178,12 @@
int ret = 0;
char clk_name[64];
+ /* CDC clocks are not supported for 8974 v1 & v2
+ * only pro msm's support it
+ */
+ if (platform_is_8974())
+ return;
+
snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
ret = clk_get_set_enable(clk_name, 0 , 1);
if (ret)
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 182f454..64f21ea 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -220,6 +220,10 @@
#define MIPI_DSI_BASE (0xFD922800)
#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
#define MIPI_DSI1_BASE (0xFD922E00)
+#define DSI0_PHY_BASE (0xFD922B00)
+#define DSI1_PHY_BASE (0xFD923100)
+#define DSI0_PLL_BASE (0xFD922A00)
+#define DSI1_PLL_BASE (0xFD923000)
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define EDP_BASE (0xFD923400)
diff --git a/platform/msm_shared/clock.c b/platform/msm_shared/clock.c
index d69f2c7..35ed5c6 100644
--- a/platform/msm_shared/clock.c
+++ b/platform/msm_shared/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -53,6 +53,17 @@
return clk->ops->get_parent(clk);
}
+int clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+ if (!clk)
+ return 0;
+
+ if (!clk->ops->reset)
+ return 0;
+
+ return clk->ops->reset(clk, action);
+}
+
/*
* Standard clock functions defined in include/clk.h
*/
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index c97c6cf..f5e321a 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -25,6 +25,7 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <arch/defines.h>
#include <assert.h>
#include <reg.h>
#include <err.h>
@@ -224,3 +225,50 @@
vote_regval &= ~vclk->en_mask;
writel_relaxed(vote_regval, vclk->vote_reg);
}
+
+/* Reset clock */
+static int __clock_lib2_branch_clk_reset(uint32_t bcr_reg, enum clk_reset_action action)
+{
+ uint32_t reg;
+ int ret = 0;
+
+ reg = readl(bcr_reg);
+
+ switch (action) {
+ case CLK_RESET_ASSERT:
+ reg |= BIT(0);
+ break;
+ case CLK_RESET_DEASSERT:
+ reg &= ~BIT(0);
+ break;
+ default:
+ ret = 1;
+ }
+
+ writel(reg, bcr_reg);
+
+ /* Wait for writes to go through */
+ dmb();
+
+ return ret;
+}
+
+int clock_lib2_reset_clk_reset(struct clk *c, enum clk_reset_action action)
+{
+ struct reset_clk *rst = to_reset_clk(c);
+
+ if (!rst)
+ return 0;
+
+ return __clock_lib2_branch_clk_reset(rst->bcr_reg, action);
+}
+
+int clock_lib2_branch_clk_reset(struct clk *c, enum clk_reset_action action)
+{
+ struct branch_clk *bclk = to_branch_clk(c);
+
+ if (!bclk)
+ return 0;
+
+ return __clock_lib2_branch_clk_reset(bclk->bcr_reg, action);
+}
diff --git a/platform/msm_shared/include/clock.h b/platform/msm_shared/include/clock.h
index 9e3482b..fd878d2 100644
--- a/platform/msm_shared/include/clock.h
+++ b/platform/msm_shared/include/clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -187,4 +187,10 @@
* @num: number of clocks in the list
*/
void clk_init(struct clk_lookup *clist, unsigned num);
+/**
+ * clk_reset - Reset block using BCR
+ * @clk: pointer to clock
+ * @action: clock assert or deassert
+ */
+int clk_reset(struct clk *clk, enum clk_reset_action);
#endif
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index afa0d8c..d353684 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -183,6 +183,16 @@
struct clk c;
};
+struct reset_clk {
+ uint32_t bcr_reg;
+ struct clk c;
+};
+
+static inline struct reset_clk *to_reset_clk(struct clk *clk)
+{
+ return container_of(clk, struct reset_clk, c);
+}
+
static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
{
return container_of(clk, struct rcg_clk, c);
@@ -216,4 +226,7 @@
/* Vote clock functions*/
int clock_lib2_vote_clk_enable(struct clk *c);
void clock_lib2_vote_clk_disable(struct clk *c);
+/* clock reset function */
+int clock_lib2_reset_clk_reset(struct clk *c, enum clk_reset_action action);
+int clock_lib2_branch_clk_reset(struct clk *c, enum clk_reset_action action);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 54dc82f..0a90531 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -86,6 +86,7 @@
#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
+#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDSS_MAX_LINE_BUF_WIDTH 2048
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 477ed97..b2b8504 100755
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -972,6 +972,8 @@
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
+int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
+ uint32_t ctl_base, uint32_t phy_base);
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index a660e29..1a61ee3 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -33,6 +33,14 @@
#include <bits.h>
#include <kernel/event.h>
+//#define DEBUG_SDHCI
+
+#ifdef DEBUG_SDHCI
+#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
+#else
+#define DBG(...)
+#endif
+
/*
* Capabilities for the host controller
* These values are read from the capabilities
@@ -124,7 +132,7 @@
/*
* Helper macros for writing byte, word & long registers
*/
-#define REG_READ8(host, a) readb(host->base + a);
+#define REG_READ8(host, a) readb(host->base + a)
#define REG_WRITE8(host, v, a) writeb(v, (host->base + a))
#define REG_READ32(host, a) readl(host->base + a)
@@ -156,9 +164,11 @@
#define SDHCI_ERR_INT_STS_EN_REG (0x036)
#define SDHCI_NRML_INT_SIG_EN_REG (0x038)
#define SDHCI_ERR_INT_SIG_EN_REG (0x03A)
+#define SDHCI_AUTO_CMD_ERR (0x03C)
#define SDHCI_HOST_CTRL2_REG (0x03E)
#define SDHCI_CAPS_REG1 (0x040)
#define SDHCI_CAPS_REG2 (0x044)
+#define SDHCI_ADM_ERR_REG (0x054)
#define SDHCI_ADM_ADDR_REG (0x058)
/*
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index a075460..180f23a 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -76,7 +76,8 @@
#define CDC_SWITCH_BYPASS_OFF BIT(0)
#define CDC_SWITCH_RC_EN BIT(1)
#define START_CDC_TRAFFIC BIT(6)
-#define FW_CLK_SW_RST_DIS BIT(13)
+#define FF_CLK_SW_RST_DIS_START 0xD
+#define FF_CLK_SW_RST_DIS_WIDTH 0x1
#define CDC_SW_TRIGGER_FULL_CALIB BIT(16)
#define CDC_HW_AUTO_CAL_EN BIT(17)
#define CDC_TIMER_EN BIT(16)
@@ -102,6 +103,9 @@
#define CORE_VERSION_MAJOR_MASK 0xF0000000
#define CORE_VERSION_MAJOR_SHIFT 0x1C
+#define SDHCI_DLL_TIMEOUT 50
+#define CDC_STATUS_TIMEOUT 50
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index e1106bf..ad18d8b 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -59,7 +59,9 @@
uint32_t mdss_mdp_intf_off;
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
- if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102)
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_106)
+ mdss_mdp_intf_off = 0x59100;
+ else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102)
mdss_mdp_intf_off = 0;
else
mdss_mdp_intf_off = 0xEC00;
@@ -122,13 +124,12 @@
int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
- /* TZ returns an errornous ret val even if the VBIF registers were
- * successfully unlocked. Ignore TZ return value till it's fixed */
- if (!access_secure || 1) {
+ if (!access_secure) {
dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n");
- /* Force VBIF Clocks on */
- if (mdp_hw_rev < MDSS_MDP_HW_REV_103)
+ /* Force VBIF Clocks on, not needed for 8084 */
+ if ((mdp_hw_rev < MDSS_MDP_HW_REV_103) ||
+ (mdp_hw_rev == MDSS_MDP_HW_REV_106))
writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
/*
@@ -145,9 +146,11 @@
writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_101)) {
+ MDSS_MDP_HW_REV_101) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_106)) {
writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
- writel(0x00000003, VBIF_VBIF_DDR_ARB_CTRL);
+ writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
}
}
}
@@ -189,7 +192,10 @@
uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0;
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
- if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
+ if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) {
+ /* 8Kb per SMP on 8916 */
+ smp_size = 8192;
+ } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
(mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
smp_size = 8192;
fixed_smp_cnt = 2;
@@ -201,7 +207,8 @@
else
right_sspp_client_id = 0x11; /* 17 */
- if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101))
+ if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106))
left_sspp_client_id = (pinfo->use_dma_pipe) ? 0x4 : 0x07; /* 4 or 7 */
else
left_sspp_client_id = (pinfo->use_dma_pipe) ? 0xA : 0x10; /* 10 or 16 */
@@ -384,7 +391,9 @@
MDSS_MDP_HW_REV_102))
map = 0xE9;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
- MDSS_MDP_HW_REV_101))
+ MDSS_MDP_HW_REV_101) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_106))
map = 0xA5;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_103))
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 03fed9b..04d6bdf 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1025,9 +1025,9 @@
mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post;
mipi_pinfo.signature = pinfo->mipi.signature;
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE);
+ mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE, DSI0_PHY_BASE);
if (pinfo->mipi.dual_dsi)
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE);
+ mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE, DSI1_PHY_BASE);
ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.broadcast);
if (ret) {
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 72f2f94..7777ef1 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -64,7 +64,22 @@
return dividend / divisor;
}
-int32_t mdss_dsi_auto_pll_config(uint32_t ctl_base,
+void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base)
+{
+ writel(0x0c, pll_base + 0x0064); /* LKDetect CFG2 */
+ udelay(100);
+ writel(0x0d, pll_base + 0x0064); /* LKDetect CFG2 */
+}
+
+void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base)
+{
+ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
+ udelay(1);
+ writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+ udelay(1);
+}
+
+int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
struct mdss_dsi_pll_config *pd)
{
uint32_t rem, divider;
@@ -90,22 +105,22 @@
mdss_dsi_phy_sw_reset(ctl_base);
/* Loop filter resistance value */
- writel(lpfr_lut[i].resistance, ctl_base + 0x022c);
+ writel(lpfr_lut[i].resistance, pll_base + 0x002c);
/* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
+ writel(0x70, pll_base + 0x0030);
+ writel(0x15, pll_base + 0x0034);
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
+ writel(0x02, pll_base + 0x0008); /* ChgPump */
/* postDiv1 - calculated in pll config*/
- writel(pd->posdiv1, ctl_base + 0x0204);
+ writel(pd->posdiv1, pll_base + 0x0004);
/* postDiv2 - fixed devision 4 */
- writel(0x03, ctl_base + 0x0224);
+ writel(0x03, pll_base + 0x0024);
/* postDiv3 - calculated in pll config */
- writel(pd->posdiv3, ctl_base + 0x0228); /* postDiv3 */
+ writel(pd->posdiv3, pll_base + 0x0028); /* postDiv3 */
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
+ writel(0x2b, pll_base + 0x0078); /* Cal CFG3 */
+ writel(0x66, pll_base + 0x007c); /* Cal CFG4 */
+ writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
if (rem) {
@@ -149,25 +164,25 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(sdm_cfg1 , ctl_base + 0x023c); /* SDM CFG1 */
- writel(sdm_cfg2 , ctl_base + 0x0240); /* SDM CFG2 */
- writel(sdm_cfg3 , ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
+ writel(sdm_cfg1 , pll_base + 0x003c); /* SDM CFG1 */
+ writel(sdm_cfg2 , pll_base + 0x0040); /* SDM CFG2 */
+ writel(sdm_cfg3 , pll_base + 0x0044); /* SDM CFG3 */
+ writel(0x00, pll_base + 0x0048); /* SDM CFG4 */
udelay(10);
- writel(refclk_cfg, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(pd->directpath, ctl_base + 0x0210); /* VREG CFG */
- writel(sdm_cfg0, ctl_base + 0x0238); /* SDM CFG0 */
+ writel(refclk_cfg, pll_base + 0x0000); /* REFCLK CFG */
+ writel(0x00, pll_base + 0x0014); /* PWRGEN CFG */
+ writel(0x71, pll_base + 0x000c); /* VCOLPF CFG */
+ writel(pd->directpath, pll_base + 0x0010); /* VREG CFG */
+ writel(sdm_cfg0, pll_base + 0x0038); /* SDM CFG0 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(cal_cfg10, ctl_base + 0x0294); /* CAL CFG10 */
- writel(cal_cfg11, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
+ writel(0x0a, pll_base + 0x006c); /* CAL CFG0 */
+ writel(0x30, pll_base + 0x0084); /* CAL CFG6 */
+ writel(0x00, pll_base + 0x0088); /* CAL CFG7 */
+ writel(0x60, pll_base + 0x008c); /* CAL CFG8 */
+ writel(0x00, pll_base + 0x0090); /* CAL CFG9 */
+ writel(cal_cfg10, pll_base + 0x0094); /* CAL CFG10 */
+ writel(cal_cfg11, pll_base + 0x0098); /* CAL CFG11 */
+ writel(0x20, pll_base + 0x009c); /* EFUSE CFG */
}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 8e4a762..99b7b6a 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -197,43 +197,28 @@
udelay(100);
}
-void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t ctl_base)
-{
- writel(0x0c, ctl_base + 0x0264); /* LKDetect CFG2 */
- udelay(100);
- writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
-}
-
-void mdss_dsi_uniphy_pll_sw_reset(uint32_t ctl_base)
-{
- writel(0x01, ctl_base + 0x0268); /* PLL TEST CFG */
- udelay(1);
- writel(0x00, ctl_base + 0x0268); /* PLL TEST CFG */
- udelay(1);
-}
-
int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd)
{
/* DSI0 and DSI1 have a common regulator */
- uint32_t off = 0x0580; /* phy regulator ctrl settings */
+ uint32_t off = 0x0280; /* phy regulator ctrl settings */
/* Regulator ctrl 0 */
- writel(0x00, MIPI_DSI0_BASE + off + (4 * 0));
+ writel(0x00, DSI0_PHY_BASE + off + (4 * 0));
/* Regulator ctrl - CAL_PWD_CFG */
- writel(pd->regulator[6], MIPI_DSI0_BASE + off + (4 * 6));
+ writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6));
/* Regulator ctrl - TEST */
- writel(pd->regulator[5], MIPI_DSI0_BASE + off + (4 * 5));
+ writel(pd->regulator[5], DSI0_PHY_BASE + off + (4 * 5));
/* Regulator ctrl 3 */
- writel(pd->regulator[3], MIPI_DSI0_BASE + off + (4 * 3));
+ writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3));
/* Regulator ctrl 2 */
- writel(pd->regulator[2], MIPI_DSI0_BASE + off + (4 * 2));
+ writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2));
/* Regulator ctrl 1 */
- writel(pd->regulator[1], MIPI_DSI0_BASE + off + (4 * 1));
+ writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1));
/* Regulator ctrl 0 */
- writel(pd->regulator[0], MIPI_DSI0_BASE + off + (4 * 0));
+ writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0));
/* Regulator ctrl 4 */
- writel(pd->regulator[4], MIPI_DSI0_BASE + off + (4 * 4));
+ writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
dmb();
}
@@ -289,7 +274,8 @@
return 0;
}
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo, uint32_t ctl_base)
+int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo,
+ uint32_t ctl_base, uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, off = 0, ln, offset;
@@ -300,54 +286,54 @@
pd = (pinfo->mdss_dsi_phy_config);
/* Strength ctrl 0 */
- writel(pd->strength[0], ctl_base + 0x0484);
+ writel(pd->strength[0], phy_base + 0x0184);
mdss_dsi_phy_regulator_init(pd);
/* Strength ctrl 0 */
- writel(0x00, ctl_base + 0x04dc);
+ writel(0x00, phy_base + 0x01dc);
- off = 0x0440; /* phy timing ctrl 0 - 11 */
+ off = 0x0140; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
- writel(pd->timing[i], ctl_base + off);
+ writel(pd->timing[i], phy_base + off);
dmb();
off += 4;
}
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x00, ctl_base + 0x0474);
+ writel(0x00, phy_base + 0x0174);
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x5f, ctl_base + 0x0470);
+ writel(0x5f, phy_base + 0x0170);
/* Strength ctrl 1 */
- writel(pd->strength[1], ctl_base + 0x0488);
+ writel(pd->strength[1], phy_base + 0x0188);
dmb();
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
for (ln = 0; ln < 5; ln++) {
- off = 0x0300 + (ln * 0x40);
+ off = (ln * 0x40);
for (i = 0; i < 9; i++) {
offset = i + (ln * 9);
- writel(pd->laneCfg[offset], ctl_base + off);
+ writel(pd->laneCfg[offset], phy_base + off);
dmb();
off += 4;
}
}
/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x5f, ctl_base + 0x0470);
+ writel(0x5f, phy_base + 0x0170);
/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
- if (ctl_base == MIPI_DSI0_BASE)
- writel(0x01, ctl_base + 0x04d4);
+ if (phy_base == DSI0_PHY_BASE)
+ writel(0x01, phy_base + 0x01d4);
else
- writel(0x00, ctl_base + 0x04d4);
+ writel(0x00, phy_base + 0x01d4);
dmb();
- off = 0x04b4; /* phy BIST ctrl 0 - 5 */
+ off = 0x01b4; /* phy BIST ctrl 0 - 5 */
for (i = 0; i < 6; i++) {
- writel(pd->bistCtrl[i], ctl_base + off);
+ writel(pd->bistCtrl[i], phy_base + off);
off += 4;
}
dmb();
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index f0d51ac..d89e01d 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -822,6 +822,8 @@
{
uint32_t mmc_ret = 0;
+ DBG("\n Enabling HS200 Mode Start\n");
+
/* Set 4/8 bit SDR bus width */
mmc_ret = mmc_set_bus_width(host, card, width);
if (mmc_ret) {
@@ -864,6 +866,8 @@
if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
dprintf(CRITICAL, "Tuning for hs200 failed\n");
+ DBG("\n Enabling HS200 Mode Done\n");
+
return mmc_ret;
}
@@ -877,6 +881,8 @@
{
uint8_t mmc_ret = 0;
+ DBG("\n Enabling DDR Mode Start\n");
+
/* Set width for 8 bit DDR mode by default */
mmc_ret = mmc_set_bus_width(host, card, DATA_DDR_BUS_WIDTH_8BIT);
@@ -892,6 +898,8 @@
/* Set the DDR mode in controller */
sdhci_set_uhs_mode(host, SDHCI_DDR50_MODE);
+ DBG("\n Enabling DDR Mode Done\n");
+
return 0;
}
@@ -947,6 +955,7 @@
* 4. Enable HS400 mode & execute tuning
*/
+ DBG("\n Enabling HS400 Mode Start\n");
/* HS400 mode is supported only in DDR 8-bit */
if (width != DATA_BUS_WIDTH_8BIT)
{
@@ -1008,6 +1017,8 @@
if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
dprintf(CRITICAL, "Tuning for hs400 failed\n");
+ DBG("\n Enabling HS400 Mode Done\n");
+
return mmc_ret;
}
@@ -1052,6 +1063,12 @@
clock_config_mmc(cfg->slot, cfg->max_clk_rate);
+ /* Configure the CDC clocks needed for emmc storage
+ * we use slot '1' for emmc
+ */
+ if (cfg->slot == 1)
+ clock_config_cdc(cfg->slot);
+
/*
* MSM specific sdhc init
*/
@@ -1879,7 +1896,15 @@
else
cmd.cmd_index = CMD32_ERASE_WR_BLK_START;
- cmd.argument = erase_start;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = erase_start * card->block_size;
+ else
+ cmd.argument = erase_start;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
@@ -1914,7 +1939,15 @@
else
cmd.cmd_index = CMD33_ERASE_WR_BLK_END;
- cmd.argument = erase_end;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = erase_end * card->block_size;
+ else
+ cmd.argument = erase_end;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index 23e0a8f..dd7deb1 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -32,29 +32,95 @@
#include <qmp_phy.h>
#include <reg.h>
#include <bits.h>
+#include <clock.h>
+#include <debug.h>
+
+#define HS_PHY_COMMON_CTRL 0xEC
+#define USE_CORECLK BIT(14)
+#define PLLBTUNE BIT(15)
+#define FSEL (0x7 << 4)
+#define DIS_RETENTION BIT(18)
/* USB3.0 QMP phy reset */
void usb30_qmp_phy_reset(void)
{
+ int ret = 0;
uint32_t val;
- /* phy com reset */
- val = readl(GCC_USB30_PHY_COM_BCR) | BIT(0);
- writel(val, GCC_USB30_PHY_COM_BCR);
- udelay(10);
- writel(val & ~BIT(0), GCC_USB30_PHY_COM_BCR);
+ struct clk *usb2b_clk = NULL;
+ struct clk *usb_pipe_clk = NULL;
+ struct clk *phy_com_clk = NULL;
+ struct clk *phy_clk = NULL;
- /* SS PHY reset */
- val = readl(GCC_USB3_PHY_BCR) | BIT(0);
- writel(val, GCC_USB3_PHY_BCR);
- udelay(10);
- writel(val & ~BIT(0), GCC_USB3_PHY_BCR);
+ usb2b_clk = clk_get("usb2b_phy_sleep_clk");
+ ASSERT(usb2b_clk);
- /* pipe clk reset */
- val = readl(GCC_USB30PHY_PHY_BCR) | BIT(0);
- writel(val, GCC_USB30PHY_PHY_BCR);
- udelay(10);
- writel(val & ~BIT(0), GCC_USB30PHY_PHY_BCR);
+ phy_com_clk = clk_get("usb30_phy_com_reset");
+ ASSERT(phy_com_clk);
+
+ phy_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_clk);
+
+ usb_pipe_clk = clk_get("usb30_pipe_clk");
+ ASSERT(usb_pipe_clk);
+
+ /* ASSERT */
+ ret = clk_reset(usb2b_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb2b_phy_clk\n");
+ return;
+ }
+
+ ret = clk_reset(phy_com_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert phy_com_clk\n");
+ goto deassert_usb2b_clk;
+ }
+
+ ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert phy_clk\n");
+ goto deassert_phy_com_clk;
+ }
+
+ ret = clk_reset(usb_pipe_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(usb_pipe_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+
+deassert_phy_clk:
+ ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dprintf(CRITICAL, "Failed to deassert phy_clk\n");
+
+deassert_phy_com_clk:
+ ret = clk_reset(phy_com_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dprintf(CRITICAL, "Failed to deassert phy_com_clk\n");
+
+deassert_usb2b_clk:
+ ret = clk_reset(usb2b_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dprintf(CRITICAL, "Failed to deassert usb2b_phy_clk\n");
+
+ /* Override the phy common control values */
+ val = readl(MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
+ val |= USE_CORECLK | PLLBTUNE;
+ val &= ~FSEL;
+ val &= ~DIS_RETENTION;
+ writel(val, MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
}
/* USB 3.0 phy init: HPG for QMP phy*/
@@ -98,7 +164,7 @@
writel(0x6C, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
writel(0xC7, QMP_PHY_BASE + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
writel(0x40, QMP_PHY_BASE + QSERDES_RX_SIGDET_ENABLES);
- writel(0x70, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
+ writel(0x73, QMP_PHY_BASE + QSERDES_RX_SIGDET_CNTRL);
writel(0x06, QMP_PHY_BASE + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
writel(0x48, QMP_PHY_BASE + PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL);
writel(0x01, QMP_PHY_BASE + QSERDES_COM_SSC_EN_CENTER);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index f07e22c..ea5d9d3 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -155,6 +155,7 @@
$(LOCAL_DIR)/dev_tree.o
endif
ifeq ($(PLATFORM),msm8916)
+DEFINES += DISPLAY_TYPE_MDSS=1
OBJS += $(LOCAL_DIR)/qgic.o \
$(LOCAL_DIR)/qtimer.o \
$(LOCAL_DIR)/qtimer_mmap.o \
@@ -170,7 +171,12 @@
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dload_util.o \
$(LOCAL_DIR)/gpio.o \
- $(LOCAL_DIR)/dev_tree.o
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/mdp5.o \
+ $(LOCAL_DIR)/display.o \
+ $(LOCAL_DIR)/mipi_dsi.o \
+ $(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o
endif
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index a278dea..e77fa60 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -39,6 +39,57 @@
#include <sdhci.h>
#include <sdhci_msm.h>
+static void sdhci_dumpregs(struct sdhci_host *host)
+{
+ DBG("****************** SDHC REG DUMP START ********************\n");
+
+ DBG("Version: 0x%08x\n", REG_READ32(host, SDHCI_ARG2_REG));
+ DBG("Arg2: 0x%08x\t Blk Cnt: 0x%08x\n",
+ REG_READ32(host, SDHCI_ARG2_REG),
+ REG_READ16(host, SDHCI_BLK_CNT_REG));
+ DBG("Arg1: 0x%08x\t Blk Sz : 0x%08x\n",
+ REG_READ32(host, SDHCI_ARGUMENT_REG),
+ REG_READ16(host, SDHCI_BLKSZ_REG));
+ DBG("Command: 0x%08x\t Trans mode: 0x%08x\n",
+ REG_READ16(host, SDHCI_CMD_REG),
+ REG_READ16(host, SDHCI_TRANS_MODE_REG));
+ DBG("Resp0: 0x%08x\t Resp1: 0x%08x\n",
+ REG_READ32(host, SDHCI_RESP_REG),
+ REG_READ32(host, SDHCI_RESP_REG + 0x4));
+ DBG("Resp2: 0x%08x\t Resp3: 0x%08x\n",
+ REG_READ32(host, SDHCI_RESP_REG + 0x8),
+ REG_READ32(host, SDHCI_RESP_REG + 0xC));
+ DBG("Prsnt State: 0x%08x\t Host Ctrl1: 0x%08x\n",
+ REG_READ32(host, SDHCI_PRESENT_STATE_REG),
+ REG_READ8(host, SDHCI_HOST_CTRL1_REG));
+ DBG("Timeout ctrl: 0x%08x\t Power Ctrl: 0x%08x\n",
+ REG_READ8(host, SDHCI_TIMEOUT_REG),
+ REG_READ8(host, SDHCI_PWR_CTRL_REG));
+ DBG("Error stat: 0x%08x\t Int Status: 0x%08x\n",
+ REG_READ32(host, SDHCI_ERR_INT_STS_REG),
+ REG_READ32(host, SDHCI_NRML_INT_STS_REG));
+ DBG("Host Ctrl2: 0x%08x\t Clock ctrl: 0x%08x\n",
+ REG_READ32(host, SDHCI_HOST_CTRL2_REG),
+ REG_READ32(host, SDHCI_CLK_CTRL_REG));
+ DBG("Caps1: 0x%08x\t Caps2: 0x%08x\n",
+ REG_READ32(host, SDHCI_CAPS_REG1),
+ REG_READ32(host, SDHCI_CAPS_REG1));
+ DBG("Adma Err: 0x%08x\t Auto Cmd err: 0x%08x\n",
+ REG_READ8(host, SDHCI_ADM_ERR_REG),
+ REG_READ16(host, SDHCI_AUTO_CMD_ERR));
+ DBG("Adma addr1: 0x%08x\t Adma addr2: 0x%08x\n",
+ REG_READ32(host, SDHCI_ADM_ADDR_REG),
+ REG_READ32(host, SDHCI_ADM_ADDR_REG + 0x4));
+
+ DBG("****************** SDHC REG DUMP END ********************\n");
+
+ DBG("************* SDHC VENDOR REG DUMPS START ***************\n");
+ DBG("SDCC_DLL_CONFIG_REG: 0x%08x\n", REG_READ32(host, SDCC_DLL_CONFIG_REG));
+ DBG("SDCC_VENDOR_SPECIFIC_FUNC: 0x%08x\n", REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC));
+ DBG("SDCC_REG_DLL_STATUS: 0x%08x\n", REG_READ32(host, SDCC_REG_DLL_STATUS));
+ DBG("************* SDHC VENDOR REG DUMPS END ***************\n");
+}
+
/*
* Function: sdhci reset
* Arg : Host structure & mask to write to reset register
@@ -138,6 +189,8 @@
host->cur_clk_rate = clk;
+ DBG("\n %s: clock_rate: %d clock_div:0x%08x\n", __func__, clk, div);
+
return 0;
}
@@ -203,6 +256,8 @@
voltage |= SDHCI_BUS_PWR_EN;
+ DBG("\n %s: voltage: 0x%02x\n", __func__, voltage);
+
REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG);
}
@@ -307,6 +362,8 @@
return 1;
}
+ DBG("\n %s: bus width:0x%04x\n", __func__, width);
+
REG_WRITE8(host, (reg | width), SDHCI_HOST_CTRL1_REG);
return 0;
@@ -386,6 +443,19 @@
if (int_status == SDHCI_INT_STS_CMD_COMPLETE)
break;
+ /*
+ * If Tuning is in progress ignore cmd crc & cmd end bit errors
+ */
+ if (host->tuning_in_progress)
+ {
+ err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG);
+ if ((err_status & SDHCI_CMD_CRC_MASK) || (err_status & SDHCI_DAT_END_BIT_MASK))
+ {
+ sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
+ return 0;
+ }
+ }
+
retry++;
udelay(500);
if (retry == SDHCI_MAX_CMD_RETRY) {
@@ -487,8 +557,9 @@
}
else if (sdhci_cmd_err_status(host))
{
- dprintf(CRITICAL, "Error: Command completed with errors\n");
ret = 1;
+ /* Dump sdhc registers on error */
+ sdhci_dumpregs(host);
}
/* Reset Command & Dat lines on error */
need_reset = 1;
@@ -529,7 +600,8 @@
sg_list[0].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA
| SDHCI_ADMA_TRANS_END;
- arch_clean_invalidate_cache_range((addr_t)sg_list, sizeof(struct desc_entry));
+ sg_len = 1;
+ table_len = sizeof(struct desc_entry);
} else {
/* Calculate the number of entries in desc table */
sg_len = len / SDHCI_ADMA_DESC_LINE_SZ;
@@ -582,6 +654,12 @@
arch_clean_invalidate_cache_range((addr_t)sg_list, table_len);
+ for (i = 0; i < sg_len; i++)
+ {
+ DBG("\n %s: sg_list: addr: 0x%08x len: 0x%04x attr: 0x%04x\n", __func__, sg_list[i].addr,
+ (sg_list[i].len ? sg_list[i].len : SDHCI_ADMA_DESC_LINE_SZ), sg_list[i].tran_att);
+ }
+
return sg_list;
}
@@ -656,6 +734,9 @@
uint32_t flags;
struct desc_entry *sg_list = NULL;
+ DBG("\n %s: START: cmd:0x%04d, arg:0x%08x, resp_type:0x%04x, data_present:%d\n",
+ __func__, cmd->cmd_index, cmd->argument, cmd->resp_type, cmd->data_present);
+
if (cmd->data_present)
ASSERT(cmd->data.data_ptr);
@@ -725,6 +806,23 @@
flags |= (cmd->data_present << SDHCI_CMD_DATA_PRESENT_BIT);
flags |= (cmd->cmd_type << SDHCI_CMD_CMD_TYPE_BIT);
+ /* Enable Command CRC & Index check for commands with response
+ * R1, R6, R7 & R1B. Also only CRC check for R2 response
+ */
+ switch(cmd->resp_type) {
+ case SDHCI_CMD_RESP_R1:
+ case SDHCI_CMD_RESP_R6:
+ case SDHCI_CMD_RESP_R7:
+ case SDHCI_CMD_RESP_R1B:
+ flags |= (1 << SDHCI_CMD_CRC_CHECK_BIT) | (1 << SDHCI_CMD_IDX_CHECK_BIT);
+ break;
+ case SDHCI_CMD_RESP_R2:
+ flags |= (1 << SDHCI_CMD_CRC_CHECK_BIT);
+ break;
+ default:
+ break;
+ };
+
/* Set the timeout value */
REG_WRITE8(host, SDHCI_CMD_TIMEOUT, SDHCI_TIMEOUT_REG);
@@ -775,6 +873,9 @@
if (sg_list)
free(sg_list);
+ DBG("\n %s: END: cmd:%04d, arg:0x%08x, resp:0x%08x 0x%08x 0x%08x 0x%08x\n",
+ __func__, cmd->cmd_index, cmd->argument, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
return 0;
}
@@ -798,6 +899,9 @@
caps[0] = REG_READ32(host, SDHCI_CAPS_REG1);
caps[1] = REG_READ32(host, SDHCI_CAPS_REG2);
+
+ DBG("\n %s: Host capability: cap1:0x%08x, cap2: 0x%08x\n", __func__, caps[0], caps[1]);
+
host->caps.base_clk_rate = (caps[0] & SDHCI_CLK_RATE_MASK) >> SDHCI_CLK_RATE_BIT;
host->caps.base_clk_rate *= 1000000;
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index fb278a7..e0d2790 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -151,6 +151,9 @@
/* Enable sdhc mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, SDHCI_HC_MODE_EN);
+ /* Set the FF_CLK_SW_RST_DIS to 1 */
+ RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), FF_CLK_SW_RST_DIS_START, FF_CLK_SW_RST_DIS_WIDTH, 1);
+
/*
* Reset the controller
*/
@@ -247,13 +250,16 @@
else if (host->cur_clk_rate <= 200000000)
reg_val = 0x7;
+ DBG("\n %s: DLL freq: 0x%08x\n", __func__, reg_val);
+
REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val);
}
/* Initialize DLL (Programmable Delay Line) */
-static void sdhci_msm_init_dll(struct sdhci_host *host)
+static uint32_t sdhci_msm_init_dll(struct sdhci_host *host)
{
uint32_t pwr_save = 0;
+ uint32_t timeout = SDHCI_DLL_TIMEOUT;
pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN;
@@ -276,17 +282,31 @@
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), SDCC_DLL_CONFIG_REG);
/* Write 1 to CLK_OUT_EN */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
- /* Wait for DLL_LOCK in DLL_STATUS register */
+ /* Wait for DLL_LOCK in DLL_STATUS register, wait time 50us */
while(!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT));
+ {
+ udelay(1);
+ timeout--;
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "%s: Failed to get DLL lock: 0x%08x\n", __func__, REG_READ32(host, SDCC_REG_DLL_STATUS));
+ return 1;
+ }
+ }
+
/* Set the powersave back on */
if (pwr_save)
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
+
+ return 0;
}
/* Configure DLL with delay value based on 'phase' */
-static void sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase)
+static uint32_t sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase)
{
uint32_t core_cfg = 0;
+ uint32_t timeout = SDHCI_DLL_TIMEOUT;
+
/* Gray code values from SWI */
uint32_t gray_code [] = { 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, 0x8 };
@@ -304,8 +324,17 @@
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
- /* Wait until CLK_OUT_EN is 1 */
- while(!(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN));
+ /* Wait until CLK_OUT_EN is 1, wait time 50us */
+ while(!(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN))
+ {
+ timeout--;
+ udelay(1);
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "%s: clk_out_en timed out: %08x\n", __func__, REG_READ32(host, SDCC_DLL_CONFIG_REG));
+ return 1;
+ }
+ }
core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
@@ -314,7 +343,7 @@
REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
- return;
+ return 0;
}
/*
@@ -427,17 +456,15 @@
uint32_t timeout;
uint32_t cdc_err;
+ DBG("\n CDCLP533 Calibration Start\n");
+
/* Reset & Initialize the DLL block */
- sdhci_msm_init_dll(host);
+ if (sdhci_msm_init_dll(host))
+ return 1;
/* Write the save phase */
- sdhci_msm_config_dll(host, host->msm_host->saved_phase);
-
- /* Configure the clocks needed for CDC */
- clock_config_cdc(host->msm_host->slot);
-
- /* Set the FF_CLK_SW_RST_DIS to 1 */
- REG_WRITE32(host, (REG_READ32(host, SDCC_MCI_HC_MODE) | FW_CLK_SW_RST_DIS), SDCC_MCI_HC_MODE);
+ if (sdhci_msm_config_dll(host, host->msm_host->saved_phase))
+ return 1;
/* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | CMD_DAT_TRACK_SEL), SDCC_DLL_CONFIG_REG);
@@ -492,7 +519,7 @@
REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CAL_TIMER_CFG0) | CDC_TIMER_EN), SDCC_CSR_CDC_CAL_TIMER_CFG0);
/* Wait for CALIBRATION_DONE in CDC_STATUS */
- timeout = 50;
+ timeout = CDC_STATUS_TIMEOUT;
while (!(REG_READ32(host, SDCC_CSR_CDC_STATUS0) & BIT(0)))
{
timeout--;
@@ -513,6 +540,8 @@
/* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) | START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+ DBG("\n CDCLP533 Calibration Done\n");
+
return 0;
}
@@ -531,6 +560,7 @@
uint32_t phase = 0;
uint32_t tuned_phase_cnt = 0;
int ret = 0;
+ int i;
struct sdhci_msm_data *msm_host;
msm_host = host->msm_host;
@@ -563,14 +593,22 @@
ASSERT(tuning_data);
/* Reset & Initialize the DLL block */
- sdhci_msm_init_dll(host);
+ if (sdhci_msm_init_dll(host))
+ {
+ ret = 1;
+ goto free;
+ }
while (phase < MAX_PHASES)
{
struct mmc_command cmd = {0};
/* configure dll to set phase delay */
- sdhci_msm_config_dll(host, phase);
+ if (sdhci_msm_config_dll(host, phase))
+ {
+ ret = 1;
+ goto free;
+ }
cmd.cmd_index = CMD21_SEND_TUNING_BLOCK;
cmd.argument = 0x0;
@@ -592,6 +630,12 @@
/* Find the appropriate tuned phase */
if (tuned_phase_cnt)
{
+ DBG("\n Tuned phase\n");
+ for (i = 0 ; i < tuned_phase_cnt ; i++)
+ {
+ DBG("%d\t", tuned_phases[i]);
+ }
+
ret = sdhci_msm_find_appropriate_phase(host, tuned_phases, tuned_phase_cnt);
if (ret < 0)
@@ -604,7 +648,10 @@
phase = (uint32_t) ret;
ret = 0;
- sdhci_msm_config_dll(host, phase);
+ DBG("\n: %s: Tuned Phase: 0x%08x\n", __func__, phase);
+
+ if (sdhci_msm_config_dll(host, phase))
+ goto free;
/* Save the tuned phase */
host->msm_host->saved_phase = phase;
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index 00a1872..dc1b141 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -2,6 +2,8 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -33,7 +35,7 @@
#include "smem.h"
-static struct smem *smem = (void *)(MSM_SHARED_BASE);
+static struct smem *smem;
/* buf MUST be 4byte aligned, and len MUST be a multiple of 8. */
unsigned smem_read_alloc_entry(smem_mem_type_t type, void *buf, int len)
@@ -42,6 +44,11 @@
unsigned *dest = buf;
unsigned src;
unsigned size;
+ uint32_t smem_addr = 0;
+
+ smem_addr = platform_get_smem_base_addr();
+
+ smem = (struct smem *)smem_addr;
if (((len & 0x3) != 0) || (((unsigned)buf & 0x3) != 0))
return 1;
@@ -59,7 +66,7 @@
if (size != (unsigned)((len + 7) & ~0x00000007))
return 1;
- src = MSM_SHARED_BASE + readl(&ainfo->offset);
+ src = smem_addr + readl(&ainfo->offset);
for (; len > 0; src += 4, len -= 4)
*(dest++) = readl(src);
@@ -74,6 +81,11 @@
unsigned *dest = buf;
unsigned src;
unsigned size = len;
+ uint32_t smem_addr = 0;
+
+ smem_addr = platform_get_smem_base_addr();
+
+ smem = (struct smem *)smem_addr;
if (((len & 0x3) != 0) || (((unsigned)buf & 0x3) != 0))
return 1;
@@ -85,7 +97,7 @@
if (readl(&ainfo->allocated) == 0)
return 1;
- src = MSM_SHARED_BASE + readl(&ainfo->offset) + offset;
+ src = smem_addr + readl(&ainfo->offset) + offset;
for (; size > 0; src += 4, size -= 4)
*(dest++) = readl(src);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 1e533f9..15874f0 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -45,6 +45,8 @@
#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
+#define SMEM_TARGET_INFO_IDENTIFIER 0x49494953
+
enum smem_ram_ptable_version
{
SMEM_RAM_PTABLE_VERSION_0,
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index f551a7a..0a2eca0 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2012, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -29,6 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include <debug.h>
+#include <kernel/thread.h>
#include <reg.h>
#include <sys/types.h>
#include <platform/iomap.h>
@@ -339,6 +340,8 @@
}
}
+ //We need to make sure the DM_NO_CHARS_FOR_TX&DM_TF are are programmed atmoically.
+ enter_critical_section();
/* We are here. FIFO is ready to be written. */
/* Write number of characters to be written */
writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
@@ -366,6 +369,7 @@
tx_char_left = num_of_chars - (i + 1) * 4;
tx_data = tx_data + num_chars_written;
}
+ exit_critical_section();
return MSM_BOOT_UART_DM_E_SUCCESS;
}
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index d341d62..197b16d 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -50,70 +50,70 @@
#define GPIO_STATE_HIGH 2
#define RESET_GPIO_SEQ_LEN 3
-static uint32_t dsi_pll_lock_status(uint32_t ctl_base)
+static uint32_t dsi_pll_lock_status(uint32_t pll_base)
{
uint32_t counter, status;
udelay(100);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
- status = readl(ctl_base + 0x02c0) & 0x01;
+ status = readl(pll_base + 0x00c0) & 0x01;
for (counter = 0; counter < 5 && !status; counter++) {
udelay(100);
- status = readl(ctl_base + 0x02c0) & 0x01;
+ status = readl(pll_base + 0x00c0) & 0x01;
}
return status;
}
-static uint32_t dsi_pll_enable_seq_b(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_b(uint32_t pll_base)
{
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- return dsi_pll_lock_status(ctl_base);
+ return dsi_pll_lock_status(pll_base);
}
-static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
{
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(250);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- return dsi_pll_lock_status(ctl_base);
+ return dsi_pll_lock_status(pll_base);
}
-static void dsi_pll_enable_seq(uint32_t ctl_base)
+static void dsi_pll_enable_seq(uint32_t pll_base)
{
uint32_t counter, status;
for (counter = 0; counter < 3; counter++) {
- status = dsi_pll_enable_seq_b(ctl_base);
+ status = dsi_pll_enable_seq_b(pll_base);
if (status)
break;
- status = dsi_pll_enable_seq_d(ctl_base);
+ status = dsi_pll_enable_seq_d(pll_base);
if (status)
break;
- status = dsi_pll_enable_seq_d(ctl_base);
+ status = dsi_pll_enable_seq_d(pll_base);
if(status)
break;
}
@@ -161,12 +161,14 @@
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
- mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(DSI0_PLL_BASE);
if (pinfo->mipi.dual_dsi &&
!(pinfo->mipi.broadcast)) {
- mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI1_BASE);
+ mdss_dsi_auto_pll_config(DSI1_PLL_BASE,
+ MIPI_DSI1_BASE, pll_data);
+ dsi_pll_enable_seq(DSI1_PLL_BASE);
}
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index a7ddfe0..5fd54f4 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -119,5 +119,4 @@
HW_PLATFORM_SUBTYPE_SKUG = 5,
};
-extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
#endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 71b46c5..9f1a873 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -78,6 +78,11 @@
HW_PLATFORM_SUBTYPE_SKUG = 5,
};
+enum mtp_cdp_subtype
+{
+ HW_PLATFORM_SUBTYPE_QVGA = 4,
+};
+
static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE };
@@ -280,6 +285,11 @@
*/
}
+bool target_is_cdp_qvga()
+{
+ return board_hardware_subtype() == HW_PLATFORM_SUBTYPE_QVGA;
+}
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
@@ -306,6 +316,8 @@
break;
case HW_PLATFORM_SUBTYPE_SKUG:
break;
+ case HW_PLATFORM_SUBTYPE_QVGA:
+ break;
default:
dprintf(CRITICAL, "Platform Subtype : %u is not supported\n", platform_subtype);
ASSERT(0);
diff --git a/target/msm8226/meminfo.c b/target/msm8226/meminfo.c
index e5a53d2..5de0ef0 100644
--- a/target/msm8226/meminfo.c
+++ b/target/msm8226/meminfo.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,6 +34,7 @@
#include <libfdt.h>
#include <platform/iomap.h>
#include <dev_tree.h>
+#include <target.h>
/* Funtion to add the ram partition entries into device tree.
* The function assumes that all the entire fixed memory regions should
@@ -77,10 +78,24 @@
void *target_get_scratch_address(void)
{
- return ((void *)SCRATCH_ADDR);
+ void *scratch_addr = 0;
+
+ if(target_is_cdp_qvga())
+ scratch_addr = (void *)SCRATCH_ADDR_128MAP;
+ else
+ scratch_addr = (void *)SCRATCH_ADDR_512MAP;
+
+ return scratch_addr;
}
unsigned target_get_max_flash_size(void)
{
- return (512 * 1024 * 1024);
+ uint32_t max_flash_size = 0;
+
+ if(target_is_cdp_qvga())
+ max_flash_size = SCRATCH_SIZE_128MAP;
+ else
+ max_flash_size = SCRATCH_SIZE_512MAP;
+
+ return max_flash_size;
}
diff --git a/target/msm8226/rules.mk b/target/msm8226/rules.mk
index d31f2bc..7bef55e 100755
--- a/target/msm8226/rules.mk
+++ b/target/msm8226/rules.mk
@@ -5,7 +5,7 @@
PLATFORM := msm8226
-MEMBASE := 0x0FF00000 # SDRAM
+MEMBASE := 0x07F00000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x00000
@@ -14,6 +14,10 @@
KERNEL_ADDR := BASE_ADDR+0x00008000
RAMDISK_ADDR := BASE_ADDR+0x01000000
SCRATCH_ADDR := 0x10000000
+SCRATCH_ADDR_128MAP := 0x04200000
+SCRATCH_ADDR_512MAP := 0x10000000
+SCRATCH_SIZE_128MAP := 0x03D00000
+SCRATCH_SIZE_512MAP := 0x20000000
DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
@@ -35,7 +39,11 @@
TAGS_ADDR=$(TAGS_ADDR) \
KERNEL_ADDR=$(KERNEL_ADDR) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
- SCRATCH_ADDR=$(SCRATCH_ADDR)
+ SCRATCH_ADDR=$(SCRATCH_ADDR) \
+ SCRATCH_ADDR_128MAP=$(SCRATCH_ADDR_128MAP) \
+ SCRATCH_ADDR_512MAP=$(SCRATCH_ADDR_512MAP) \
+ SCRATCH_SIZE_128MAP=$(SCRATCH_SIZE_128MAP) \
+ SCRATCH_SIZE_512MAP=$(SCRATCH_SIZE_512MAP)
OBJS += \
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 1b5703d..b26d3e6 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -55,145 +55,145 @@
.fdbck = 0x1
};
-static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
{
uint32_t i = 0;
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
if (i != 0)
- writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
+ writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
udelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
}
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
@@ -225,14 +225,14 @@
return 0;
}
-static void dsi_pll_enable_seq(uint32_t ctl_base)
+static void dsi_pll_enable_seq(uint32_t pll_base)
{
- if (dsi_pll_enable_seq_m(ctl_base)) {
- } else if (dsi_pll_enable_seq_d(ctl_base)) {
- } else if (dsi_pll_enable_seq_d(ctl_base)) {
- } else if (dsi_pll_enable_seq_f1(ctl_base)) {
- } else if (dsi_pll_enable_seq_c(ctl_base)) {
- } else if (dsi_pll_enable_seq_e(ctl_base)) {
+ if (dsi_pll_enable_seq_m(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_f1(pll_base)) {
+ } else if (dsi_pll_enable_seq_c(pll_base)) {
+ } else if (dsi_pll_enable_seq_e(pll_base)) {
} else {
dprintf(CRITICAL, "Not able to enable the pll\n");
}
@@ -260,8 +260,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
diff --git a/target/msm8610/include/target/display.h b/target/msm8610/include/target/display.h
index 5e9fa26..1d7f963 100644
--- a/target/msm8610/include/target/display.h
+++ b/target/msm8610/include/target/display.h
@@ -111,5 +111,4 @@
#define MIPI_VSYNC_BACK_PORCH_LINES 10
#define MIPI_VSYNC_FRONT_PORCH_LINES 12
-extern int mdss_dsi_v2_phy_init(struct mipi_dsi_panel_config *);
#endif
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
new file mode 100644
index 0000000..632241b
--- /dev/null
+++ b/target/msm8916/include/target/display.h
@@ -0,0 +1,114 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM8916_DISPLAY_H
+#define _TARGET_MSM8916_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 25, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = {
+ "msmgpio", 98, 3, 1, 0, 1
+};
+
+static struct gpio_pin te_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin pwm_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 17, 0, 2850000, 100000, 100, 0, 0, 0, 0},
+ { "vddio", 6, 0, 1800000, 100000, 100, 0, 0, 0, 0},
+ { "vdda", 2, 1, 1200000, 100000, 100, 0, 20, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR 0x83200000
+
+#define MIPI_HSYNC_PULSE_WIDTH 12
+#define MIPI_HSYNC_BACK_PORCH_DCLK 32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 144
+
+#define MIPI_VSYNC_PULSE_WIDTH 4
+#define MIPI_VSYNC_BACK_PORCH_LINES 3
+#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+
+#endif
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index de53133..afc63ac 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -320,6 +320,47 @@
writel(val, USB_USBCMD);
}
+uint8_t target_panel_auto_detect_enabled()
+{
+ uint8_t ret = 0;
+ uint32_t hw_subtype = board_hardware_subtype();
+
+ switch(board_hardware_id()) {
+ case HW_PLATFORM_SURF:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+static uint8_t splash_override;
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ uint8_t splash_screen = 0;
+ if (!splash_override) {
+ switch (board_hardware_id()) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_SURF:
+ splash_screen = 1;
+ break;
+ default:
+ splash_screen = 0;
+ break;
+ }
+ dprintf(SPEW, "Target_cont_splash=%d\n", splash_screen);
+ }
+ return splash_screen;
+}
+
+void target_force_cont_splash_disable(uint8_t override)
+{
+ splash_override = override;
+}
+
void target_usb_stop(void)
{
/* Disable VBUS mimicing in the controller. */
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
new file mode 100644
index 0000000..31e8db2
--- /dev/null
+++ b/target/msm8916/oem_panel.c
@@ -0,0 +1,233 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_jdi_1080p_video.h"
+#include "include/panel_nt35590_720p_video.h"
+#include "include/panel_nt35590_720p_cmd.h"
+
+#define DISPLAY_MAX_PANEL_DETECTION 2
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+static uint32_t auto_pan_loop = 0;
+
+enum {
+JDI_1080P_VIDEO_PANEL,
+NT35590_720P_VIDEO_PANEL,
+NT35590_720P_CMD_PANEL,
+UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
+ {"nt35590_720p_video", NT35590_720P_VIDEO_PANEL},
+ {"nt35590_720p_cmd", NT35590_720P_CMD_PANEL},
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep their panel specific off instructions
+ * in this function
+ */
+ return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ bool ret = true;
+
+ switch (panel_id) {
+ case JDI_1080P_VIDEO_PANEL:
+ panelstruct->paneldata = &jdi_1080p_video_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 1;
+ panelstruct->panelres = &jdi_1080p_video_panel_res;
+ panelstruct->color = &jdi_1080p_video_color;
+ panelstruct->videopanel = &jdi_1080p_video_video_panel;
+ panelstruct->commandpanel = &jdi_1080p_video_command_panel;
+ panelstruct->state = &jdi_1080p_video_state;
+ panelstruct->laneconfig = &jdi_1080p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_1080p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &jdi_1080p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = jdi_1080p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_1080P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_1080p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = JDI_1080P_VIDEO_SIGNATURE;
+ break;
+ case NT35590_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35590_720p_video_panel_data;
+ panelstruct->panelres = &nt35590_720p_video_panel_res;
+ panelstruct->color = &nt35590_720p_video_color;
+ panelstruct->videopanel = &nt35590_720p_video_video_panel;
+ panelstruct->commandpanel = &nt35590_720p_video_command_panel;
+ panelstruct->state = &nt35590_720p_video_state;
+ panelstruct->laneconfig = &nt35590_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35590_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &nt35590_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35590_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35590_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35590_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = NT35590_720P_VIDEO_SIGNATURE;
+ break;
+ case NT35590_720P_CMD_PANEL:
+ panelstruct->paneldata = &nt35590_720p_cmd_panel_data;
+ panelstruct->panelres = &nt35590_720p_cmd_panel_res;
+ panelstruct->color = &nt35590_720p_cmd_color;
+ panelstruct->videopanel = &nt35590_720p_cmd_video_panel;
+ panelstruct->commandpanel = &nt35590_720p_cmd_command_panel;
+ panelstruct->state = &nt35590_720p_cmd_state;
+ panelstruct->laneconfig = &nt35590_720p_cmd_lane_config;
+ panelstruct->paneltiminginfo = &nt35590_720p_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_cmd_panel_reset_seq;
+ panelstruct->backlightinfo = &nt35590_720p_cmd_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35590_720p_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35590_720P_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35590_720p_cmd_timings, TIMING_SIZE);
+ pinfo->mipi.signature = NT35590_720P_CMD_SIGNATURE;
+ break;
+ default:
+ case UNKNOWN_PANEL:
+ memset(panelstruct, 0, sizeof(struct panel_struct));
+ memset(pinfo->mipi.panel_cmds, 0, sizeof(struct mipi_dsi_cmd));
+ pinfo->mipi.num_of_panel_cmds = 0;
+ memset(phy_db->timing, 0, TIMING_SIZE);
+ ret = false;
+ break;
+ }
+ return ret;
+}
+
+uint32_t oem_panel_max_auto_detect_panels()
+{
+ return target_panel_auto_detect_enabled() ?
+ DISPLAY_MAX_PANEL_DETECTION : 0;
+}
+
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ int32_t panel_override_id;
+ bool ret = true;
+
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_SURF:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ switch (auto_pan_loop) {
+ case 0:
+ panel_id = JDI_1080P_VIDEO_PANEL;
+ break;
+ case 1:
+ panel_id = NT35590_720P_VIDEO_PANEL;
+ break;
+ default:
+ panel_id = UNKNOWN_PANEL;
+ ret = false;
+ dprintf(CRITICAL, "Unknown panel\n");
+ return ret;
+ }
+ auto_pan_loop++;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n",
+ hw_id);
+ return false;
+ }
+
+panel_init:
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8916/rules.mk b/target/msm8916/rules.mk
index 2f24cbe..d8085cd 100644
--- a/target/msm8916/rules.mk
+++ b/target/msm8916/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8916
@@ -10,11 +11,16 @@
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x90000000
+DEFINES += DISPLAY_SPLASH_SCREEN=1
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
MODULES += \
dev/keys \
lib/ptable \
dev/pmic/pm8x41 \
- lib/libfdt
+ lib/libfdt \
+ dev/gcdb/display
DEFINES += \
MEMSIZE=$(MEMSIZE) \
@@ -25,4 +31,6 @@
OBJS += \
$(LOCAL_DIR)/init.o \
- $(LOCAL_DIR)/meminfo.o
+ $(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
new file mode 100644
index 0000000..f5acd1c
--- /dev/null
+++ b/target/msm8916/target_display.c
@@ -0,0 +1,372 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <pm8x41_wled.h>
+#include <board.h>
+#include <mdp5.h>
+#include <scm.h>
+#include <platform/gpio.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define DDR_LDO_ID 2
+#define QFPROM_LDO_ID 6
+
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+
+static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
+{
+ uint32_t i = 0;
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+ for (i = 0; (i < 4) && !pll_locked; i++) {
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
+ if (i != 0)
+ writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
+ udelay(1);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+ }
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
+
+ return pll_locked;
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ struct pm8x41_mpp mpp;
+ int rc;
+
+ mpp.base = PM8x41_MMP4_BASE;
+ mpp.vin = MPP_VIN0;
+ if (enable) {
+ pm_pwm_enable(false);
+ rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+ if (rc < 0)
+ mpp.mode = MPP_HIGH;
+ else {
+ mpp.mode = MPP_DTEST1;
+ pm_pwm_enable(true);
+ }
+ pm8x41_config_output_mpp(&mpp);
+ pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+ } else {
+ pm_pwm_enable(false);
+ pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+ }
+ mdelay(20);
+ return 0;
+}
+
+static void dsi_pll_enable_seq(uint32_t pll_base)
+{
+ if (dsi_pll_enable_seq_m(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_f1(pll_base)) {
+ } else if (dsi_pll_enable_seq_c(pll_base)) {
+ } else if (dsi_pll_enable_seq_e(pll_base)) {
+ } else {
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ }
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+ int32_t ret = 0;
+ struct mdss_dsi_pll_config *pll_data;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
+
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mdss_bus_clocks_enable();
+ mdp_clock_enable();
+ ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+ if (ret) {
+ dprintf(CRITICAL,
+ "%s: Failed to restore MDP security configs",
+ __func__);
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(0);
+ return ret;
+ }
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(DSI0_PLL_BASE);
+ gcc_dsi_clocks_enable(pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
+ } else if(!target_cont_splash_screen()) {
+ gcc_dsi_clocks_disable();
+ mdp_clock_disable();
+ mdss_bus_clocks_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return 0;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
+{
+ int ret = NO_ERROR;
+ if (enable) {
+ if (pinfo->mipi.use_enable_gpio) {
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength,
+ enable_gpio.pin_state);
+
+ gpio_set_dir(enable_gpio.pin_id, 2);
+ }
+
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ bkl_gpio.pin_direction, bkl_gpio.pin_pull,
+ bkl_gpio.pin_strength, bkl_gpio.pin_state);
+ gpio_set_dir(bkl_gpio.pin_id, 2);
+
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+
+ gpio_set_dir(reset_gpio.pin_id, 2);
+
+ /* reset */
+ for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+ if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW);
+ else
+ gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH);
+ mdelay(resetseq->sleep[i]);
+ }
+ } else if(!target_cont_splash_screen()) {
+ gpio_set_dir(reset_gpio.pin_id, 0);
+ if (pinfo->mipi.use_enable_gpio)
+ gpio_set_dir(enable_gpio.pin_id, 0);
+ }
+
+ return ret;
+}
+
+int target_ldo_ctrl(uint8_t enable)
+{
+ uint32_t ret = NO_ERROR;
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
+
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ dprintf(SPEW, "Setting %i\n",
+ ldo_entry_array[ldocounter].ldo_id);
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
+
+
+ /* Set voltage during power on */
+ if (enable) {
+ /* TODO: Set the LDO voltage before enabling it */
+ pm8x41_ldo_control(&ldo_entry, enable);
+
+ } else if(!target_cont_splash_screen() &&
+ ldo_entry_array[ldocounter].ldo_id != DDR_LDO_ID &&
+ ldo_entry_array[ldocounter].ldo_id != QFPROM_LDO_ID) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
+ }
+
+ return ret;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+ return gcdb_display_cmdline_arg(pbuf, buf_size);
+}
+
+void target_display_init(const char *panel_name)
+{
+ uint32_t panel_loop = 0;
+ uint32_t ret = 0;
+ do {
+ ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
+ if (!ret || ret == ERR_NOT_SUPPORTED) {
+ break;
+ } else {
+ target_force_cont_splash_disable(true);
+ msm_display_off();
+ target_force_cont_splash_disable(false);
+ }
+ } while (++panel_loop <= oem_panel_max_auto_detect_panels());
+}
+
+void target_display_shutdown(void)
+{
+ gcdb_display_shutdown();
+}
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index db177d0..420636d 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -109,6 +109,4 @@
#define HDMI_PANEL_NAME "hdmi"
#define HDMI_CONTROLLER_STRING "hdmi:0"
-extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-
#endif
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index b85c096..b3ee411 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -522,17 +522,6 @@
else
pm8x41_reset_configure(reset_type);
- /* Disable Watchdog Debug.
- * Required becuase of a H/W bug which causes the system to
- * reset partially even for non watchdog resets.
- */
- writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
-
- dsb();
-
- /* Wait until the write takes effect. */
- while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
-
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 7950979..1499845 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -58,70 +58,70 @@
.full_current_scale = 0x19
};
-static uint32_t dsi_pll_lock_status(uint32_t ctl_base)
+static uint32_t dsi_pll_lock_status(uint32_t pll_base)
{
uint32_t counter, status;
udelay(100);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
- status = readl(ctl_base + 0x02c0) & 0x01;
+ status = readl(pll_base + 0x00c0) & 0x01;
for (counter = 0; counter < 5 && !status; counter++) {
udelay(100);
- status = readl(ctl_base + 0x02c0) & 0x01;
+ status = readl(pll_base + 0x00c0) & 0x01;
}
return status;
}
-static uint32_t dsi_pll_enable_seq_b(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_b(uint32_t pll_base)
{
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(500);
- return dsi_pll_lock_status(ctl_base);
+ return dsi_pll_lock_status(pll_base);
}
-static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
{
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(250);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0220); /* GLB CFG */
udelay(500);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0220); /* GLB CFG */
udelay(500);
- return dsi_pll_lock_status(ctl_base);
+ return dsi_pll_lock_status(pll_base);
}
-static void dsi_pll_enable_seq(uint32_t ctl_base)
+static void dsi_pll_enable_seq(uint32_t pll_base)
{
uint32_t counter, status;
for (counter = 0; counter < 3; counter++) {
- status = dsi_pll_enable_seq_b(ctl_base);
+ status = dsi_pll_enable_seq_b(pll_base);
if (status)
break;
- status = dsi_pll_enable_seq_d(ctl_base);
+ status = dsi_pll_enable_seq_d(pll_base);
if (status)
break;
- status = dsi_pll_enable_seq_d(ctl_base);
+ status = dsi_pll_enable_seq_d(pll_base);
if(status)
break;
}
@@ -219,12 +219,14 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(DSI0_PLL_BASE);
if (panel.panel_info.mipi.dual_dsi &&
!(panel.panel_info.mipi.broadcast)) {
- mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI1_BASE);
+ mdss_dsi_auto_pll_config(DSI1_PLL_BASE,
+ MIPI_DSI1_BASE, pll_data);
+ dsi_pll_enable_seq(DSI1_PLL_BASE);
}
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,