Merge "platform: msm_shared: Add soc ids for variants of MSM8x26."
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index c929bab..9ed0d4d 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -351,8 +351,7 @@
return offset;
/* Try to place the new node after the parent's properties and all the sub nodes already present. */
- fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
- count++; /* Track the BIGIN_NODEs */
+ tag = fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
do {
if (tag == FDT_BEGIN_NODE)
count++;
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 215e1d9..3bc2610 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -409,7 +409,7 @@
}
/* Initialize all clocks needed by Display */
-void mmss_clock_init(void)
+void mmss_clock_init(uint32_t dsi_pixel0_cfg_rcgr)
{
int ret;
@@ -451,7 +451,7 @@
}
/* Configure Pixel clock */
- writel(0x100, DSI_PIXEL0_CFG_RCGR);
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
writel(0x1, DSI_PIXEL0_CMD_RCGR);
writel(0x1, DSI_PIXEL0_CBCR);
}
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index cb96f00..ffafbf7 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -68,6 +68,9 @@
#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI0_PHY_PLL_OUT BIT(8)
+#define PIXEL_SRC_DIV_1_5 BIT(1)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index c7236bf..2fd66c5 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -282,6 +282,80 @@
}
+int mdss_sharp_dsi_uniphy_pll_config(void)
+{
+ mdss_dsi_phy_sw_reset();
+
+ /* Configuring the Pll Vco clk to 500 Mhz */
+
+ /* Loop filter resistance value */
+ writel(0x08, MIPI_DSI_BASE + 0x022c);
+ /* Loop filter capacitance values : c1 and c2 */
+ writel(0x70, MIPI_DSI_BASE + 0x0230);
+ writel(0x15, MIPI_DSI_BASE + 0x0234);
+
+ writel(0x02, MIPI_DSI_BASE + 0x0208); /* ChgPump */
+ writel(0x00, MIPI_DSI_BASE + 0x0204); /* postDiv1 */
+ writel(0x03, MIPI_DSI_BASE + 0x0224); /* postDiv2 */
+ writel(0x0b, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
+
+ writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
+ writel(0x66, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
+ writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+
+ writel(0x0c, MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
+ writel(0x55, MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
+ writel(0x05, MIPI_DSI_BASE + 0x0244); /* SDM CFG3 */
+ writel(0x00, MIPI_DSI_BASE + 0x0248); /* SDM CFG4 */
+
+ udelay(10);
+
+ writel(0x01, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
+ writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
+ writel(0x01, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
+ writel(0x02, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
+ writel(0x00, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
+
+ writel(0x60, MIPI_DSI_BASE + 0x028c); /* CAL CFG8 */
+ writel(0xf4, MIPI_DSI_BASE + 0x0294); /* CAL CFG10 */
+ writel(0x01, MIPI_DSI_BASE + 0x0298); /* CAL CFG11 */
+ writel(0x0a, MIPI_DSI_BASE + 0x026c); /* CAL CFG0 */
+ writel(0x30, MIPI_DSI_BASE + 0x0284); /* CAL CFG6 */
+ writel(0x00, MIPI_DSI_BASE + 0x0288); /* CAL CFG7 */
+ writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
+ writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
+
+ mdss_dsi_uniphy_pll_sw_reset();
+ writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting();
+
+ while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01)) {
+ mdss_dsi_uniphy_pll_sw_reset();
+ writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+ mdelay(2);
+ mdss_dsi_uniphy_pll_lock_detect_setting();
+ }
+
+}
+
int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mdss_dsi_phy_ctrl *pd;
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index fb9da87..45f900a 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -527,6 +527,7 @@
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_DRAGON:
dprintf(SPEW, "Target_cont_splash=1\n");
return 1;
break;
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 5968b88..883cead 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -35,6 +35,7 @@
#include <board.h>
#include <mdp5.h>
#include <platform/gpio.h>
+#include <platform/clock.h>
#include <target/display.h>
static struct msm_fb_panel_data panel;
@@ -43,6 +44,7 @@
extern int msm_display_init(struct msm_fb_panel_data *pdata);
extern int msm_display_off();
extern int mdss_dsi_uniphy_pll_config(void);
+extern int mdss_sharp_dsi_uniphy_pll_config(void);
static int msm8974_backlight_on()
{
@@ -68,7 +70,7 @@
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_uniphy_pll_config();
- mmss_clock_init();
+ mmss_clock_init(DSI0_PHY_PLL_OUT);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable();
@@ -79,6 +81,23 @@
return 0;
}
+static int msm8974_mdss_sharp_dsi_panel_clock(uint8_t enable)
+{
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mdp_clock_init();
+ mdss_sharp_dsi_uniphy_pll_config();
+ mmss_clock_init(DSI0_PHY_PLL_OUT);
+ } else if (!target_cont_splash_screen()) {
+ /* Add here for continuous splash */
+ mmss_clock_disable();
+ mdp_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return 0;
+}
+
/* Pull DISP_RST_N high to get panel out of reset */
static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
{
@@ -166,6 +185,18 @@
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
break;
+ case HW_PLATFORM_DRAGON:
+ mipi_sharp_video_qhd_init(&(panel.panel_info));
+ panel.clk_func = msm8974_mdss_sharp_dsi_panel_clock;
+ panel.power_func = msm8974_mipi_panel_power;
+ panel.fb.base = MIPI_FB_ADDR;
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB888;
+ panel.mdp_rev = MDP_REV_50;
+ break;
default:
return;
};