platform: msm_shared: cleanup register programming of EOT_PACKET_CTRL
The current register programming logic of EOT_PACKET_CTRL can cause
issues for video mode panels where tx_eot_append bit that gets
programmed during mdss_dsi_host_init gets reset to 0x0 during
mdss_dsi_video_mode_config. For command mode panels, EOT_PACKET_CTRL
is being programmed to 0x1 always. Also, rx_eot_append bit programming
is not taken care at present. Cleanup the register programming of
EOT_PACKET_CTRL to take care of this.
Change-Id: Ia4fe30c37e1c3ba7292ed86404016558d031d660
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 44fb235..68d784d 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -405,6 +405,10 @@
tmp |= BIT(16); /* enable burst mode */
writel(tmp, mipi->sctl_base + 0x01b8);
}
+
+ writel(((mipi->rx_eot_ignore & 0x1) << 4) |
+ (mipi->tx_eot_append & 0x1),
+ mipi->sctl_base + EOT_PACKET_CTRL);
}
writel(0x0001, mipi->ctl_base + SOFT_RESET);
@@ -430,8 +434,8 @@
writel(tmp, mipi->ctl_base + 0x01b8);
}
- if ((mipi->mode == DSI_VIDEO_MODE) && mipi->tx_eot_append)
- writel(0x1, mipi->ctl_base + EOT_PACKET_CTRL);
+ writel(((mipi->rx_eot_ignore & 0x1) << 4) | (mipi->tx_eot_append & 0x1),
+ mipi->ctl_base + EOT_PACKET_CTRL);
#endif
@@ -596,8 +600,6 @@
mdp_get_revision() != MDP_REV_305)
writel(0x1, ctl_base + TIMING_FLUSH);
- writel(0x0, ctl_base + EOT_PACKET_CTRL);
-
writel(0x00000100, ctl_base + MISR_VIDEO_CTRL);
if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) {
@@ -802,7 +804,6 @@
ctl_base + CTRL);
writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL);
writel(0x10000000, ctl_base + MISR_CMD_CTRL);
- writel(0x1, ctl_base + EOT_PACKET_CTRL);
#endif
return 0;
}