Merge "platform: msm_shared: add check on ext csd variable"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index fdf4abb..531ff4e 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1069,7 +1069,8 @@
* 4. Sanity Check on kernel_addr and ramdisk_addr and copy data.
*/
- dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
/* Read image without signature */
@@ -1079,7 +1080,9 @@
return -1;
}
- dprintf(INFO, "Loading boot image (%d): done\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
/* Authenticate Kernel */
@@ -1409,7 +1412,8 @@
imagesize_actual = (page_size + kernel_actual + ramdisk_actual);
#endif
- dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"),imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
/* Read image without signature */
@@ -1419,7 +1423,8 @@
return -1;
}
- dprintf(INFO, "Loading boot image (%d): done\n", imagesize_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"), imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
offset = imagesize_actual;
@@ -1463,8 +1468,9 @@
ramdisk_actual = ROUND_TO_PAGE(hdr->ramdisk_size, page_mask);
second_actual = ROUND_TO_PAGE(hdr->second_size, page_mask);
- dprintf(INFO, "Loading boot image (%d): start\n",
- kernel_actual + ramdisk_actual);
+ dprintf(INFO, "Loading (%s) image (%d): start\n",
+ (!boot_into_recovery ? "boot" : "recovery"), kernel_actual + ramdisk_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_START);
if (flash_read(ptn, offset, (void *)hdr->kernel_addr, kernel_actual)) {
@@ -1479,8 +1485,9 @@
}
offset += ramdisk_actual;
- dprintf(INFO, "Loading boot image (%d): done\n",
- kernel_actual + ramdisk_actual);
+ dprintf(INFO, "Loading (%s) image (%d): done\n",
+ (!boot_into_recovery ? "boot" : "recovery"), kernel_actual + ramdisk_actual);
+
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
if(hdr->second_size != 0) {
@@ -3270,6 +3277,8 @@
#endif
dprintf(SPEW, "Display Init: Start\n");
#if ENABLE_WBC
+ /* Wait if the display shutdown is in progress */
+ while(pm_app_display_shutdown_in_prgs());
if (!pm_appsbl_display_init_done())
target_display_init(device.display_panel);
else
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
index 15797a1..96441e2 100644
--- a/app/aboot/recovery.c
+++ b/app/aboot/recovery.c
@@ -592,6 +592,10 @@
if (scratch_addr != buf)
memcpy(scratch_addr, buf, size);
+
+ /* Set Lun for misc partition */
+ mmc_set_lun(partition_get_lun(index));
+
if (mmc_write(ptn + offset, aligned_size, (unsigned int *)scratch_addr))
{
dprintf(CRITICAL, "Writing MMC failed\n");
diff --git a/dev/gcdb/display/fastboot_oem_display.h b/dev/gcdb/display/fastboot_oem_display.h
index 9dd8b5c..b0a1371 100644
--- a/dev/gcdb/display/fastboot_oem_display.h
+++ b/dev/gcdb/display/fastboot_oem_display.h
@@ -76,6 +76,7 @@
{"jdi_fhd_video", "qcom,mdss_dsi_jdi_fhd_video", false},
{"jdi_qhd_dualdsi_cmd", "qcom,mdss_dsi_jdi_qhd_dualmipi_cmd", true},
{"jdi_qhd_dualdsi_video", "qcom,dsi_jdi_qhd_video", true},
+ {"jdi_4k_dualdsi_video_nofbc", "qcom,dsi_jdi_4k_nofbc_video", true},
{"nt35521_720p_video", "qcom,mdss_dsi_nt35521_720p_video", false},
{"nt35521_wxga_video", "qcom,mdss_dsi_nt35521_wxga_video", false},
{"nt35590_720p_cmd", "qcom,mdss_dsi_nt35590_720p_cmd", false},
@@ -101,6 +102,8 @@
{"truly_1080p_video", "qcom,mdss_dsi_truly_1080p_video", false},
{"truly_wvga_cmd", "qcom,mdss_dsi_truly_wvga_cmd", false},
{"truly_wvga_video", "qcom,mdss_dsi_truly_wvga_video", false},
+ {"adv16", "qcom,mdss_dsi_adv7533_1080p", false},
+ {"adv4", "qcom,mdss_dsi_adv7533_720p", false},
};
struct sim_lookup_list lookup_sim[] = {
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 1d2db47..b78cecc 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -42,6 +42,7 @@
uint32_t h_period = 0, v_period = 0;
uint32_t width = pinfo->xres;
struct dsc_desc *dsc = NULL;
+ int bpp_lane;
if (pinfo->mipi.dual_dsi)
width /= 2;
@@ -62,19 +63,22 @@
pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width +
pinfo->lcdc.yres_pad;
+ bpp_lane = pinfo->bpp / pinfo->mipi.num_of_lanes;
+
/*
* If a bit clock rate is not specified, calculate it based
* on panel parameters
*/
if (pinfo->mipi.bitclock == 0)
pll_data.bit_clock = (h_period * v_period *
- pinfo->mipi.frame_rate * pinfo->bpp) /
- pinfo->mipi.num_of_lanes;
+ pinfo->mipi.frame_rate * bpp_lane);
else
pll_data.bit_clock = pinfo->mipi.bitclock;
- pll_data.pixel_clock = (pll_data.bit_clock * pinfo->mipi.num_of_lanes) /
- pinfo->bpp;
+ pll_data.pixel_clock = (pll_data.bit_clock / bpp_lane);
+
+ dprintf(SPEW, "%s: bit_clk=%d pix_clk=%d\n", __func__,
+ pll_data.bit_clock, pll_data.pixel_clock);
pll_data.byte_clock = pll_data.bit_clock >> 3;
@@ -273,6 +277,11 @@
return ERROR;
}
+ pll_data.vco_clock = pll_data.bit_clock * pll_data.ndiv *
+ pll_data.n1div;
+
+ rate = pll_data.vco_clock;
+
rate /= pll_data.n1div;
rate /= FIX_PIXEL_CLOCK_DIV;
@@ -287,7 +296,6 @@
__func__, pll_data.n2div);
return ERROR;
}
- pll_data.vco_clock = pll_data.bit_clock * pll_data.ndiv * pll_data.n1div;
dprintf(SPEW, "%s: vco:%u n1div:%d n2div:%d bit_clk:%u pixel_clk:%u\n",
__func__, pll_data.vco_clock, pll_data.n1div, pll_data.n2div,
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index d4fe865..6035ec3 100644
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -408,20 +408,51 @@
return panelstruct;
}
+static void mdss_dsi_check_swap_status(void)
+{
+ char *panel_dest, *dsi_controller;
+ struct oem_panel_data *oem_data = mdss_dsi_get_oem_data_ptr();
+
+ if (!oem_data->swap_dsi_ctrl)
+ return;
+
+ if (panelstruct.paneldata->panel_operating_mode &
+ (SPLIT_DISPLAY_FLAG | DUAL_DSI_FLAG)) {
+ dprintf(CRITICAL, "DSI swap invalid for split DSI panel!\n");
+ return;
+ }
+
+ /* Swap the panel destination and use appropriate PLL */
+ if (!strcmp(panelstruct.paneldata->panel_destination, "DISPLAY_1")) {
+ panel_dest = "DISPLAY_2";
+ dsi_controller = "dsi:1:";
+ panelstruct.paneldata->panel_operating_mode |= USE_DSI1_PLL_FLAG;
+ } else {
+ panel_dest = "DISPLAY_1";
+ dsi_controller = "dsi:0:";
+ panelstruct.paneldata->panel_operating_mode &= ~USE_DSI1_PLL_FLAG;
+ }
+ panelstruct.paneldata->panel_destination = panel_dest;
+ panelstruct.paneldata->panel_controller = dsi_controller;
+}
+
static void mdss_dsi_set_pll_src(void)
{
struct oem_panel_data *oem_data = mdss_dsi_get_oem_data_ptr();
- if (panelstruct.paneldata->panel_operating_mode & USE_DSI1_PLL_FLAG)
+ /* Set PLL_SRC to PLL1 for non dual-DSI cases only */
+ if (!is_dsi_config_dual() &&
+ (panelstruct.paneldata->panel_operating_mode &
+ USE_DSI1_PLL_FLAG))
oem_data->dsi_pll_src = DSI_PLL1;
- if (strcmp(oem_data->sec_panel, "")) {
+ if (is_dsi_config_dual()) {
if (oem_data->dsi_pll_src != DSI_PLL_DEFAULT) {
dprintf(CRITICAL, "Dual DSI config detected!"
"Use default PLL\n");
oem_data->dsi_pll_src = DSI_PLL_DEFAULT;
}
- } else if (panelstruct.paneldata->slave_panel_node_id) {
+ } else if (is_dsi_config_split()) {
if((dsi_video_mode_phy_db.pll_type != DSI_PLL_TYPE_THULIUM)
&& (oem_data->dsi_pll_src == DSI_PLL1)) {
dprintf(CRITICAL, "Split DSI on 28nm/20nm!"
@@ -441,10 +472,9 @@
if (oem_data->dsi_pll_src == DSI_PLL1)
panelstruct.paneldata->panel_operating_mode |=
USE_DSI1_PLL_FLAG;
- else
+ else if (oem_data->dsi_pll_src == DSI_PLL0)
panelstruct.paneldata->panel_operating_mode &=
~USE_DSI1_PLL_FLAG;
-
}
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base)
@@ -458,6 +488,7 @@
if (pan_type == PANEL_TYPE_DSI) {
target_dsi_phy_config(&dsi_video_mode_phy_db);
+ mdss_dsi_check_swap_status();
mdss_dsi_set_pll_src();
if (dsi_panel_init(&(panel.panel_info), &panelstruct)) {
dprintf(CRITICAL, "DSI panel init failed!\n");
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 088aa05..aaed691 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -72,6 +72,7 @@
char sec_panel[MAX_PANEL_ID_LEN];
bool cont_splash;
bool skip;
+ bool swap_dsi_ctrl;
uint32_t sim_mode;
char dsi_config[DSI_CFG_SIZE];
uint32_t dsi_pll_src;
@@ -83,4 +84,30 @@
DSI_PLL1,
};
+static inline bool is_dsi_config_split(void)
+{
+ struct panel_struct panelstruct = mdss_dsi_get_panel_data();
+
+ return panelstruct.paneldata->panel_node_id &&
+ panelstruct.paneldata->slave_panel_node_id &&
+ (panelstruct.paneldata->panel_operating_mode & (DUAL_DSI_FLAG |
+ SPLIT_DISPLAY_FLAG | DST_SPLIT_FLAG));
+}
+
+static inline bool is_dsi_config_dual(void)
+{
+ struct oem_panel_data *oem_data = mdss_dsi_get_oem_data_ptr();
+
+ return !is_dsi_config_split() && oem_data->sec_panel &&
+ strcmp(oem_data->sec_panel, "");
+}
+
+static inline bool is_dsi_config_single()
+{
+ struct panel_struct panelstruct = mdss_dsi_get_panel_data();
+
+ return panelstruct.paneldata->panel_node_id && !is_dsi_config_split()
+ && !is_dsi_config_dual();
+}
+
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/gcdb_display_param.c b/dev/gcdb/display/gcdb_display_param.c
index 7bc472f..7d189a5 100644
--- a/dev/gcdb/display/gcdb_display_param.c
+++ b/dev/gcdb/display/gcdb_display_param.c
@@ -37,7 +37,8 @@
#include "target/display.h"
#include "fastboot_oem_display.h"
-struct oem_panel_data oem_data = {{'\0'}, {'\0'}, false, false, SIM_NONE, "single_dsi", DSI_PLL_DEFAULT};
+struct oem_panel_data oem_data = {{'\0'}, {'\0'}, false, false, false, SIM_NONE,
+ "single_dsi", DSI_PLL_DEFAULT};
static int panel_name_to_dt_string(struct panel_lookup_list supp_panels[],
uint32_t supp_panels_size,
@@ -195,6 +196,10 @@
ch = strstr((char *) panel_name, ":disable");
oem_data.cont_splash = ch ? false : true;
+ /* Interposer card to swap DSI0 and DSI1 lanes */
+ ch = strstr((char *) panel_name, ":swap");
+ oem_data.swap_dsi_ctrl = ch ? true : false;
+
/* DSI PLL source */
ch = strstr((char *) panel_name, ":pll0");
if (ch) {
diff --git a/dev/gcdb/display/include/panel_fl10802_fwvga_video.h b/dev/gcdb/display/include/panel_fl10802_fwvga_video.h
index 8e30f57..4a511df 100644
--- a/dev/gcdb/display/include/panel_fl10802_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_fl10802_fwvga_video.h
@@ -210,7 +210,7 @@
static char fl10802_fwvga_video_on_cmd17[] = {
0x02, 0x00, 0x39, 0xC0,
- 0x53, 0x2C, 0xFF, 0xFF,
+ 0x53, 0x24, 0xFF, 0xFF,
};
static char fl10802_fwvga_video_on_cmd18[] = {
@@ -220,7 +220,7 @@
static char fl10802_fwvga_video_on_cmd19[] = {
0x02, 0x00, 0x39, 0xC0,
- 0x51, 0xFF, 0xFF, 0xFF,
+ 0x51, 0x00, 0xFF, 0xFF,
};
static char fl10802_fwvga_video_on_cmd20[] = {
@@ -231,6 +231,11 @@
0x29, 0x00, 0x05, 0x80
};
+static char fl10802_fwvga_video_on_cmd22[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xFF, 0xFF, 0xFF,
+};
+
static struct mipi_dsi_cmd fl10802_fwvga_video_on_command[] = {
{0x8, fl10802_fwvga_video_on_cmd0, 0x00},
{0xc, fl10802_fwvga_video_on_cmd1, 0x00},
@@ -253,10 +258,11 @@
{0x8, fl10802_fwvga_video_on_cmd18, 0x00},
{0x8, fl10802_fwvga_video_on_cmd19, 0x00},
{0x4, fl10802_fwvga_video_on_cmd20, 0x78},
- {0x4, fl10802_fwvga_video_on_cmd21, 0x78}
+ {0x4, fl10802_fwvga_video_on_cmd21, 0x78},
+ {0x8, fl10802_fwvga_video_on_cmd22, 0x00}
};
-#define FL10802_FWVGA_VIDEO_ON_COMMAND 22
+#define FL10802_FWVGA_VIDEO_ON_COMMAND 23
static char fl10802_fwvga_videooff_cmd0[] = {
@@ -322,7 +328,7 @@
/* Backlight setting */
/*---------------------------------------------------------------------------*/
static struct backlight fl10802_fwvga_video_backlight = {
- 1, 1, 255, 100, 2, "PMIC_8941"
+ BL_DCS, 1, 255, 100, 2, "PMIC_8941"
};
#define FL10802_FWVGA_VIDEO_SIGNATURE 0xFFFF
diff --git a/dev/gcdb/display/include/panel_hx8394d_720p_video.h b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
index ac4806f..1c05b35 100644
--- a/dev/gcdb/display/include/panel_hx8394d_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
@@ -47,7 +47,7 @@
static struct panel_config hx8394d_720p_video_panel_data = {
"qcom,mdss_dsi_hx8394d_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
};
/*---------------------------------------------------------------------------*/
@@ -259,14 +259,6 @@
0x79, 0x1a, 0x12, 0x00, 0x3e, 0x42, 0x16, 0x1e, 0x15, 0x03, 0x04, 0x00
};
-
-
-static struct mipi_dsi_cmd hx8394d_720p_video_rotation[] = {
-
-};
-#define HX8394D_720P_VIDEO_ROTATION 0
-
-
static struct panel_timing hx8394d_720p_video_timing_info = {
0, 4, 0x04, 0x1b
};
diff --git a/dev/gcdb/display/include/panel_hx8399a_1080p_video.h b/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
index 0ac37ac..f2d828e 100644
--- a/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
+++ b/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
@@ -40,7 +40,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config hx8399a_1080p_video_panel_data = {
"qcom,mdss_dsi_hx8399a_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 866400000, 0, 0, 0, NULL
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video_nofbc.h b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video_nofbc.h
new file mode 100644
index 0000000..ae73869
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video_nofbc.h
@@ -0,0 +1,184 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_JDI_4K_DUALDSI_VIDEO_NOFBC__H_
+#define _PANEL_JDI_4K_DUALDSI_VIDEO_NOFBC__H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_4k_dualdsi_video_nofbc_panel_data = {
+ "qcom,dsi_jdi_4k_nofbc_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 40, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0, 0,
+ "qcom,dsi_jdi_4k_nofbc_video",
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_4k_dualdsi_video_nofbc_panel_res = {
+ 3840, 2160, 100, 80, 12, 0, 16, 16, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_4k_dualdsi_video_nofbc_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char jdi_4k_dualdsi_video_on_cmd0[] = {
+ 0x51, 0xff, 0x15, 0x80,
+};
+
+static char jdi_4k_dualdsi_video_on_cmd1[] = {
+ 0x53, 0x24, 0x15, 0x80,
+};
+
+static char jdi_4k_dualdsi_video_on_cmd2[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char jdi_4k_dualdsi_video_on_cmd3[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_0[] = {
+ 0xb0, 0x04, 0x23, 0x80
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_1[] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xb3, 0x14, 0x08, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+
+static char jdi_4k_dualdsi_video_on_cmd_ip_2[] = {
+ 0xd6, 0x01, 0x23, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_4k_dualdsi_video_nofbc_on_command[] = {
+ {0x4, jdi_4k_dualdsi_video_on_cmd0, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd1, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd2, 0xc9},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_0, 0x0a},
+ {0xc, jdi_4k_dualdsi_video_on_cmd_ip_1, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd_ip_2, 0x0a},
+ {0x4, jdi_4k_dualdsi_video_on_cmd3, 0x78}
+};
+
+#define JDI_4K_DUALDSI_VIDEO_NOFBC_ON_COMMAND 7
+
+static char jdi_4k_dualdsi_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_4k_dualdsi_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_4k_dualdsi_video_nofbc_off_command[] = {
+ {0x4, jdi_4k_dualdsi_videooff_cmd0, 0x32},
+ {0x4, jdi_4k_dualdsi_videooff_cmd1, 0x78}
+};
+
+#define JDI_4K_DUALDSI_VIDEO_NOFBC_OFF_COMMAND 2
+
+
+static struct command_state jdi_4k_dualdsi_video_nofbc_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_4k_dualdsi_video_nofbc_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_4k_dualdsi_video_nofbc_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_4k_dualdsi_video_nofbc_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_4k_dualdsi_video_nofbc_timings[] = {
+ 0x3e, 0x38, 0x26, 0x00, 0x68, 0x6e, 0x2a, 0x3c, 0x2c, 0x03, 0x04, 0x00
+};
+
+
+static const uint32_t jdi_4k_dualdsi_thulium_video_nofbc_timings[] = {
+ 0x2c, 0x27, 0x0e, 0x10, 0x0a, 0x03, 0x04, 0xa0,
+ 0x2c, 0x27, 0x0e, 0x10, 0x0a, 0x03, 0x04, 0xa0,
+ 0x2c, 0x27, 0x0e, 0x10, 0x0a, 0x03, 0x04, 0xa0,
+ 0x2c, 0x27, 0x0e, 0x10, 0x0a, 0x03, 0x04, 0xa0,
+ 0x2c, 0x32, 0x0e, 0x0f, 0x0a, 0x03, 0x04, 0xa0,
+};
+
+static struct panel_timing jdi_4k_dualdsi_video_nofbc_timing_info = {
+ 0x0, 0x04, 0x0d, 0x3e
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_4k_dualdsi_video_nofbc_reset_seq = {
+ {0, 0, 1, }, {200, 200, 200, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_4k_dualdsi_video_nofbc_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+static struct labibb_desc jdi_4k_dualdsi_video_nofbc_labibb = {
+ 0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+#endif /*_PANEL_JDI_4K_DUALDSI_VIDEO_NOFBC__H_*/
diff --git a/dev/gcdb/display/include/panel_r69007_wqxga_cmd.h b/dev/gcdb/display/include/panel_r69007_wqxga_cmd.h
new file mode 100644
index 0000000..ab68848
--- /dev/null
+++ b/dev/gcdb/display/include/panel_r69007_wqxga_cmd.h
@@ -0,0 +1,381 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_R69007_WQXGA_CMD_H_
+#define _PANEL_R69007_WQXGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config r69007_wqxga_cmd_panel_data = {
+ "qcom,mdss_dsi_r69007_wqxga_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0,
+ "qcom,mdss_dsi_r69007_wqxga_cmd"
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution r69007_wqxga_cmd_panel_res = {
+ 1440, 2560, 112, 70, 10, 0, 9, 8, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info r69007_wqxga_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char r69007_wqxga_cmd_on_cmd0[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd1[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xB3, 0x00, 0x00, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd2[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xB6, 0x3b, 0xd3, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd3[] = {
+ 0x28, 0x00, 0x29, 0xC0,
+ 0xC1, 0x80, 0x08, 0x11,
+ 0x1F, 0xFC, 0xF2, 0xC9,
+ 0x1F, 0x5F, 0x98, 0xB3,
+ 0xFE, 0xFF, 0xF7, 0xFE,
+ 0xFF, 0xD7, 0x31, 0xF1,
+ 0xCB, 0x3F, 0x3F, 0xFD,
+ 0xEF, 0x03, 0x24, 0x69,
+ 0x18, 0xAA, 0x40, 0x01,
+ 0x42, 0x02, 0x08, 0x00,
+ 0x01, 0x00, 0x01, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd4[] = {
+ 0x0F, 0x00, 0x29, 0xC0,
+ 0xC2, 0x01, 0xFA, 0x00,
+ 0x04, 0x64, 0x08, 0x00,
+ 0x60, 0x00, 0x38, 0x70,
+ 0x00, 0x00, 0x00, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd5[] = {
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xC3, 0x07, 0x01, 0x08,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd6[] = {
+ 0x12, 0x00, 0x29, 0xC0,
+ 0xC4, 0x70, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x00, 0x02, 0x01,
+ 0x00, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd7[] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xC6, 0x3C, 0x00, 0x3C,
+ 0x02, 0x37, 0x01, 0x0E,
+ 0x01, 0x02, 0x01, 0x02,
+ 0x03, 0x0F, 0x04, 0x3C,
+ 0x46, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd8[] = {
+ 0x1F, 0x00, 0x29, 0xC0,
+ 0xC7, 0x00, 0x16, 0x22,
+ 0x2C, 0x3B, 0x48, 0x51,
+ 0x5D, 0x40, 0x47, 0x53,
+ 0x61, 0x6A, 0x71, 0x78,
+ 0x00, 0x16, 0x22, 0x2C,
+ 0x3B, 0x48, 0x51, 0x5D,
+ 0x40, 0x47, 0x53, 0x61,
+ 0x6A, 0x71, 0x78, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd9[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xC8, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xFC, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xFC, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xFC, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd10[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xC9, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xFC, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xFC, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xFC, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd11[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xCB, 0xAA, 0x1E, 0xE3,
+ 0x55, 0xF1, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static char r69007_wqxga_cmd_on_cmd12[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCC, 0x07, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd13[] = {
+ 0x0B, 0x00, 0x29, 0xC0,
+ 0xCD, 0x3A, 0x86, 0x3A,
+ 0x86, 0x8D, 0x8D, 0x04,
+ 0x04, 0x00, 0x00, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd14[] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xD0, 0x2A, 0x01, 0x91,
+ 0x6A, 0xDC, 0x59, 0x19,
+ 0x00, 0x00, 0x00, 0x19,
+ 0x99, 0x04, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd15[] = {
+ 0x21, 0x00, 0x29, 0xC0,
+ 0xD3, 0x1B, 0x3B, 0xBB,
+ 0x77, 0x77, 0x77, 0xBB,
+ 0xB3, 0x33, 0x00, 0x80,
+ 0xA7, 0xAF, 0x5B, 0x5B,
+ 0x33, 0x33, 0x33, 0xC0,
+ 0x00, 0xF2, 0x0F, 0x7D,
+ 0x7C, 0xFF, 0x0F, 0x99,
+ 0x00, 0x33, 0x00, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd16[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD4, 0x57, 0x33, 0x05,
+ 0x00, 0xF4, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd17[] = {
+ 0x0C, 0x00, 0x29, 0xC0,
+ 0xD5, 0x66, 0x00, 0x00,
+ 0x01, 0x3D, 0x01, 0x3D,
+ 0x00, 0x38, 0x00, 0x38,
+};
+
+static char r69007_wqxga_cmd_on_cmd18[] = {
+ 0x22, 0x00, 0x29, 0xC0,
+ 0xD7, 0x04, 0xff, 0x23,
+ 0x15, 0x75, 0xa4, 0xc3,
+ 0x1f, 0xc3, 0x1f, 0xd9,
+ 0x07, 0x1c, 0x1f, 0x30,
+ 0x8e, 0x87, 0xc7, 0xe3,
+ 0xf1, 0xcc, 0xf0, 0x1f,
+ 0xf0, 0x0d, 0x70, 0x00,
+ 0x2A, 0x00, 0x7e, 0x1d,
+ 0x07, 0x00, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd19[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xDE, 0x00, 0x3f, 0xff,
+ 0x10, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd20[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD6, 0x01, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd21[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd22[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2A, 0x00, 0x00, 0x05,
+ 0x9F, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd23[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2B, 0x00, 0x00, 0x09,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd24[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x2C, 0x00, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd25[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x36, 0x40, 0xFF, 0xFF,
+};
+
+static char r69007_wqxga_cmd_on_cmd26[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static char r69007_wqxga_cmd_on_cmd27[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r69007_wqxga_cmd_on_command[] = {
+ {0x8, r69007_wqxga_cmd_on_cmd0, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd1, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd2, 0x00},
+ {0x2c, r69007_wqxga_cmd_on_cmd3, 0x00},
+ {0x14, r69007_wqxga_cmd_on_cmd4, 0x00},
+ {0x10, r69007_wqxga_cmd_on_cmd5, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd6, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd7, 0x00},
+ {0x24, r69007_wqxga_cmd_on_cmd8, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd9, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd10, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd11, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd12, 0x00},
+ {0x10, r69007_wqxga_cmd_on_cmd13, 0x00},
+ {0x18, r69007_wqxga_cmd_on_cmd14, 0x00},
+ {0x28, r69007_wqxga_cmd_on_cmd15, 0x00},
+ {0xc, r69007_wqxga_cmd_on_cmd16, 0x00},
+ {0x10, r69007_wqxga_cmd_on_cmd17, 0x00},
+ {0x28, r69007_wqxga_cmd_on_cmd18, 0x00},
+ {0xc, r69007_wqxga_cmd_on_cmd19, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd20, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd21, 0x00},
+ {0xc, r69007_wqxga_cmd_on_cmd22, 0x00},
+ {0xc, r69007_wqxga_cmd_on_cmd23, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd24, 0x00},
+ {0x8, r69007_wqxga_cmd_on_cmd25, 0x00},
+ {0x4, r69007_wqxga_cmd_on_cmd26, 0x78},
+ {0x4, r69007_wqxga_cmd_on_cmd27, 0x14}
+};
+
+#define R69007_WQXGA_CMD_ON_COMMAND 28
+
+
+static char r69007_wqxga_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char r69007_wqxga_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd r69007_wqxga_cmd_off_command[] = {
+ {0x4, r69007_wqxga_cmdoff_cmd0, 0x32},
+ {0x4, r69007_wqxga_cmdoff_cmd1, 0x78}
+};
+
+#define R69007_WQXGA_CMD_OFF_COMMAND 2
+
+
+static struct command_state r69007_wqxga_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info r69007_wqxga_cmd_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info r69007_wqxga_cmd_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration r69007_wqxga_cmd_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t r69007_wqxga_cmd_timings[] = {
+ 0xDA, 0x34, 0x24, 0x00, 0x64, 0x68, 0x28, 0x38, 0x2A, 0x03, 0x04, 0x00
+};
+
+static const uint32_t r69007_wqxga_thulium_cmd_timings[] = {
+ 0x23, 0x1F, 0x07, 0x09, 0x05, 0x03, 0x04, 0xa0,
+ 0x23, 0x1F, 0x07, 0x09, 0x05, 0x03, 0x04, 0xa0,
+ 0x23, 0x1F, 0x07, 0x09, 0x05, 0x03, 0x04, 0xa0,
+ 0x23, 0x1F, 0x07, 0x09, 0x05, 0x03, 0x04, 0xa0,
+ 0x23, 0x19, 0x08, 0x08, 0x05, 0x03, 0x04, 0xa0
+};
+
+static struct panel_timing r69007_wqxga_cmd_timing_info = {
+ 0x0, 0x04, 0x03, 0x29
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence r69007_wqxga_cmd_reset_seq = {
+ {1, 0, 1, }, {2, 5, 120, }, 2
+};
+
+static struct labibb_desc r69007_wqxga_cmd_labibb = {
+ 0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight r69007_wqxga_cmd_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_R69007_WQXGA_CMD_H_*/
diff --git a/dev/pmic/pmi8994/include/pm_app_smbchg.h b/dev/pmic/pmi8994/include/pm_app_smbchg.h
index bfc12ca..81a7b39 100644
--- a/dev/pmic/pmi8994/include/pm_app_smbchg.h
+++ b/dev/pmic/pmi8994/include/pm_app_smbchg.h
@@ -201,5 +201,6 @@
bool pm_appsbl_display_init_done();
bool pm_appsbl_charging_in_progress();
pm_err_flag_type pm_appsbl_set_dcin_suspend();
+bool pm_app_display_shutdown_in_prgs();
#endif //PM_APP_SMBCHG__H
diff --git a/dev/pmic/pmi8994/pm_app_smbchg.c b/dev/pmic/pmi8994/pm_app_smbchg.c
index d3d1d6b..4b9693b 100644
--- a/dev/pmic/pmi8994/pm_app_smbchg.c
+++ b/dev/pmic/pmi8994/pm_app_smbchg.c
@@ -40,11 +40,12 @@
#include "pm_smbchg_driver.h"
#include "pm_comm.h"
#include "pm_smbchg_dc_chgpth.h"
+#include <kernel/thread.h>
#include <debug.h>
#include <platform/timer.h>
#include <sys/types.h>
#include <target.h>
-
+#include <pm8x41.h>
/*===========================================================================
@@ -64,16 +65,27 @@
#define PM_MIN_ADC_READY_DELAY 1 * 1000 //1ms
#define PM_MAX_ADC_READY_DELAY 2000 //2s
#define SBL_PACKED_SRAM_CONFIG_SIZE 3
-
+#define PM_CHARGE_DISPLAY_TIMEOUT 5 * 1000 //5 secs
#define boot_log_message(...) dprintf(CRITICAL, __VA_ARGS__)
static pm_smbchg_bat_if_low_bat_thresh_type pm_dbc_bootup_volt_threshold;
+/* Need to maintain flags to track
+ * 1. charge_in_progress: Charging progress and exit the loop once charging is completed.
+ * 2. display_initialized: Track if the display is already initialized to make sure display
+ * thread does not reinitialize the display again.
+ * 3. display_shutdown_in_prgs: To avoid race condition between regualr display initialization and
+ * display shutdown in display thread.
+ */
+
static bool display_initialized;
static bool charge_in_progress;
+static bool display_shutdown_in_prgs;
+
char panel_name[256];
pm_err_flag_type pm_smbchg_get_charger_path(uint32 device_index, pm_smbchg_usb_chgpth_pwr_pth_type* charger_path);
pm_err_flag_type pm_appsbl_chg_config_vbat_low_threshold(uint32 device_index, pm_smbchg_specific_data_type *chg_param_ptr);
+static void display_thread_initialize();
/*===========================================================================
@@ -173,6 +185,7 @@
vbatt_weak_status = FALSE;
break; //bootup
}
+ dprintf(INFO, "Vbatt Level: %u\n", vbat_adc);
}
else
{
@@ -227,14 +240,11 @@
charge_in_progress = true;
#if DISPLAY_SPLASH_SCREEN
- if (!display_initialized)
- target_display_init(panel_name);
- display_initialized = true;
+ display_thread_initialize();
#endif
/* Wait for 500 msecs before looking for vbat */
udelay(PM_WEAK_BATTERY_CHARGING_DELAY); //500ms
-
//Check if Charging in progress
err_flag |= pm_smbchg_chgr_get_chgr_sts(device_index, &vbatt_chging_status);
if ( err_flag != PM_ERR_FLAG__SUCCESS ) { break;}
@@ -584,3 +594,83 @@
return err_flag;
}
+
+static bool is_power_key_pressed()
+{
+ int count = 0;
+
+ if (pm8x41_get_pwrkey_is_pressed())
+ {
+ while(count++ < 10 && pm8x41_get_pwrkey_is_pressed())
+ thread_sleep(100);
+
+ dprintf(INFO, "Power Key Pressed\n");
+ return true;
+ }
+
+ return false;
+}
+
+bool pm_app_display_shutdown_in_prgs()
+{
+ return display_shutdown_in_prgs;
+}
+
+static int display_charger_screen()
+{
+ static bool display_init_first_time;
+
+ /* By default first time display the charger screen
+ * Wait for 5 seconds and turn off the display
+ * If user presses power key & charging is in progress display the charger screen
+ */
+ do {
+ if (!display_init_first_time || (is_power_key_pressed() && charge_in_progress))
+ {
+ /* Display charger screen */
+ target_display_init(panel_name);
+ /* wait for 5 seconds to show the charger screen */
+ display_initialized = true;
+ thread_sleep(PM_CHARGE_DISPLAY_TIMEOUT);
+ /* Shutdown the display: If the charging is complete
+ * continue boot up with display on
+ */
+ if (charge_in_progress)
+ {
+ display_shutdown_in_prgs = true;
+ target_display_shutdown();
+ display_shutdown_in_prgs = false;
+ display_initialized = false;
+ }
+ display_init_first_time = true;
+ }
+ /* Wait for 100ms before reading the pmic interrupt status
+ * again, reading the pmic interrupt status in a loop without delays
+ * reports false key presses */
+ thread_sleep(100);
+ } while (charge_in_progress);
+
+ return 0;
+}
+
+/* Create a thread to monitor power key press events
+ * and turn on/off the display for battery
+ */
+static void display_thread_initialize()
+{
+ thread_t *thr = NULL;
+ static bool is_thread_start;
+
+ if (!is_thread_start)
+ {
+ thr = thread_create("display_charger_screen", &display_charger_screen, NULL, DEFAULT_PRIORITY, DEFAULT_STACK_SIZE);
+ if (!thr)
+ {
+ dprintf(CRITICAL, "Error: Could not create display charger screen thread\n");
+ return;
+ }
+ thread_resume(thr);
+
+ is_thread_start = true;
+ }
+}
diff --git a/dev/qpnp_haptic/qpnp_haptic.c b/dev/qpnp_haptic/qpnp_haptic.c
index 1bdadee..e1200a1 100644
--- a/dev/qpnp_haptic/qpnp_haptic.c
+++ b/dev/qpnp_haptic/qpnp_haptic.c
@@ -29,6 +29,8 @@
#include <spmi.h>
#include <platform/iomap.h>
#include <pm_vib.h>
+#include <target.h>
+#include <vibrator.h>
#define HAPTIC_BASE (PMI_ADDR_BASE+ 0xC000)
#define QPNP_HAP_EN_CTL_REG (HAPTIC_BASE + 0x46)
@@ -71,6 +73,7 @@
#define QPNP_HAP_BRAKE_VMAX_MASK 0xFF
#define QPNP_HAP_BRAKE_VMAX 0xF
#define QPNP_HAP_ERM 0x1
+#define QPNP_HAP_LRA 0x0
#define QPNP_HAP_PLAY_MASK 0x80
#define QPNP_HAP_PLAY_EN 0x80
#define QPNP_HAP_MASK 0x80
@@ -84,17 +87,23 @@
/* Turn on vibrator */
void pm_vib_turn_on(void)
{
+ uint32_t vib_type = VIB_ERM_TYPE;
+ vib_type = get_vibration_type();
/* Configure the ACTUATOR TYPE register as ERM*/
pmic_spmi_reg_mask_write(QPNP_HAP_ACT_TYPE_REG,
- QPNP_HAP_ACT_TYPE_MASK, QPNP_HAP_ERM);
+ QPNP_HAP_ACT_TYPE_MASK,
+ VIB_ERM_TYPE == vib_type ? QPNP_HAP_ERM
+ : QPNP_HAP_LRA);
/* Disable auto resonance for ERM */
pmic_spmi_reg_mask_write(QPNP_HAP_LRA_AUTO_RES_REG,
- QPNP_HAP_LRA_AUTO_MASK, QPNP_HAP_LRA_AUTO_DISABLE);
+ QPNP_HAP_LRA_AUTO_MASK,
+ QPNP_HAP_LRA_AUTO_DISABLE);
/* Configure the PLAY MODE register as direct*/
pmic_spmi_reg_mask_write(QPNP_HAP_PLAY_MODE_REG,
- QPNP_HAP_PLAY_MODE_MASK, QPNP_HAP_DIRECT);
+ QPNP_HAP_PLAY_MODE_MASK,
+ QPNP_HAP_DIRECT);
/* Configure the VMAX register */
pmic_spmi_reg_mask_write(QPNP_HAP_VMAX_REG,
diff --git a/dev/vib/include/vibrator.h b/dev/vib/include/vibrator.h
index d6fb8bf..2ec1346 100644
--- a/dev/vib/include/vibrator.h
+++ b/dev/vib/include/vibrator.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -29,6 +29,8 @@
#define __DEV_VIB_VIBRATOR_H
#define VIB_TIMER_DEFAULT_TIMEOUT 250
+#define VIB_LRA_TYPE 0x00
+#define VIB_ERM_TYPE 0x01
void vib_turn_on(void);
void vib_turn_off(void);
diff --git a/include/platform.h b/include/platform.h
index 50ef337..9c8e698 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -71,4 +71,5 @@
uint32_t platform_get_max_periph();
int platform_is_msm8996();
uint64_t platform_get_ddr_start();
+bool platform_use_qmp_misc_settings();
#endif
diff --git a/include/target.h b/include/target.h
index b7f92a2..f2e2acd 100644
--- a/include/target.h
+++ b/include/target.h
@@ -87,4 +87,9 @@
int target_cont_splash_screen(void);
bool target_build_variant_user();
void pmic_reset_configure(uint8_t reset_type);
+
+#if PON_VIB_SUPPORT
+uint32_t get_vibration_type();
+#endif
+
#endif
diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
index 5803acd..f92f556 100644
--- a/platform/mdm9640/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -180,6 +180,8 @@
/* SS QMP (Qulacomm Multi Protocol) */
#define QMP_PHY_BASE 0x78000
+#define AHB2_PHY_BASE 0x0007e000
+#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
/* QMP register offset */
#define PLATFORM_QMP_OFFSET 0x8
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index 6a568db..035c7cb 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -150,6 +150,18 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+
+/* RPMB send receive buffer needs to be mapped
+ * as device memory, define the start address
+ * and size in MB
+ */
+#define RPMB_SND_RCV_BUF 0x90000000
+#define RPMB_SND_RCV_BUF_SZ 0x1
+
+/* QSEECOM: Secure app region notification */
+#define APP_REGION_ADDR 0x85E00000
+#define APP_REGION_SIZE 0x500000
+
/* MDSS */
#define MIPI_DSI_BASE (0x1A98000)
#define MIPI_DSI0_BASE MIPI_DSI_BASE
diff --git a/platform/msm8952/platform.c b/platform/msm8952/platform.c
index af4f279..2da8ced 100644
--- a/platform/msm8952/platform.c
+++ b/platform/msm8952/platform.c
@@ -61,12 +61,13 @@
static mmu_section_t mmu_section_table[] = {
/* Physical addr, Virtual addr, Size (in MB), Flags */
- { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
- { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
- { APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
- { MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
- { SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
- { MIPI_FB_ADDR, MIPI_FB_ADDR, 42, COMMON_MEMORY},
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
+ { MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+ { MIPI_FB_ADDR, MIPI_FB_ADDR, 42, COMMON_MEMORY},
+ { RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
void platform_early_init(void)
@@ -117,7 +118,7 @@
sections = 90;
while(sections--)
{
- arm_mmu_map_section(ddr_start + sections * MB, ddr_start + sections* MB, COMMON_MEMORY);
+ arm_mmu_map_section(ddr_start + sections * MB, ddr_start + sections* MB, SCRATCH_MEMORY);
}
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index 2ae1d17..8aa0fab 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -78,6 +78,9 @@
#define QUSB2_PHY_BASE 0x7411000
#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
+#define AHB2_PHY_BASE 0x7416000
+#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
+
/* Clocks */
#define CLK_CTL_BASE 0x300000
@@ -209,8 +212,8 @@
#define DSI0_REGULATOR_BASE (0x994000)
#define DSI1_REGULATOR_BASE (0x996000)
-#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
-#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
+#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0D0
+#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0D4
#define MDP_BASE (0x900000)
#define REG_MDP(off) (MDP_BASE + (off))
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index 090e81c..08c0025 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -222,3 +222,11 @@
{
return ddr_start;
}
+
+bool platform_use_qmp_misc_settings()
+{
+ if (board_soc_version() < 0x30000)
+ return true;
+
+ return false;
+}
diff --git a/platform/msm_shared/bam.c b/platform/msm_shared/bam.c
index 723ce00..ef39321 100644
--- a/platform/msm_shared/bam.c
+++ b/platform/msm_shared/bam.c
@@ -139,16 +139,7 @@
/* Reset and initialize the bam module */
void bam_init(struct bam_instance *bam)
{
- /* Check for only one pipe's direction.
- * The other is assumed to be the opposite system
- * transaction.
- */
- if (bam->pipe[0].trans_type == SYS2BAM ||
- bam->pipe[0].trans_type == BAM2SYS)
- {
- /* Program the threshold count */
- writel(bam->threshold, BAM_DESC_CNT_TRSHLD_REG(bam->base));
- }
+ /* bam is initialized by TZ, so nothing needs to be done here */
}
/* Funtion to setup a simple fifo structure.
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index 6f0cc8f..0861cc8 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -286,9 +286,6 @@
uint32_t config = CRYPTO_RESET_CONFIG
| (dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].pipe_num >> 1) << PIPE_SET_SELECT_SHIFT;
- /* Configure CE clocks. */
- clock_config_ce(dev->instance);
-
/* Setup BAM */
if (crypto_bam_init(dev) != CRYPTO_ERR_NONE)
{
diff --git a/platform/msm_shared/crypto5_wrapper.c b/platform/msm_shared/crypto5_wrapper.c
index 0be227a..868eca0 100644
--- a/platform/msm_shared/crypto5_wrapper.c
+++ b/platform/msm_shared/crypto5_wrapper.c
@@ -28,6 +28,7 @@
#include <debug.h>
#include <crypto5_wrapper.h>
+#include <platform/clock.h>
/* This file is a wrapper to the crypto5_eng.c.
* This is required so that we maintian the backward compatibility
@@ -52,7 +53,8 @@
void ce_clock_init(void)
{
- /* Clock init is done during crypto_init. */
+ /* Configure CE clocks. */
+ clock_config_ce(dev.instance);
}
void crypto_eng_reset(void)
diff --git a/platform/msm_shared/include/bam.h b/platform/msm_shared/include/bam.h
index bfeb34b..67b2f5f 100644
--- a/platform/msm_shared/include/bam.h
+++ b/platform/msm_shared/include/bam.h
@@ -71,7 +71,6 @@
#define BAM_DATA_READ 0
#define BAM_DATA_WRITE 1
-#define BAM_DESC_CNT_TRSHLD_REG(x) (0x0008 + (x))
#define COUNT_TRESHOLD_MASK 0xFF
#define BAM_IRQ_MASK (1 << 31)
#define P_IRQ_MASK (1)
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 06c4804..0474f37 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -781,7 +781,7 @@
writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
if (dsc->dsi_dsc_config)
- dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_VIDEO_MODE, dsc);
+ dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_CMD_MODE, dsc);
} else {
writel((img_width * ystride + 1) << 16 | 0x0039,
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index 54a8831..91aed89 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -36,6 +36,7 @@
#include <clock.h>
#include <debug.h>
#include <qtimer.h>
+#include <platform.h>
#define HS_PHY_COMMON_CTRL 0xEC
#define USE_CORECLK BIT(14)
@@ -64,15 +65,11 @@
{0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
{0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
{0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
- {0x178, 0x01}, /* QSERDES_COM_HSCLK_SEL */
+ {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */
{0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */
{0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
{0x3C, 0x04}, /* QSERDES_COM_SYS_CLK_CTRL */
- /* Res_code Settings */
- {0xC4, 0x15}, /* USB3PHY_QSERDES_COM_RESCODE_DIV_NUM */
- {0x1B8, 0x1F}, /* QSERDES_COM_CMN_MISC2 */
-
/* PLL & Loop filter settings */
{0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
{0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
@@ -134,6 +131,15 @@
{0x600, 0x00}, /* USB3_PHY_SW_RESET */
};
+#if PLATFORM_USE_QMP_MISC
+struct qmp_reg qmp_misc_settings_rev2[] =
+{
+ {0x178, 0x01}, /* QSERDES_COM_HSCLK_SEL */
+ {0xC4, 0x15}, /* USB3PHY_QSERDES_COM_RESCODE_DIV_NUM */
+ {0x1B8, 0x1F}, /* QSERDES_COM_CMN_MISC2 */
+};
+#endif
+
__WEAK uint32_t target_override_pll()
{
return 0;
@@ -265,6 +271,11 @@
for (i = 0 ; i < qmp_reg_size; i++)
writel(qmp_settings_rev2[i].val, QMP_PHY_BASE + qmp_settings_rev2[i].off);
+#if PLATFORM_USE_QMP_MISC
+ if (platform_use_qmp_misc_settings())
+ for (i = 0; i < ARRAY_SIZE(qmp_misc_settings_rev2); i++)
+ writel(qmp_misc_settings_rev2[i].val, QMP_PHY_BASE + qmp_misc_settings_rev2[i].off);
+#endif
if (target_override_pll())
{
qmp_reg_size = sizeof(qmp_override_pll_rev2) / sizeof(struct qmp_reg);
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index fab6e09..871bbcc 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -25,7 +25,7 @@
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
+#include <arch/defines.h>
#include <platform/iomap.h>
#include <qusb2_phy.h>
#include <reg.h>
@@ -55,6 +55,10 @@
udelay(10);
writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR);
+ /* configure the abh2 phy to wait state */
+ writel(0x11, PERIPH_SS_AHB2PHY_TOP_CFG);
+ dmb();
+
/* set CLAMP_N_EN and stay with disabled USB PHY */
writel(0x23, QUSB2PHY_PORT_POWERDOWN);
diff --git a/platform/msm_shared/rpmb/rpmb.c b/platform/msm_shared/rpmb/rpmb.c
index 1283190..8ddfbd3 100644
--- a/platform/msm_shared/rpmb/rpmb.c
+++ b/platform/msm_shared/rpmb/rpmb.c
@@ -76,6 +76,7 @@
}
info.dev_type = EMMC_RPMB;
}
+#ifdef UFS_SUPPORT
else
{
struct ufs_dev *ufs_dev = (struct ufs_dev *) dev;
@@ -84,6 +85,7 @@
info.rel_wr_count = ufs_dev->rpmb_rw_size;
info.dev_type = UFS_RPMB;
}
+#endif
/* Register & start the listener */
ret = rpmb_listener_start();
@@ -105,18 +107,26 @@
int rpmb_read(uint32_t *req, uint32_t req_len, uint32_t *resp, uint32_t *resp_len)
{
+ int ret = 0;
if (platform_boot_dev_isemmc())
- return rpmb_read_emmc(dev, req, req_len, resp, resp_len);
+ ret = rpmb_read_emmc(dev, req, req_len, resp, resp_len);
+#ifdef UFS_SUPPORT
else
- return rpmb_read_ufs(dev, req, req_len, resp, resp_len);
+ ret = rpmb_read_ufs(dev, req, req_len, resp, resp_len);
+#endif
+ return ret;
}
int rpmb_write(uint32_t *req, uint32_t req_len, uint32_t rel_wr_count, uint32_t *resp, uint32_t *resp_len)
{
+ int ret = 0;
if (platform_boot_dev_isemmc())
- return rpmb_write_emmc(dev, req, req_len, rel_wr_count, resp, resp_len);
+ ret = rpmb_write_emmc(dev, req, req_len, rel_wr_count, resp, resp_len);
+#ifdef UFS_SUPPORT
else
- return rpmb_write_ufs(dev, req, req_len, rel_wr_count, resp, resp_len);
+ ret = rpmb_write_ufs(dev, req, req_len, rel_wr_count, resp, resp_len);
+#endif
+ return ret;
}
/* This API calls into TZ app to read device_info */
diff --git a/platform/msm_shared/rpmb/rules.mk b/platform/msm_shared/rpmb/rules.mk
index 0e76433..da7b90e 100644
--- a/platform/msm_shared/rpmb/rules.mk
+++ b/platform/msm_shared/rpmb/rules.mk
@@ -4,5 +4,7 @@
OBJS += $(LOCAL_DIR)/rpmb.o \
$(LOCAL_DIR)/rpmb_listener.o \
- $(LOCAL_DIR)/rpmb_emmc.o \
- $(LOCAL_DIR)/rpmb_ufs.o
+ $(LOCAL_DIR)/rpmb_emmc.o
+ifeq ($(ENABLE_UFS_SUPPORT), 1)
+ OBJS += $(LOCAL_DIR)/rpmb_ufs.o
+endif
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index baa1b37..4f54119 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -596,6 +596,7 @@
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/qseecom_lk.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/dload_util.o \
@@ -613,6 +614,25 @@
$(LOCAL_DIR)/mipi_dsi_autopll.o
endif
+ifeq ($(PLATFORM),msmtitanium)
+ OBJS += $(LOCAL_DIR)/qgic.o \
+ $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/qseecom_lk.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o
+endif
+
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
OBJS += \
$(LOCAL_DIR)/boot_device.o
@@ -630,7 +650,6 @@
OBJS += $(LOCAL_DIR)/partial_goods.o
endif
-
ifeq ($(ENABLE_REBOOT_MODULE), 1)
OBJS += $(LOCAL_DIR)/reboot.o
endif
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 7fbe57f..44eb81d 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -427,9 +427,16 @@
FSM9916 = 276,
APQ8076 = 277,
MSM8976 = 278,
+ MDMCALIFORNIUM1 = 279,
+ MDMCALIFORNIUM2 = 283,
+ MDMCALIFORNIUM3 = 284,
+ MDMCALIFORNIUM4 = 285,
+ MDMCALIFORNIUM5 = 286,
APQ8052 = 289,
MDMFERMIUM = 290,
APQ8096 = 291,
+ MSMTITANIUM = 293,
+ MSMTHORIUM = 294,
};
enum platform {
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
new file mode 100755
index 0000000..25c1eff
--- /dev/null
+++ b/platform/msmtitanium/acpuclock.c
@@ -0,0 +1,90 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <platform.h>
+
+#define MAX_LOOPS 500
+
+void hsusb_clock_init(void)
+{
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+}
diff --git a/platform/msmtitanium/gpio.c b/platform/msmtitanium/gpio.c
new file mode 100644
index 0000000..05b4977
--- /dev/null
+++ b/platform/msmtitanium/gpio.c
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+
+ writel(val, (uint32_t *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set_dir(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (uint32_t *)GPIO_IN_OUT_ADDR(gpio));
+
+ return;
+}
+
+uint32_t gpio_status(uint32_t gpio)
+{
+ return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
+}
+
+/* Configure gpio for blsp uart 2 */
+void gpio_config_uart_dm(uint8_t id)
+{
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/msmtitanium/include/platform/clock.h b/platform/msmtitanium/include/platform/clock.h
new file mode 100644
index 0000000..4174744
--- /dev/null
+++ b/platform/msmtitanium/include/platform/clock.h
@@ -0,0 +1,44 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSMTITANIUM_CLOCK_H
+#define __MSMTITANIUM_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+#endif
diff --git a/platform/msmtitanium/include/platform/gpio.h b/platform/msmtitanium/include/platform/gpio.h
new file mode 100644
index 0000000..1d05ede
--- /dev/null
+++ b/platform/msmtitanium/include/platform/gpio.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSMTITANIUM_GPIO_H
+#define __PLATFORM_MSMTITANIUM_GPIO_H
+
+#include <bits.h>
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN BIT(0)
+#define GPIO_OUT BIT(1)
+
+void gpio_config_uart_dm(uint8_t id);
+uint32_t gpio_status(uint32_t gpio);
+void gpio_set_dir(uint32_t gpio, uint32_t dir);
+void gpio_tlmm_config(uint32_t gpio,
+ uint8_t func,
+ uint8_t dir,
+ uint8_t pull,
+ uint8_t drvstr,
+ uint32_t enable);
+#endif
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
new file mode 100755
index 0000000..833520a
--- /dev/null
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -0,0 +1,166 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSMTITANIUM_IOMAP_H_
+#define _PLATFORM_MSMTITANIUM_IOMAP_H_
+
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x08000000
+
+#define SDRAM_START_ADDR 0x80000000
+
+#define MSM_SHARED_BASE 0x86300000
+#define MSM_SHARED_IMEM_BASE 0x08600000
+
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define APPS_SS_BASE 0x0B000000
+#define APPS_SS_END 0x0B200000
+
+#define MSM_GIC_DIST_BASE APPS_SS_BASE
+#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
+#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
+#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
+#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
+#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
+
+#define PERIPH_SS_BASE 0x07800000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
+#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
+
+#define CLK_CTL_BASE 0x1800000
+
+#define SPMI_BASE 0x02000000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
+#define PMIC_ARB_CORE 0x200F000
+
+#define TLMM_BASE_ADDR 0x1000000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
+
+#define MPM2_MPM_CTRL_BASE 0x004A0000
+#define MPM2_MPM_PS_HOLD 0x004AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
+
+/* CRYPTO ENGINE */
+#define MSM_CE1_BASE 0x073A000
+#define MSM_CE1_BAM_BASE 0x0704000
+#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
+#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
+#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
+#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
+#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
+#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
+
+
+/* GPLL */
+#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
+#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
+#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
+
+/* SDCC */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
+#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
+
+/* SDHCI */
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
+
+/* UART */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
+
+/* USB */
+#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
+#define MSM_USB30_QSCRATCH_BASE 0x070F8800
+#define MSM_USB30_BASE 0x7000000
+#define USB2_PHY_SEL 0x01937000
+
+/* RPMB send receive buffer needs to be mapped
+ * as device memory, define the start address
+ * and size in MB
+ */
+#define RPMB_SND_RCV_BUF 0x90000000
+#define RPMB_SND_RCV_BUF_SZ 0x1
+
+/* QSEECOM: Secure app region notification */
+#define APP_REGION_ADDR 0x85E00000
+#define APP_REGION_SIZE 0x500000
+
+#define TCSR_TZ_WONCE 0x193D000
+#define TCSR_BOOT_MISC_DETECT 0x193D100
+
+#define DDR_START 0x80000000
+#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
+#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
+#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
+#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
+#endif
diff --git a/platform/msmtitanium/include/platform/irqs.h b/platform/msmtitanium/include/platform/irqs.h
new file mode 100755
index 0000000..db33501
--- /dev/null
+++ b/platform/msmtitanium/include/platform/irqs.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IRQS_MSMTITANIUM_H
+#define __IRQS_MSMTITANIUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 257)
+
+#define USB30_EE1_IRQ (GIC_SPI_START + 134)
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
+#define USB1_HS_IRQ (GIC_SPI_START + 134)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#define SMD_IRQ (GIC_SPI_START + 168)
+#endif /* __IRQS_MSMTITANIUM_H */
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
new file mode 100644
index 0000000..092ca54
--- /dev/null
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -0,0 +1,419 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <platform.h>
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define gpll4_source_val 2
+#define cxo_mm_source_val 0
+#define gpll0_mm_source_val 6
+#define gpll6_mm_source_val 3
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 800000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(5),
+ .status_reg = (void *) GPLL4_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1152000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 10, 1, 4),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F(100000000, gpll0, 8, 0, 0),
+ F(177770000, gpll0, 4.5, 0, 0),
+ F(200000000, gpll0, 4, 0, 0),
+ F(384000000, gpll4, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 10, 1, 4),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F(100000000, gpll0, 8, 0, 0),
+ F(177770000, gpll0, 4.5, 0, 0),
+ F(200000000, gpll0, 4, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 72, 15625),
+ F( 7372800, gpll0, 1, 144, 15625),
+ F(14745600, gpll0, 1, 288, 15625),
+ F(16000000, gpll0, 10, 1, 5),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 1, 3, 100),
+ F(25000000, gpll0, 16, 1, 2),
+ F(32000000, gpll0, 1, 1, 25),
+ F(40000000, gpll0, 1, 1, 20),
+ F(46400000, gpll0, 1, 29, 500),
+ F(48000000, gpll0, 1, 3, 50),
+ F(51200000, gpll0, 1, 8, 125),
+ F(56000000, gpll0, 1, 7, 100),
+ F(58982400, gpll0, 1,1152, 15625),
+ F(60000000, gpll0, 1, 3, 40),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(10),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(100000000, gpll0, 10, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F(160000000, gpll0, 5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(2),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(0),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(1),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_titanium[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_titanium, ARRAY_SIZE(msm_clocks_titanium));
+}
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
new file mode 100755
index 0000000..2168570
--- /dev/null
+++ b/platform/msmtitanium/platform.c
@@ -0,0 +1,170 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/clock.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+#include <boot_stats.h>
+#include <platform.h>
+
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define APPS_SS_SIZE ((APPS_SS_END - APPS_SS_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
+ { MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+};
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+ scm_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+ qtimer_uninit();
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ return ((addr_t)BS_INFO_ADDR);
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup MMU mapping for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t ddr_start = get_ddr_start();
+ uint32_t smem_addr = platform_get_smem_base_addr();
+
+ /*Mapping the ddr start address for loading the kernel about 90 MB*/
+ sections = 90;
+ while(sections--)
+ {
+ arm_mmu_map_section(ddr_start + sections * MB, ddr_start + sections* MB, COMMON_MEMORY);
+ }
+
+
+ /* Mapping the SMEM addr */
+ arm_mmu_map_section(smem_addr, smem_addr, COMMON_MEMORY);
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+/* DYNAMIC SMEM REGION feature enables LK to dynamically
+ * read the SMEM addr info from TCSR_TZ_WONCE register.
+ * The first word read, if indicates a MAGIC number, then
+ * Dynamic SMEM is assumed to be enabled. Read the remaining
+ * SMEM info for SMEM Size and Phy_addr from the other bytes.
+ */
+uint32_t platform_get_smem_base_addr()
+{
+ struct smem_addr_info *smem_info = NULL;
+
+ smem_info = (struct smem_addr_info *)readl(TCSR_TZ_WONCE);
+ if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
+ return smem_info->phy_addr;
+ else
+ return MSM_SHARED_BASE;
+}
diff --git a/platform/msmtitanium/rules.mk b/platform/msmtitanium/rules.mk
new file mode 100755
index 0000000..96b14d5
--- /dev/null
+++ b/platform/msmtitanium/rules.mk
@@ -0,0 +1,26 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+#Compiling this as cortex-a8 until the compiler supports krait
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_A7
+DEFINES += ARM_CORE_V8
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/msmtitanium-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/project/msm8952.mk b/project/msm8952.mk
index 54d4fa8..6a06c96 100644
--- a/project/msm8952.mk
+++ b/project/msm8952.mk
@@ -13,6 +13,8 @@
endif
EMMC_BOOT := 1
+ENABLE_SECAPP_LOADER := 1
+ENABLE_RPMB_SUPPORT := 1
ENABLE_SMD_SUPPORT := 1
#ENABLE_PWM_SUPPORT := true
@@ -31,6 +33,7 @@
#Enable the feature of long press power on
DEFINES += LONG_PRESS_POWER_ON=1
+DEFINES += USE_RPMB_FOR_DEVINFO=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -41,6 +44,13 @@
DEFINES += MMC_SDHCI_SUPPORT=1
endif
+#enable fbcon display menu
+ENABLE_FBCON_DISPLAY_MSG := 1
+
+ifeq ($(ENABLE_FBCON_DISPLAY_MSG),1)
+DEFINES += FBCON_DISPLAY_MSG=1
+endif
+
#enable power on vibrator feature
ENABLE_HAP_VIB_SUPPORT := true
diff --git a/project/msm8996.mk b/project/msm8996.mk
index ae2599e..a5f86f3 100644
--- a/project/msm8996.mk
+++ b/project/msm8996.mk
@@ -77,6 +77,8 @@
DEFINES += ENABLE_PARTIAL_GOODS_SUPPORT=1
endif
+ENABLE_MDTP_SUPPORT := 1
+
ifeq ($(ENABLE_MDTP_SUPPORT),1)
DEFINES += MDTP_SUPPORT=1
DEFINES += MDTP_EFUSE_ADDRESS=0x00070178 # QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR
@@ -96,5 +98,7 @@
ENABLE_REBOOT_MODULE := 1
#fuse for Qusb tun2 config
DEFINES += QFPROM_CORR_CALIB_ROW12_MSB=0x0007424C
+#Use misc settings for qmp
+DEFINES += PLATFORM_USE_QMP_MISC=1
#Use PON register for reboot reason
DEFINES += USE_PON_REBOOT_REG=1
diff --git a/project/msmtitanium.mk b/project/msmtitanium.mk
new file mode 100755
index 0000000..d1449a5
--- /dev/null
+++ b/project/msmtitanium.mk
@@ -0,0 +1,73 @@
+# top level project rules for the MSMTITANIUM project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msmtitanium
+
+MODULES += app/aboot
+
+ifeq ($(TARGET_BUILD_VARIANT),user)
+DEBUG := 0
+else
+DEBUG := 1
+endif
+
+EMMC_BOOT := 1
+ENABLE_SECAPP_LOADER := 1
+
+ENABLE_SMD_SUPPORT := 1
+#ENABLE_PWM_SUPPORT := true
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_LOG_BUF=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+DEFINES += CRYPTO_BAM=1
+DEFINES += SPMI_CORE_V2=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += BAM_V170=1
+
+#Enable the feature of long press power on
+#DEFINES += LONG_PRESS_POWER_ON=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_USB30_SUPPORT := 1
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
+
+#enable power on vibrator feature
+#ENABLE_PON_VIB_SUPPORT := true
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+DEFINES += SMD_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
+
+CFLAGS += -Werror
+
+DEFINES += USE_TARGET_HS200_DELAY=1
+
+#Enable the external reboot functions
+ENABLE_REBOOT_MODULE := 1
diff --git a/target/init.c b/target/init.c
index fba226c..c3893d3 100644
--- a/target/init.c
+++ b/target/init.c
@@ -28,6 +28,11 @@
#include <compiler.h>
#include <dload_util.h>
#include <sdhci_msm.h>
+#if PON_VIB_SUPPORT
+#include <smem.h>
+#include <vibrator.h>
+#include <board.h>
+#endif
#define EXPAND(NAME) #NAME
#define TARGET(NAME) EXPAND(NAME)
@@ -221,6 +226,31 @@
return DDR_CONFIG_VAL;
}
+#if PON_VIB_SUPPORT
+uint32_t get_vibration_type()
+{
+ uint32_t ret = VIB_ERM_TYPE;
+ uint32_t hw_id = board_hardware_id();
+ uint32_t platform = board_platform_id();
+ switch(hw_id){
+ case HW_PLATFORM_MTP:
+ switch(platform){
+ case MSM8952:
+ ret = VIB_ERM_TYPE;
+ break;
+ case MSM8976:
+ ret = VIB_LRA_TYPE;
+ break;
+ }
+ break;
+ case HW_PLATFORM_QRD:
+ ret = VIB_ERM_TYPE;
+ break;
+ }
+ return ret;
+}
+#endif
+
/* Return Build variant */
__WEAK bool target_build_variant_user()
{
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 5db6e08..3cc3923 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -553,7 +553,7 @@
if (is_cold_boot &&
(!(pon_reason & HARD_RST)) &&
(!(pon_reason & KPDPWR_N)) &&
- ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
return 1;
else
return 0;
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
index 6d84eef..7b6e473 100644
--- a/target/msm8909/oem_panel.c
+++ b/target/msm8909/oem_panel.c
@@ -319,6 +319,7 @@
memcpy(phy_db->timing,
fl10802_fwvga_video_timings, TIMING_SIZE);
pinfo->mipi.signature = FL10802_FWVGA_VIDEO_SIGNATURE;
+ pinfo->mipi.cmds_post_tg = 1;
break;
case UNKNOWN_PANEL:
default:
diff --git a/target/msm8952/init.c b/target/msm8952/init.c
index 2f1ea36..0c711de 100644
--- a/target/msm8952/init.c
+++ b/target/msm8952/init.c
@@ -54,6 +54,9 @@
#include <spmi.h>
#include <sdhci_msm.h>
#include <clock.h>
+#include <boot_device.h>
+#include <secapp_loader.h>
+#include <rpmb.h>
#include "target/display.h"
@@ -248,6 +251,7 @@
void target_init(void)
{
+ int ret = 0;
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
@@ -273,6 +277,41 @@
if (target_use_signed_kernel())
target_crypto_init_params();
+ clock_ce_enable(CE1_INSTANCE);
+
+ /* Initialize Qseecom */
+ ret = qseecom_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to initialize qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Start Qseecom */
+ ret = qseecom_tz_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to start qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ /*
+ * Load the sec app for first time
+ */
+ if (load_sec_app() < 0)
+ {
+ dprintf(CRITICAL, "Failed to load App for verified\n");
+ ASSERT(0);
+ }
+
+ if (rpmb_init() < 0)
+ {
+ dprintf(CRITICAL, "RPMB init failed\n");
+ ASSERT(0);
+ }
+
#if SMD_SUPPORT
rpm_smd_init();
#endif
@@ -309,6 +348,7 @@
case MSM8952:
case MSM8956:
case MSM8976:
+ case MSMTHORIUM:
board->baseband = BASEBAND_MSM;
break;
case APQ8052:
@@ -454,6 +494,23 @@
if (target_is_ssd_enabled())
clock_ce_disable(CE1_INSTANCE);
+
+ if (is_sec_app_loaded())
+ {
+ if (send_milestone_call_to_tz() < 0)
+ {
+ dprintf(CRITICAL, "Failed to unload App for rpmb\n");
+ ASSERT(0);
+ }
+ }
+
+ if (rpmb_uninit() < 0)
+ {
+ dprintf(CRITICAL, "RPMB uninit failed\n");
+ ASSERT(0);
+ }
+
+ clock_ce_disable(CE1_INSTANCE);
#if SMD_SUPPORT
rpm_smd_uninit();
#endif
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
index 57e069f..4d448bf 100644
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -53,6 +53,7 @@
#include "include/panel_hx8399a_1080p_video.h"
#include "include/panel_nt35597_wqxga_dsc_video.h"
#include "include/panel_nt35597_wqxga_dsc_cmd.h"
+#include "include/panel_hx8394d_720p_video.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -67,6 +68,7 @@
HX8399A_1080P_VIDEO_PANEL,
NT35597_WQXGA_DSC_VIDEO_PANEL,
NT35597_WQXGA_DSC_CMD_PANEL,
+ HX8394D_720P_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -88,6 +90,7 @@
{"hx8399a_1080p_video", HX8399A_1080P_VIDEO_PANEL},
{"nt35597_wqxga_dsc_video", NT35597_WQXGA_DSC_VIDEO_PANEL},
{"nt35597_wqxga_dsc_cmd", NT35597_WQXGA_DSC_CMD_PANEL},
+ {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
};
static uint32_t panel_id;
@@ -403,6 +406,31 @@
pinfo->dsc.dsi_dsc_config = mdss_dsc_dsi_config;
pinfo->dsc.mdp_dsc_config = mdss_dsc_mdp_config;
break;
+ case HX8394D_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8394d_720p_video_panel_data;
+ panelstruct->panelres = &hx8394d_720p_video_panel_res;
+ panelstruct->color = &hx8394d_720p_video_color;
+ panelstruct->videopanel = &hx8394d_720p_video_video_panel;
+ panelstruct->commandpanel = &hx8394d_720p_video_command_panel;
+ panelstruct->state = &hx8394d_720p_video_state;
+ panelstruct->laneconfig = &hx8394d_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8394d_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394d_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &hx8394d_720p_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8394d_720p_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8394D_720P_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8394d_720p_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8394D_720P_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8394d_720p_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
diff --git a/target/msm8952/rules.mk b/target/msm8952/rules.mk
index 142cd88..fd3a56e 100644
--- a/target/msm8952/rules.mk
+++ b/target/msm8952/rules.mk
@@ -12,7 +12,7 @@
MEMSIZE := 0x00300000 # 3MB
BASE_ADDR := 0x80000000
-SCRATCH_ADDR := 0x90000000
+SCRATCH_ADDR := 0x90100000
DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index f4664ec..b2585fc 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -51,15 +51,6 @@
#include "include/display_resource.h"
#include "gcdb_display.h"
-#define DSC_CMD_PANEL "dsc_cmd_panel"
-#define DSC_VID_PANEL "dsc_vid_panel"
-#define DSC_VID_PANEL_ADV7533_1080P "dsc_vid_panel_adv7533_1080p"
-#define DSC_CMD_PANEL_ADV7533_1080P "dsc_cmd_panel_adv7533_1080p"
-#define DSC_CMD_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_cmd:cfg:single_dsi"
-#define DSC_VID_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_video:cfg:single_dsi"
-#define DSC_CMD_PANEL_ADV7533_1080P_STRING "1:dsi:0:qcom,mdss_dsi_adv7533_1080p:1:qcom,mdss_dsi_nt35597_dsc_wqxga_cmd:cfg:dual_dsi"
-#define DSC_VID_PANEL_ADV7533_1080P_STRING "1:dsi:0:qcom,mdss_dsi_adv7533_1080p:1:qcom,mdss_dsi_nt35597_dsc_wqxga_video:cfg:dual_dsi"
-
/*---------------------------------------------------------------------------*/
/* GPIO configuration */
/*---------------------------------------------------------------------------*/
@@ -529,55 +520,7 @@
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
{
- int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
- bool ret = true;
- struct oem_panel_data oem = mdss_dsi_get_oem_data();
-
- if (!strcmp(oem.panel, DSC_CMD_PANEL)) {
- if (buf_size < (prefix_string_len +
- strlen(DSC_CMD_PANEL_STRING))) {
- dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
- return false;
- }
- strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
- buf_size -= prefix_string_len;
- pbuf += prefix_string_len;
- strlcpy(pbuf, DSC_CMD_PANEL_STRING, buf_size);
- } else if (!strcmp(oem.panel, DSC_VID_PANEL)) {
- if (buf_size < (prefix_string_len +
- strlen(DSC_VID_PANEL_STRING))) {
- dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
- return false;
- }
- strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
- buf_size -= prefix_string_len;
- pbuf += prefix_string_len;
- strlcpy(pbuf, DSC_VID_PANEL_STRING, buf_size);
- } else if (!strcmp(oem.panel, DSC_VID_PANEL_ADV7533_1080P)) {
- if (buf_size < (prefix_string_len +
- strlen(DSC_VID_PANEL_ADV7533_1080P_STRING))) {
- dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
- return false;
- }
- strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
- buf_size -= prefix_string_len;
- pbuf += prefix_string_len;
- strlcpy(pbuf, DSC_VID_PANEL_ADV7533_1080P_STRING, buf_size);
- } else if (!strcmp(oem.panel, DSC_CMD_PANEL_ADV7533_1080P)) {
- if (buf_size < (prefix_string_len +
- strlen(DSC_CMD_PANEL_ADV7533_1080P_STRING))) {
- dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
- return false;
- }
- strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
- buf_size -= prefix_string_len;
- pbuf += prefix_string_len;
- strlcpy(pbuf, DSC_CMD_PANEL_ADV7533_1080P_STRING, buf_size);
- } else {
- ret = gcdb_display_cmdline_arg(pbuf, buf_size);
- }
-
- return ret;
+ return gcdb_display_cmdline_arg(pbuf, buf_size);
}
void target_display_init(const char *panel_name)
@@ -592,10 +535,6 @@
if (!strcmp(oem.panel, NO_PANEL_CONFIG)
|| !strcmp(oem.panel, SIM_VIDEO_PANEL)
|| !strcmp(oem.panel, SIM_CMD_PANEL)
- || !strcmp(oem.panel, DSC_CMD_PANEL)
- || !strcmp(oem.panel, DSC_VID_PANEL)
- || !strcmp(oem.panel, DSC_CMD_PANEL_ADV7533_1080P)
- || !strcmp(oem.panel, DSC_VID_PANEL_ADV7533_1080P)
|| oem.skip) {
dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
oem.panel);
diff --git a/target/msm8996/init.c b/target/msm8996/init.c
index 4d1fad1..a80ad30 100644
--- a/target/msm8996/init.c
+++ b/target/msm8996/init.c
@@ -293,8 +293,16 @@
* Charging should happen as early as possible, any other driver
* initialization before this should consider the power impact
*/
- if (board_hardware_id() == HW_PLATFORM_MTP)
- pm_appsbl_chg_check_weak_battery_status(1);
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ pm_appsbl_chg_check_weak_battery_status(1);
+ break;
+ default:
+ /* Charging not supported */
+ break;
+ };
#endif
/* Initialize Qseecom */
@@ -347,12 +355,13 @@
int target_cont_splash_screen()
{
uint8_t splash_screen = 0;
- if(!splash_override) {
+ if(!splash_override && !pm_appsbl_charging_in_progress()) {
switch(board_hardware_id())
{
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_QRD:
dprintf(SPEW, "Target_cont_splash=1\n");
splash_screen = 1;
break;
diff --git a/target/msm8996/oem_panel.c b/target/msm8996/oem_panel.c
index 3fbb979..25ef683 100644
--- a/target/msm8996/oem_panel.c
+++ b/target/msm8996/oem_panel.c
@@ -53,6 +53,7 @@
#include "include/panel_sharp_wqxga_dualdsi_video.h"
#include "include/panel_jdi_qhd_dualdsi_video.h"
#include "include/panel_jdi_qhd_dualdsi_cmd.h"
+#include "include/panel_r69007_wqxga_cmd.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -65,6 +66,7 @@
NT35597_WQXGA_DSC_CMD_PANEL,
JDI_QHD_DUALDSI_VIDEO_PANEL,
JDI_QHD_DUALDSI_CMD_PANEL,
+ R69007_WQXGA_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -80,6 +82,7 @@
{"nt35597_wqxga_dsc_cmd", NT35597_WQXGA_DSC_CMD_PANEL},
{"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
+ {"r69007_wqxga_cmd", R69007_WQXGA_CMD_PANEL},
};
static uint32_t panel_id;
@@ -341,6 +344,36 @@
jdi_qhd_dualdsi_thulium_video_timings,
MAX_TIMING_CONFIG * sizeof(uint32_t));
break;
+ case R69007_WQXGA_CMD_PANEL:
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
+ panelstruct->paneldata = &r69007_wqxga_cmd_panel_data;
+ panelstruct->panelres = &r69007_wqxga_cmd_panel_res;
+ panelstruct->color = &r69007_wqxga_cmd_color;
+ panelstruct->videopanel = &r69007_wqxga_cmd_video_panel;
+ panelstruct->commandpanel = &r69007_wqxga_cmd_command_panel;
+ panelstruct->state = &r69007_wqxga_cmd_state;
+ panelstruct->laneconfig = &r69007_wqxga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &r69007_wqxga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &r69007_wqxga_cmd_reset_seq;
+ panelstruct->backlightinfo = &r69007_wqxga_cmd_backlight;
+
+ pinfo->labibb = &r69007_wqxga_cmd_labibb;
+
+ pinfo->mipi.panel_on_cmds
+ = r69007_wqxga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = R69007_WQXGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = r69007_wqxga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = R69007_WQXGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ r69007_wqxga_thulium_cmd_timings,
+ MAX_TIMING_CONFIG * sizeof(uint32_t));
+ break;
default:
case UNKNOWN_PANEL:
pan_type = PANEL_TYPE_UNKNOWN;
@@ -381,6 +414,9 @@
case HW_PLATFORM_SURF:
panel_id = SHARP_WQXGA_DUALDSI_VIDEO_PANEL;
break;
+ case HW_PLATFORM_QRD:
+ panel_id = R69007_WQXGA_CMD_PANEL;
+ break;
default:
dprintf(CRITICAL, "Display not enabled for %d HW type\n"
, hw_id);
diff --git a/target/msm8996/target_display.c b/target/msm8996/target_display.c
index 839e23e..ebede20 100644
--- a/target/msm8996/target_display.c
+++ b/target/msm8996/target_display.c
@@ -124,7 +124,6 @@
static int thulium_wled_backlight_ctrl(uint8_t enable)
{
qpnp_wled_enable_backlight(enable);
- qpnp_ibb_enable(enable);
return NO_ERROR;
}
@@ -243,8 +242,6 @@
pm_pwm_enable(false);
pm8x41_enable_mpp(&mpp, MPP_DISABLE);
}
- /* Need delay before power on regulators */
- mdelay(20);
/* Enable WLED backlight control */
ret = thulium_wled_backlight_ctrl(enable);
break;
@@ -260,8 +257,6 @@
} else {
pm8x41_enable_mpp(&mpp, MPP_DISABLE);
}
- /* Need delay before power on regulators */
- mdelay(20);
ret = thulium_pwm_backlight_ctrl(enable);
break;
default:
@@ -421,7 +416,7 @@
mdelay(10);
wled_init(pinfo);
qpnp_ibb_enable(true); /* +5V and -5V */
- mdelay(50);
+ mdelay(20);
if (pinfo->lcd_reg_en)
lcd_reg_enable();
diff --git a/target/msmtitanium/init.c b/target/msmtitanium/init.c
new file mode 100755
index 0000000..8a80a8c
--- /dev/null
+++ b/target/msmtitanium/init.c
@@ -0,0 +1,327 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <platform/gpio.h>
+#include <dev/keys.h>
+#include <spmi_v2.h>
+#include <pm8x41.h>
+#include <pm8x41_hw.h>
+#include <board.h>
+#include <baseband.h>
+#include <hsusb.h>
+#include <scm.h>
+#include <platform/irqs.h>
+#include <platform/clock.h>
+#include <platform/timer.h>
+#include <crypto5_wrapper.h>
+#include <partition_parser.h>
+#include <stdlib.h>
+#include <rpm-smd.h>
+#include <spmi.h>
+#include <sdhci_msm.h>
+#include <clock.h>
+
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+#define TLMM_VOL_UP_BTN_GPIO 85
+
+#define FASTBOOT_MODE 0x77665500
+#define PON_SOFT_RB_SPARE 0x88F
+
+struct mmc_device *dev;
+
+static uint32_t mmc_pwrctl_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(1, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0},
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0},
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK , 0},
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0},
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
+ };
+
+ struct tlmm_cfgs sdc1_rclk_cfg[] =
+ {
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, 0},
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+ tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
+}
+
+void target_sdc_init()
+{
+ struct mmc_config_data config;
+
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
+
+ config.slot = MMC_SLOT;
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 1;
+
+ if (!(dev = mmc_init(&config))) {
+ /* Try different config. values */
+ config.max_clk_rate = MMC_CLK_200MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
+
+ if (!(dev = mmc_init(&config))) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+}
+
+void *target_mmc_device()
+{
+ return (void *) dev;
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+
+ gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+ /* Wait for the gpio config to take effect - debounce time */
+ thread_sleep(10);
+
+ /* Get status of GPIO */
+ status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
+
+ /* Active high signal. */
+ return status;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ /* Volume down button tied in with PMIC RESIN. */
+ return pm8x41_resin_status();
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ target_sdc_init();
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+
+#if LONG_PRESS_POWER_ON
+ shutdown_detect();
+#endif
+}
+
+void target_serialno(unsigned char *buf)
+{
+ uint32_t serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned board_machtype(void)
+{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ /* This is already filled as part of board.c */
+}
+
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+
+ switch(platform) {
+ case MSMTITANIUM:
+ board->baseband = BASEBAND_MSM;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ };
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+ int ret = 0;
+ ret = scm_dload_mode(mode);
+
+ pm8x41_clear_pmic_watchdog();
+
+ return ret;
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N)))
+ return 1;
+ else
+ return 0;
+}
+
+/* UTMI MUX configuration to connect PHY to SNPS controller:
+ * Configure primary HS phy mux to use UTMI interface
+ * (connected to usb30 controller).
+ */
+static void tcsr_hs_phy_mux_configure(void)
+{
+ uint32_t reg;
+
+ reg = readl(USB2_PHY_SEL);
+
+ writel(reg | 0x1, USB2_PHY_SEL);
+}
+
+/* configure hs phy mux if using dwc controller */
+void target_usb_phy_mux_configure(void)
+{
+ if(!strcmp(target_usb_controller(), "dwc"))
+ {
+ tcsr_hs_phy_mux_configure();
+ }
+}
+
+/* Initialize target specific USB handlers */
+target_usb_iface_t* target_usb30_init()
+{
+ target_usb_iface_t *t_usb_iface;
+
+ t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ ASSERT(t_usb_iface);
+
+ t_usb_iface->mux_config = target_usb_phy_mux_configure;
+ //t_usb_iface->clock_init = clock_usb30_init;
+
+ return t_usb_iface;
+}
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+ return "dwc";
+}
+
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
+
+
+void pmic_reset_configure(uint8_t reset_type)
+{
+ pm8x41_reset_configure(reset_type);
+}
diff --git a/target/msmtitanium/meminfo.c b/target/msmtitanium/meminfo.c
new file mode 100644
index 0000000..b2f46df
--- /dev/null
+++ b/target/msmtitanium/meminfo.c
@@ -0,0 +1,85 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ ram_partition ptn_entry;
+ unsigned int index;
+ int ret = 0;
+ uint32_t len = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Calculating the size of the mem_info_ptr */
+ for (index = 0 ; index < len; index++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ptn_entry.start,
+ ptn_entry.size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+ goto target_dev_tree_mem_err;
+ }
+ }
+ }
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
diff --git a/target/msmtitanium/rules.mk b/target/msmtitanium/rules.mk
new file mode 100644
index 0000000..b338bea
--- /dev/null
+++ b/target/msmtitanium/rules.mk
@@ -0,0 +1,29 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := msmtitanium
+
+MEMBASE := 0x8F600000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x80000000
+SCRATCH_ADDR := 0x90000000
+
+MODULES += \
+ dev/keys \
+ dev/vib \
+ lib/ptable \
+ dev/pmic/pm8x41 \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o
diff --git a/target/msmtitanium/tools/makefile b/target/msmtitanium/tools/makefile
new file mode 100644
index 0000000..da48f0d
--- /dev/null
+++ b/target/msmtitanium/tools/makefile
@@ -0,0 +1,12 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTOUT_DIR := $(BUILDDIR)
+else
+APPSBOOTOUT_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+APPSBOOTHEADER: emmc_appsboot.mbn
+
+emmc_appsboot.mbn: $(OUTELF_STRIP)
+ $(hide) cp -f $(OUTELF_STRIP) $(APPSBOOTOUT_DIR)/emmc_appsboot.mbn