Merge "platform: msm8909: Add support for splash on 8909"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index ce8751c..fcd0ee8 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -55,6 +55,7 @@
#include <platform/iomap.h>
#include <boot_device.h>
#include <boot_verifier.h>
+#include <image_verify.h>
#if DEVICE_TREE
#include <libfdt.h>
@@ -156,7 +157,7 @@
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
-static device_info device = {DEVICE_MAGIC, 0, 0, 0, 0, 0};
+static device_info device = {DEVICE_MAGIC, 0, 0, 0, 0, {0}};
struct atag_ptbl_entry
{
@@ -593,7 +594,7 @@
uint32_t tags_phys = PA((addr_t)tags);
struct kernel64_hdr *kptr = (struct kernel64_hdr*)kernel;
- ramdisk = PA(ramdisk);
+ ramdisk = (void *)PA((addr_t)ramdisk);
final_cmdline = update_cmdline((const char*)cmdline);
@@ -601,7 +602,7 @@
dprintf(INFO, "Updating device tree: start\n");
/* Update the Device Tree */
- ret = update_device_tree((void *)tags, final_cmdline, ramdisk, ramdisk_size);
+ ret = update_device_tree((void *)tags,(const char *)final_cmdline, ramdisk, ramdisk_size);
if(ret)
{
dprintf(CRITICAL, "ERROR: Updating Device Tree Failed \n");
@@ -634,7 +635,7 @@
dprintf(INFO, "booting linux @ %p, ramdisk @ %p (%d), tags/device tree @ %p\n",
- entry, ramdisk, ramdisk_size, tags_phys);
+ entry, ramdisk, ramdisk_size, (void *)tags_phys);
enter_critical_section();
@@ -781,7 +782,7 @@
}
buf = (char *) memalign(CACHE_LINE, ROUNDUP(page_size, CACHE_LINE));
ASSERT(buf);
- if (mmc_read(offset, (unsigned int *)buf, page_size))
+ if (mmc_read(offset, (uint32_t *)buf, page_size))
{
dprintf(INFO, "mmc read failure /bootselect %d\n", page_size);
free(buf);
@@ -890,7 +891,7 @@
}
}
- if (mmc_read(ptn + offset, (unsigned int *) buf, page_size)) {
+ if (mmc_read(ptn + offset, (uint32_t *) buf, page_size)) {
dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
return -1;
}
@@ -914,7 +915,7 @@
* which lives in the second page for arm64 targets.
*/
- if (mmc_read(ptn + page_size, (unsigned int *) kbuf, page_size)) {
+ if (mmc_read(ptn + page_size, (uint32_t *) kbuf, page_size)) {
dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
return -1;
}
@@ -983,7 +984,7 @@
dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
- if (check_aboot_addr_range_overlap(image_addr, imagesize_actual))
+ if (check_aboot_addr_range_overlap((uint32_t)image_addr, imagesize_actual))
{
dprintf(CRITICAL, "Boot image buffer address overlaps with aboot addresses.\n");
return -1;
@@ -1001,7 +1002,7 @@
offset = imagesize_actual;
- if (check_aboot_addr_range_overlap(image_addr + offset, page_size))
+ if (check_aboot_addr_range_overlap((uint32_t)image_addr + offset, page_size))
{
dprintf(CRITICAL, "Signature read buffer address overlaps with aboot addresses.\n");
return -1;
@@ -1014,7 +1015,7 @@
return -1;
}
- verify_signed_bootimg(image_addr, imagesize_actual);
+ verify_signed_bootimg((uint32_t)image_addr, imagesize_actual);
/* Move kernel, ramdisk and device tree to correct address */
memmove((void*) hdr->kernel_addr, (char *)(image_addr + page_size), hdr->kernel_size);
@@ -1308,7 +1309,7 @@
return -1;
}
- verify_signed_bootimg(image_addr, imagesize_actual);
+ verify_signed_bootimg((uint32_t)image_addr, imagesize_actual);
/* Move kernel and ramdisk to correct address */
memmove((void*) hdr->kernel_addr, (char *)(image_addr + page_size), hdr->kernel_size);
@@ -1849,7 +1850,6 @@
void cmd_erase_mmc(const char *arg, void *data, unsigned sz)
{
- BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
unsigned long long ptn = 0;
unsigned long long size = 0;
int index = INVALID_PTN;
@@ -1884,6 +1884,7 @@
return;
}
#else
+ BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
size = partition_get_size(index);
if (size > DEFAULT_ERASE_SIZE)
size = DEFAULT_ERASE_SIZE;
@@ -1916,7 +1917,7 @@
uint8_t lun = 0;
bool lun_set = false;
- token = strtok(arg, ":");
+ token = strtok((char *)arg, ":");
pname = token;
token = strtok(NULL, ":");
if(token)
@@ -2001,7 +2002,7 @@
unsigned long long ptn = 0;
unsigned long long size = 0;
int index = INVALID_PTN;
- int i;
+ uint32_t i;
uint8_t lun = 0;
index = partition_get_index(arg);
@@ -2424,7 +2425,7 @@
fastboot_okay("");
}
-static struct fbimage logo_header = {0};
+static struct fbimage logo_header = {{{0}, 0, 0, 0, {0}}, 0};
struct fbimage* splash_screen_flash();
int splash_screen_check_header(struct fbimage *logo)
@@ -2504,7 +2505,7 @@
return NULL;
}
- if (mmc_read(ptn, (unsigned int *) logo, sizeof(logo->header))) {
+ if (mmc_read(ptn, (uint32_t *) logo, sizeof(logo->header))) {
dprintf(CRITICAL, "ERROR: Cannot read splash image header\n");
return NULL;
}
@@ -2522,7 +2523,7 @@
}
uint8_t *base = (uint8_t *) fb_display->base;
if (mmc_read(ptn + sizeof(logo->header),
- base,
+ (uint32_t *)base,
((((logo->header.width * logo->header.height * fb_display->bpp/8) + 511) >> 9) << 9))) {
fbcon_clear();
dprintf(CRITICAL, "ERROR: Cannot read splash image from partition\n");
@@ -2630,7 +2631,7 @@
{"preflash", cmd_preflash},
{"oem enable-charger-screen", cmd_oem_enable_charger_screen},
{"oem disable-charger-screen", cmd_oem_disable_charger_screen},
- {"oem-select-display-panel", cmd_oem_select_display_panel},
+ {"oem select-display-panel", cmd_oem_select_display_panel},
#endif
};
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index f905627..4017ec3 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -287,7 +287,7 @@
while (len > 0) {
xfer = (len > MAX_USBFS_BULK_SIZE) ? MAX_USBFS_BULK_SIZE : len;
- req->buf = PA((addr_t)buf);
+ req->buf = (unsigned char *)PA((addr_t)buf);
req->length = xfer;
req->complete = req_complete;
r = udc_request_queue(out, req);
@@ -313,7 +313,7 @@
* Force reload of buffer from memory
* since transaction is complete now.
*/
- arch_invalidate_cache_range(_buf, count);
+ arch_invalidate_cache_range((addr_t)_buf, count);
return count;
oops:
@@ -333,7 +333,7 @@
while (len > 0) {
xfer = (len > MAX_USBFS_BULK_SIZE) ? MAX_USBFS_BULK_SIZE : len;
- req->buf = PA((addr_t)_buf);
+ req->buf = (unsigned char *)PA((addr_t)_buf);
req->length = xfer;
req->complete = req_complete;
r = udc_request_queue(in, req);
@@ -372,10 +372,10 @@
if (reason == 0)
reason = "";
- snprintf(response, MAX_RSP_SIZE, "%s%s", code, reason);
+ snprintf((char *)response, MAX_RSP_SIZE, "%s%s", code, reason);
fastboot_state = STATE_COMPLETE;
- usb_if.usb_write(response, strlen(response));
+ usb_if.usb_write(response, strlen((const char *)response));
}
@@ -389,9 +389,9 @@
if (reason == 0)
return;
- snprintf(response, MAX_RSP_SIZE, "INFO%s", reason);
+ snprintf((char *)response, MAX_RSP_SIZE, "INFO%s", reason);
- usb_if.usb_write(response, strlen(response));
+ usb_if.usb_write(response, strlen((const char *)response));
}
void fastboot_fail(const char *reason)
@@ -429,8 +429,8 @@
return;
}
- snprintf(response, MAX_RSP_SIZE, "DATA%08x", len);
- if (usb_if.usb_write(response, strlen(response)) < 0)
+ snprintf((char *)response, MAX_RSP_SIZE, "DATA%08x", len);
+ if (usb_if.usb_write(response, strlen((const char *)response)) < 0)
return;
r = usb_if.usb_read(download_base, len);
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
index 71ee2ef..0c55e9b 100644
--- a/app/aboot/recovery.c
+++ b/app/aboot/recovery.c
@@ -42,6 +42,7 @@
#include <target.h>
#include <partition_parser.h>
#include <mmc.h>
+#include <malloc.h>
#include "recovery.h"
#include "bootimg.h"
@@ -393,7 +394,7 @@
unsigned char data[size];
int index = INVALID_PTN;
- index = partition_get_index((unsigned char *) ptn_name);
+ index = partition_get_index((const char *) ptn_name);
ptn = partition_get_offset(index);
mmc_set_lun(partition_get_lun(index));
if(ptn == 0) {
@@ -416,7 +417,7 @@
int index = INVALID_PTN;
size = mmc_get_device_blocksize();
- index = partition_get_index((unsigned char *) ptn_name);
+ index = partition_get_index((const char *) ptn_name);
ptn = partition_get_offset(index);
mmc_set_lun(partition_get_lun(index));
if(ptn == 0) {
diff --git a/app/rpmbtests/ufs_rpmb.c b/app/rpmbtests/ufs_rpmb.c
index 4798b98..7342a82 100644
--- a/app/rpmbtests/ufs_rpmb.c
+++ b/app/rpmbtests/ufs_rpmb.c
@@ -35,12 +35,12 @@
#include <ucs.h>
#include <dme.h>
#include <rpmb.h>
+#include <rand.h>
#include <string.h>
#include <stdlib.h>
#include <endian.h>
+#include <target.h>
#include "ufs_rpmb.h"
-#include <platform/iomap.h>
-#include <kernel/mutex.h>
void rpmb_run_test()
{
@@ -89,7 +89,6 @@
bool rpmb_test(struct ufs_dev *dev, uint16_t address, uint16_t rpmb_num_blocks)
{
struct rpmb_frame data_frame, result_frame[rpmb_num_blocks];
- uint8_t *temp = (uint8_t )&address;
int i = 0, ret;
uint32_t response_len = 0;
// check if address + sectors requested for read do not exceed total size of rpmb
@@ -117,7 +116,7 @@
if (ret)
{
dprintf(CRITICAL, "RPMB Read error\n");
- return;
+ return false;
}
for (i = 0; i < rpmb_num_blocks; i++)
{
diff --git a/arch/arm/mmu.c b/arch/arm/mmu.c
index 2027b41..d50c43a 100644
--- a/arch/arm/mmu.c
+++ b/arch/arm/mmu.c
@@ -27,6 +27,7 @@
#include <arch/arm.h>
#include <arch/defines.h>
#include <arch/arm/mmu.h>
+#include <platform.h>
#if ARM_WITH_MMU
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index e2e497f..cff176f 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -144,7 +144,7 @@
{
uint32_t refclk = 19200000;
uint32_t vco_rate = pll_data.vco_clock;
- uint32_t tmp, mod;
+ uint32_t tmp;
vco_rate /= 2;
pll_data.dec_start = vco_rate / refclk;
@@ -157,16 +157,13 @@
pll_data.frac_start = tmp;
vco_rate *= 2; /* restore */
- tmp = vco_rate / refclk;/* div 1000 first */
- mod = vco_rate % refclk;
- tmp *= 127;
- mod *= 127;
- mod /= refclk;
- tmp += mod;
+ tmp = vco_rate / (refclk / 1000);/* div 1000 first */
+ tmp *= 1024;
+ tmp /= 1000;
tmp /= 10;
- pll_data.lock_comp = tmp;
+ pll_data.lock_comp = tmp - 1;
- dprintf(SPEW, "%s: dec_start=%u dec_frac=%u lock_comp=%u\n", __func__,
+ dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
}
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index ee0070d..b261a34 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -43,8 +43,8 @@
#define HALFBIT_CLOCK3 44000000 /* VCO min clock div by 8 */
#define HALFBIT_CLOCK4 40000000 /* VCO min clock div by 9 */
-#define VCO_MIN_CLOCK_20NM 1000000000
-#define VCO_MAX_CLOCK_20NM 2000000000
+#define VCO_MIN_CLOCK_20NM 300000000
+#define VCO_MAX_CLOCK_20NM 1500000000
#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
index 3704222..2fccf8c 100644
--- a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -76,7 +76,7 @@
static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_on_command[] = {
{0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0x0a},
- {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x0a}
+ {0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x02}
};
#define SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND 2
@@ -137,7 +137,7 @@
/* Panel reset sequence */
/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence sharp_wqxga_dualdsi_video_reset_seq = {
- {1, 0, 1, }, {10, 10, 120, }, 2
+ {1, 0, 1, }, {2, 5, 120, }, 2
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 9734574..c09da68 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -63,10 +63,18 @@
pinfo->lcdc.v_front_porch = pstruct->panelres->vfront_porch;
pinfo->lcdc.v_pulse_width = pstruct->panelres->vpulse_width;
pinfo->lcdc.hsync_skew = pstruct->panelres->hsync_skew;
- pinfo->lcdc.xres_pad = pstruct->panelres->hleft_border +
- pstruct->panelres->hright_border;
- pinfo->lcdc.yres_pad = pstruct->panelres->vtop_border +
- pstruct->panelres->vbottom_border;
+
+ pinfo->border_top = pstruct->panelres->vtop_border;
+ pinfo->border_bottom = pstruct->panelres->vbottom_border;
+ pinfo->border_left = pstruct->panelres->hleft_border;
+ pinfo->border_right = pstruct->panelres->hright_border;
+
+ dprintf(SPEW, "%s: left=%d right=%d top=%d bottom=%d\n", __func__,
+ pinfo->border_left, pinfo->border_right,
+ pinfo->border_top, pinfo->border_bottom);
+
+ pinfo->xres += (pinfo->border_left + pinfo->border_right);
+ pinfo->yres += (pinfo->border_top + pinfo->border_bottom);
if (pstruct->paneldata->panel_operating_mode & DUAL_PIPE_FLAG)
pinfo->lcdc.dual_pipe = 1;
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 9315f72..328d21d 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -37,11 +37,10 @@
static uint8_t mpp_slave_id;
-uint8_t pmi8994_config_mpp_slave_id(uint8_t slave_id)
+void pmi8994_config_mpp_slave_id(uint8_t slave_id)
{
mpp_slave_id = slave_id;
}
-
/* SPMI helper functions */
uint8_t pm8x41_reg_read(uint32_t addr)
{
diff --git a/include/dev/gpio.h b/include/dev/gpio.h
index 6e1bce8..50386e9 100644
--- a/include/dev/gpio.h
+++ b/include/dev/gpio.h
@@ -2,6 +2,8 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -26,6 +28,8 @@
* SUCH DAMAGE.
*/
+#include <platform/gpio.h>
+
#ifndef __DEV_GPIO_H
#define __DEV_GPIO_H
diff --git a/include/platform.h b/include/platform.h
index b427b04..a76c68b 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -44,6 +44,7 @@
void platform_init_mmu_mappings(void);
addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr);
addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr);
+addr_t get_bs_info_addr(void);
void display_init(void);
void display_shutdown(void);
@@ -56,4 +57,7 @@
void reboot_device(unsigned);
int set_download_mode(enum dload_mode mode);
uint32_t platform_get_smem_base_addr();
+uint32_t platform_get_sclk_count(void);
+void clock_config_cdc(uint32_t interface);
+int platform_is_msm8939();
#endif
diff --git a/include/stdio.h b/include/stdio.h
index ebabfca..5052636 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -4,9 +4,21 @@
#include <debug.h>
#include <printf.h>
+typedef struct {
+ char *fpos; /* Current position of file pointer (absolute address) */
+ void *base; /* Pointer to the base of the file */
+ unsigned short handle; /* File handle */
+ short flags; /* Flags (see FileFlags) */
+ short unget; /* 1-byte buffer for ungetc (b15=1 if non-empty) */
+ unsigned long alloc; /* Number of currently allocated bytes for the file */
+ unsigned short buffincrement; /* Number of bytes allocated at once */
+} FILE;
+
void putc(char c);
int puts(const char *str);
int getc(char *c); // XXX not really getc
+size_t fwrite(const void *buf, size_t size, size_t count, FILE *stream);
+int sscanf(const char *str, const char *format, ...);
#endif
diff --git a/include/stdlib.h b/include/stdlib.h
index 5c5145a..4db77fa 100644
--- a/include/stdlib.h
+++ b/include/stdlib.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013, 2014 The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -39,6 +39,9 @@
long atol(const char *num);
unsigned long atoul(const char *num);
int itoa(int num, unsigned char* str, int len, int base);
+long int strtol(const char *nptr, char **endptr, int base);
+char *getenv(const char *atypeofinformation);
+void qsort(void *buf, size_t num, size_t size, int (*compare) (const void *, const void *));
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
diff --git a/include/target.h b/include/target.h
index 16a4268..055634b 100644
--- a/include/target.h
+++ b/include/target.h
@@ -25,7 +25,6 @@
#ifndef __TARGET_H
#define __TARGET_H
-
/* Target helper functions exposed to USB driver */
typedef struct {
void (*mux_config) ();
@@ -76,4 +75,12 @@
uint32_t target_hw_interposer();
uint32_t target_override_pll();
uint32_t target_ddr_cfg_val();
+void target_usb_init(void);
+void target_usb_stop(void);
+uint32_t target_get_hlos_subtype(void);
+void shutdown_device();
+bool target_warm_boot(void);
+bool target_use_signed_kernel(void);
+int _emmc_recovery_init(void);
+void ulpi_write(unsigned val, unsigned reg);
#endif
diff --git a/kernel/thread.c b/kernel/thread.c
index 58dff8d..2c205ee 100644
--- a/kernel/thread.c
+++ b/kernel/thread.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008-2009 Travis Geiselbrecht
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -262,6 +264,7 @@
thread_resched();
panic("somehow fell through thread_exit()\n");
+ for(;;);
}
static void idle_thread_routine(void)
diff --git a/kernel/timer.c b/kernel/timer.c
index dd5cf9f..9a472f5 100644
--- a/kernel/timer.c
+++ b/kernel/timer.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008-2009 Travis Geiselbrecht
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -264,7 +266,8 @@
#endif
// XXX fix this, should return ret
- return INT_RESCHEDULE;
+ ret = INT_RESCHEDULE;
+ return ret;
}
void timer_init(void)
diff --git a/platform/fsm9010/include/platform/iomap.h b/platform/fsm9010/include/platform/iomap.h
index 65f46fa..fca1800 100644
--- a/platform/fsm9010/include/platform/iomap.h
+++ b/platform/fsm9010/include/platform/iomap.h
@@ -35,7 +35,7 @@
#define SDRAM_START_ADDR 0x00000000
#define SDRAM_SEC_BANK_START_ADDR 0x10000000
-#define MSM_SHARED_BASE 0x0FA00000
+#define MSM_SHARED_BASE 0x13600000
#define RPM_MSG_RAM_BASE 0xFC42B000
#define SYSTEM_IMEM_BASE 0xFE800000
diff --git a/platform/init.c b/platform/init.c
index 412184e..095f6e2 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -97,7 +97,7 @@
__WEAK addr_t get_bs_info_addr()
{
- return NULL;
+ return 0;
}
__WEAK uint32_t platform_get_sclk_count(void)
@@ -105,8 +105,9 @@
return 0;
}
-__WEAK void clock_config_cdc(uint8_t slot)
+__WEAK void clock_config_cdc(uint32_t slot)
{
+
}
__WEAK int get_target_boot_params(const char *cmdline, const char *part,
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 52aa420..36b2a3a 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -614,7 +614,7 @@
switch(dtb_info) {
case DTB_FOUNDRY:
current_info = ((dt_node_tmp1->dt_entry_m->platform_id) & 0x00ff0000);
- board_info = board_foundry_id();
+ board_info = board_foundry_id() << 16;
break;
case DTB_PMIC_MODEL:
for (i = 0; i < 4; i++) {
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index 8b22384..61efb47 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -53,7 +53,7 @@
return UFS_SUCCESS;
dme_send_linkstartup_req_err:
- dprintf(CRITICAL, "DME_LINKSTARTUP command failed.\n");
+ dprintf(CRITICAL, "%s:%d DME_LINKSTARTUP command failed.\n",__func__, __LINE__);
return -UFS_FAILURE;
}
@@ -75,7 +75,7 @@
return UFS_SUCCESS;
dme_get_req_err:
- dprintf(CRITICAL, "DME_GET command failed.\n");
+ dprintf(CRITICAL, "%s:%d DME_GET command failed.\n", __func__, __LINE__);
return -UFS_FAILURE;
}
@@ -89,9 +89,15 @@
resp_upiu = (struct upiu_trans_mgmt_query_hdr *) req_upiu->resp_ptr;
if (resp_upiu->opcode != req_upiu->opcode)
+ {
+ dprintf(CRITICAL, "%s:%d Opcode from respose does not match with Opcode from request\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
if (resp_upiu->basic_hdr.response != UPIU_QUERY_RESP_SUCCESS)
+ {
+ dprintf(CRITICAL, "%s:%d UPIU Response is not SUCCESS\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
switch (resp_upiu->opcode)
{
@@ -99,7 +105,7 @@
case UPIU_QUERY_OP_SET_FLAG:
if (buf_len < sizeof(uint32_t))
{
- dprintf(CRITICAL, "Insufficient buffer space.\n");
+ dprintf(CRITICAL, "%s:%d Insufficient buffer space.\n", __func__, __LINE__);
return -UFS_FAILURE;
}
@@ -109,8 +115,9 @@
case UPIU_QUERY_OP_CLEAR_FLAG:
case UPIU_QUERY_OP_READ_DESCRIPTOR:
break;
- default: dprintf(CRITICAL, "UPIU query opcode not supported.\n");
- return -UFS_FAILURE;
+ default:
+ dprintf(CRITICAL, "%s:%d UPIU query opcode not supported.\n", __func__, __LINE__);
+ return -UFS_FAILURE;
}
return UFS_SUCCESS;
@@ -171,7 +178,10 @@
if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Power On Write Read Request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
@@ -184,9 +194,16 @@
dprintf(CRITICAL, "Power on Write Protect request failed. Retrying again.\n");
if (dme_send_query_upiu(dev, &set_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Power On Write Set Request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
+
if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Power On Write Read Request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
if (*result == 1)
break;
@@ -216,7 +233,10 @@
if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Device Init Read request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
@@ -228,10 +248,16 @@
try_again--;
if (dme_send_query_upiu(dev, &set_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Device Init Set request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
if (dme_send_query_upiu(dev, &read_query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Device Init Read request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
if (*result == 1)
break;
@@ -251,11 +277,14 @@
sizeof(struct ufs_string_desc)};
if (dme_send_query_upiu(dev, &query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Read String Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
if (desc->desc_len != 0)
return UFS_SUCCESS;
-
+ dprintf(CRITICAL, "%s:%d DME Read String Descriptor is length 0\n", __func__, __LINE__);
return -UFS_FAILURE;
}
@@ -266,9 +295,12 @@
int index=0,len=0;
if(desc->desc_len <= 0)
+ {
+ dprintf(CRITICAL, "%s:%d Invalid string descriptor length\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
- ptr = desc->serial_num;
+ ptr = (uint16_t *) desc->serial_num;
len = (desc->desc_len-2)/2;
for(index=0; index<len; index++)
@@ -284,8 +316,8 @@
{
STACKBUF_DMA_ALIGN(dev_desc, sizeof(struct ufs_dev_desc));
STACKBUF_DMA_ALIGN(desc, sizeof(struct ufs_string_desc));
- struct ufs_dev_desc *device_desc = dev_desc;
- struct ufs_string_desc *str_desc = desc;
+ struct ufs_dev_desc *device_desc = (struct ufs_dev_desc *) dev_desc;
+ struct ufs_string_desc *str_desc = (struct ufs_string_desc *) desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_DEVICE,
0,
@@ -294,7 +326,10 @@
sizeof(struct ufs_dev_desc)};
if (dme_send_query_upiu(dev, &query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Read Device Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
/* Flush buffer. */
arch_invalidate_cache_range((addr_t) device_desc, sizeof(struct ufs_dev_desc));
@@ -303,7 +338,7 @@
dev->num_lus = device_desc->num_lu;
/* Get serial number for the device based on the string index. */
- if (dme_read_string_desc(dev, device_desc->serial_num, desc))
+ if (dme_read_string_desc(dev, device_desc->serial_num, (struct ufs_string_desc *) desc))
return -UFS_FAILURE;
/* Flush buffer. */
@@ -319,7 +354,7 @@
{
struct ufs_geometry_desc *desc;
STACKBUF_DMA_ALIGN(geometry_desc, sizeof(struct ufs_geometry_desc));
- desc = geometry_desc;
+ desc = (struct ufs_geometry_desc *) geometry_desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_GEOMETRY,
0,
@@ -328,7 +363,10 @@
sizeof(struct ufs_geometry_desc)};
if (dme_send_query_upiu(dev, &query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Read Geometry Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
// Flush buffer.
arch_invalidate_cache_range((addr_t) desc, sizeof(struct ufs_geometry_desc));
@@ -339,7 +377,7 @@
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index)
{
STACKBUF_DMA_ALIGN(unit_desc, sizeof(struct ufs_unit_desc));
- struct ufs_unit_desc *desc = unit_desc;
+ struct ufs_unit_desc *desc = (struct ufs_unit_desc *) unit_desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_UNIT,
index,
@@ -348,8 +386,10 @@
sizeof(struct ufs_unit_desc)};
if (dme_send_query_upiu(dev, &query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Read Unit Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
-
+ }
/* Flush buffer. */
arch_invalidate_cache_range((addr_t) desc, sizeof(struct ufs_unit_desc));
@@ -367,7 +407,7 @@
int dme_read_config_desc(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(desc, sizeof(struct ufs_config_desc));
- struct ufs_config_desc *config_desc = desc;
+ struct ufs_config_desc *config_desc = (struct ufs_config_desc *)desc;
struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
UFS_DESC_IDN_CONFIGURATION,
0,
@@ -376,7 +416,10 @@
sizeof(struct ufs_config_desc)};
if (dme_send_query_upiu(dev, &query))
+ {
+ dprintf(CRITICAL, "%s:%d DME Read Config Descriptor request failed\n", __func__, __LINE__);
return -UFS_FAILURE;
+ }
/* Flush buffer. */
arch_invalidate_cache_range((addr_t) config_desc, sizeof(struct ufs_config_desc));
@@ -417,14 +460,14 @@
}
else if (ret == -UFS_FAILURE)
{
- dprintf(CRITICAL, "sending nop out failed.\n");
+ dprintf(CRITICAL, "%s:%d Sending nop out failed.\n", __func__, __LINE__);
goto upiu_send_nop_out_err;
}
/* Check response UPIU */
if (resp_upiu.trans_type != UPIU_TYPE_NOP_IN)
{
- dprintf(CRITICAL, "Command failed. command = %x. Invalid response.\n", req_upiu.trans_type);
+ dprintf(CRITICAL, "%s:%d Command failed. command = %x. Invalid response.\n",__func__,__LINE__, req_upiu.trans_type);
ret = -UFS_FAILURE;
goto upiu_send_nop_out_err;
}
@@ -456,8 +499,9 @@
case UPIU_QUERY_OP_SET_FLAG:
req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_WRITE_REQ;
break;
- default: dprintf(CRITICAL, "UPIU query opcode not supported.\n");
- return -UFS_FAILURE;
+ default:
+ dprintf(CRITICAL, "%s:%d UPIU query opcode not supported.\n", __func__, __LINE__);
+ return -UFS_FAILURE;
}
return UFS_SUCCESS;
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index 2473ae2..0bc2b3d 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -231,14 +231,35 @@
int dme_get_req(struct ufs_dev *dev, struct dme_get_req_type *req);
int utp_build_query_req_upiu(struct upiu_trans_mgmt_query_hdr *req_upiu,
struct upiu_req_build_type *upiu_data);
+
+/* Nop Query is used to check the connection to the device
+ */
int dme_send_nop_query(struct ufs_dev *dev);
+
+/* Device Init is used to set the fDeviceInit flag to initiate device
+ * initialization
+ */
int dme_set_fdeviceinit(struct ufs_dev *dev);
+
+/* Power On WP Enable is used to enable Power on WP for all LUN's
+ * that have WP bit enabled.
+ */
int dme_set_fpoweronwpen(struct ufs_dev *dev);
+
+/* Unit descriptor gives the characteristics and capabilities of
+ * logical units.
+ */
int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index);
+/* Device descriptor is the main descriptor and it provides the device
+ * class, sub-class, the protocol to access the device and the maximum
+ * number oflogical units in the device.
+ */
+int dme_read_device_desc(struct ufs_dev *dev);
+
/* Geometry Descriptor contains RPMB read write size which indicates total
- number of rpmb frames allowed in a single SCSI security command
+ number of rpmb frames allowed in a single SCSI security command.
*/
-int dme_read_geometry_desc(struct ufs_dev *dev);
+int dme_read_geo_desc(struct ufs_dev *dev);
#endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 0592833..e2c9923 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -242,6 +242,10 @@
uint32_t pipe_type;
char lowpowerstop;
char lcd_reg_en;
+ uint32_t border_top;
+ uint32_t border_bottom;
+ uint32_t border_left;
+ uint32_t border_right;
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index 30abec5..cb4c573 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -30,11 +30,9 @@
#ifndef __PLATFORM_MSM_SHARED_QGIC_H
#define __PLATFORM_MSM_SHARED_QGIC_H
-#include <platform/iomap.h>
-#include <platform/interrupts.h>
+#include "qgic_common.h"
#define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off))
-#define GIC_DIST_REG(off) (MSM_GIC_DIST_BASE + (off))
#define GIC_CPU_CTRL GIC_CPU_REG(0x00)
#define GIC_CPU_PRIMASK GIC_CPU_REG(0x04)
@@ -44,29 +42,12 @@
#define GIC_CPU_RUNNINGPRI GIC_CPU_REG(0x14)
#define GIC_CPU_HIGHPRI GIC_CPU_REG(0x18)
-#define GIC_DIST_CTRL GIC_DIST_REG(0x000)
-#define GIC_DIST_CTR GIC_DIST_REG(0x004)
-#define GIC_DIST_ENABLE_SET GIC_DIST_REG(0x100)
-#define GIC_DIST_ENABLE_CLEAR GIC_DIST_REG(0x180)
-#define GIC_DIST_PENDING_SET GIC_DIST_REG(0x200)
-#define GIC_DIST_PENDING_CLEAR GIC_DIST_REG(0x280)
-#define GIC_DIST_ACTIVE_BIT GIC_DIST_REG(0x300)
-#define GIC_DIST_PRI GIC_DIST_REG(0x400)
-#define GIC_DIST_TARGET GIC_DIST_REG(0x800)
-#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00)
-#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
-
#define INTERRUPT_LVL_N_TO_N 0x0
#define INTERRUPT_LVL_1_TO_N 0x1
#define INTERRUPT_EDGE_N_TO_N 0x2
#define INTERRUPT_EDGE_1_TO_N 0x3
-struct ihandler {
- int_handler func;
- void *arg;
-};
-
-void qgic_init(void);
-void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type);
+uint32_t qgic_read_iar(void);
+void qgic_write_eoi(uint32_t);
#endif
diff --git a/platform/msm_shared/include/qgic_common.h b/platform/msm_shared/include/qgic_common.h
new file mode 100644
index 0000000..431803d
--- /dev/null
+++ b/platform/msm_shared/include/qgic_common.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2011,2014 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM_SHARED_QGIC_COMMON_H
+#define __PLATFORM_MSM_SHARED_QGIC_COMMON_H
+
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/interrupts.h>
+
+#define GIC_DIST_REG(off) (MSM_GIC_DIST_BASE + (off))
+
+#define GIC_DIST_CTRL GIC_DIST_REG(0x000)
+#define GIC_DIST_CTR GIC_DIST_REG(0x004)
+#define GIC_DIST_ENABLE_SET GIC_DIST_REG(0x100)
+#define GIC_DIST_ENABLE_CLEAR GIC_DIST_REG(0x180)
+#define GIC_DIST_PENDING_SET GIC_DIST_REG(0x200)
+#define GIC_DIST_PENDING_CLEAR GIC_DIST_REG(0x280)
+#define GIC_DIST_ACTIVE_BIT GIC_DIST_REG(0x300)
+#define GIC_DIST_PRI GIC_DIST_REG(0x400)
+#define GIC_DIST_TARGET GIC_DIST_REG(0x800)
+#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00)
+#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
+
+struct ihandler {
+ int_handler func;
+ void *arg;
+};
+
+void qgic_init(void);
+void qgic_dist_config(uint32_t);
+void qgic_dist_init(void);
+void qgic_cpu_init(void);
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type);
+#endif
diff --git a/platform/msm_shared/include/qgic_v3.h b/platform/msm_shared/include/qgic_v3.h
new file mode 100644
index 0000000..e0c159d
--- /dev/null
+++ b/platform/msm_shared/include/qgic_v3.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM_SHARED_QGIC_V3_H
+#define __PLATFORM_MSM_SHARED_QGIC_V3_H
+
+#include "qgic_common.h"
+
+#define GICD_IROUTER GIC_DIST_REG(0x6000)
+#define GICR_WAKER_CPU0 MSM_GIC_REDIST_BASE
+
+#define ENABLE_GRP0_SEC BIT(0)
+#define ENABLE_GRP1_NS BIT(1)
+#define ENABLE_ARE BIT(4)
+
+uint32_t qgic_read_iar(void);
+void qgic_write_eoi(uint32_t);
+
+#endif
diff --git a/platform/msm_shared/include/qpic_panel.h b/platform/msm_shared/include/qpic_panel.h
index af6230e..79f9bac 100644
--- a/platform/msm_shared/include/qpic_panel.h
+++ b/platform/msm_shared/include/qpic_panel.h
@@ -110,8 +110,8 @@
#define OP_WRITE_MEMORY_START 0x2C /* size not fixed */
/* ILI9341 commands */
-#define OP_ILI9341_INTERFACE_CONTROL 0xf6
-#define OP_ILI9341_TEARING_EFFECT_LINE_ON 0x35
+#define OP_ILI9341_INTERFACE_CONTROL 0xf6
+#define OP_ILI9341_TEARING_EFFECT_LINE_ON 0x35
struct qpic_panel_io_desc {
int rst_gpio;
diff --git a/platform/msm_shared/include/ucs.h b/platform/msm_shared/include/ucs.h
index 58fb188..094946e 100644
--- a/platform/msm_shared/include/ucs.h
+++ b/platform/msm_shared/include/ucs.h
@@ -165,7 +165,7 @@
int ucs_scsi_send_inquiry(struct ufs_dev *dev);
int ucs_do_scsi_read(struct ufs_dev *dev, struct scsi_rdwr_req *req);
int ucs_do_scsi_write(struct ufs_dev *dev, struct scsi_rdwr_req *req);
-
+int ucs_do_scsi_unmap(struct ufs_dev *dev, struct scsi_unmap_req *req);
/*
* ucs_do_sci_rpmb_read function takes a RPMB frame, sector address and number of
* blocks to be read from RPMB partition as input and returns one or more RPMB
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index ff0709e..c199b17 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -142,12 +142,17 @@
uint32_t src_size, out_size, stride;
uint32_t fb_off = 0;
uint32_t flip_bits = 0;
+ uint32_t src_xy = 0, dst_xy = 0;
+ uint32_t height, width;
+
+ height = fb->height - pinfo->border_top - pinfo->border_bottom;
+ width = fb->width - pinfo->border_left - pinfo->border_right;
/* write active region size*/
- src_size = (fb->height << 16) + fb->width;
+ src_size = (height << 16) + width;
out_size = src_size;
if (pinfo->lcdc.dual_pipe) {
- out_size = (fb->height << 16) + (fb->width / 2);
+ out_size = (height << 16) + (width / 2);
if ((pipe_base == MDP_VP_0_RGB_1_BASE) ||
(pipe_base == MDP_VP_0_DMA_1_BASE) ||
(pipe_base == MDP_VP_0_VIG_1_BASE))
@@ -156,13 +161,24 @@
stride = (fb->stride * fb->bpp/8);
+ if (fb_off == 0) { /* left */
+ dst_xy = (pinfo->border_top << 16) | pinfo->border_left;
+ src_xy = dst_xy;
+ } else { /* right */
+ dst_xy = (pinfo->border_top << 16);
+ src_xy = (pinfo->border_top << 16) | fb_off;
+ }
+
+ dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
+ __func__, out_size, fb_off, src_xy, dst_xy);
+
writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE);
writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE);
writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE);
writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE);
- writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY);
- writel(0x00, pipe_base + PIPE_SSPP_OUT_XY);
+ writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY);
+ writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY);
/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 9e7ee60..b5d386f 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -98,7 +98,7 @@
break;
if (i == LPFR_LUT_SIZE) {
dprintf(INFO, "unable to get loop filter resistance. vco=%d\n"
- , lpfr_lut[i].vco_rate);
+ , lpfr_lut[i-1].vco_rate);
rc = ERROR;
return rc;
}
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 12bcd4d..0a7d5b4 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -35,7 +35,7 @@
#include <target.h>
#include <string.h>
#include <partition_parser.h>
-
+#include <dme.h>
/*
* Weak function for UFS.
* These are needed to avoid link errors for platforms which
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index 49299e7..7250c62 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -32,11 +32,7 @@
*/
#include <reg.h>
-#include <bits.h>
-#include <debug.h>
#include <arch/arm.h>
-#include <kernel/thread.h>
-#include <platform/irqs.h>
#include <qgic.h>
static struct ihandler handler[NR_IRQS];
@@ -53,15 +49,11 @@
if (mask)
break;
}
-
- if (!mask)
- dprintf(CRITICAL, "GIC CPU mask not found\n");
-
return mask;
}
/* Intialize distributor */
-static void qgic_dist_init(void)
+void qgic_dist_init(void)
{
uint32_t i;
uint32_t num_irq = 0;
@@ -81,123 +73,29 @@
num_irq = readl(GIC_DIST_CTR) & 0x1f;
num_irq = (num_irq + 1) * 32;
- /* Set each interrupt line to use N-N software model
- * and edge sensitive, active high
- */
- for (i = 32; i < num_irq; i += 16)
- writel(0xffffffff, GIC_DIST_CONFIG + i * 4 / 16);
-
- writel(0xffffffff, GIC_DIST_CONFIG + 4);
-
/* Set up interrupts for this CPU */
for (i = 32; i < num_irq; i += 4)
writel(cpumask, GIC_DIST_TARGET + i * 4 / 4);
- /* Set priority of all interrupts */
-
- /*
- * In bootloader we dont care about priority so
- * setting up equal priorities for all
- */
- for (i = 0; i < num_irq; i += 4)
- writel(0xa0a0a0a0, GIC_DIST_PRI + i * 4 / 4);
-
- /* Disabling interrupts */
- for (i = 0; i < num_irq; i += 32)
- writel(0xffffffff, GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
-
- writel(0x0000ffff, GIC_DIST_ENABLE_SET);
+ qgic_dist_config(num_irq);
/*Enabling GIC */
writel(1, GIC_DIST_CTRL);
}
/* Intialize cpu specific controller */
-static void qgic_cpu_init(void)
+void qgic_cpu_init(void)
{
writel(0xf0, GIC_CPU_PRIMASK);
writel(1, GIC_CPU_CTRL);
}
-/* Initialize QGIC. Called from platform specific init code */
-void qgic_init(void)
+uint32_t qgic_read_iar()
{
- qgic_dist_init();
- qgic_cpu_init();
+ return readl(GIC_CPU_INTACK);
}
-/* IRQ handler */
-enum handler_return gic_platform_irq(struct arm_iframe *frame)
+void qgic_write_eoi(uint32_t num)
{
- uint32_t num;
- enum handler_return ret;
-
- num = readl(GIC_CPU_INTACK);
- if (num >= NR_IRQS)
- return 0;
-
- ret = handler[num].func(handler[num].arg);
writel(num, GIC_CPU_EOI);
-
- return ret;
-}
-
-/* FIQ handler */
-void gic_platform_fiq(struct arm_iframe *frame)
-{
- PANIC_UNIMPLEMENTED;
-}
-
-/* Mask interrupt */
-status_t gic_mask_interrupt(unsigned int vector)
-{
- uint32_t reg = GIC_DIST_ENABLE_CLEAR + (vector / 32) * 4;
- uint32_t bit = 1 << (vector & 31);
-
- writel(bit, reg);
-
- return 0;
-}
-
-/* Un-mask interrupt */
-status_t gic_unmask_interrupt(unsigned int vector)
-{
- uint32_t reg = GIC_DIST_ENABLE_SET + (vector / 32) * 4;
- uint32_t bit = 1 << (vector & 31);
-
- writel(bit, reg);
-
- return 0;
-}
-
-/* Register interrupt handler */
-void gic_register_int_handler(unsigned int vector, int_handler func, void *arg)
-{
- ASSERT(vector < NR_IRQS);
-
- enter_critical_section();
- handler[vector].func = func;
- handler[vector].arg = arg;
- exit_critical_section();
-}
-
-void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type)
-{
- uint32_t register_number, register_address, bit_number, value;
- register_number = spi_number >> 4; // r = n DIV 16
- bit_number = (spi_number % 16) << 1; // b = (n MOD 16) * 2
- value = readl(GIC_DIST_CONFIG + (register_number << 2));
- // there are two bits per register to indicate the level
- if (type == INTERRUPT_LVL_N_TO_N)
- value &= ~(BIT(bit_number)|BIT(bit_number+1)); // 0x0 0x0
- else if (type == INTERRUPT_LVL_1_TO_N)
- value = (value & ~BIT(bit_number+1)) | BIT(bit_number); // 0x0 0x1
- else if (type == INTERRUPT_EDGE_N_TO_N)
- value = BIT(bit_number+1) | (value & ~BIT(bit_number));// 0x1 0x0
- else if (type == INTERRUPT_EDGE_1_TO_N)
- value |= (BIT(bit_number)|BIT(bit_number+1)); // 0x1 0x1
- else
- dprintf(CRITICAL, "Invalid interrupt type change requested\n");
- register_address = GIC_DIST_CONFIG + (register_number << 2);
- writel(value, register_address);
}
diff --git a/platform/msm_shared/qgic_common.c b/platform/msm_shared/qgic_common.c
new file mode 100644
index 0000000..7abb5a1
--- /dev/null
+++ b/platform/msm_shared/qgic_common.c
@@ -0,0 +1,155 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Fundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <reg.h>
+#include <bits.h>
+#include <arch/arm.h>
+#include <kernel/thread.h>
+#include <platform/irqs.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <debug.h>
+
+static struct ihandler handler[NR_IRQS];
+
+/* Intialize distributor */
+void qgic_dist_config(uint32_t num_irq)
+{
+ uint32_t i;
+
+ /* Set each interrupt line to use N-N software model
+ * and edge sensitive, active high
+ */
+ for (i = 32; i < num_irq; i += 16)
+ writel(0xffffffff, GIC_DIST_CONFIG + i * 4 / 16);
+
+ writel(0xffffffff, GIC_DIST_CONFIG + 4);
+
+ /* Set priority of all interrupts */
+
+ /*
+ * In bootloader we dont care about priority so
+ * setting up equal priorities for all
+ */
+ for (i = 0; i < num_irq; i += 4)
+ writel(0xa0a0a0a0, GIC_DIST_PRI + i * 4 / 4);
+
+ /* Disabling interrupts */
+ for (i = 0; i < num_irq; i += 32)
+ writel(0xffffffff, GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+
+ writel(0x0000ffff, GIC_DIST_ENABLE_SET);
+}
+
+/* Initialize QGIC. Called from platform specific init code */
+void qgic_init(void)
+{
+ qgic_dist_init();
+ qgic_cpu_init();
+}
+
+/* IRQ handler */
+enum handler_return gic_platform_irq(struct arm_iframe *frame)
+{
+ uint32_t num;
+ enum handler_return ret;
+
+ /* Read the interrupt number to be served*/
+ num = qgic_read_iar();
+
+ if (num >= NR_IRQS)
+ return 0;
+
+ ret = handler[num].func(handler[num].arg);
+
+ /* End of interrupt */
+ qgic_write_eoi(num);
+
+ return ret;
+}
+
+/* FIQ handler */
+void gic_platform_fiq(struct arm_iframe *frame)
+{
+ PANIC_UNIMPLEMENTED;
+}
+
+/* Mask interrupt */
+status_t gic_mask_interrupt(unsigned int vector)
+{
+ uint32_t reg = GIC_DIST_ENABLE_CLEAR + (vector / 32) * 4;
+ uint32_t bit = 1 << (vector & 31);
+
+ writel(bit, reg);
+
+ return 0;
+}
+
+/* Un-mask interrupt */
+status_t gic_unmask_interrupt(unsigned int vector)
+{
+ uint32_t reg = GIC_DIST_ENABLE_SET + (vector / 32) * 4;
+ uint32_t bit = 1 << (vector & 31);
+
+ writel(bit, reg);
+
+ return 0;
+}
+
+/* Register interrupt handler */
+void gic_register_int_handler(unsigned int vector, int_handler func, void *arg)
+{
+ ASSERT(vector < NR_IRQS);
+
+ enter_critical_section();
+ handler[vector].func = func;
+ handler[vector].arg = arg;
+ exit_critical_section();
+}
+
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type)
+{
+ uint32_t register_number, register_address, bit_number, value;
+ register_number = spi_number >> 4; // r = n DIV 16
+ bit_number = (spi_number % 16) << 1; // b = (n MOD 16) * 2
+ value = readl(GIC_DIST_CONFIG + (register_number << 2));
+ // there are two bits per register to indicate the level
+ if (type == INTERRUPT_LVL_N_TO_N)
+ value &= ~(BIT(bit_number)|BIT(bit_number+1)); // 0x0 0x0
+ else if (type == INTERRUPT_LVL_1_TO_N)
+ value = (value & ~BIT(bit_number+1)) | BIT(bit_number); // 0x0 0x1
+ else if (type == INTERRUPT_EDGE_N_TO_N)
+ value = BIT(bit_number+1) | (value & ~BIT(bit_number));// 0x1 0x0
+ else if (type == INTERRUPT_EDGE_1_TO_N)
+ value |= (BIT(bit_number)|BIT(bit_number+1)); // 0x1 0x1
+ else
+ dprintf(CRITICAL, "Invalid interrupt type change requested\n");
+ register_address = GIC_DIST_CONFIG + (register_number << 2);
+ writel(value, register_address);
+}
diff --git a/platform/msm_shared/qgic_v3.c b/platform/msm_shared/qgic_v3.c
new file mode 100644
index 0000000..1177a23
--- /dev/null
+++ b/platform/msm_shared/qgic_v3.c
@@ -0,0 +1,145 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Fundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <reg.h>
+#include <bits.h>
+#include <debug.h>
+#include <arch/arm.h>
+#include <arch/defines.h>
+#include <qgic_v3.h>
+
+#define GIC_WAKER_PROCESSORSLEEP BIT(1)
+#define GIC_WAKER_CHILDRENASLEEP BIT(2)
+
+void qgic_dist_init()
+{
+ uint32_t num_irq;
+ uint32_t affinity;
+ uint32_t i;
+
+ /* Read the mpidr register to find out the boot up cluster */
+ __asm__ volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (affinity));
+
+ /* For aarch32 mode we have only 3 affinity values: aff0:aff1:aff2*/
+ affinity = affinity & 0x00ffffff;
+
+ writel(0, GIC_DIST_CTRL);
+
+ /*
+ * Find out how many interrupts are supported.
+ */
+ num_irq = readl(GIC_DIST_CTR) & 0x1f;
+ num_irq = (num_irq + 1) * 32;
+
+ /* Do the qgic dist initialization */
+ qgic_dist_config(num_irq);
+
+ /* Write the affinity value, for routing all the SPIs */
+ for (i = 32; i < num_irq; i++)
+ writel(affinity, GICD_IROUTER + i * 8);
+
+ /* Enable affinity routing of grp0/grp1 interrupts */
+ writel(ENABLE_GRP0_SEC | ENABLE_GRP1_NS | ENABLE_ARE, GIC_DIST_CTRL);
+}
+
+void qgic_cpu_init()
+{
+ uint32_t waker = 0;
+ uint32_t retry = 1000;
+ uint32_t sre = 0;
+ uint32_t pmr = 0xff;
+ uint32_t eoimode = 0;
+ uint32_t grpen1 = 0x1;
+
+ /* For cpu init need to wake up the redistributor */
+ writel((readl(GICR_WAKER_CPU0) & ~GIC_WAKER_PROCESSORSLEEP), GICR_WAKER_CPU0);
+
+ /* Wait until redistributor is up */
+ while(readl(GICR_WAKER_CPU0) & GIC_WAKER_CHILDRENASLEEP)
+ {
+ retry--;
+ if (!retry)
+ {
+ dprintf(CRITICAL, "Failed to wake redistributor for CPU0\n");
+ ASSERT(0);
+ }
+ mdelay(1);
+ }
+
+
+ /* Make sure the system register access is enabled for us */
+ __asm__ volatile("mrc p15, 0, %0, c12, c12, 5" : "=r" (sre));
+ sre |= BIT(0);
+ __asm__ volatile("mcr p15, 0, %0, c12, c12, 5" :: "r" (sre));
+
+ isb();
+
+ /* If system register access is not set, we fail */
+ __asm__ volatile("mrc p15, 0, %0, c12, c12, 5" : "=r" (sre));
+ if (!(sre & BIT(0)))
+ {
+ dprintf(CRITICAL, "Failed to set SRE for NS world\n");
+ ASSERT(0);
+ }
+
+ /* Set the priortiy mask register, interrupts with priority
+ * higher than this value will be signalled to processor.
+ * Lower value means higher priority.
+ */
+ __asm__ volatile("mcr p15, 0, %0, c4, c6, 0" :: "r" (pmr));
+ isb();
+
+ /* Make sure EOI is handled in NS EL3 */
+ __asm__ volatile("mrc p15, 0, %0, c12, c12, 4" : "=r" (eoimode));
+ eoimode &= ~BIT(1);
+ __asm__ volatile("mcr p15, 0, %0, c12, c12, 4" :: "r" (eoimode));
+ isb();
+
+ /* Enable grp1 interrupts for NS EL3*/
+ __asm__ volatile("mcr p15, 0, %0, c12, c12, 7" :: "r" (grpen1));
+ isb();
+}
+
+uint32_t qgic_read_iar()
+{
+ uint32_t iar;
+
+ /* Read the interrupt ack register, for the current interrupt number */
+ __asm__ volatile("mrc p15, 0, %0, c12, c12, 0" : "=r" (iar));
+ isb();
+
+ return iar;
+}
+
+void qgic_write_eoi(uint32_t iar)
+{
+ /* Write end of interrupt to indicate CPU that this interrupt is processed*/
+ __asm__ volatile("mcr p15, 0, %0, c12, c12, 1" :: "r" (iar));
+ isb();
+}
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index 5e4ceab..b3b3477 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -61,6 +61,9 @@
struct clk *phy_com_clk = NULL;
struct clk *phy_clk = NULL;
+#if USB_RESET_FROM_CLK
+ clock_reset_usb_phy();
+#else
/* Look if phy com clock is present */
phy_com_clk = clk_get("usb30_phy_com_reset");
if (phy_com_clk)
@@ -131,6 +134,7 @@
ret = clk_reset(usb2b_clk, CLK_RESET_DEASSERT);
if (ret)
dprintf(CRITICAL, "Failed to deassert usb2b_phy_clk\n");
+#endif
/* Override the phy common control values */
val = readl(MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
diff --git a/platform/msm_shared/qpic_panel.c b/platform/msm_shared/qpic_panel.c
index 71993a7..2b9e4e2 100644
--- a/platform/msm_shared/qpic_panel.c
+++ b/platform/msm_shared/qpic_panel.c
@@ -127,6 +127,9 @@
int mdss_qpic_panel_init(struct qpic_panel_io_desc *panel_io)
{
+ qpic_panel_on = ili9341_on;
+ qpic_panel_off = ili9341_off;
+
return 0;
}
diff --git a/platform/msm_shared/rpm-smd.c b/platform/msm_shared/rpm-smd.c
index 6144fba..d623542 100644
--- a/platform/msm_shared/rpm-smd.c
+++ b/platform/msm_shared/rpm-smd.c
@@ -114,7 +114,7 @@
case RPM_CMD_TYPE:
cmd.hdr.type = RPM_CMD_MAGIC;
cmd.hdr.len = CMD_MSG_LENGTH;//0x8;
- len_to_smd = 0x12;
+ len_to_smd = sizeof(rpm_cmd);
fill_kvp_object(&cmd.data, data, len);
ret = smd_write(&ch, (void *)&cmd, len_to_smd, SMD_APPS_RPM);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 6f5c089..c905e23 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -14,7 +14,12 @@
$(LOCAL_DIR)/jtag.o \
$(LOCAL_DIR)/partition_parser.o \
$(LOCAL_DIR)/hsusb.o \
- $(LOCAL_DIR)/boot_stats.o
+ $(LOCAL_DIR)/boot_stats.o \
+ $(LOCAL_DIR)/qgic_common.o
+
+ifeq ($(ENABLE_QGIC3), 1)
+OBJS += $(LOCAL_DIR)/qgic_v3.o
+endif
ifeq ($(ENABLE_SMD_SUPPORT),1)
OBJS += \
@@ -483,6 +488,31 @@
$(LOCAL_DIR)/mipi_dsi_autopll.o
endif
+ifeq ($(PLATFORM),thulium)
+ OBJS += $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/ufs.o \
+ $(LOCAL_DIR)/utp.o \
+ $(LOCAL_DIR)/uic.o \
+ $(LOCAL_DIR)/ucs.o \
+ $(LOCAL_DIR)/ufs_hci.o \
+ $(LOCAL_DIR)/dme.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
+ $(LOCAL_DIR)/qusb2_phy.o
+endif
+
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
OBJS += \
$(LOCAL_DIR)/boot_device.o
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 48f62be..c7ff1b8 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -313,12 +313,8 @@
{
int ret;
img_req cmd;
+ scmcall_arg scm_arg = {0};
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return -1;
- }
cmd.img_ptr = (uint32*) img_ptr;
cmd.img_len_ptr = img_len_ptr;
@@ -328,7 +324,19 @@
*/
arch_clean_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
- ret = scm_call(SCM_SVC_SSD, SSD_ENCRYPT_ID, &cmd, sizeof(cmd), NULL, 0);
+ if (!scm_arm_support)
+ {
+ ret = scm_call(SCM_SVC_SSD, SSD_ENCRYPT_ID, &cmd, sizeof(cmd), NULL, 0);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD,SSD_ENCRYPT_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = cmd.img_ptr;
+ scm_arg.x3 = cmd.img_len_ptr;
+
+ ret = scm_call2(&scm_arg, NULL);
+ }
/* Values at img_ptr and img_len_ptr are updated by TZ. Must be invalidated
* before we use them.
@@ -383,13 +391,8 @@
ssd_parse_md_req parse_req;
ssd_parse_md_rsp parse_rsp;
int prev_len = 0;
-
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return -1;
- }
-
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
/* Populate meta-data ptr. Here md_len is the meta-data length.
* The Code below follows a growing length approach. First send
* min(img_len_ptr,SSD_HEADER_MIN_SIZE) say 128 bytes for example.
@@ -404,13 +407,25 @@
do
{
- ret = scm_call(SCM_SVC_SSD,
- SSD_PARSE_MD_ID,
- &parse_req,
- sizeof(parse_req),
- &parse_rsp,
- sizeof(parse_rsp));
+ if (!scm_arm_support)
+ {
+ ret = scm_call(SCM_SVC_SSD,
+ SSD_PARSE_MD_ID,
+ &parse_req,
+ sizeof(parse_req),
+ &parse_rsp,
+ sizeof(parse_rsp));
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PARSE_MD_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = parse_req.md_len;
+ scm_arg.x3 = parse_req.md;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ parse_rsp.status = scm_ret.x1;
+ }
if(!ret && (parse_rsp.status == SSD_PMD_PARSING_INCOMPLETE))
{
prev_len = parse_req.md_len;
@@ -454,12 +469,9 @@
uint32 ctx_id = 0;
ssd_decrypt_img_frag_req decrypt_req;
ssd_decrypt_img_frag_rsp decrypt_rsp;
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return -1;
- }
ret = ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id);
switch(ret)
@@ -478,13 +490,27 @@
decrypt_req.frag_len = *img_len_ptr;
decrypt_req.frag = *img_ptr;
- ret = scm_call(SCM_SVC_SSD,
- SSD_DECRYPT_IMG_FRAG_ID,
- &decrypt_req,
- sizeof(decrypt_req),
- &decrypt_rsp,
- sizeof(decrypt_rsp));
+ if (!scm_arm_support)
+ {
+ ret = scm_call(SCM_SVC_SSD,
+ SSD_DECRYPT_IMG_FRAG_ID,
+ &decrypt_req,
+ sizeof(decrypt_req),
+ &decrypt_rsp,
+ sizeof(decrypt_rsp));
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_DECRYPT_IMG_FRAG_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x4,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_BUFFER_READWRITE);
+ scm_arg.x2 = decrypt_req.md_ctx_id;
+ scm_arg.x3 = decrypt_req.last_frag;
+ scm_arg.x4 = decrypt_req.frag_len;
+ scm_arg.x5[0] = decrypt_req.frag;
+ ret = scm_call2(&scm_arg, &scm_ret);
+ decrypt_rsp.status = scm_ret.x1;
+ }
if(!ret){
ret = decrypt_rsp.status;
}
@@ -542,7 +568,7 @@
else
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, TZ_INFO_GET_FEATURE_ID);
- scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x1,SMC_PARAM_TYPE_VALUE);
scm_arg.x2 = feature_req.feature_id;
ret = scm_call2(&scm_arg, &scm_ret);
@@ -560,24 +586,33 @@
int ret=0;
ssd_protect_keystore_req protect_req;
ssd_protect_keystore_rsp protect_rsp;
-
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return -1;
- }
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
protect_req.keystore_ptr = img_ptr;
protect_req.keystore_len = img_len;
arch_clean_invalidate_cache_range((addr_t) img_ptr, img_len);
- ret = scm_call(SCM_SVC_SSD,
- SSD_PROTECT_KEYSTORE_ID,
- &protect_req,
- sizeof(protect_req),
- &protect_rsp,
- sizeof(protect_rsp));
+ if (!scm_arm_support)
+ {
+ ret = scm_call(SCM_SVC_SSD,
+ SSD_PROTECT_KEYSTORE_ID,
+ &protect_req,
+ sizeof(protect_req),
+ &protect_rsp,
+ sizeof(protect_rsp));
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PROTECT_KEYSTORE_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = protect_req.keystore_ptr;
+ scm_arg.x3 = protect_req.keystore_len;
+
+ ret = scm_call2(&scm_arg, &scm_ret);
+ protect_rsp.status = scm_ret.x1;
+ }
if(!ret)
{
if(protect_rsp.status == TZBSP_SSD_PKS_SUCCESS)
@@ -602,26 +637,34 @@
size_t cmd_len;
void *resp_buf = NULL;
size_t resp_len = 0;
+ scmcall_arg scm_arg = {0};
uint32_t fuse_id = HLOS_IMG_TAMPER_FUSE;
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
- if (scm_arm_support)
+ if (!scm_arm_support)
{
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return;
+ /*no response */
+ resp_buf = NULL;
+ resp_len = 0;
+
+ svc_id = SCM_SVC_FUSE;
+ cmd_id = SCM_BLOW_SW_FUSE_ID;
+
+ scm_call(svc_id, cmd_id, cmd_buf, cmd_len, resp_buf, resp_len);
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_BLOW_SW_FUSE_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = cmd_buf;
+ scm_arg.x3 = cmd_len;
+
+ scm_call2(&scm_arg, NULL);
+
}
- /*no response */
- resp_buf = NULL;
- resp_len = 0;
-
- svc_id = SCM_SVC_FUSE;
- cmd_id = SCM_BLOW_SW_FUSE_ID;
-
- scm_call(svc_id, cmd_id, cmd_buf, cmd_len, resp_buf, resp_len);
- return;
}
uint8_t get_tamper_fuse_cmd()
@@ -634,24 +677,33 @@
uint8_t resp_buf;
uint32_t fuse_id = HLOS_IMG_TAMPER_FUSE;
-
- if (scm_arm_support)
- {
- dprintf(INFO, "%s:SCM call is not supported\n",__func__);
- return;
- }
+ scmcall_arg scm_arg = {0};
+ scmcall_ret scm_ret = {0};
cmd_buf = (void *)&fuse_id;
cmd_len = sizeof(fuse_id);
- /*response */
- resp_len = sizeof(resp_buf);
+ if (!scm_arm_support)
+ {
+ /*response */
+ resp_len = sizeof(resp_buf);
- svc_id = SCM_SVC_FUSE;
- cmd_id = SCM_IS_SW_FUSE_BLOWN_ID;
+ svc_id = SCM_SVC_FUSE;
+ cmd_id = SCM_IS_SW_FUSE_BLOWN_ID;
- scm_call(svc_id, cmd_id, cmd_buf, cmd_len, &resp_buf, resp_len);
- return resp_buf;
+ scm_call(svc_id, cmd_id, cmd_buf, cmd_len, &resp_buf, resp_len);
+ return resp_buf;
+ }
+ else
+ {
+ scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_IS_SW_FUSE_BLOWN_ID);
+ scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
+ scm_arg.x2 = cmd_buf;
+ scm_arg.x3 = cmd_len;
+
+ scm_call2(&scm_arg, &scm_ret);
+ return (uint8_t)scm_ret.x1;
+ }
}
#define SHA256_DIGEST_LENGTH (256/8)
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 04d82a8..d89251e 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -366,6 +366,7 @@
MSM8236 = 242,
MSM8636 = 243,
MSM8909 = 245,
+ MSMTHULIUM = 246,
APQ8016 = 247,
MSM8216 = 248,
MSM8116 = 249,
diff --git a/platform/msm_shared/ucs.c b/platform/msm_shared/ucs.c
index 432f3a7..49ecf1b 100644
--- a/platform/msm_shared/ucs.c
+++ b/platform/msm_shared/ucs.c
@@ -94,7 +94,6 @@
uint32_t blks_remaining;
uint32_t blks_to_transfer;
uint64_t bytes_to_transfer;
- uint32_t start_blk;
uint64_t max_size;
blks_remaining = blk_cnt;
blks_to_transfer = blks_remaining;
@@ -128,7 +127,7 @@
memset(&req_upiu, 0, sizeof(struct scsi_req_build_type));
req_upiu.cdb = (addr_t) cdb_out_param;
- req_upiu.data_buffer_addr = req_buf;
+ req_upiu.data_buffer_addr = (addr_t) req_buf;
req_upiu.data_len = bytes_to_transfer;
req_upiu.flags = UPIU_FLAGS_WRITE;
req_upiu.lun = UFS_WLUN_RPMB;
@@ -161,7 +160,7 @@
memset(&req_upiu, 0, sizeof(struct scsi_req_build_type));
req_upiu.cdb = (addr_t) cdb_in_param;
- req_upiu.data_buffer_addr = resp_buf;
+ req_upiu.data_buffer_addr = (addr_t) resp_buf;
req_upiu.data_len = bytes_to_transfer;
req_upiu.flags = UPIU_FLAGS_READ;
req_upiu.lun = UFS_WLUN_RPMB;
@@ -414,7 +413,7 @@
struct scsi_sense_cdb *cdb_param;
uint8_t buf[SCSI_SENSE_BUF_LEN];
- cdb_param = cdb;
+ cdb_param = (struct scsi_sense_cdb *) cdb;
memset(cdb, 0, sizeof(struct scsi_sense_cdb));
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
index 3cb1487..aa5f90b 100644
--- a/platform/msm_shared/ufs.c
+++ b/platform/msm_shared/ufs.c
@@ -102,7 +102,7 @@
}
// gets the number of rpmb frames allowed in a single UPIU commands
- ret = dme_read_geo_desc(dev, UFS_WLUN_RPMB);
+ ret = dme_read_geo_desc(dev);
if (ret != UFS_SUCCESS)
{
dprintf(CRITICAL, "UFS dme_read_geo_desc failed for RPMB Partition\n");
@@ -219,7 +219,6 @@
int ufs_init(struct ufs_dev *dev)
{
uint32_t ret = UFS_SUCCESS;
- uint64_t cap;
uint8_t lun = 0;
dev->block_size = 4096;
diff --git a/platform/msm_shared/utp.c b/platform/msm_shared/utp.c
index 317cd69..e0463b2 100644
--- a/platform/msm_shared/utp.c
+++ b/platform/msm_shared/utp.c
@@ -40,6 +40,7 @@
#include <ufs.h>
#include <platform/iomap.h>
#include <platform/clock.h>
+#include <platform/timer.h>
#include <arch/ops.h>
#include <endian.h>
#include <stdlib.h>
@@ -54,7 +55,7 @@
/* Make sure we have more nodes than just the head in the list. */
if (list_next(irq->list, irq->list) == NULL)
{
- dprintf(CRITICAL, "UTRD/ UTMRD processed signalled and the wait queue is empty\n");
+ dprintf(CRITICAL, "%s:%d UTRD/ UTMRD processed signalled and the wait queue is empty\n", __func__, __LINE__);
ASSERT(0);
}
@@ -74,7 +75,7 @@
if (event_signal(req->event, false))
{
- dprintf(CRITICAL, "Event signal failed.\n");
+ dprintf(CRITICAL, "%s:%d Event signal failed.\n",__func__, __LINE__);
ASSERT(0);
}
@@ -113,11 +114,8 @@
if (!found)
{
- /* TODO: This case shouldd wait on a semaphore instead od returning error.
- * Return error until LK adds semaphore support.
- */
doorbell_bit_val = 0;
- dprintf(CRITICAL, "Unable to find a free slot for transaction.\n");
+ dprintf(CRITICAL, "%s:%d Unable to find a free slot for transaction.\n",__func__, __LINE__);
}
return doorbell_bit_val;
@@ -232,8 +230,8 @@
udelay(1);
if(retry == UTP_MAX_COMMAND_RETRY)
{
- dprintf(CRITICAL, "UTP command never completed.\n");
- return 1;
+ dprintf(CRITICAL, "%s:%d UTP command never completed.\n", __func__, __LINE__);
+ return ERR_TIMED_OUT;
}
#ifdef DEBUG_UFS
dprintf(INFO, "Waiting for UTRCS/URMRCS Completion...\n");
@@ -313,15 +311,11 @@
#endif
ret = utp_poll_utrd_complete(dev);
- if (ret)
+ if (ret == ERR_TIMED_OUT)
{
- if (ret == ERR_TIMED_OUT)
- {
- /* Transaction not completed even after timeout ms. */
- ret = utp_utrd_process_timeout_req(dev, utrd_req, &req);
- }
- else
- ret = -UFS_FAILURE;
+ /* Transaction not completed even after timeout ms. */
+ dprintf(CRITICAL, "%s:%d Transaction timeout after polling %d times\n",__func__, __LINE__, UTP_MAX_COMMAND_RETRY);
+ ret = utp_utrd_process_timeout_req(dev, utrd_req, &req);
goto utp_enqueue_utrd_err;
}
else
@@ -336,7 +330,7 @@
/* Check the response. */
if (desc->overall_cmd_status != UTRD_OCS_SUCCESS)
{
- dprintf(CRITICAL, "Command failed. command type = %x\n", utrd_req->cmd_type);
+ dprintf(CRITICAL, "%s:%d Command failed. command type = %x\n", __func__, __LINE__, utrd_req->cmd_type);
ret = -UFS_FAILURE;
goto utp_enqueue_utrd_err;
}
@@ -363,7 +357,7 @@
if (*num_prdt > UTP_MAX_PRD_TABLE_ENTRIES)
{
- dprintf(CRITICAL, "Data length exceeds for a single upiu transfer.\n");
+ dprintf(CRITICAL, "%s:%d Data length exceeds for a single upiu transfer.\n", __func__,__LINE__);
return -UFS_FAILURE;
}
@@ -388,6 +382,7 @@
{
if (upiu_data->data_buffer_addr & 0x3)
{
+ dprintf(CRITICAL, "%s:%d Alignment and length check failed for data tranfer command.\n", __func__, __LINE__);
return -UFS_FAILURE;
}
}
@@ -475,7 +470,7 @@
req_upiu = (struct upiu_gen_hdr*) memalign((size_t ) lcm(CACHE_LINE, UTP_CMD_DESC_BASE_ALIGNMENT_SIZE), ROUNDUP(cmd_desc_len, CACHE_LINE));
if (!req_upiu)
{
- dprintf(CRITICAL, "Unable to allocate request upiu\n");
+ dprintf(CRITICAL, "%s:%d Unable to allocate request upiu\n",__func__, __LINE__);
return -UFS_FAILURE;
}
@@ -506,7 +501,7 @@
ret = utp_enqueue_utrd(dev, &utrd);
if (ret)
{
- dprintf(CRITICAL, "Command failed. command = %x\n", req_upiu->basic_hdr.trans_type);
+ dprintf(CRITICAL, "%s:%d Command failed. command = %x\n", __func__, __LINE__, req_upiu->basic_hdr.trans_type);
goto utp_enqueue_upiu_err;
}
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
new file mode 100644
index 0000000..3b76b91
--- /dev/null
+++ b/platform/thulium/acpuclock.c
@@ -0,0 +1,271 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <reg.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/timer.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <pm8x41.h>
+
+void clock_init_mmc(uint32_t interface)
+{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, true);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, true);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, true);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, true);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+}
+
+/* Function to asynchronously reset CE (Crypto Engine).
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
+
+void clock_usb30_gdsc_enable(void)
+{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
+ ASSERT(0);
+ }
+
+ pm8x41_lnbb_clock_ctrl(1);
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret = 0;
+
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ return;
+}
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ return;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+}
diff --git a/platform/thulium/gpio.c b/platform/thulium/gpio.c
new file mode 100644
index 0000000..281584f
--- /dev/null
+++ b/platform/thulium/gpio.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+/* Remove the file after the gpio patch to move this to msm_shared gets merged. */
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+ return;
+}
+
+/* Configure gpio for blsp uart */
+void gpio_config_uart_dm(uint8_t id)
+{
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/thulium/include/platform/clock.h b/platform/thulium/include/platform/clock.h
new file mode 100644
index 0000000..0a5836c
--- /dev/null
+++ b/platform/thulium/include/platform/clock.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSM8996_CLOCK_H
+#define __MSM8996_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void mdp_clock_init(void);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
+void clock_reset_usb_phy();
+
+#endif
diff --git a/platform/thulium/include/platform/gpio.h b/platform/thulium/include/platform/gpio.h
new file mode 100644
index 0000000..c00512b
--- /dev/null
+++ b/platform/thulium/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM8996_GPIO_H
+#define __PLATFORM_MSM8996_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
new file mode 100644
index 0000000..2c17d12
--- /dev/null
+++ b/platform/thulium/include/platform/iomap.h
@@ -0,0 +1,176 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_THULIUM_IOMAP_H_
+#define _PLATFORM_THULIUM_IOMAP_H_
+
+#define MSM_SHARED_BASE 0x86000000
+
+#define MSM_IOMAP_HMSS_START 0x09800000
+
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x10000000
+
+#define MSM_SHARED_IMEM_BASE 0x066BF000
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
+#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
+
+#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
+#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE 0x07400000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
+#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
+#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
+
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
+
+/* USB3.0 */
+#define MSM_USB30_BASE 0x6A00000
+#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE 0x7410000
+
+/* QUSB2 PHY */
+#define QUSB2_PHY_BASE 0x7411000
+#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
+#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
+
+/* Clocks */
+#define CLK_CTL_BASE 0x300000
+
+/* GPLL */
+#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
+#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
+
+/* UART Clocks */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x17004)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x1C004)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x1C00C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x1C010)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x1C014)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x1C018)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x1C01C)
+
+/* USB3 clocks */
+#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
+#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
+#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
+#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
+#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
+#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
+#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
+#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
+
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF014)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF018)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
+#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
+#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
+#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
+#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
+#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
+#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
+#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
+
+/* SDCC */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
+
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
+
+#define UFS_BASE 0x624000
+
+#define SPMI_BASE 0x4000000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
+
+#define MSM_CE_BAM_BASE 0x67A000
+#define MSM_CE_BASE 0x644000
+
+#define TLMM_BASE_ADDR 0x1010000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
+
+#define MPM2_MPM_CTRL_BASE 0x4A1000
+#define MPM2_MPM_PS_HOLD 0x4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000)
+
+/* SDHCI - power control registers */
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* Boot config */
+#define SEC_CTRL_CORE_BASE 0x70000
+#define BOOT_CONFIG_OFFSET 0x00006044
+#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+
+/* Fix This */
+#define PLATFORM_QMP_OFFSET 0x8
+
+#endif
diff --git a/platform/thulium/include/platform/irqs.h b/platform/thulium/include/platform/irqs.h
new file mode 100644
index 0000000..dd0f31a
--- /dev/null
+++ b/platform/thulium/include/platform/irqs.h
@@ -0,0 +1,68 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_THULIUM_H
+#define __IRQS_THULIUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 31)
+
+#define USB30_EE1_IRQ (GIC_SPI_START + 131)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB30_EE1_IRQ
+
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 134)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+
+#define UFS_IRQ (GIC_SPI_START + 265)
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 265)
+
+/* Fix this: where this comes from? */
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#endif /* __IRQS_THULIUM_H */
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
new file mode 100644
index 0000000..1dad8cc
--- /dev/null
+++ b/platform/thulium/platform.c
@@ -0,0 +1,132 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define MSM_SHARED_SIZE 2
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* SCRATCH memory - cacheable, write through */
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { KERNEL_ADDR, KERNEL_ADDR, KERNEL_SIZE, SCRATCH_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, SCRATCH_SIZE, SCRATCH_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, MSM_SHARED_SIZE, SCRATCH_MEMORY},
+};
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+ scm_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+#if DISPLAY_SPLASH_SCREEN
+ display_shutdown();
+#endif
+
+ qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
diff --git a/platform/thulium/rules.mk b/platform/thulium/rules.mk
new file mode 100644
index 0000000..10afc50
--- /dev/null
+++ b/platform/thulium/rules.mk
@@ -0,0 +1,28 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/thulium-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
new file mode 100644
index 0000000..b02bec4
--- /dev/null
+++ b/platform/thulium/thulium-clock.c
@@ -0,0 +1,419 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define gpll4_source_val 5
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_rst =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(4),
+ .status_reg = (void *) GPLL4_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1600000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F(63160000, gpll0, 9.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F( 96000000, gpll4, 16, 0, 0),
+ F(192000000, gpll4, 8, 0, 0),
+ F(384000000, gpll4, 4, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk = {
+ .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "sys_noc_usb30_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
+ F( 125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_master_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = {
+ F( 1200000, cxo, 16, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_phy_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_phy_aux_clk = {
+ .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_phy_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_pipe_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t )USB30_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_rst,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = {
+ .cbcr_reg = (uint32_t *)USB_PHY_CFG_AHB2PHY_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
+/* Clock lookup table */
+static struct clk_lookup msm_thulium_clocks[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ /* USB30 clocks */
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+
+ CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_thulium_clocks, ARRAY_SIZE(msm_thulium_clocks));
+}
diff --git a/project/thulium.mk b/project/thulium.mk
new file mode 100644
index 0000000..e86a6c7
--- /dev/null
+++ b/project/thulium.mk
@@ -0,0 +1,48 @@
+# top level project rules for the thulium project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := thulium
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 1
+ENABLE_UFS_SUPPORT := 1
+ENABLE_BOOT_CONFIG_SUPPORT := 1
+ENABLE_USB30_SUPPORT := 1
+ENABLE_QGIC3 := 1
+
+DEFINES +=VIRTIO=1
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82200000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x82000000
+DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
+DEFINES += USB_RESET_FROM_CLK=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_UFS_SUPPORT),1)
+DEFINES += UFS_SUPPORT=1
+endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
index 63f02b5..36cdc57 100644
--- a/target/fsm9010/rules.mk
+++ b/target/fsm9010/rules.mk
@@ -7,7 +7,7 @@
MEMBASE := 0x0F900000 # SDRAM
MEMSIZE := 0x00100000 # 1MB
-BASE_ADDR := 0x00000000
+BASE_ADDR := 0x0b600000
TAGS_ADDR := BASE_ADDR+0x01e00000
KERNEL_ADDR := BASE_ADDR+0x00008000
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
index 43100e1..aff6aa6 100644
--- a/target/fsm9900/init.c
+++ b/target/fsm9900/init.c
@@ -162,37 +162,35 @@
#if MMC_SDHCI_SUPPORT
static void target_mmc_sdhci_init()
{
+ static uint32_t mmc_clks[] = {
+ MMC_CLK_96MHZ, MMC_CLK_50MHZ };
+
struct mmc_config_data config = {0};
+ int i;
config.bus_width = DATA_BUS_WIDTH_8BIT;
- config.max_clk_rate = MMC_CLK_96MHZ;
/* Trying Slot 1*/
config.slot = 1;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
- if (!(dev = mmc_init(&config))) {
- /* Trying Slot 2 next */
- config.slot = 2;
- config.sdhc_base = mmc_sdhci_base[config.slot - 1];
- config.pwrctl_base = mmc_sdc_base[config.slot - 1];
- config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
-
- if (!(dev = mmc_init(&config))) {
- dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
+ for (i = 0; i < ARRAY_SIZE(mmc_clks); ++i) {
+ config.max_clk_rate = mmc_clks[i];
+ dprintf(INFO, "SDHC Running at %u MHz\n",
+ config.max_clk_rate / 1000000);
+ dev = mmc_init(&config);
+ if (dev && partition_read_table() == 0)
+ return;
}
- /*
- * MMC initialization is complete, read the partition table info
- */
- if (partition_read_table()) {
+ if (dev == NULL)
+ dprintf(CRITICAL, "mmc init failed!");
+ else
dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
+ ASSERT(0);
}
void *target_mmc_device()
diff --git a/target/mdm9635/init.c b/target/mdm9635/init.c
index 647cf95..7557d75 100644
--- a/target/mdm9635/init.c
+++ b/target/mdm9635/init.c
@@ -148,10 +148,25 @@
flash_set_ptable(&flash_ptable);
rpm_smd_init();
}
+
+int target_cont_splash_screen()
+{
+ /*
+ * FOR OEMs - Set cont_splash_screen to keep the splash enable after LK.
+ * By default: the cont-splash-screen is ON
+ */
+ return false;
+}
+
void target_uninit()
{
- rpm_smd_uninit();
+#if DISPLAY_SPLASH_SCREEN
+ /* target_display_shutdown will uninitialize it in case of cont-splash */
+ if(target_cont_splash_screen())
+#endif
+ rpm_smd_uninit();
}
+
/* Do target specific usb initialization */
void target_usb_init(void)
{
diff --git a/target/mdm9635/qpic_panel_drv.c b/target/mdm9635/qpic_panel_drv.c
new file mode 100644
index 0000000..c5a7c20
--- /dev/null
+++ b/target/mdm9635/qpic_panel_drv.c
@@ -0,0 +1,186 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <endian.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <regulator.h>
+#include <rpm-smd.h>
+#include <platform/timer.h>
+
+#include "qpic.h"
+#include "qpic_panel.h"
+
+#define GPIOMUX_FUNC_1 1
+#define GPIOMUX_FUNC_GPIO 0
+
+#define RST_GPIO_ID 23
+#define CS_GPIO_ID 21
+#define AD8_GPIO_ID 20
+#define TE_GPIO_ID 22
+#define BL_GPIO_ID 84
+
+#define MEM_ACCESS_MODE 0x48
+#define MEM_ACCESS_FORMAT 0x66
+
+static uint32_t ldo6[][11] = {
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 0,
+ },
+ {
+ LDOA_RES_TYPE, 6,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 1800000,
+ },
+};
+
+static uint32_t ldo12[][11] = {
+ {
+ LDOA_RES_TYPE, 12,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 0,
+ },
+ {
+ LDOA_RES_TYPE, 12,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+ KEY_MICRO_VOLT, 4, 2700000,
+ },
+};
+
+static void panel_io_off(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ /* Turning off all gpios */
+ gpio_tlmm_config(RST_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(CS_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(AD8_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(TE_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_tlmm_config(BL_GPIO_ID, GPIOMUX_FUNC_GPIO, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_set(BL_GPIO_ID, 0x0);
+
+ /* Disabling vdd & avdd voltage */
+ rpm_send_data(&ldo6[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
+ rpm_send_data(&ldo12[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
+
+ /* uninitializing smd */
+ rpm_smd_uninit();
+
+ return;
+}
+
+void ili9341_off(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ panel_io_off(qpic_panel_io);
+}
+
+static int panel_io_on(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ int rc = 0;
+
+ /* Setting vdd & avdd voltage */
+ rpm_send_data(&ldo6[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+ rpm_send_data(&ldo12[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+ /* Turning on all gpios */
+ gpio_tlmm_config(RST_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(CS_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(AD8_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(TE_GPIO_ID, GPIOMUX_FUNC_1, GPIO_INPUT,GPIO_NO_PULL,
+ GPIO_10MA, GPIO_ENABLE);
+ gpio_tlmm_config(BL_GPIO_ID, GPIOMUX_FUNC_GPIO, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_10MA, GPIO_DISABLE);
+ gpio_set(BL_GPIO_ID, 0x2);
+
+ mdelay(20);
+ return rc;
+}
+
+int ili9341_on(struct qpic_panel_io_desc *qpic_panel_io)
+{
+ uint8_t param[4];
+ int ret;
+
+ ret = panel_io_on(qpic_panel_io);
+ if (ret)
+ return ret;
+ qpic_send_pkt(OP_SOFT_RESET, NULL, 0);
+ /* wait for 120 ms after reset as panel spec suggests */
+ mdelay(120);
+ qpic_send_pkt(OP_SET_DISPLAY_OFF, NULL, 0);
+ /* wait for 20 ms after disply off */
+ mdelay(20);
+
+ /* set memory access control */
+ param[0] = MEM_ACCESS_MODE;
+ qpic_send_pkt(OP_SET_ADDRESS_MODE, param, 1);
+ /* wait for 20 ms after command sent as panel spec suggests */
+ mdelay(20);
+
+ param[0] = MEM_ACCESS_FORMAT;
+ qpic_send_pkt(OP_SET_PIXEL_FORMAT, param, 1);
+ mdelay(20);
+
+ /* set interface */
+ param[0] = 1;
+ param[1] = 0;
+ param[2] = 0;
+ qpic_send_pkt(OP_ILI9341_INTERFACE_CONTROL, param, 3);
+ mdelay(20);
+
+ qpic_send_pkt(OP_EXIT_SLEEP_MODE, NULL, 0);
+ mdelay(20);
+
+ qpic_send_pkt(OP_ENTER_NORMAL_MODE, NULL, 0);
+ mdelay(20);
+
+ qpic_send_pkt(OP_SET_DISPLAY_ON, NULL, 0);
+ mdelay(20);
+
+ param[0] = 0;
+ qpic_send_pkt(OP_ILI9341_TEARING_EFFECT_LINE_ON, param, 1);
+
+ param[0] = qpic_read_data(OP_GET_PIXEL_FORMAT, 1);
+
+ return 0;
+}
diff --git a/target/mdm9635/rules.mk b/target/mdm9635/rules.mk
index 62fb3e2..0c84c38 100644
--- a/target/mdm9635/rules.mk
+++ b/target/mdm9635/rules.mk
@@ -12,14 +12,17 @@
SCRATCH_REGION2 := 0x01300000
SCRATCH_REGION2_SIZE := 0x06B00000 # 107MB
+DEFINES += DISPLAY_SPLASH_SCREEN=0
DEFINES += NO_KEYPAD_DRIVER=1
DEFINES += PERIPH_BLK_BLSP=1
+DEVS += fbcon
MODULES += \
dev/keys \
- lib/ptable \
dev/pmic/pm8x41 \
- lib/libfdt
+ lib/ptable \
+ lib/libfdt \
+ dev/fbcon
DEFINES += \
MEMBASE=$(MEMBASE) \
@@ -33,4 +36,6 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/qpic_panel_drv.o \
$(LOCAL_DIR)/keypad.o
diff --git a/target/mdm9635/target_display.c b/target/mdm9635/target_display.c
new file mode 100644
index 0000000..de54ea3
--- /dev/null
+++ b/target/mdm9635/target_display.c
@@ -0,0 +1,72 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <msm_panel.h>
+#include "splash.h"
+
+/* PANEL INFO */
+#define QVGA_PANEL_XRES 240
+#define QVGA_PANEL_YRES 320
+#define BPP_16 16
+
+/* FB Base Address */
+#define QPIC_FB_ADDR 0x06D00000
+
+static struct msm_fb_panel_data panel;
+
+void target_display_init(const char *panel_name)
+{
+ uint32_t ret = 0;
+ dprintf(SPEW, "%s: Panel name = %s\n", __func__, panel_name);
+
+ /* Setting panel info */
+ panel.panel_info.xres = QVGA_PANEL_XRES;
+ panel.panel_info.yres = QVGA_PANEL_YRES;
+ panel.panel_info.bpp = BPP_16;
+ panel.panel_info.type = QPIC_PANEL;
+
+ /* Setting FB info */
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB565;
+ panel.fb.base = QPIC_FB_ADDR;
+
+ ret = msm_display_init(&panel);
+ if (ret)
+ dprintf(CRITICAL, "%s: ERROR: Display init failed\n", __func__);
+}
+
+void target_display_shutdown(void)
+{
+ msm_display_off();
+}
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 9f3d611..bb22fa4 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -89,7 +89,7 @@
* PLL power up sequence.
* Add necessary delays recommeded by hardware.
*/
- writel(0x0D, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
+ writel(0x01, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
udelay(500);
diff --git a/target/thulium/init.c b/target/thulium/init.c
new file mode 100644
index 0000000..c1b13bb
--- /dev/null
+++ b/target/thulium/init.c
@@ -0,0 +1,351 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <pm8x41.h>
+#include <crypto5_wrapper.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <platform/timer.h>
+#include <stdlib.h>
+#include <ufs.h>
+#include <boot_device.h>
+#include <qmp_phy.h>
+
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+
+static void set_sdc_power_ctrl(void);
+static uint32_t mmc_pwrctl_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+struct mmc_device *dev;
+struct ufs_dev ufs_device;
+
+extern void ulpi_write(unsigned val, unsigned reg);
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(2, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ uint8_t status = 0;
+ struct pm8x41_gpio gpio;
+
+ /* Configure the GPIO */
+ gpio.direction = PM_GPIO_DIR_IN;
+ gpio.function = 0;
+ gpio.pull = PM_GPIO_PULL_UP_30;
+ gpio.vin_sel = 2;
+
+ pm8x41_gpio_config(2, &gpio);
+
+ /* Wait for the pmic gpio config to take effect */
+ thread_sleep(1);
+
+ /* Get status of P_GPIO_5 */
+ pm8x41_gpio_get(3, &status);
+
+ return !status; /* active low */
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ return pm8x41_resin_status();
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+void target_uninit(void)
+{
+ if (platform_boot_dev_isemmc())
+ {
+ mmc_put_card_to_sleep(dev);
+ /* Disable HC mode before jumping to kernel */
+ sdhci_mode_disable(&dev->host);
+ }
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ };
+
+ struct tlmm_cfgs sdc1_rclk_cfg[] =
+ {
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+ tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
+}
+
+void target_sdc_init()
+{
+ struct mmc_config_data config = {0};
+
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
+
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_192MHZ;
+
+ /* Try slot 1*/
+ config.slot = 1;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
+ {
+ /* Try slot 2 */
+ config.slot = 2;
+ config.max_clk_rate = MMC_CLK_200MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
+ {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+}
+
+void *target_mmc_device()
+{
+ if (platform_boot_dev_isemmc())
+ return (void *) dev;
+ else
+ return (void *) &ufs_device;
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
+
+ platform_read_boot_config();
+
+ if (platform_boot_dev_isemmc())
+ {
+ target_sdc_init();
+ }
+ else
+ {
+ ufs_device.base = UFS_BASE;
+ ufs_init(&ufs_device);
+ }
+
+ /* Storage initialization is complete, read the partition table info */
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+}
+
+unsigned board_machtype(void)
+{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ /* This is filled from board.c */
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+
+ switch(platform) {
+ case MSMTHULIUM:
+ board->baseband = BASEBAND_MSM;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ };
+}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+ unsigned int serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned check_reboot_mode(void)
+{
+ uint32_t restart_reason = 0;
+ uint32_t restart_reason_addr;
+
+ restart_reason_addr = RESTART_REASON_ADDR;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(restart_reason_addr);
+ writel(0x00, restart_reason_addr);
+
+ return restart_reason;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ uint8_t reset_type = 0;
+
+ /* Write the reboot reason */
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ if(reboot_reason)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+void target_usb_phy_reset()
+{
+ usb30_qmp_phy_reset();
+ qusb2_phy_reset();
+}
+
+target_usb_iface_t* target_usb30_init()
+{
+ target_usb_iface_t *t_usb_iface;
+
+ t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ ASSERT(t_usb_iface);
+
+ t_usb_iface->phy_init = usb30_qmp_phy_init;
+ t_usb_iface->phy_reset = target_usb_phy_reset;
+ t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->vbus_override = 1;
+
+ return t_usb_iface;
+}
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+ return "dwc";
+}
+
+uint32_t target_override_pll()
+{
+ return 1;
+}
+
+void target_fastboot_init(void)
+{
+ /* We are entering fastboot mode, so read partition table */
+ mmc_read_partition_table(1);
+}
diff --git a/target/thulium/meminfo.c b/target/thulium/meminfo.c
new file mode 100644
index 0000000..9aa1dd5
--- /dev/null
+++ b/target/thulium/meminfo.c
@@ -0,0 +1,88 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ ram_partition ptn_entry;
+ unsigned int index;
+ int ret = 0;
+ uint32_t len = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Calculating the size of the mem_info_ptr */
+ for (index = 0 ; index < len; index++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ptn_entry.start,
+ ptn_entry.size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n"
+);
+ goto target_dev_tree_mem_err;
+ }
+
+ }
+ }
+
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
diff --git a/target/thulium/rules.mk b/target/thulium/rules.mk
new file mode 100644
index 0000000..5ec0e88
--- /dev/null
+++ b/target/thulium/rules.mk
@@ -0,0 +1,41 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := thulium
+
+MEMBASE := 0x8F000000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x0000000
+
+SCRATCH_ADDR := 0x8F100000
+SCRATCH_SIZE := 512
+KERNEL_ADDR := 0x80000000
+KERNEL_SIZE := 62
+
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
+MODULES += \
+ dev/keys \
+ dev/pmic/pm8x41 \
+ lib/ptable \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ TAGS_ADDR=$(TAGS_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ KERNEL_SIZE=$(KERNEL_SIZE) \
+ RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR) \
+ SCRATCH_SIZE=$(SCRATCH_SIZE)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o \
diff --git a/target/thulium/tools/makefile b/target/thulium/tools/makefile
new file mode 100644
index 0000000..8297318
--- /dev/null
+++ b/target/thulium/tools/makefile
@@ -0,0 +1,13 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTOUT_DIR := $(BUILDDIR)
+else
+APPSBOOTOUT_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+ABOOTMBN := emmc_appsboot.mbn
+APPSBOOTHEADER: $(ABOOTMBN)
+
+$(ABOOTMBN): $(OUTELF_STRIP)
+ $(hide) cp -f $(OUTELF_STRIP) $(APPSBOOTOUT_DIR)/$(ABOOTMBN)