Merge "target: msm8994: Use chip serial for usb enumberation instead of ufs serial"
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index 6daea96..4cfd180 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -42,7 +42,13 @@
/* int atomic_swap(int *ptr, int val); */
FUNCTION(atomic_swap)
- swp r0, r2, [r1]
+.L_loop_swap:
+ ldrex r12, [r0]
+ strex r2, r1, [r0]
+ cmp r2 , #0
+ bne .L_loop_swap
+
+ mov r0, r12
bx lr
/* int atomic_add(int *ptr, int val); */
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index 395e338..2aab705 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -233,7 +233,7 @@
}
fbcon_putImage(fbimg, flag);
- if (fbimg)
+ if(flag)
free(fbimg);
}
@@ -244,9 +244,9 @@
unsigned total_y;
unsigned bytes_per_bpp;
unsigned image_base;
- unsigned width, pitch, height;
- unsigned char *logo_base;
- struct logo_img_header *header;
+ unsigned width = 0, pitch = 0, height = 0;
+ unsigned char *logo_base = NULL;
+ struct logo_img_header *header = NULL;
if (!config) {
@@ -268,7 +268,7 @@
#if DISPLAY_TYPE_MIPI
if (bytes_per_bpp == 3)
{
- if(flag) {
+ if(flag && header) {
if (header->width == config->width && header->height == config->height)
return;
else {
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index f18ecea..2fc904a 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -35,6 +35,7 @@
/*---------------------------------------------------------------------------*/
#include <debug.h>
#include "include/display_resource.h"
+#include "panel_display.h"
#define TIMING_SIZE 48
#define REGULATOR_SIZE 28
@@ -54,7 +55,9 @@
int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo);
int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
-bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
+int gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
void gcdb_display_shutdown();
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo, struct mdss_dsi_phy_ctrl *phy_db);
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
index 846a56d..e6fac4a 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
@@ -39,7 +39,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35597_wqxga_cmd_panel_data = {
"qcom,dsi_nt35597_wqxga_cmd", /* panel_node_id */
- "dsi:1:", /* panel_controller */
+ "dsi:0:", /* panel_controller */
"qcom,mdss-dsi-panel", /* panel_compatible */
11, /* panel_interface */
1, /* panel_type */
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
index 8d93e2a..7912ba8 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
@@ -39,7 +39,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config nt35597_wqxga_video_panel_data = {
"qcom,dsi_nt35597_wqxga_video", /* panel_node_id */
- "dsi:1:", /* panel_controller */
+ "dsi:0:", /* panel_controller */
"qcom,mdss-dsi-panel", /* panel_compatible */
10, /* panel_interface */
0, /* panel_type */
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 6dfc10a..717f09b 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -234,4 +234,7 @@
void pm8x41_diff_clock_ctrl(uint8_t enable);
void pm8x41_clear_pmic_watchdog(void);
void pm8x41_lnbb_clock_ctrl(uint8_t enable);
+void pmi8994_config_mpp_slave_id(uint8_t slave_id);
+void pm_pwm_enable(bool enable);
+int pm_pwm_config(unsigned int duty_us, unsigned int period_us);
#endif
diff --git a/dev/pmic/pm8x41/pm_pwm.c b/dev/pmic/pm8x41/pm_pwm.c
index b7ecf68..87e2651 100644
--- a/dev/pmic/pm8x41/pm_pwm.c
+++ b/dev/pmic/pm8x41/pm_pwm.c
@@ -165,7 +165,8 @@
unsigned int period_us,
unsigned int duty_us)
{
- unsigned int max_pwm_value, tmp;
+ int max_pwm_value;
+ unsigned int tmp;
/* Figure out pwm_value with overflow handling */
tmp = 1 << (sizeof(tmp) * 8 - pwm_config->pwm_size);
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
index bc4cc0e..b96150c 100644
--- a/dev/qpnp_wled/qpnp_wled.c
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -27,8 +27,12 @@
*/
#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
#include <err.h>
#include <qpnp_wled.h>
+#include <pm8x41_wled.h>
+#include <qtimer.h>
static int fls(uint16_t n)
{
@@ -42,7 +46,6 @@
static int qpnp_wled_sec_access(struct qpnp_wled *wled, uint16_t base_addr)
{
- int rc;
uint8_t reg = QPNP_WLED_SEC_UNLOCK;
pm8x41_wled_reg_write(QPNP_WLED_SEC_ACCESS_REG(base_addr), reg);
@@ -53,7 +56,7 @@
/* set wled to a level of brightness */
static int qpnp_wled_set_level(struct qpnp_wled *wled, int level)
{
- int i, rc;
+ int i;
uint8_t reg;
/* set brightness registers */
@@ -85,8 +88,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_MODULE_EN_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_EN_MASK;
reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_MODULE_EN_REG(base_addr), reg);
@@ -112,8 +113,6 @@
return rc;
} else {
reg = pm8x41_wled_reg_read(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_EN_MASK;
reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
@@ -128,11 +127,11 @@
/* enable / disable wled brightness */
void qpnp_wled_enable_backlight(int enable)
{
- int level, rc;
+ int rc;
if (!gwled) {
dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
- return ERROR;
+ return;
}
if (enable) {
@@ -154,13 +153,10 @@
static int qpnp_wled_set_display_type(struct qpnp_wled *wled, uint16_t base_addr)
{
- int rc;
uint8_t reg = 0;
/* display type */
reg = pm8x41_wled_reg_read(QPNP_WLED_DISP_SEL_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_DISP_SEL_MASK;
reg |= (wled->disp_type_amoled << QPNP_WLED_DISP_SEL_SHIFT);
@@ -171,13 +167,10 @@
static int qpnp_wled_module_ready(struct qpnp_wled *wled, uint16_t base_addr, bool state)
{
- int rc;
uint8_t reg;
reg = pm8x41_wled_reg_read(
QPNP_WLED_MODULE_RDY_REG(base_addr));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MODULE_RDY_MASK;
reg |= (state << QPNP_WLED_MODULE_RDY_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_MODULE_RDY_REG(base_addr), reg);
@@ -199,8 +192,6 @@
/* Configure the FEEDBACK OUTPUT register */
reg = pm8x41_wled_reg_read(
QPNP_WLED_FDBK_OP_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_FDBK_OP_MASK;
reg |= wled->fdbk_op;
pm8x41_wled_reg_write(QPNP_WLED_FDBK_OP_REG(wled->ctrl_base), reg);
@@ -213,8 +204,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_VREF_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_VREF_MASK;
temp = wled->vref_mv - QPNP_WLED_VREF_MIN_MV;
reg |= (temp / QPNP_WLED_VREF_STEP_MV);
@@ -228,8 +217,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_ILIM_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_ILIM_MASK;
reg |= (wled->ilim_ma / QPNP_WLED_ILIM_STEP_MA);
pm8x41_wled_reg_write(QPNP_WLED_ILIM_REG(wled->ctrl_base), reg);
@@ -242,8 +229,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_BOOST_DUTY_MASK;
reg |= (wled->boost_duty_ns / QPNP_WLED_BOOST_DUTY_STEP_NS);
pm8x41_wled_reg_write(QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base), reg);
@@ -256,8 +241,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_SWITCH_FREQ_MASK;
reg |= temp;
pm8x41_wled_reg_write(QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), reg);
@@ -279,8 +262,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_OVP_REG(wled->ctrl_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_OVP_MASK;
reg |= temp;
pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
@@ -300,8 +281,6 @@
temp = 0;
}
reg = pm8x41_wled_reg_read(QPNP_WLED_MOD_REG(wled->sink_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MOD_FREQ_MASK;
reg |= (temp << QPNP_WLED_MOD_FREQ_SHIFT);
@@ -332,8 +311,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_HYB_THRES_REG(wled->sink_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_HYB_THRES_MASK;
temp = fls(wled->hyb_thres / QPNP_WLED_HYB_THRES_MIN) - 1;
@@ -350,24 +327,18 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_MOD_EN_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_MOD_EN_MASK;
reg |= (QPNP_WLED_MOD_EN << QPNP_WLED_MOD_EN_SHFT);
pm8x41_wled_reg_write(QPNP_WLED_MOD_EN_REG(wled->sink_base,
wled->strings[i]), reg);
/* SYNC DELAY */
- if (wled->sync_dly_us < QPNP_WLED_SYNC_DLY_MIN_US)
- wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MIN_US;
- else if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
+ if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MAX_US;
reg = pm8x41_wled_reg_read(
QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_SYNC_DLY_MASK;
temp = wled->sync_dly_us / QPNP_WLED_SYNC_DLY_STEP_US;
reg |= temp;
@@ -375,16 +346,12 @@
wled->strings[i]), reg);
/* FULL SCALE CURRENT */
- if (wled->fs_curr_ua < QPNP_WLED_FS_CURR_MIN_UA)
- wled->fs_curr_ua = QPNP_WLED_FS_CURR_MIN_UA;
- else if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
+ if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
wled->fs_curr_ua = QPNP_WLED_FS_CURR_MAX_UA;
reg = pm8x41_wled_reg_read(
QPNP_WLED_FS_CURR_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_FS_CURR_MASK;
temp = wled->fs_curr_ua / QPNP_WLED_FS_CURR_STEP_UA;
reg |= temp;
@@ -395,8 +362,6 @@
reg = pm8x41_wled_reg_read(
QPNP_WLED_CABC_REG(wled->sink_base,
wled->strings[i]));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_CABC_MASK;
reg |= (wled->en_cabc << QPNP_WLED_CABC_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_CABC_REG(wled->sink_base,
@@ -405,8 +370,6 @@
/* Enable CURRENT SINK */
reg = pm8x41_wled_reg_read(
QPNP_WLED_CURR_SINK_REG(wled->sink_base));
- if (reg < 0)
- return reg;
temp = wled->strings[i] + QPNP_WLED_CURR_SINK_SHIFT;
reg |= (1 << temp);
pm8x41_wled_reg_write(QPNP_WLED_CURR_SINK_REG(wled->sink_base), reg);
@@ -415,8 +378,6 @@
/* LAB fast precharge */
reg = pm8x41_wled_reg_read(
QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_LAB_FAST_PC_MASK;
reg |= (wled->lab_fast_precharge << QPNP_WLED_LAB_FAST_PC_SHIFT);
pm8x41_wled_reg_write(QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base), reg);
@@ -432,20 +393,14 @@
return rc;
/* IBB active bias */
- if (wled->ibb_pwrup_dly_ms < QPNP_WLED_IBB_PWRUP_DLY_MIN_MS)
- wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MIN_MS;
- else if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
+ if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MAX_MS;
- if (wled->ibb_pwrdn_dly_ms < QPNP_WLED_IBB_PWRDN_DLY_MIN_MS)
- wled->ibb_pwrdn_dly_ms = QPNP_WLED_IBB_PWRDN_DLY_MIN_MS;
- else if (wled->ibb_pwrdn_dly_ms > QPNP_WLED_IBB_PWRDN_DLY_MAX_MS)
+ if (wled->ibb_pwrdn_dly_ms > QPNP_WLED_IBB_PWRDN_DLY_MAX_MS)
wled->ibb_pwrdn_dly_ms = QPNP_WLED_IBB_PWRDN_DLY_MAX_MS;
reg = pm8x41_wled_reg_read(
QPNP_WLED_IBB_BIAS_REG(wled->ibb_base));
- if (reg < 0)
- return reg;
reg &= QPNP_WLED_IBB_BIAS_MASK;
reg |= (!wled->ibb_bias_active << QPNP_WLED_IBB_BIAS_SHIFT);
@@ -482,7 +437,7 @@
/* Setup wled default parameters */
static int qpnp_wled_setup(struct qpnp_wled *wled, struct qpnp_wled_config_data *config)
{
- int rc, i;
+ int i;
wled->sink_base = QPNP_WLED_SINK_BASE;
wled->ctrl_base = QPNP_WLED_CTRL_BASE;
@@ -530,7 +485,7 @@
int qpnp_wled_init(struct qpnp_wled_config_data *config)
{
- int rc, i;
+ int rc;
struct qpnp_wled *wled;
wled = malloc(sizeof(struct qpnp_wled));
@@ -558,7 +513,8 @@
static int qpnp_labibb_regulator_set_voltage(struct qpnp_wled *wled)
{
- int rc=-1, new_uV;
+ int rc = -1;
+ uint32_t new_uV;
uint8_t val, mask=0;
if (wled->lab_min_volt < wled->lab_init_volt) {
diff --git a/include/target.h b/include/target.h
index 055634b..055fdb7 100644
--- a/include/target.h
+++ b/include/target.h
@@ -83,4 +83,5 @@
bool target_use_signed_kernel(void);
int _emmc_recovery_init(void);
void ulpi_write(unsigned val, unsigned reg);
+void target_crypto_init_params(void);
#endif
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 269073c..974108e 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -467,9 +467,9 @@
fdtend = fdtstart + fdt_totalsize(fdt);
FDT_CHECK_HEADER(fdt);
- if ((fdt_num_mem_rsv(fdt)+1) > (UINT_MAX / sizeof(struct fdt_reserve_entry))) {
+ if ((fdt_num_mem_rsv(fdt) + 1) >
+ (int) (UINT_MAX / sizeof(struct fdt_reserve_entry)))
return err;
- }
mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
* sizeof(struct fdt_reserve_entry);
@@ -504,7 +504,7 @@
/* Need to reorder */
newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+ struct_size + fdt_size_dt_strings(fdt);
- if (bufsize < newsize)
+ if (bufsize < (int) newsize)
return -FDT_ERR_NOSPACE;
/* First attempt to build converted tree at beginning of buffer */
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index a3bb284..0a07c14 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -119,4 +119,12 @@
void clock_ce_disable(uint8_t instance);
void clock_usb30_init(void);
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void mmss_dsi_clock_disable(uint32_t dual_dsi);
+void mmss_bus_clock_enable(void);
+void mmss_bus_clock_disable(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable();
+
#endif
diff --git a/platform/msm8909/acpuclock.c b/platform/msm8909/acpuclock.c
index 413816b..b8e0df4 100644
--- a/platform/msm8909/acpuclock.c
+++ b/platform/msm8909/acpuclock.c
@@ -393,3 +393,42 @@
ASSERT(0);
}
}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ uint8_t ret = 0;
+ char clk_name[64];
+
+ struct clk *qup_clk;
+ qup_id = qup_id + 1;
+
+ if((blsp_id != BLSP_ID_1)) {
+ dprintf(CRITICAL, "Incorrect BLSP-%d configuration\n", blsp_id);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "blsp1_qup%u_ahb_iface_clk", qup_id);
+
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+ return;
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup%u_i2c_apps_clk", qup_id);
+
+ qup_clk = clk_get(clk_name);
+
+ if (!qup_clk) {
+ dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+ return;
+ }
+
+ ret = clk_enable(qup_clk);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+ return;
+ }
+}
diff --git a/platform/msm8909/gpio.c b/platform/msm8909/gpio.c
index 70d4dc4..6ec4e33 100644
--- a/platform/msm8909/gpio.c
+++ b/platform/msm8909/gpio.c
@@ -68,3 +68,62 @@
return readl(GPIO_IN_OUT_ADDR(gpio)) & GPIO_IN;
}
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ if(blsp_id == BLSP_ID_1) {
+ switch (qup_id) {
+ case QUP_ID_1:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(6, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(7, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_2:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(111, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(112, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_3:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(29, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(30, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_4:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(14, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(15, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_5:
+ /* configure I2C SDA gpio */
+ gpio_tlmm_config(18, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure I2C SCL gpio */
+ gpio_tlmm_config(19, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+ break;
+
+ default:
+ dprintf(CRITICAL, "Incorrect QUP id %d\n",qup_id);
+ ASSERT(0);
+ };
+ } else {
+ dprintf(CRITICAL, "Incorrect BLSP id %d\n",blsp_id);
+ ASSERT(0);
+ }
+}
diff --git a/platform/msm8909/include/platform/clock.h b/platform/msm8909/include/platform/clock.h
index ffdaef0..ce98437 100644
--- a/platform/msm8909/include/platform/clock.h
+++ b/platform/msm8909/include/platform/clock.h
@@ -73,5 +73,7 @@
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(void);
void mdp_gdsc_ctrl(uint8_t enable);
#endif
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index 2523f49..18ae9e1 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -103,10 +103,30 @@
#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
/* I2C */
-#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
-#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018)
-#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014)
+#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)
+#define GCC_BLSP1_QUP1_APPS_CBCR (CLK_CTL_BASE + 0x2008)
+#define GCC_BLSP1_QUP1_CFG_RCGR (CLK_CTL_BASE + 0x2010)
+#define GCC_BLSP1_QUP1_CMD_RCGR (CLK_CTL_BASE + 0x200C)
+#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3004)
+#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3000)
+
+#define GCC_BLSP1_QUP3_APPS_CBCR (CLK_CTL_BASE + 0x4020)
+#define GCC_BLSP1_QUP3_CFG_RCGR (CLK_CTL_BASE + 0x4004)
+#define GCC_BLSP1_QUP3_CMD_RCGR (CLK_CTL_BASE + 0x4000)
+
+#define GCC_BLSP1_QUP4_APPS_CBCR (CLK_CTL_BASE + 0x5020)
+#define GCC_BLSP1_QUP4_CFG_RCGR (CLK_CTL_BASE + 0x5004)
+#define GCC_BLSP1_QUP4_CMD_RCGR (CLK_CTL_BASE + 0x5000)
+
+#define GCC_BLSP1_QUP5_APPS_CBCR (CLK_CTL_BASE + 0x6020)
+#define GCC_BLSP1_QUP5_CFG_RCGR (CLK_CTL_BASE + 0x6004)
+#define GCC_BLSP1_QUP5_CMD_RCGR (CLK_CTL_BASE + 0x6000)
+
+#define GCC_BLSP1_QUP6_APPS_CBCR (CLK_CTL_BASE + 0x7020)
+#define GCC_BLSP1_QUP6_CFG_RCGR (CLK_CTL_BASE + 0x7004)
+#define GCC_BLSP1_QUP6_CMD_RCGR (CLK_CTL_BASE + 0x7000)
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
diff --git a/platform/msm8909/include/platform/irqs.h b/platform/msm8909/include/platform/irqs.h
index 3ef97b1..3bb43ac 100644
--- a/platform/msm8909/include/platform/irqs.h
+++ b/platform/msm8909/include/platform/irqs.h
@@ -64,4 +64,5 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
NR_BOARD_IRQS)
+#define BLSP_QUP_IRQ(blsp_id, qup_id) (GIC_SPI_START + 95 + qup_id)
#endif /* __IRQS_MSM8909_H */
diff --git a/platform/msm8909/msm8909-clock.c b/platform/msm8909/msm8909-clock.c
index 78ece16..da7e222 100644
--- a/platform/msm8909/msm8909-clock.c
+++ b/platform/msm8909/msm8909-clock.c
@@ -389,6 +389,30 @@
},
};
+static struct rcg_clk gcc_blsp1_qup1_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP1_APPS_CBCR,
+ .parent = &gcc_blsp1_qup1_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src =
{
@@ -414,6 +438,102 @@
},
};
+static struct rcg_clk gcc_blsp1_qup3_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP3_APPS_CBCR,
+ .parent = &gcc_blsp1_qup3_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup4_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP4_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP4_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP4_APPS_CBCR,
+ .parent = &gcc_blsp1_qup4_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup5_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP5_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP5_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP5_APPS_CBCR,
+ .parent = &gcc_blsp1_qup5_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk gcc_blsp1_qup6_i2c_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_BLSP1_QUP6_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP1_QUP6_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
+ .cbcr_reg = GCC_BLSP1_QUP6_APPS_CBCR,
+ .parent = &gcc_blsp1_qup6_i2c_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Display clocks */
static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
@@ -548,8 +668,18 @@
CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk_src", gcc_blsp1_qup1_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk", gcc_blsp1_qup1_i2c_apps_clk.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk_src", gcc_blsp1_qup3_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk", gcc_blsp1_qup3_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk_src", gcc_blsp1_qup4_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk", gcc_blsp1_qup4_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c),
CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index 3f6bd14..a8d63e0 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -108,6 +108,8 @@
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(uint32_t dual_dsi);
void mdp_gdsc_ctrl(uint8_t enable);
void edp_clk_enable(void);
void clock_ce_enable(uint8_t instance);
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index 578e56e..c4efe85 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -115,4 +115,12 @@
void clock_ce_disable(uint8_t instance);
void clock_usb30_init(void);
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d);
+void mmss_dsi_clock_disable(uint32_t dual_dsi);
+void mmss_bus_clock_enable(void);
+void mmss_bus_clock_disable(void);
+void mdp_clock_enable(void);
+void mdp_clock_disable(void);
+
#endif
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 1774aa5..ab64e78 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -305,6 +305,10 @@
#undef MDP_INTF_1_TIMING_ENGINE_EN
#endif
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
+
+#ifdef MDP_INTF_2_TIMING_ENGINE_EN
+#undef MDP_INTF_2_TIMING_ENGINE_EN
+#endif
#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
#ifdef MDP_CTL_0_BASE
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 39072aa..a2ea734 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -41,7 +41,8 @@
HW_PLATFORM_SUBTYPE_UNKNOWN,
LINUX_MACHTYPE_UNKNOWN,
BASEBAND_MSM,
- {{PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}},
+ {{PMIC_IS_INVALID, 0, 0}, {PMIC_IS_INVALID, 0, 0},
+ {PMIC_IS_INVALID, 0, 0}},
0,
};
diff --git a/platform/msm_shared/boot_device.c b/platform/msm_shared/boot_device.c
index c120b6c..ac29dac 100644
--- a/platform/msm_shared/boot_device.c
+++ b/platform/msm_shared/boot_device.c
@@ -69,9 +69,7 @@
void platform_boot_dev_cmdline(char *buf)
{
uint32_t val = 0;
- void *dev;
-
- dev = target_mmc_device();
+ void *dev = target_mmc_device();
val = platform_get_boot_dev();
switch(val)
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
old mode 100644
new mode 100755
index 32071b5..cc41ed1
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -485,7 +485,7 @@
}
/* free queue's memory */
list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -541,7 +541,7 @@
static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list)
{
- uint32_t cur_dt_hlos_subtype;
+ uint32_t cur_dt_hlos_ddr;
uint32_t cur_dt_hw_platform;
uint32_t cur_dt_hw_subtype;
uint32_t cur_dt_msm_id;
@@ -555,9 +555,8 @@
cur_dt_hw_platform = (cur_dt_entry->variant_id & 0x000000ff);
cur_dt_hw_subtype = (cur_dt_entry->board_hw_subtype & 0xff);
-
- /* Determine the bits 23:8 to check the DT with the DDR Size */
- cur_dt_hlos_subtype = (cur_dt_entry->board_hw_subtype & 0xffff00);
+ /* Determine the bits 10:8 to check the DT with the DDR Size */
+ cur_dt_hlos_ddr = (cur_dt_entry->board_hw_subtype & 0x700);
/* 1. must match the msm_id, platform_hw_id, platform_subtype and DDR size
* soc, board major/minor, pmic major/minor must less than board info
@@ -567,7 +566,7 @@
if((cur_dt_msm_id == (board_platform_id() & 0x0000ffff)) &&
(cur_dt_hw_platform == board_hardware_id()) &&
(cur_dt_hw_subtype == board_hardware_subtype()) &&
- (cur_dt_hlos_subtype == target_get_hlos_subtype()) &&
+ (cur_dt_hlos_ddr == (target_get_hlos_subtype() & 0x700)) &&
(cur_dt_entry->soc_rev <= board_soc_version()) &&
((cur_dt_entry->variant_id & 0x00ffff00) <= (board_target_id() & 0x00ffff00)) &&
((cur_dt_entry->pmic_rev[0] & 0x00ffff00) <= (board_pmic_target(0) & 0x00ffff00)) &&
@@ -623,6 +622,14 @@
board_pmic_model[i] = (board_pmic_target(i) & 0xff);
}
break;
+ case DTB_PANEL_TYPE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0x1800);
+ board_info = (target_get_hlos_subtype() & 0x1800);
+ break;
+ case DTB_BOOT_DEVICE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0xf0000);
+ board_info = (target_get_hlos_subtype() & 0xf0000);
+ break;
default:
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
dtb_info);
@@ -662,6 +669,12 @@
current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
}
break;
+ case DTB_PANEL_TYPE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0x1800);
+ break;
+ case DTB_BOOT_DEVICE:
+ current_info = ((dt_node_tmp1->dt_entry_m->board_hw_subtype) & 0xf0000);
+ break;
default:
dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
dtb_info);
@@ -690,7 +703,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
delete_current_dt = 0;
@@ -759,7 +772,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -803,7 +816,7 @@
dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
@@ -829,6 +842,20 @@
if (!platform_dt_absolute_compat_match(dt_list, DTB_PMIC_MODEL))
return NULL;
+ /* check panel type
+ * the panel type must exact match board panel type, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_PANEL_TYPE))
+ return NULL;
+
+ /* check boot device subtype
+ * the boot device subtype must exact match board boot device subtype, this is compatibility check,
+ * if couldn't find the exact match from DTB, will exact match 0x0.
+ */
+ if (!platform_dt_absolute_compat_match(dt_list, DTB_BOOT_DEVICE))
+ return NULL;
+
/* check soc version
* the suitable soc version must less than or equal to board soc version
*/
@@ -1013,7 +1040,7 @@
list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
/* free node memory */
- dt_node_tmp2 = dt_node_tmp1->node.prev;
+ dt_node_tmp2 = (struct dt_entry_node *) dt_node_tmp1->node.prev;
dt_entry_list_delete(dt_node_tmp1);
dt_node_tmp1 = dt_node_tmp2;
}
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index 6c59ecf..1b20dc3 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -32,6 +32,11 @@
#include <mdp4.h>
#include <mipi_dsi.h>
#include <boot_stats.h>
+#include <platform.h>
+#include <malloc.h>
+#ifdef DISPLAY_TYPE_MDSS
+#include <target/display.h>
+#endif
static struct msm_fb_panel_data *panel;
@@ -220,7 +225,7 @@
if (ret)
goto msm_display_on_out;
- ret = mdss_hdmi_on();
+ ret = mdss_hdmi_on(pinfo);
if (ret)
goto msm_display_on_out;
break;
@@ -272,7 +277,7 @@
/* Enable clock */
if (pdata->clk_func)
- ret = pdata->clk_func(1);
+ ret = pdata->clk_func(1, &(panel->panel_info));
/* Only enabled for auto PLL calculation */
if (pdata->pll_clk_func)
@@ -404,7 +409,7 @@
/* Disable clock */
if (panel->clk_func)
- ret = panel->clk_func(0);
+ ret = panel->clk_func(0, pinfo);
/* Only for AUTO PLL calculation */
if (panel->pll_clk_func)
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index 1f68b9d..cfdb5b9 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -29,6 +29,7 @@
#include <certificate.h>
#include <crypto_hash.h>
#include <string.h>
+#include <openssl/err.h>
#include "image_verify.h"
#include "scm.h"
diff --git a/platform/msm_shared/include/boot_device.h b/platform/msm_shared/include/boot_device.h
index ad17f75..c216586 100644
--- a/platform/msm_shared/include/boot_device.h
+++ b/platform/msm_shared/include/boot_device.h
@@ -58,4 +58,6 @@
uint32_t platform_get_boot_dev();
uint32_t platform_boot_dev_isemmc();
void platform_boot_dev_cmdline(char *buf);
+
+void *target_mmc_device();
#endif
diff --git a/platform/msm_shared/include/clock.h b/platform/msm_shared/include/clock.h
index fd878d2..1369b55 100644
--- a/platform/msm_shared/include/clock.h
+++ b/platform/msm_shared/include/clock.h
@@ -193,4 +193,6 @@
* @action: clock assert or deassert
*/
int clk_reset(struct clk *clk, enum clk_reset_action);
+
+void clock_bumpup_pipe3_clk();
#endif
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
old mode 100644
new mode 100755
index a6534c0..04ce64d
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -123,6 +123,8 @@
DTB_PMIC2,
DTB_PMIC3,
DTB_PMIC_MODEL,
+ DTB_PANEL_TYPE,
+ DTB_BOOT_DEVICE,
};
enum dt_err_codes
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index d979645..ee4e4fc 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -104,8 +104,11 @@
void mdp_disable(void);
void mdp_start_dma(void);
int mdp_dsi_video_off();
+int mdp_dsi_cmd_off(void);
int mdp_dsi_video_on(struct msm_panel_info *pinfo);
+int mdp_dma_on(struct msm_panel_info *pinfo);
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_on();
int mdp_lcdc_off();
@@ -117,4 +120,7 @@
int mdp_edp_on(struct msm_panel_info *pinfo);
int mdp_edp_off(void);
+int mdss_hdmi_init(void);
+int mdss_hdmi_on(struct msm_panel_info *pinfo);
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 07f1a12..6c293af 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -192,6 +192,7 @@
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
unsigned short num_of_lanes);
int mdp_dsi_video_on(struct msm_panel_info *pinfo);
@@ -200,5 +201,17 @@
int mdp_edp_on(struct msm_panel_info *pinfo);
int mdp_edp_off(void);
void mdp_disable(void);
-
+void mdp_gdsc_ctrl(uint8_t enable);
+int mdp_get_revision();
+uint8_t target_is_edp();
+void target_edp_panel_init(struct msm_panel_info *pinfo);
+int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
+int target_edp_panel_enable(void);
+int target_edp_panel_disable(void);
+int target_edp_bl_ctrl(int enable);
+int mdss_hdmi_init(void);
+int mdss_hdmi_on(struct msm_panel_info *pinfo);
+int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int msm_display_off();
+void display_shutdown(void);
#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 7f27de8..2ec9398 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -154,7 +154,7 @@
int is_pll_20nm;
};
-typedef struct mdss_dsi_pll_config {
+struct mdss_dsi_pll_config {
uint32_t pixel_clock;
uint32_t pixel_clock_mhz;
uint32_t byte_clock;
@@ -181,7 +181,7 @@
struct mipi_dsi_cmd {
uint32_t size;
- uint8_t *payload;
+ char *payload;
int wait;
};
@@ -200,10 +200,6 @@
char cmds_post_tg;
};
-static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
-static struct mipi_dsi_cmd read_ddb_start_cmd =
- {sizeof(read_id_a1h_cmd), read_id_a1h_cmd};
-
enum { /* mipi dsi panel */
DSI_VIDEO_MODE,
DSI_CMD_MODE,
@@ -214,10 +210,12 @@
**********************************************************/
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
+void mdss_dsi_phy_sw_reset(uint32_t ctl_base);
int mdss_dsi_phy_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base);
void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi,
uint32_t phy_base);
+int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo);
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
@@ -236,12 +234,30 @@
uint8_t eof_bllp_pwr,
uint8_t interleav,
uint32_t ctl_base);
+int mdss_dsi_cmd_mode_config(uint16_t disp_width,
+ uint16_t disp_height,
+ uint16_t img_width,
+ uint16_t img_height,
+ uint16_t dst_format,
+ uint8_t ystride,
+ uint8_t lane_en,
+ uint8_t interleav,
+ uint32_t ctl_base);
int mipi_dsi_on(struct msm_panel_info *pinfo);
+int mipi_cmd_trigger();
int mipi_dsi_off(struct msm_panel_info *pinfo);
int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi,
struct mipi_dsi_cmd *cmds, int count, char dual_dsi);
int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len,
int rdbk_len);
-
+int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd);
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd);
+void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
+uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
+void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
+void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base);
+int mdss_dsi_post_on(struct msm_fb_panel_data *panel);
#endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 6c55f0e..dbf02b5 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -301,10 +301,10 @@
int rotate;
/* function entry chain */
- int (*power_func) (int enable, struct msm_panel_info *);
- int (*clk_func) (int enable);
- int (*bl_func) (int enable);
- int (*pll_clk_func) (int enable, struct msm_panel_info *);
+ int (*power_func) (uint8_t enable, struct msm_panel_info *);
+ uint32_t (*clk_func) (uint8_t enable, struct msm_panel_info *pinfo);
+ int (*bl_func) (uint8_t enable);
+ uint32_t (*pll_clk_func) (uint8_t enable, struct msm_panel_info *);
int (*post_power_func)(int enable);
int (*pre_init_func)(void);
};
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 2c5e14b..1614a95 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -152,7 +152,7 @@
struct tz_prng_data {
uint8_t *out_buf;
uint32_t out_buf_size;
-}__packed;
+}__PACKED;
/* SCM support as per ARM spec */
/*
diff --git a/platform/msm_shared/include/smd.h b/platform/msm_shared/include/smd.h
index b8f645f..00cd4ec 100644
--- a/platform/msm_shared/include/smd.h
+++ b/platform/msm_shared/include/smd.h
@@ -121,7 +121,7 @@
void smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type, uint32_t *response);
int smd_write(smd_channel_info_t *ch, void *data, uint32_t len, int type);
int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type);
-void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type);
+int smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type);
void smd_notify_rpm();
enum handler_return smd_irq_handler(void* data);
void smd_set_state(smd_channel_info_t *ch, uint32_t state, uint32_t flag);
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index f466d26..c3ed506 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -217,7 +217,7 @@
return NO_ERROR;
}
-int mdss_hdmi_on(void)
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
{
return NO_ERROR;
}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index 705819e..f592a19 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -429,7 +429,7 @@
return NO_ERROR;
}
-int mdss_hdmi_on(void)
+int mdss_hdmi_on(struct msm_panel_info *pinfo)
{
return NO_ERROR;
}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 6c84522..cd7e5a4 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -192,8 +192,7 @@
dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
__func__, out_size, fb_off, src_xy, dst_xy);
-
- writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
+ writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE);
writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE);
writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE);
@@ -407,11 +406,11 @@
struct intf_timing_params itp = {0};
if (pinfo == NULL)
- return ERR_INVALID_ARGS;
+ return;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
- return ERR_INVALID_ARGS;
+ return;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
@@ -652,7 +651,7 @@
comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
width, fbc->slice_height, fbc->pred_mode, enc_mode,
fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
- dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
+ dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n",
fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
budget_ctl = ((fbc->line_x_budget) << 12) |
@@ -792,8 +791,6 @@
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
uint32_t intf_sel, sintf_sel;
uint32_t intf_base, sintf_base;
uint32_t left_pipe, right_pipe;
@@ -859,8 +856,6 @@
int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
uint32_t left_pipe, right_pipe;
mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
@@ -895,8 +890,6 @@
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
- int ret = NO_ERROR;
- struct lcdc_panel_info *lcdc = NULL;
uint32_t left_pipe, right_pipe;
mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE);
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 0bb3274..9a6e21e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -53,7 +53,7 @@
#define MIPI_DSI1_BASE MIPI_DSI_BASE
#endif
-static struct fbcon_config mipi_fb_cfg = {
+struct fbcon_config mipi_fb_cfg = {
.height = 0,
.width = 0,
.stride = 0,
@@ -63,7 +63,10 @@
.update_done = NULL,
};
-static int cmd_mode_status = 0;
+static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
+static struct mipi_dsi_cmd read_ddb_start_cmd =
+ {sizeof(read_id_a1h_cmd), read_id_a1h_cmd, 0x00};
+
void secure_writel(uint32_t, uint32_t);
uint32_t secure_readl(uint32_t);
@@ -73,7 +76,7 @@
{
uint32_t rec_buf[1];
uint32_t *lp = rec_buf, data;
- int ret = response_value;
+ uint32_t ret = response_value;
uint32_t panel_signature = mipi->signature;
#if (DISPLAY_TYPE_MDSS == 1)
@@ -239,7 +242,7 @@
int rdbk_len)
{
uint32_t *lp, data;
- char *dp;
+ uint32_t *dp;
int i, off;
int rlen, res;
uint32_t ctl_base;
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index b5d386f..69bd7a1 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -32,6 +32,7 @@
#include <smem.h>
#include <mipi_dsi.h>
#include <platform/iomap.h>
+#include <platform/timer.h>
#define LPFR_LUT_SIZE 10
@@ -39,7 +40,7 @@
#define FRAC_DIVIDER 10000
-typedef struct lpfr_cfg {
+struct lpfr_cfg {
uint32_t vco_rate;
uint8_t resistance;
};
@@ -89,7 +90,6 @@
uint32_t ref_clk_to_pll = 0, frac_n_value = 0;
uint32_t sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
uint32_t gen_vco_clk, cal_cfg10, cal_cfg11;
- uint32_t res;
uint8_t i, rc = NO_ERROR;
/* Configure the Loop filter resistance */
@@ -189,4 +189,5 @@
writel(cal_cfg10, pll_base + 0x0094); /* CAL CFG10 */
writel(cal_cfg11, pll_base + 0x0098); /* CAL CFG11 */
writel(0x20, pll_base + 0x009c); /* EFUSE CFG */
+ return rc;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index baa520b..780b56e 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -32,6 +32,8 @@
#include <smem.h>
#include <mipi_dsi.h>
#include <platform/iomap.h>
+#include <qtimer.h>
+#include <arch/defines.h>
#define LPFR_LUT_SIZE 10
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index d3d534b..da0634f 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -29,7 +29,10 @@
#include <debug.h>
#include <reg.h>
#include <mipi_dsi.h>
+#include <mdp5.h>
+#include <platform/timer.h>
#include <platform/iomap.h>
+#include <arch/defines.h>
#if (DISPLAY_TYPE_MDSS == 0)
#define MIPI_DSI0_BASE MIPI_DSI_BASE
@@ -216,7 +219,7 @@
udelay(100);
}
-static int mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
+static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
{
/* DSI0 and DSI1 have a common regulator */
uint32_t off = 0x0280; /* phy regulator ctrl settings */
@@ -243,7 +246,7 @@
}
}
-static int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
+static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
uint32_t phy_base)
{
/* DSI0 and DSI1 have a common regulator */
@@ -412,6 +415,7 @@
/* DSI_0_CLKOUT_TIMING_CTRL */
writel(0x41b, ctl_base + 0x0c4);
dmb();
+ return 0;
}
@@ -461,6 +465,7 @@
dmb();
writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
dmb();
+ return 0;
}
int mdss_dsi_phy_init (struct mipi_panel_info *mipi,
diff --git a/platform/msm_shared/qgic_v3.c b/platform/msm_shared/qgic_v3.c
index 1177a23..692801b 100644
--- a/platform/msm_shared/qgic_v3.c
+++ b/platform/msm_shared/qgic_v3.c
@@ -32,6 +32,7 @@
#include <debug.h>
#include <arch/arm.h>
#include <arch/defines.h>
+#include <qtimer.h>
#include <qgic_v3.h>
#define GIC_WAKER_PROCESSORSLEEP BIT(1)
@@ -70,7 +71,6 @@
void qgic_cpu_init()
{
- uint32_t waker = 0;
uint32_t retry = 1000;
uint32_t sre = 0;
uint32_t pmr = 0xff;
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index b3b3477..dbd5f1d 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -35,6 +35,7 @@
#include <bits.h>
#include <clock.h>
#include <debug.h>
+#include <qtimer.h>
#define HS_PHY_COMMON_CTRL 0xEC
#define USE_CORECLK BIT(14)
@@ -49,8 +50,7 @@
return 0;
}
-/* USB3.0 QMP phy reset */
-void usb30_qmp_phy_reset(void)
+static void qmp_phy_qmp_reset()
{
int ret = 0;
uint32_t val;
@@ -61,9 +61,6 @@
struct clk *phy_com_clk = NULL;
struct clk *phy_clk = NULL;
-#if USB_RESET_FROM_CLK
- clock_reset_usb_phy();
-#else
/* Look if phy com clock is present */
phy_com_clk = clk_get("usb30_phy_com_reset");
if (phy_com_clk)
@@ -134,7 +131,6 @@
ret = clk_reset(usb2b_clk, CLK_RESET_DEASSERT);
if (ret)
dprintf(CRITICAL, "Failed to deassert usb2b_phy_clk\n");
-#endif
/* Override the phy common control values */
val = readl(MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
@@ -144,6 +140,16 @@
writel(val, MSM_USB30_QSCRATCH_BASE + HS_PHY_COMMON_CTRL);
}
+/* USB3.0 QMP phy reset */
+void usb30_qmp_phy_reset(void)
+{
+#if USB_RESET_FROM_CLK
+ clock_reset_usb_phy();
+#else
+ qmp_phy_qmp_reset();
+#endif
+}
+
/* USB 3.0 phy init: HPG for QMP phy*/
void usb30_qmp_phy_init()
{
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index efe4188..7cb57bc 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -903,7 +903,7 @@
struct cmd_element *cmd_list_read_ptr = ce_read_array;
struct cmd_element *cmd_list_ptr_start = ce_array;
struct cmd_element *cmd_list_read_ptr_start = ce_read_array;
- uint32_t status, nand_ret;
+ uint32_t status;
int num_desc = 0;
uint32_t blk_addr = page / flash.num_pages_per_blk;
@@ -972,7 +972,7 @@
status = qpic_nand_check_status(status);
/* Dummy read to unlock pipe. */
- nand_ret = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG);
+ qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG);
/* Check for status errors*/
if (status)
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index fce33f2..4f2ad47 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -30,6 +30,7 @@
#include <reg.h>
#include <bits.h>
#include <debug.h>
+#include <qtimer.h>
__WEAK int platform_is_msm8994()
{
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 6dc8a00..03b61c9 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -59,7 +59,7 @@
{
uint32_t ret;
scmcall_arg scm_arg = {0};
- scmcall_arg scm_ret = {0};
+ scmcall_ret scm_ret = {0};
/* Make a call to check if SCM call available using new interface,
* if this returns 0 then scm implementation as per arm spec
* otherwise use the old interface for scm calls
@@ -334,8 +334,8 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD,SSD_ENCRYPT_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd.img_ptr;
- scm_arg.x3 = cmd.img_len_ptr;
+ scm_arg.x2 = (uint32_t) cmd.img_ptr;
+ scm_arg.x3 = (uint32_t) cmd.img_len_ptr;
ret = scm_call2(&scm_arg, NULL);
}
@@ -423,7 +423,7 @@
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PARSE_MD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_VALUE,SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = parse_req.md_len;
- scm_arg.x3 = parse_req.md;
+ scm_arg.x3 = (uint32_t) parse_req.md;
ret = scm_call2(&scm_arg, &scm_ret);
parse_rsp.status = scm_ret.x1;
@@ -508,7 +508,7 @@
scm_arg.x2 = decrypt_req.md_ctx_id;
scm_arg.x3 = decrypt_req.last_frag;
scm_arg.x4 = decrypt_req.frag_len;
- scm_arg.x5[0] = decrypt_req.frag;
+ scm_arg.x5[0] = (uint32_t) decrypt_req.frag;
ret = scm_call2(&scm_arg, &scm_ret);
decrypt_rsp.status = scm_ret.x1;
@@ -609,7 +609,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_SSD, SSD_PROTECT_KEYSTORE_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = protect_req.keystore_ptr;
+ scm_arg.x2 = (uint32_t) protect_req.keystore_ptr;
scm_arg.x3 = protect_req.keystore_len;
ret = scm_call2(&scm_arg, &scm_ret);
@@ -660,7 +660,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_BLOW_SW_FUSE_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd_buf;
+ scm_arg.x2 = (uint32_t) cmd_buf;
scm_arg.x3 = cmd_len;
scm_call2(&scm_arg, NULL);
@@ -700,7 +700,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_FUSE, SCM_IS_SW_FUSE_BLOWN_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE,SMC_PARAM_TYPE_VALUE);
- scm_arg.x2 = cmd_buf;
+ scm_arg.x2 = (uint32_t) cmd_buf;
scm_arg.x3 = cmd_len;
scm_call2(&scm_arg, &scm_ret);
@@ -708,7 +708,6 @@
}
}
-#define SHA256_DIGEST_LENGTH (256/8)
/*
* struct qseecom_save_partition_hash_req
* @partition_id - partition id.
@@ -752,7 +751,7 @@
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_ES, SCM_SAVE_PARTITION_HASH_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x3, 0, SMC_PARAM_TYPE_BUFFER_READWRITE);
scm_arg.x2 = req.partition_id;
- scm_arg.x3 = (uint8_t *)&req.digest;
+ scm_arg.x3 = (uint32_t) &req.digest;
scm_arg.x4 = sizeof(req.digest);
if (scm_call2(&scm_arg, NULL))
@@ -855,7 +854,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_MILESTONE_32_64_ID, SCM_SVC_MILESTONE_CMD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ);
- scm_arg.x2 = (void *)¶m;
+ scm_arg.x2 = (uint32_t ) ¶m;
scm_arg.x3 = sizeof(el1_system_param);
scm_call2(&scm_arg, NULL);
@@ -892,7 +891,7 @@
{
scm_arg.x0 = MAKE_SIP_SCM_CMD(TZ_SVC_CRYPTO, PRNG_CMD_ID);
scm_arg.x1 = MAKE_SCM_ARGS(0x2,SMC_PARAM_TYPE_BUFFER_READWRITE);
- scm_arg.x2 = (uint8_t *) rbuf;
+ scm_arg.x2 = (uint32_t) rbuf;
scm_arg.x3 = r_len;
ret = scm_call2(&scm_arg, NULL);
diff --git a/platform/msm_shared/smd.c b/platform/msm_shared/smd.c
index a076f65..61d8f1f 100644
--- a/platform/msm_shared/smd.c
+++ b/platform/msm_shared/smd.c
@@ -34,10 +34,13 @@
#include <platform/irqs.h>
#include <platform/iomap.h>
#include <platform/interrupts.h>
+#include <platform/timer.h>
#include <reg.h>
#include <malloc.h>
#include <bits.h>
+#define SMD_CHANNEL_ACCESS_RETRY 1000000
+
smd_channel_alloc_entry_t *smd_channel_alloc_entry;
static event_t smd_closed;
@@ -64,7 +67,7 @@
ch->port_info->ch0.state_updated = flag;
}
-void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type)
+int smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type)
{
int i = 0;
@@ -77,12 +80,14 @@
}
}
- /* Channel not found */
+ /* Channel not found, retry again */
if(i == SMEM_NUM_SMD_STREAM_CHANNELS)
{
- dprintf(CRITICAL, "smd channel type %x not found\n", ch_type);
- ASSERT(0);
+ dprintf(SPEW, "Channel not found, wait and retry for the update\n");
+ return -1;
}
+
+ return 0;
}
int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type)
@@ -92,8 +97,10 @@
uint32_t fifo_buf_size = 0;
uint32_t size = 0;
- smd_get_channel_entry(ch, ch_type);
+ ret = smd_get_channel_entry(ch, ch_type);
+ if (ret)
+ return ret;
ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
&size);
@@ -112,20 +119,35 @@
int smd_init(smd_channel_info_t *ch, uint32_t ch_type)
{
unsigned ret = 0;
+ int chnl_found = 0;
+ uint64_t timeout = SMD_CHANNEL_ACCESS_RETRY;
smd_channel_alloc_entry = (smd_channel_alloc_entry_t*)memalign(CACHE_LINE, SMD_CHANNEL_ALLOC_MAX);
ASSERT(smd_channel_alloc_entry);
- ret = smem_read_alloc_entry(SMEM_CHANNEL_ALLOC_TBL,
- (void*)smd_channel_alloc_entry,
- SMD_CHANNEL_ALLOC_MAX);
- if(ret)
- {
- dprintf(CRITICAL,"ERROR reading smem channel alloc tbl\n");
- return -1;
- }
+ dprintf(INFO, "Waiting for the RPM to populate smd channel table\n");
- smd_get_channel_info(ch, ch_type);
+ do
+ {
+ ret = smem_read_alloc_entry(SMEM_CHANNEL_ALLOC_TBL,
+ (void*)smd_channel_alloc_entry,
+ SMD_CHANNEL_ALLOC_MAX);
+ if(ret)
+ {
+ dprintf(CRITICAL,"ERROR reading smem channel alloc tbl\n");
+ return -1;
+ }
+
+ chnl_found = smd_get_channel_info(ch, ch_type);
+ timeout--;
+ udelay(10);
+ } while(timeout && chnl_found);
+
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "Apps timed out waiting for RPM-->APPS channel entry\n");
+ ASSERT(0);
+ }
register_int_handler(SMD_IRQ, smd_irq_handler, ch);
@@ -249,7 +271,6 @@
arch_invalidate_cache_range((addr_t)response, smd_hdr.pkt_size);
- return response;
}
void smd_signal_read_complete(smd_channel_info_t *ch, uint32_t len)
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index d8858b9..a6324a4 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -879,8 +879,8 @@
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
@@ -944,8 +944,8 @@
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
@@ -1208,15 +1208,14 @@
static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev,
uint32_t *event)
{
- uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
- dwc_dep_cmd_id_t cmd = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
switch (event_id)
{
case DWC_EVENT_EP_CMD_COMPLETE:
{
- DBG("\n cmd = %s has no action. ignored.", cmd_lookup[cmd]);
+ DBG("\n cmd = %s has no action. ignored.",
+ cmd_lookup[DWC_EVENT_EP_EVENT_CMD_TYPE(*event)]);
}
break;
case DWC_EVENT_EP_XFER_NOT_READY:
diff --git a/platform/msm_shared/usb30_dwc.h b/platform/msm_shared/usb30_dwc.h
index 5a43696..1a69a61 100644
--- a/platform/msm_shared/usb30_dwc.h
+++ b/platform/msm_shared/usb30_dwc.h
@@ -493,6 +493,7 @@
static enum handler_return dwc_irq_handler_ee1(void* arg);
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index);
+void dwc_ep_cmd_clear_stall(dwc_dev_t *dev, uint8_t ep_phy_num);
static int dwc_request_queue(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_request_t *req);
#endif
diff --git a/project/msm8994.mk b/project/msm8994.mk
index 26b097e..bef93ce 100644
--- a/project/msm8994.mk
+++ b/project/msm8994.mk
@@ -61,3 +61,6 @@
ifeq ($(ENABLE_SMD_SUPPORT),1)
DEFINES += SMD_SUPPORT=1
endif
+
+# Turn on Werror
+CFLAGS += -Werror
diff --git a/project/thulium.mk b/project/thulium.mk
index 217cf50..f9cbe6a 100644
--- a/project/thulium.mk
+++ b/project/thulium.mk
@@ -53,3 +53,5 @@
ifeq ($(ENABLE_USB30_SUPPORT),1)
DEFINES += USB30_SUPPORT=1
endif
+
+CFLAGS += -Werror
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 11259f5..354c08e 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -95,15 +95,15 @@
int ret = NO_ERROR;
switch (panel_id) {
case TOSHIBA_720P_VIDEO_PANEL:
- ret = mdss_dsi_cmds_tx(toshiba_720p_video_rotation,
+ ret = mdss_dsi_cmds_tx(NULL, toshiba_720p_video_rotation,
TOSHIBA_720P_VIDEO_ROTATION, 0);
break;
case NT35590_720P_CMD_PANEL:
- ret = mdss_dsi_cmds_tx(nt35590_720p_cmd_rotation,
+ ret = mdss_dsi_cmds_tx(NULL, nt35590_720p_cmd_rotation,
NT35590_720P_CMD_ROTATION, 0);
break;
case NT35590_720P_VIDEO_PANEL:
- ret = mdss_dsi_cmds_tx(nt35590_720p_video_rotation,
+ ret = mdss_dsi_cmds_tx(NULL, nt35590_720p_video_rotation,
NT35590_720P_VIDEO_ROTATION, 0);
break;
}
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index fbfaeb8..003201e 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -306,8 +306,9 @@
return NO_ERROR;
}
-static int msm8974_mdss_edp_panel_clock(int enable)
+static int msm8974_mdss_edp_panel_clock(int enable, struct msm_panel_info *pinfo)
{
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
@@ -315,7 +316,7 @@
} else if (!target_cont_splash_screen()) {
/* Add here for continuous splash */
edp_clk_disable();
- mdp_clock_disable();
+ mdp_clock_disable(dual_dsi);
mdp_gdsc_ctrl(enable);
}
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index ac227a4..fca02c9 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -350,7 +350,7 @@
return pan_type;
}
-bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
diff --git a/target/thulium/init.c b/target/thulium/init.c
index 50e48d9..1230c7f 100644
--- a/target/thulium/init.c
+++ b/target/thulium/init.c
@@ -53,6 +53,8 @@
#include <ufs.h>
#include <boot_device.h>
#include <qmp_phy.h>
+#include <sdhci_msm.h>
+#include <qusb2_phy.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0