Merge "platform: msm8994: Add qusb2 phy tuning registers"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
old mode 100755
new mode 100644
index 3b5092d..5d036f5
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -328,11 +328,13 @@
if (cmdline_len > 0) {
const char *src;
- unsigned char *dst = (unsigned char*) malloc((cmdline_len + 4) & (~3));
- ASSERT(dst != NULL);
+ unsigned char *dst;
+
+ cmdline_final = (unsigned char*) malloc((cmdline_len + 4) & (~3));
+ ASSERT(cmdline_final != NULL);
+ dst = cmdline_final;
/* Save start ptr for debug print */
- cmdline_final = dst;
if (have_cmdline) {
src = cmdline;
while ((*dst++ = *src++));
@@ -471,7 +473,7 @@
if (boot_dev_buf)
free(boot_dev_buf);
- dprintf(INFO, "cmdline: %s\n", cmdline_final);
+ dprintf(INFO, "cmdline: %s\n", cmdline_final ? cmdline_final : "");
return cmdline_final;
}
@@ -592,6 +594,7 @@
generate_atags(tags, final_cmdline, ramdisk, ramdisk_size);
#endif
+ free(final_cmdline);
/* Perform target specific cleanup */
target_uninit();
@@ -2497,6 +2500,13 @@
memset(display_panel_buf, '\0', MAX_PANEL_BUF_SIZE);
+ /*
+ * Check power off reason if user force reset,
+ * if yes phone will do normal boot.
+ */
+ if (is_user_force_reset())
+ goto normal_boot;
+
/* Check if we should do something other than booting up */
if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
{
@@ -2532,6 +2542,7 @@
boot_into_fastboot = true;
}
+normal_boot:
if (!boot_into_fastboot)
{
if (target_is_emmc_boot())
diff --git a/dev/gcdb/display/include/panel_jdi_fhd_video.h b/dev/gcdb/display/include/panel_jdi_fhd_video.h
new file mode 100644
index 0000000..95522dd
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_fhd_video.h
@@ -0,0 +1,215 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_JDI_FHD_VIDEO_H_
+#define _PANEL_JDI_FHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_fhd_video_panel_data = {
+ "qcom,mdss_dsi_jdi_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_fhd_video_panel_res = {
+ 1080, 1920, 12, 28, 4, 0, 18, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_fhd_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char jdi_fhd_video_on_cmd0[] = {
+ 0xFF, 0xF0, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd1[] = {
+ 0xDD, 0x02, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd2[] = {
+ 0xE3, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd3[] = {
+ 0xFB, 0x01, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd4[] = {
+ 0xFF, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd5[] = {
+ 0x35, 0x00, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd6[] = {
+ 0x51, 0xFF, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd7[] = {
+ 0x53, 0x2C, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd8[] = {
+ 0xFF, 0x26, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd9[] = {
+ 0x02, 0xFF, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd10[] = {
+ 0xFF, 0x10, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd11[] = {
+ 0xBB, 0x13, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd12[] = {
+ 0xFF, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd13[] = {
+ 0x11, 0xFF, 0x05, 0x80
+};
+
+static char jdi_fhd_video_on_cmd14[] = {
+ 0x29, 0xFF, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_fhd_video_on_command[] = {
+ {0x4, jdi_fhd_video_on_cmd0, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd1, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd2, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd3, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd4, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd5, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd6, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd7, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd8, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd9, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd10, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd11, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd12, 0x0a},
+ {0x4, jdi_fhd_video_on_cmd13, 0xC8},
+ {0x4, jdi_fhd_video_on_cmd14, 0x28}
+};
+
+#define JDI_FHD_VIDEO_ON_COMMAND 15
+
+
+static char jdi_fhd_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_fhd_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_fhd_video_off_command[] = {
+ {0x4, jdi_fhd_videooff_cmd0, 0x32},
+ {0x4, jdi_fhd_videooff_cmd1, 0x78}
+};
+
+#define JDI_FHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state jdi_fhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_fhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_fhd_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_fhd_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_fhd_video_timings[] = {
+ 0xce, 0x2e, 0x1e, 0x00, 0x5a, 0x5c, 0x24, 0x30, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing jdi_fhd_video_timing_info = {
+ 0x0, 0x04, 0x0a, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_fhd_video_reset_seq = {
+ {1, 0, 1, }, {20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_fhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_JDI_FHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 8631279..427a548 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -108,7 +108,7 @@
}
pinfo->bpp = pstruct->color->color_format;
pinfo->clk_rate = pstruct->paneldata->panel_clockrate;
- pinfo->rotation = pstruct->paneldata->panel_orientation;
+ pinfo->orientation = pstruct->paneldata->panel_orientation;
pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode;
pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id;
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 8ad7370..0fe7975 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -77,3 +77,5 @@
void pm8x41_wled_led_mod_enable(uint8_t enable);
void pm8x41_wled_enable(uint8_t enable);
void pm8x41_wled_config_slave_id(uint8_t slave_id);
+uint8_t pm8x41_wled_reg_read(uint32_t addr);
+void pm8x41_wled_reg_write(uint32_t addr, uint8_t val);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 169994a..3b9783d 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -35,6 +35,13 @@
#include <pm8x41.h>
#include <platform/timer.h>
+static uint8_t mpp_slave_id;
+
+uint8_t pmi8994_config_mpp_slave_id(uint8_t slave_id)
+{
+ mpp_slave_id = slave_id;
+}
+
/* SPMI helper functions */
uint8_t pm8x41_reg_read(uint32_t addr)
{
@@ -394,16 +401,16 @@
{
ASSERT(mpp);
- REG_WRITE(mpp->base + MPP_EN_CTL, enable << MPP_EN_CTL_ENABLE_SHIFT);
+ REG_WRITE(((mpp->base + MPP_EN_CTL) + (mpp_slave_id << 16)), enable << MPP_EN_CTL_ENABLE_SHIFT);
}
void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp)
{
ASSERT(mpp);
- REG_WRITE(mpp->base + MPP_DIG_VIN_CTL, mpp->vin);
+ REG_WRITE(((mpp->base + MPP_DIG_VIN_CTL) + (mpp_slave_id << 16)), mpp->vin);
- REG_WRITE(mpp->base + MPP_MODE_CTL, mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT));
+ REG_WRITE(((mpp->base + MPP_MODE_CTL) + (mpp_slave_id << 16)), mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT));
}
uint8_t pm8x41_get_is_cold_boot()
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index 42283e1..9c3b6d3 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -33,7 +33,7 @@
static uint8_t wled_slave_id;
-static void wled_reg_write(uint32_t addr, uint8_t val)
+void pm8x41_wled_reg_write(uint32_t addr, uint8_t val)
{
uint32_t new_addr;
if (wled_slave_id) {
@@ -45,6 +45,21 @@
}
}
+uint8_t pm8x41_wled_reg_read(uint32_t addr)
+{
+ uint32_t new_addr;
+ uint8_t val;
+
+ if (wled_slave_id) {
+ new_addr = addr + (wled_slave_id << 16);
+ val = REG_READ(new_addr);
+ } else {
+ new_addr = addr + (DEFAULT_SLAVE_ID << 16);
+ val = REG_READ(new_addr);
+ }
+ return val;
+}
+
void pm8x41_wled_config_slave_id(uint8_t slave_id)
{
wled_slave_id = slave_id;
@@ -57,22 +72,22 @@
return;
}
- wled_reg_write(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
+ pm8x41_wled_reg_write(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
- wled_reg_write(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
- wled_reg_write(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
- wled_reg_write(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
- wled_reg_write(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
- wled_reg_write(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
- wled_reg_write(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
+ pm8x41_wled_reg_write(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
- wled_reg_write(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
- wled_reg_write(PM_WLED_OVP, wled_ctrl->ovp);
- wled_reg_write(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
- wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
- wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
+ pm8x41_wled_reg_write(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
+ pm8x41_wled_reg_write(PM_WLED_OVP, wled_ctrl->ovp);
+ pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
+ pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
+ pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
- wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
+ pm8x41_wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
dprintf(SPEW, "WLED Configuration Success.\n");
}
@@ -87,7 +102,7 @@
PM_WLED_LED3_SINK_MASK;
}
- wled_reg_write(PM_WLED_CURRENT_SINK, value);
+ pm8x41_wled_reg_write(PM_WLED_CURRENT_SINK, value);
dprintf(SPEW, "WLED Sink Success\n");
@@ -103,7 +118,7 @@
PM_WLED_LED3_ILED_SYNC_MASK;
}
- wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
+ pm8x41_wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
dprintf(SPEW, "WLED ILED Sync Success\n");
@@ -116,9 +131,9 @@
if (enable)
value = PM_WLED_LED_MODULATOR_EN;
- wled_reg_write(PM_WLED_LED_CTNL_REG(1), value);
- wled_reg_write(PM_WLED_LED_CTNL_REG(2), value);
- wled_reg_write(PM_WLED_LED_CTNL_REG(3), value);
+ pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(1), value);
+ pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(2), value);
+ pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(3), value);
dprintf(SPEW, "WLED LED Module Enable Success\n");
@@ -131,7 +146,7 @@
if (enable)
value = PM_WLED_ENABLE_MODULE_MASK;
- wled_reg_write(PM_WLED_ENABLE, value);
+ pm8x41_wled_reg_write(PM_WLED_ENABLE, value);
dprintf(SPEW, "WLED Enable Success\n");
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
new file mode 100644
index 0000000..751509d
--- /dev/null
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -0,0 +1,253 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bits.h>
+#include <debug.h>
+#include <reg.h>
+
+/* base addresses */
+#define QPNP_WLED_CTRL_BASE 0xd800
+#define QPNP_WLED_SINK_BASE 0xd900
+#define QPNP_WLED_IBB_BASE 0xdc00
+#define QPNP_WLED_LAB_BASE 0xde00
+
+/* ctrl registers */
+#define QPNP_WLED_EN_REG(b) (b + 0x46)
+#define QPNP_WLED_FDBK_OP_REG(b) (b + 0x48)
+#define QPNP_WLED_VREF_REG(b) (b + 0x49)
+#define QPNP_WLED_BOOST_DUTY_REG(b) (b + 0x4B)
+#define QPNP_WLED_SWITCH_FREQ_REG(b) (b + 0x4C)
+#define QPNP_WLED_OVP_REG(b) (b + 0x4D)
+#define QPNP_WLED_ILIM_REG(b) (b + 0x4E)
+
+#define QPNP_WLED_EN_MASK 0x7F
+#define QPNP_WLED_EN_SHIFT 7
+#define QPNP_WLED_FDBK_OP_MASK 0xF8
+#define QPNP_WLED_VREF_MASK 0xF0
+#define QPNP_WLED_VREF_STEP_MV 25
+#define QPNP_WLED_VREF_MIN_MV 300
+#define QPNP_WLED_VREF_MAX_MV 675
+#define QPNP_WLED_DFLT_VREF_MV 350
+#define QPNP_WLED_ILIM_MASK 0xF8
+#define QPNP_WLED_ILIM_MIN_MA 105
+#define QPNP_WLED_ILIM_MAX_MA 1980
+#define QPNP_WLED_ILIM_STEP_MA 280
+#define QPNP_WLED_DFLT_ILIM_MA 980
+#define QPNP_WLED_BOOST_DUTY_MASK 0xFC
+#define QPNP_WLED_BOOST_DUTY_STEP_NS 52
+#define QPNP_WLED_BOOST_DUTY_MIN_NS 26
+#define QPNP_WLED_BOOST_DUTY_MAX_NS 156
+#define QPNP_WLED_DEF_BOOST_DUTY_NS 104
+#define QPNP_WLED_DFLT_HYB_THRES 625
+#define QPNP_WLED_SWITCH_FREQ_MASK 0xF0
+#define QPNP_WLED_SWITCH_FREQ_800_KHZ 800
+#define QPNP_WLED_SWITCH_FREQ_1600_KHZ 1600
+#define QPNP_WLED_OVP_MASK 0xFC
+#define QPNP_WLED_OVP_17800_MV 17800
+#define QPNP_WLED_OVP_19400_MV 19400
+#define QPNP_WLED_OVP_29500_MV 29500
+#define QPNP_WLED_OVP_31000_MV 31000
+
+/* sink registers */
+#define QPNP_WLED_CURR_SINK_REG(b) (b + 0x46)
+#define QPNP_WLED_SYNC_REG(b) (b + 0x47)
+#define QPNP_WLED_MOD_REG(b) (b + 0x4A)
+#define QPNP_WLED_HYB_THRES_REG(b) (b + 0x4B)
+#define QPNP_WLED_MOD_EN_REG(b, n) (b + 0x50 + (n * 0x10))
+#define QPNP_WLED_SYNC_DLY_REG(b, n) (QPNP_WLED_MOD_EN_REG(b, n) + 0x01)
+#define QPNP_WLED_FS_CURR_REG(b, n) (QPNP_WLED_MOD_EN_REG(b, n) + 0x02)
+#define QPNP_WLED_CABC_REG(b, n) (QPNP_WLED_MOD_EN_REG(b, n) + 0x06)
+#define QPNP_WLED_BRIGHT_LSB_REG(b, n) (QPNP_WLED_MOD_EN_REG(b, n) + 0x07)
+#define QPNP_WLED_BRIGHT_MSB_REG(b, n) (QPNP_WLED_MOD_EN_REG(b, n) + 0x08)
+
+#define QPNP_WLED_MOD_FREQ_1200_KHZ 1200
+#define QPNP_WLED_MOD_FREQ_2400_KHZ 2400
+#define QPNP_WLED_MOD_FREQ_9600_KHZ 9600
+#define QPNP_WLED_MOD_FREQ_19200_KHZ 19200
+#define QPNP_WLED_MOD_FREQ_MASK 0x3F
+#define QPNP_WLED_MOD_FREQ_SHIFT 6
+#define QPNP_WLED_PHASE_STAG_MASK 0xDF
+#define QPNP_WLED_PHASE_STAG_SHIFT 5
+#define QPNP_WLED_DIM_RES_MASK 0xFD
+#define QPNP_WLED_DIM_RES_SHIFT 1
+#define QPNP_WLED_DIM_HYB_MASK 0xFB
+#define QPNP_WLED_DIM_HYB_SHIFT 2
+#define QPNP_WLED_DIM_ANA_MASK 0xFE
+#define QPNP_WLED_HYB_THRES_MASK 0xF8
+#define QPNP_WLED_HYB_THRES_MIN 78
+#define QPNP_WLED_DEF_HYB_THRES 625
+#define QPNP_WLED_HYB_THRES_MAX 10000
+#define QPNP_WLED_MOD_EN_MASK 0x7F
+#define QPNP_WLED_MOD_EN_SHFT 7
+#define QPNP_WLED_MOD_EN 1
+#define QPNP_WLED_SYNC_DLY_MASK 0xF8
+#define QPNP_WLED_SYNC_DLY_MIN_US 0
+#define QPNP_WLED_SYNC_DLY_MAX_US 1400
+#define QPNP_WLED_SYNC_DLY_STEP_US 200
+#define QPNP_WLED_DEF_SYNC_DLY_US 400
+#define QPNP_WLED_FS_CURR_MASK 0xF0
+#define QPNP_WLED_FS_CURR_MIN_UA 0
+#define QPNP_WLED_FS_CURR_MAX_UA 30000
+#define QPNP_WLED_FS_CURR_STEP_UA 2500
+#define QPNP_WLED_CABC_MASK 0x7F
+#define QPNP_WLED_CABC_SHIFT 7
+#define QPNP_WLED_CURR_SINK_SHIFT 4
+#define QPNP_WLED_BRIGHT_LSB_MASK 0xFF
+#define QPNP_WLED_BRIGHT_MSB_SHIFT 8
+#define QPNP_WLED_BRIGHT_MSB_MASK 0x0F
+#define QPNP_WLED_SYNC 0x0F
+#define QPNP_WLED_SYNC_RESET 0x00
+
+#define QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE 0x0B
+#define QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE 0x05
+
+#define QPNP_WLED_DISP_SEL_REG(b) (b + 0x44)
+#define QPNP_WLED_MODULE_RDY_REG(b) (b + 0x45)
+#define QPNP_WLED_MODULE_EN_REG(b) (b + 0x46)
+#define QPNP_WLED_MODULE_RDY_MASK 0x7F
+#define QPNP_WLED_MODULE_RDY_SHIFT 7
+#define QPNP_WLED_MODULE_EN_MASK 0x7F
+#define QPNP_WLED_MODULE_EN_SHIFT 7
+#define QPNP_WLED_DISP_SEL_MASK 0x7F
+#define QPNP_WLED_DISP_SEL_SHIFT 7
+
+#define QPNP_WLED_IBB_BIAS_REG(b) (b + 0x58)
+#define QPNP_WLED_IBB_BIAS_MASK 0x7F
+#define QPNP_WLED_IBB_BIAS_SHIFT 7
+#define QPNP_WLED_IBB_PWRUP_DLY_MASK 0xCF
+#define QPNP_WLED_IBB_PWRUP_DLY_SHIFT 4
+#define QPNP_WLED_IBB_PWRUP_DLY_MIN_MS 1
+#define QPNP_WLED_IBB_PWRUP_DLY_MAX_MS 8
+
+#define QPNP_WLED_LAB_IBB_RDY_REG(b) (b + 0x49)
+#define QPNP_WLED_LAB_FAST_PC_REG(b) (b + 0x5E)
+#define QPNP_WLED_LAB_FAST_PC_MASK 0xFB
+#define QPNP_WLED_LAB_START_DLY_US 8
+#define QPNP_WLED_LAB_FAST_PC_SHIFT 2
+
+#define QPNP_WLED_SEC_ACCESS_REG(b) (b + 0xD0)
+#define QPNP_WLED_SEC_UNLOCK 0xA5
+
+#define QPNP_WLED_MAX_STRINGS 4
+#define WLED_MAX_LEVEL_511 511
+#define WLED_MAX_LEVEL_4095 4095
+#define QPNP_WLED_RAMP_DLY_MS 20
+#define QPNP_WLED_TRIGGER_NONE "none"
+#define QPNP_WLED_STR_SIZE 20
+#define QPNP_WLED_MIN_MSLEEP 20
+#define QPNP_WLED_MAX_BR_LEVEL 1638
+
+/* output feedback mode */
+enum qpnp_wled_fdbk_op {
+ QPNP_WLED_FDBK_AUTO,
+ QPNP_WLED_FDBK_WLED1,
+ QPNP_WLED_FDBK_WLED2,
+ QPNP_WLED_FDBK_WLED3,
+ QPNP_WLED_FDBK_WLED4,
+};
+
+/* dimming modes */
+enum qpnp_wled_dim_mode {
+ QPNP_WLED_DIM_ANALOG,
+ QPNP_WLED_DIM_DIGITAL,
+ QPNP_WLED_DIM_HYBRID,
+};
+
+/* dimming curve shapes */
+enum qpnp_wled_dim_shape {
+ QPNP_WLED_DIM_SHAPE_LOG,
+ QPNP_WLED_DIM_SHAPE_LINEAR,
+ QPNP_WLED_DIM_SHAPE_SQUARE,
+};
+
+
+/**
+ * qpnp_wled - wed data structure
+ * @ fdbk_op - output feedback mode
+ * @ dim_mode - dimming mode
+ * @ dim_shape - dimming curve shape
+ * @ ctrl_base - base address for wled ctrl
+ * @ sink_base - base address for wled sink
+ * @ ibb_base - base address for IBB(Inverting Buck Boost)
+ * @ lab_base - base address for LAB(LCD/AMOLED Boost)
+ * @ mod_freq_khz - modulator frequency in KHZ
+ * @ hyb_thres - threshold for hybrid dimming
+ * @ sync_dly_us - sync delay in us
+ * @ vref_mv - ref voltage in mv
+ * @ switch_freq_khz - switching frequency in KHZ
+ * @ ovp_mv - over voltage protection in mv
+ * @ ilim_ma - current limiter in ma
+ * @ boost_duty_ns - boost duty cycle in ns
+ * @ fs_curr_ua - full scale current in ua
+ * @ ramp_ms - delay between ramp steps in ms
+ * @ ramp_step - ramp step size
+ * @ strings - supported list of strings
+ * @ num_strings - number of strings
+ * @ en_9b_dim_res - enable or disable 9bit dimming
+ * @ en_phase_stag - enable or disable phase staggering
+ * @ en_cabc - enable or disable cabc
+ * @ disp_type_amoled - type of display: LCD/AMOLED
+ * @ ibb_bias_active - activate display bias
+ * @ lab_fast_precharge - fast/slow precharge
+ */
+struct qpnp_wled {
+ enum qpnp_wled_fdbk_op fdbk_op;
+ enum qpnp_wled_dim_mode dim_mode;
+ enum qpnp_wled_dim_shape dim_shape;
+ uint16_t ctrl_base;
+ uint16_t sink_base;
+ uint16_t ibb_base;
+ uint16_t lab_base;
+ uint16_t mod_freq_khz;
+ uint16_t hyb_thres;
+ uint16_t sync_dly_us;
+ uint16_t vref_mv;
+ uint16_t switch_freq_khz;
+ uint16_t ovp_mv;
+ uint16_t ilim_ma;
+ uint16_t boost_duty_ns;
+ uint16_t fs_curr_ua;
+ uint16_t ibb_pwrup_dly_ms;
+ uint16_t ramp_ms;
+ uint16_t ramp_step;
+ uint8_t strings[QPNP_WLED_MAX_STRINGS];
+ uint8_t num_strings;
+ bool en_9b_dim_res;
+ bool en_phase_stag;
+ bool en_cabc;
+ bool disp_type_amoled;
+ bool ibb_bias_active;
+ bool lab_fast_precharge;
+};
+
+/* WLED Initial Setup */
+int qpnp_wled_init();
+
+/* Enable IBB */
+int qpnp_ibb_enable();
+void qpnp_wled_enable_backlight(enable);
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
new file mode 100644
index 0000000..a342197
--- /dev/null
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -0,0 +1,537 @@
+ /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <err.h>
+#include <qpnp_wled.h>
+
+static int fls(uint16_t n)
+{
+ int i = 0;
+ for (; n; n >>= 1, i++);
+ return i;
+}
+
+static struct qpnp_wled *gwled;
+
+static int qpnp_wled_sec_access(struct qpnp_wled *wled, uint16_t base_addr)
+{
+ int rc;
+ uint8_t reg = QPNP_WLED_SEC_UNLOCK;
+
+ pm8x41_wled_reg_write(QPNP_WLED_SEC_ACCESS_REG(base_addr), reg);
+
+ return 0;
+}
+
+/* set wled to a level of brightness */
+static int qpnp_wled_set_level(struct qpnp_wled *wled, int level)
+{
+ int i, rc;
+ uint8_t reg;
+
+ /* set brightness registers */
+ for (i = 0; i < wled->num_strings; i++) {
+ reg = level & QPNP_WLED_BRIGHT_LSB_MASK;
+ pm8x41_wled_reg_write(QPNP_WLED_BRIGHT_LSB_REG(wled->sink_base,
+ wled->strings[i]), reg);
+
+ reg = level >> QPNP_WLED_BRIGHT_MSB_SHIFT;
+ reg = reg & QPNP_WLED_BRIGHT_MSB_MASK;
+ pm8x41_wled_reg_write(QPNP_WLED_BRIGHT_MSB_REG(wled->sink_base,
+ wled->strings[i]), reg);
+ }
+
+ /* sync */
+ reg = QPNP_WLED_SYNC;
+ pm8x41_wled_reg_write(QPNP_WLED_SYNC_REG(wled->sink_base), reg);
+
+ reg = QPNP_WLED_SYNC_RESET;
+ pm8x41_wled_reg_write(QPNP_WLED_SYNC_REG(wled->sink_base), reg);
+
+ return 0;
+}
+
+static int qpnp_wled_enable(struct qpnp_wled *wled,
+ uint16_t base_addr, bool state)
+{
+ uint8_t reg;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_MODULE_EN_REG(base_addr));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_MODULE_EN_MASK;
+ reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_MODULE_EN_REG(base_addr), reg);
+
+ return 0;
+}
+
+int qpnp_ibb_enable(bool state)
+{
+ int rc = 0;
+ uint8_t reg;
+
+ if (!gwled) {
+ dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
+ return ERROR;
+ }
+
+ /* enable lab */
+ if (gwled->ibb_bias_active) {
+ rc = qpnp_wled_enable(gwled, gwled->lab_base, state);
+ if (rc < 0)
+ return rc;
+ udelay(QPNP_WLED_LAB_START_DLY_US + 1);
+ } else {
+ reg = pm8x41_wled_reg_read(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base));
+ if (reg < 0)
+ return reg;
+
+ reg &= QPNP_WLED_MODULE_EN_MASK;
+ reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base), reg);
+ }
+
+ rc = qpnp_wled_enable(gwled, gwled->ibb_base, state);
+
+ return rc;
+}
+
+/* enable / disable wled brightness */
+void qpnp_wled_enable_backlight(int enable)
+{
+ int level, rc;
+
+ if (!gwled) {
+ dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
+ return ERROR;
+ }
+
+ if (enable) {
+ rc = qpnp_wled_set_level(gwled, QPNP_WLED_MAX_BR_LEVEL);
+ if (rc) {
+ dprintf(CRITICAL,"wled set level failed\n");
+ return;
+ }
+ }
+ rc = qpnp_wled_enable(gwled, gwled->ctrl_base, enable);
+
+ if (rc) {
+ dprintf(CRITICAL,"wled %sable failed\n",
+ enable ? "en" : "dis");
+ return;
+ }
+
+}
+
+static int qpnp_wled_set_display_type(struct qpnp_wled *wled, uint16_t base_addr)
+{
+ int rc;
+ uint8_t reg = 0;
+
+ /* display type */
+ reg = pm8x41_wled_reg_read(QPNP_WLED_DISP_SEL_REG(base_addr));
+ if (reg < 0)
+ return reg;
+
+ reg &= QPNP_WLED_DISP_SEL_MASK;
+ reg |= (wled->disp_type_amoled << QPNP_WLED_DISP_SEL_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_DISP_SEL_REG(base_addr), reg);
+
+ return 0;
+}
+
+static int qpnp_wled_module_ready(struct qpnp_wled *wled, uint16_t base_addr, bool state)
+{
+ int rc;
+ uint8_t reg;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_MODULE_RDY_REG(base_addr));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_MODULE_RDY_MASK;
+ reg |= (state << QPNP_WLED_MODULE_RDY_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_MODULE_RDY_REG(base_addr), reg);
+
+ return 0;
+}
+
+/* Configure WLED registers */
+static int qpnp_wled_config(struct qpnp_wled *wled)
+{
+ int rc, i, temp;
+ uint8_t reg = 0;
+
+ /* Configure display type */
+ rc = qpnp_wled_set_display_type(wled, wled->ctrl_base);
+ if (rc < 0)
+ return rc;
+
+ /* Configure the FEEDBACK OUTPUT register */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_FDBK_OP_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_FDBK_OP_MASK;
+ reg |= wled->fdbk_op;
+ pm8x41_wled_reg_write(QPNP_WLED_FDBK_OP_REG(wled->ctrl_base), reg);
+
+ /* Configure the VREF register */
+ if (wled->vref_mv < QPNP_WLED_VREF_MIN_MV)
+ wled->vref_mv = QPNP_WLED_VREF_MIN_MV;
+ else if (wled->vref_mv > QPNP_WLED_VREF_MAX_MV)
+ wled->vref_mv = QPNP_WLED_VREF_MAX_MV;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_VREF_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_VREF_MASK;
+ temp = wled->vref_mv - QPNP_WLED_VREF_MIN_MV;
+ reg |= (temp / QPNP_WLED_VREF_STEP_MV);
+ pm8x41_wled_reg_write(QPNP_WLED_VREF_REG(wled->ctrl_base), reg);
+
+ /* Configure the ILIM register */
+ if (wled->ilim_ma < QPNP_WLED_ILIM_MIN_MA)
+ wled->ilim_ma = QPNP_WLED_ILIM_MIN_MA;
+ else if (wled->ilim_ma > QPNP_WLED_ILIM_MAX_MA)
+ wled->ilim_ma = QPNP_WLED_ILIM_MAX_MA;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_ILIM_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_ILIM_MASK;
+ reg |= (wled->ilim_ma / QPNP_WLED_ILIM_STEP_MA);
+ pm8x41_wled_reg_write(QPNP_WLED_ILIM_REG(wled->ctrl_base), reg);
+
+ /* Configure the MAX BOOST DUTY register */
+ if (wled->boost_duty_ns < QPNP_WLED_BOOST_DUTY_MIN_NS)
+ wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MIN_NS;
+ else if (wled->boost_duty_ns > QPNP_WLED_BOOST_DUTY_MAX_NS)
+ wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MAX_NS;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_BOOST_DUTY_MASK;
+ reg |= (wled->boost_duty_ns / QPNP_WLED_BOOST_DUTY_STEP_NS);
+ pm8x41_wled_reg_write(QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base), reg);
+
+ /* Configure the SWITCHING FREQ register */
+ if (wled->switch_freq_khz == QPNP_WLED_SWITCH_FREQ_1600_KHZ)
+ temp = QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE;
+ else
+ temp = QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_SWITCH_FREQ_MASK;
+ reg |= temp;
+ pm8x41_wled_reg_write(QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), reg);
+
+ /* Configure the OVP register */
+ if (wled->ovp_mv <= QPNP_WLED_OVP_17800_MV) {
+ wled->ovp_mv = QPNP_WLED_OVP_17800_MV;
+ temp = 3;
+ } else if (wled->ovp_mv <= QPNP_WLED_OVP_19400_MV) {
+ wled->ovp_mv = QPNP_WLED_OVP_19400_MV;
+ temp = 2;
+ } else if (wled->ovp_mv <= QPNP_WLED_OVP_29500_MV) {
+ wled->ovp_mv = QPNP_WLED_OVP_29500_MV;
+ temp = 1;
+ } else {
+ wled->ovp_mv = QPNP_WLED_OVP_31000_MV;
+ temp = 0;
+ }
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_OVP_REG(wled->ctrl_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_OVP_MASK;
+ reg |= temp;
+ pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
+
+ /* Configure the MODULATION register */
+ if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_1200_KHZ) {
+ wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_1200_KHZ;
+ temp = 3;
+ } else if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_2400_KHZ) {
+ wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_2400_KHZ;
+ temp = 2;
+ } else if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_9600_KHZ) {
+ wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_9600_KHZ;
+ temp = 1;
+ } else {
+ wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_19200_KHZ;
+ temp = 0;
+ }
+ reg = pm8x41_wled_reg_read(QPNP_WLED_MOD_REG(wled->sink_base));
+ if (reg < 0)
+ return reg;
+
+ reg &= QPNP_WLED_MOD_FREQ_MASK;
+ reg |= (temp << QPNP_WLED_MOD_FREQ_SHIFT);
+
+ reg &= QPNP_WLED_PHASE_STAG_MASK;
+ reg |= (wled->en_phase_stag << QPNP_WLED_PHASE_STAG_SHIFT);
+
+ reg &= QPNP_WLED_DIM_RES_MASK;
+ reg |= (wled->en_9b_dim_res << QPNP_WLED_DIM_RES_SHIFT);
+
+ if (wled->dim_mode == QPNP_WLED_DIM_HYBRID) {
+ reg &= QPNP_WLED_DIM_HYB_MASK;
+ reg |= (1 << QPNP_WLED_DIM_HYB_SHIFT);
+ } else {
+ reg &= QPNP_WLED_DIM_HYB_MASK;
+ reg |= (0 << QPNP_WLED_DIM_HYB_SHIFT);
+ reg &= QPNP_WLED_DIM_ANA_MASK;
+ reg |= wled->dim_mode;
+ }
+
+ pm8x41_wled_reg_write(QPNP_WLED_MOD_REG(wled->sink_base), reg);
+
+ /* Configure the HYBRID THRESHOLD register */
+ if (wled->hyb_thres < QPNP_WLED_HYB_THRES_MIN)
+ wled->hyb_thres = QPNP_WLED_HYB_THRES_MIN;
+ else if (wled->hyb_thres > QPNP_WLED_HYB_THRES_MAX)
+ wled->hyb_thres = QPNP_WLED_HYB_THRES_MAX;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_HYB_THRES_REG(wled->sink_base));
+ if (reg < 0)
+ return reg;
+
+ reg &= QPNP_WLED_HYB_THRES_MASK;
+ temp = fls(wled->hyb_thres / QPNP_WLED_HYB_THRES_MIN) - 1;
+ reg |= temp;
+ pm8x41_wled_reg_write(QPNP_WLED_HYB_THRES_REG(wled->sink_base), reg);
+
+ for (i = 0; i < wled->num_strings; i++) {
+ if (wled->strings[i] >= QPNP_WLED_MAX_STRINGS) {
+ dprintf(CRITICAL,"Invalid string number\n");
+ return ERR_NOT_VALID;
+ }
+
+ /* MODULATOR */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_MOD_EN_REG(wled->sink_base,
+ wled->strings[i]));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_MOD_EN_MASK;
+ reg |= (QPNP_WLED_MOD_EN << QPNP_WLED_MOD_EN_SHFT);
+ pm8x41_wled_reg_write(QPNP_WLED_MOD_EN_REG(wled->sink_base,
+ wled->strings[i]), reg);
+
+ /* SYNC DELAY */
+ if (wled->sync_dly_us < QPNP_WLED_SYNC_DLY_MIN_US)
+ wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MIN_US;
+ else if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
+ wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MAX_US;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
+ wled->strings[i]));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_SYNC_DLY_MASK;
+ temp = wled->sync_dly_us / QPNP_WLED_SYNC_DLY_STEP_US;
+ reg |= temp;
+ pm8x41_wled_reg_write(QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
+ wled->strings[i]), reg);
+
+ /* FULL SCALE CURRENT */
+ if (wled->fs_curr_ua < QPNP_WLED_FS_CURR_MIN_UA)
+ wled->fs_curr_ua = QPNP_WLED_FS_CURR_MIN_UA;
+ else if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
+ wled->fs_curr_ua = QPNP_WLED_FS_CURR_MAX_UA;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_FS_CURR_REG(wled->sink_base,
+ wled->strings[i]));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_FS_CURR_MASK;
+ temp = wled->fs_curr_ua / QPNP_WLED_FS_CURR_STEP_UA;
+ reg |= temp;
+ pm8x41_wled_reg_write(QPNP_WLED_FS_CURR_REG(wled->sink_base,
+ wled->strings[i]), reg);
+
+ /* CABC */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_CABC_REG(wled->sink_base,
+ wled->strings[i]));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_CABC_MASK;
+ reg |= (wled->en_cabc << QPNP_WLED_CABC_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_CABC_REG(wled->sink_base,
+ wled->strings[i]), reg);
+
+ /* Enable CURRENT SINK */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_CURR_SINK_REG(wled->sink_base));
+ if (reg < 0)
+ return reg;
+ temp = wled->strings[i] + QPNP_WLED_CURR_SINK_SHIFT;
+ reg |= (1 << temp);
+ pm8x41_wled_reg_write(QPNP_WLED_CURR_SINK_REG(wled->sink_base), reg);
+ }
+
+ /* LAB fast precharge */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base));
+ if (reg < 0)
+ return reg;
+ reg &= QPNP_WLED_LAB_FAST_PC_MASK;
+ reg |= (wled->lab_fast_precharge << QPNP_WLED_LAB_FAST_PC_SHIFT);
+ pm8x41_wled_reg_write(QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base), reg);
+
+ /* Configure lab display type */
+ rc = qpnp_wled_set_display_type(wled, wled->lab_base);
+ if (rc < 0)
+ return rc;
+
+ /* make LAB module ready */
+ rc = qpnp_wled_module_ready(wled, wled->lab_base, true);
+ if (rc < 0)
+ return rc;
+
+ /* IBB active bias */
+ if (wled->ibb_pwrup_dly_ms < QPNP_WLED_IBB_PWRUP_DLY_MIN_MS)
+ wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MIN_MS;
+ else if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
+ wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MAX_MS;
+
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_IBB_BIAS_REG(wled->ibb_base));
+ if (reg < 0)
+ return reg;
+
+ reg &= QPNP_WLED_IBB_BIAS_MASK;
+ reg |= (!wled->ibb_bias_active << QPNP_WLED_IBB_BIAS_SHIFT);
+
+ temp = fls(wled->ibb_pwrup_dly_ms) - 1;
+ reg &= QPNP_WLED_IBB_PWRUP_DLY_MASK;
+ reg |= (temp << QPNP_WLED_IBB_PWRUP_DLY_SHIFT);
+
+ rc = qpnp_wled_sec_access(wled, wled->ibb_base);
+ if (rc)
+ return rc;
+
+ pm8x41_wled_reg_write(QPNP_WLED_IBB_BIAS_REG(wled->ibb_base), reg);
+
+ /* Configure ibb display type */
+ rc = qpnp_wled_set_display_type(wled, wled->ibb_base);
+ if (rc < 0)
+ return rc;
+
+ /* make IBB module ready */
+ rc = qpnp_wled_module_ready(wled, wled->ibb_base, true);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+/* Setup wled default parameters */
+static int qpnp_wled_setup(struct qpnp_wled *wled)
+{
+ int rc, i;
+
+ wled->sink_base = QPNP_WLED_SINK_BASE;
+ wled->ctrl_base = QPNP_WLED_CTRL_BASE;
+ wled->ibb_base = QPNP_WLED_IBB_BASE;
+ wled->lab_base = QPNP_WLED_LAB_BASE;
+ wled->fdbk_op = QPNP_WLED_FDBK_AUTO;
+ wled->vref_mv = QPNP_WLED_DFLT_VREF_MV;
+ wled->switch_freq_khz = QPNP_WLED_SWITCH_FREQ_800_KHZ;
+ wled->ovp_mv = QPNP_WLED_OVP_29500_MV;
+ wled->ilim_ma = QPNP_WLED_DFLT_ILIM_MA;
+ wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MIN_NS;
+ wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_19200_KHZ;
+ wled->dim_mode = QPNP_WLED_DIM_HYBRID;
+ wled->dim_shape = QPNP_WLED_DIM_SHAPE_LINEAR;
+
+ if (wled->dim_mode == QPNP_WLED_DIM_HYBRID) {
+ wled->hyb_thres = QPNP_WLED_DFLT_HYB_THRES;
+ }
+
+ wled->sync_dly_us = 800;
+ wled->fs_curr_ua = 16000;
+ wled->en_9b_dim_res = 0;
+ wled->en_phase_stag = true;
+ wled->en_cabc = 0;
+
+ wled->num_strings = QPNP_WLED_MAX_STRINGS;
+ for (i = 0; i < wled->num_strings; i++)
+ wled->strings[i] = i;
+
+ wled->ibb_bias_active = false;
+ wled->ibb_pwrup_dly_ms = 8;
+ wled->lab_fast_precharge = false;
+ wled->disp_type_amoled = false;
+
+ return 0;
+}
+
+int qpnp_wled_init()
+{
+ int rc, i;
+ struct qpnp_wled *wled;
+
+ wled = malloc(sizeof(struct qpnp_wled));
+ if (!wled)
+ return ERR_NO_MEMORY;
+
+ memset(wled, 0, sizeof(struct qpnp_wled));
+
+ rc = qpnp_wled_setup(wled);
+ if (rc) {
+ dprintf(CRITICAL, "Setting WLED parameters failed\n");
+ return rc;
+ }
+
+ rc = qpnp_wled_config(wled);
+ if (rc) {
+ dprintf(CRITICAL, "wled config failed\n");
+ return rc;
+ }
+
+ gwled = wled;
+
+ return rc;
+}
diff --git a/dev/qpnp_wled/rules.mk b/dev/qpnp_wled/rules.mk
new file mode 100644
index 0000000..d60c07f
--- /dev/null
+++ b/dev/qpnp_wled/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+ $(LOCAL_DIR)/qpnp_wled.o
diff --git a/include/target.h b/include/target.h
index c7c05db..ba95cbb 100644
--- a/include/target.h
+++ b/include/target.h
@@ -59,6 +59,7 @@
void target_load_ssd_keystore(void);
bool target_is_ssd_enabled(void);
void *target_mmc_device();
+uint32_t is_user_force_reset(void);
bool target_display_panel_node(char *panel_name, char *pbuf,
uint16_t buf_size);
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index bad5743..c50fef7 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -34,6 +34,71 @@
#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR REG_MM(0x2304)
+#define GDSC_POWER_ON_BIT BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK BIT(19)
+
+#define VSYNC_CMD_RCGR REG_MM(0x2080)
+#define VSYNC_CFG_RCGR REG_MM(0x2084)
+#define MDSS_VSYNC_CBCR REG_MM(0x2328)
+#define MDP_CMD_RCGR REG_MM(0x2040)
+#define MDP_CFG_RCGR REG_MM(0x2044)
+#define MDP_CBCR REG_MM(0x231C)
+#define MDP_LUT_CBCR REG_MM(0x2320)
+#define MDP_AHB_CBCR REG_MM(0x2308)
+
+#define MDP_AXI_CMD_RCGR REG_MM(0x5040)
+#define MDP_AXI_CFG_RCGR REG_MM(0x5044)
+
+#define MDP_AXI_CBCR REG_MM(0x2310)
+#define MMSS_S0_AXI_CBCR REG_MM(0x5064)
+#define MMSS_MMSSNOC_AXI_CBCR REG_MM(0x506C)
+
+#define DSI_BYTE0_CMD_RCGR REG_MM(0x2120)
+#define DSI_BYTE0_CFG_RCGR REG_MM(0x2124)
+#define DSI_BYTE0_CBCR REG_MM(0x233C)
+#define DSI_ESC0_CMD_RCGR REG_MM(0x2160)
+#define DSI_ESC0_CFG_RCGR REG_MM(0x2164)
+#define DSI_ESC0_CBCR REG_MM(0x2344)
+#define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000)
+#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
+#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI_PIXEL0_M REG_MM(0x2008)
+#define DSI_PIXEL0_N REG_MM(0x200C)
+#define DSI_PIXEL0_D REG_MM(0x2010)
+
+#define DSI0_PHY_PLL_OUT BIT(8)
+#define PIXEL_SRC_DIV_1_5 BIT(1)
+
+#define DSI_BYTE1_CMD_RCGR REG_MM(0x2140)
+#define DSI_BYTE1_CFG_RCGR REG_MM(0x2144)
+#define DSI_BYTE1_CBCR REG_MM(0x2340)
+#define DSI_ESC1_CMD_RCGR REG_MM(0x2180)
+#define DSI_ESC1_CFG_RCGR REG_MM(0x2184)
+#define DSI_ESC1_CBCR REG_MM(0x2348)
+#define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020)
+#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
+#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define DSI_PIXEL1_M REG_MM(0x2028)
+#define DSI_PIXEL1_N REG_MM(0x202C)
+#define DSI_PIXEL1_D REG_MM(0x2030)
+
+#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR REG_MM(0x2334)
+#define EDPPIXEL_M REG_MM(0x20A8)
+#define EDPPIXEL_N REG_MM(0x20AC)
+#define EDPPIXEL_D REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
void platform_clock_init(void);
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 08ad2e3..3910502 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -214,4 +214,64 @@
#define PLATFORM_QMP_OFFSET 0x8
#define SMEM_TARG_INFO_ADDR 0xFE805FF0
+
+/* Display */
+#define EDP_BASE 0xFD990000
+
+#define SOFT_RESET 0x118
+#define CLK_CTRL 0x11C
+#define TRIG_CTRL 0x084
+#define CTRL 0x004
+#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
+#define ERR_INT_MASK0 0x10C
+
+#define LANE_SWAP_CTL 0x0B0
+#define TIMING_CTL 0x0C4
+
+#define VIDEO_MODE_ACTIVE_H 0x024
+#define VIDEO_MODE_ACTIVE_V 0x028
+#define VIDEO_MODE_TOTAL 0x02C
+#define VIDEO_MODE_HSYNC 0x030
+#define VIDEO_MODE_VSYNC 0x034
+#define VIDEO_MODE_VSYNC_VPOS 0x038
+
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000
+#define MIPI_DSI_BASE 0xFD998000
+#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE 0xFD9A0000
+#define DSI0_PHY_BASE 0xFD998500
+#define DSI1_PHY_BASE 0xFD9A0500
+#define DSI0_PLL_BASE 0xFD998300
+#define DSI1_PLL_BASE 0xFD9A0300
+#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define MDP_BASE (0xfd900000)
+#define REG_MDP(off) (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE REG_MDP(0x2200)
+#define MDP_VP_0_RGB_1_BASE REG_MDP(0x2600)
+#define MDP_VP_0_DMA_0_BASE REG_MDP(0x3200)
+#define MDP_VP_0_DMA_1_BASE REG_MDP(0x3600)
+#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
+#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
+
+#define DMA_CMD_OFFSET 0x048
+#define DMA_CMD_LENGTH 0x04C
+
+#define INT_CTRL 0x110
+#define CMD_MODE_DMA_SW_TRIGGER 0x090
+
+#define EOT_PACKET_CTRL 0x0CC
+#define MISR_CMD_CTRL 0x0A0
+#define MISR_VIDEO_CTRL 0x0A4
+#define VIDEO_MODE_CTRL 0x010
+#define HS_TIMER_CTRL 0x0BC
+
#endif
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 68343bf..033a88d 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -45,6 +45,8 @@
#define mmpll1_mm_source_val 2
#define mmpll3_mm_source_val 3
#define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -486,6 +488,273 @@
},
};
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_MM(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+ F_MM( 75000000, gpll0, 8, 0, 0),
+ F_MM( 240000000, gpll0, 2.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc0_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc0_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk dsi_esc1_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc1_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+ .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
+ .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_vsync_clk,
+
+ .c = {
+ .dbg_name = "vsync_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mmss_axi_clk,
+
+ .c = {
+ .dbg_name = "mdp_axi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_esc0_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
+ .parent = &dsi_esc0_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc0_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_esc1_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
+ .parent = &dsi_esc1_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc1_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_axi_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_mmssnoc_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_s0_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdp_ahb_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdp_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdp_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_mdp_clk = {
+ .cbcr_reg = (uint32_t *) MDP_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+ .cbcr_reg = MDP_LUT_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_lut_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_vsync_clk = {
+ .cbcr_reg = MDSS_VSYNC_CBCR,
+ .parent = &vsync_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_vsync_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+ .cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edpaux_clk,
+
+ .c = {
+ .dbg_name = "edpaux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+ .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .parent = &edpaux_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_edpaux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+ F_MDSS(162000000, edppll_270, 2, 0, 0),
+ F_MDSS(270000000, edppll_270, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+ .cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edplink_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edplink_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+ F_MDSS(138500000, edppll_350, 2, 0, 0),
+ F_MDSS(350000000, edppll_350, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+ .cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_mdss_edppixel_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edppixel_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk mdss_edplink_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+ .has_sibling = 0,
+ .parent = &edplink_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edplink_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+ .has_sibling = 0,
+ .parent = &edppixel_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edppixel_clk",
+ .ops = &clk_ops_branch,
+ },
+};
/* Clock lookup table */
static struct clk_lookup msm_8994_clocks[] =
@@ -510,6 +779,22 @@
CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+
+ /* mdss clocks */
+ CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
+ CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
+ CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
+ CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
+ CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+ CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c),
+ CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
+ CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
+ CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
+ CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
+
+ CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
+ CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
+ CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 581477d..5c7dee8 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -34,6 +34,7 @@
static struct board_data board = {UNKNOWN,
0,
+ 0,
HW_PLATFORM_UNKNOWN,
HW_PLATFORM_SUBTYPE_UNKNOWN,
LINUX_MACHTYPE_UNKNOWN,
@@ -131,6 +132,9 @@
board.pmic_info[i].pmic_type = board_info_v8.pmic_info[i].pmic_type;
board.pmic_info[i].pmic_version = board_info_v8.pmic_info[i].pmic_version;
}
+
+ if (format_minor == 0x9)
+ board.foundry_id = board_info_v8.foundry_id;
}
/* HLOS subtype
@@ -179,6 +183,11 @@
return board.platform_subtype;
}
+uint32_t board_foundry_id(void)
+{
+ return board.foundry_id;
+}
+
uint8_t board_pmic_info(struct board_pmic_data *info, uint8_t num_ent)
{
uint8_t i;
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 5df5a70..386b628 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -47,7 +47,7 @@
static struct dt_mem_node_info mem_node;
-static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask);
+static int platform_dt_match(struct dt_entry *cur_dt_entry, struct board_dt_entry *board_dt_data, uint32_t subtype_mask);
extern int target_is_emmc_boot(void);
extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
/* TODO: This function needs to be moved to target layer to check violations
@@ -81,6 +81,7 @@
uint32_t msm_data_count;
uint32_t board_data_count;
uint32_t soc_rev;
+ struct board_dt_entry board_dt_data;
root_offset = fdt_path_offset(dtb, "/");
if (root_offset < 0)
@@ -135,13 +136,14 @@
cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
cur_dt_entry.board_hw_subtype = board_hardware_subtype();
- target_variant_id = board_hardware_id();
+ board_dt_data.target_variant_id = board_hardware_id();
+ board_dt_data.platform_variant_id = board_platform_id();
dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
*model ? model : "unknown",
cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
- if (platform_dt_match(&cur_dt_entry, target_variant_id, 0) == 1)
+ if (platform_dt_match(&cur_dt_entry, &board_dt_data, 0) == 1)
{
dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
cur_dt_entry.platform_id,
@@ -223,9 +225,15 @@
/* Now find the matching entry in the merged list */
if (board_hardware_id() == HW_PLATFORM_QRD)
- target_variant_id = board_target_id();
+ {
+ board_dt_data.target_variant_id = board_target_id();
+ board_dt_data.platform_variant_id = board_platform_id();
+ }
else
- target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+ {
+ board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+ board_dt_data.platform_variant_id = board_platform_id();
+ }
for (i=0 ;i < num_entries; i++)
{
@@ -233,7 +241,7 @@
*model ? model : "unknown",
dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
- if (platform_dt_match(&dt_entry_v2[i], target_variant_id, 0xff) == 1)
+ if (platform_dt_match(&dt_entry_v2[i], &board_dt_data, 0xff) == 1)
{
dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
dt_entry_v2[i].platform_id,
@@ -402,7 +410,7 @@
return 0;
}
-static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask)
+static int platform_dt_match(struct dt_entry *cur_dt_entry, struct board_dt_entry *board_dt_data, uint32_t subtype_mask)
{
/*
* 1. Check if cur_dt_entry has platform_hw_version major & minor present?
@@ -418,7 +426,7 @@
* ignore the major & minor versions from the DTB entry
*/
if ((cur_dt_entry->variant_id & 0xffff00) == 0xffff00)
- cur_dt_target_id = (cur_dt_entry->variant_id & 0xff0000ff) | (target_variant_id & 0xffff00);
+ cur_dt_target_id = (cur_dt_entry->variant_id & 0xff0000ff) | (board_dt_data->target_variant_id & 0xffff00);
/*
* We have a valid platform_hw_version major & minor numbers in the board-id, so
* use the board-id from the DTB.
@@ -437,10 +445,9 @@
* 4. otherwise return 1
*/
- if((cur_dt_entry->platform_id == board_platform_id()) &&
- (cur_dt_target_id == target_variant_id) &&
+ if((cur_dt_entry->platform_id == board_dt_data->platform_variant_id) &&
+ (cur_dt_target_id == board_dt_data->target_variant_id) &&
(cur_dt_hlos_subtype == target_get_hlos_subtype())) {
-
if(cur_dt_entry->soc_rev == board_soc_version()) {
return 0;
} else if(cur_dt_entry->soc_rev < board_soc_version()) {
@@ -452,7 +459,7 @@
}
static int __dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info,
- uint32_t target_variant_id, uint32_t subtype_mask)
+ struct board_dt_entry *board_dt_data, uint32_t subtype_mask)
{
uint32_t i;
unsigned char *table_ptr;
@@ -503,7 +510,7 @@
* we pickup the DTB with highest soc rev number which is less
* than or equal to actual hardware
*/
- switch(platform_dt_match(cur_dt_entry, target_variant_id, subtype_mask)) {
+ switch(platform_dt_match(cur_dt_entry, board_dt_data, subtype_mask)) {
case 0:
best_match_dt_entry = cur_dt_entry;
found = 1;
@@ -530,17 +537,17 @@
}
if (found != 0) {
- dprintf(INFO, "Using DTB entry %u/%08x/0x%08x/%u for device %u/%08x/0x%08x/%u\n",
+ dprintf(INFO, "Using DTB entry 0x%08x/%08x/0x%08x/%u for device 0x%08x/%08x/0x%08x/%u\n",
dt_entry_info->platform_id, dt_entry_info->soc_rev,
dt_entry_info->variant_id, dt_entry_info->board_hw_subtype,
- board_platform_id(), board_soc_version(),
- board_target_id(), board_hardware_subtype());
+ board_dt_data->platform_variant_id, board_soc_version(),
+ board_dt_data->target_variant_id, board_hardware_subtype());
return 0;
}
- dprintf(CRITICAL, "ERROR: Unable to find suitable device tree for device (%u/0x%08x/0x%08x/%u)\n",
- board_platform_id(), board_soc_version(),
- board_target_id(), board_hardware_subtype());
+ dprintf(CRITICAL, "INFO: Unable to find suitable device tree for device (0x%08x/0x%08x/0x%08x/%u)\n",
+ board_dt_data->platform_variant_id, board_soc_version(),
+ board_dt_data->target_variant_id, board_hardware_subtype());
return -1;
}
@@ -552,10 +559,23 @@
*/
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info)
{
- uint32_t target_variant_id;
+ struct board_dt_entry board_dt_data;
- target_variant_id = board_target_id();
- if (__dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0xff) == 0) {
+ /* 1. Look for new board-id (platform version + hw + subtype) & new msm-id (soc ver + soc id + foundry-id) */
+ board_dt_data.target_variant_id = board_target_id();
+ /* Platform-id
+ * bit no |31 24|23 16|15 0|
+ * |reserved|foundry-id|msm-id|
+ */
+ board_dt_data.platform_variant_id = board_platform_id() | (board_foundry_id() << 16);
+ if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
+ return 0;
+ }
+
+ /* 2. Look for new board-id & old msm-id (no foundry-id) */
+ board_dt_data.target_variant_id = board_target_id();
+ board_dt_data.platform_variant_id = board_platform_id();
+ if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
return 0;
}
@@ -563,16 +583,26 @@
* for compatible with version 1 and version 2 dtbtool
* will compare the subtype inside the variant id
*/
- target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
- if (__dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0xff) == 0) {
+
+ /* 3. Look for old board-id (no platform version) & new msm-id (with foundry-id) */
+ board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+ board_dt_data.platform_variant_id = board_platform_id() | (board_foundry_id() << 16);
+ if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
+ return 0;
+ }
+ /* 4. Look for old board-id (no platform versions) & old msm-id(no foundry-id) */
+ board_dt_data.target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+ board_dt_data.platform_variant_id = board_platform_id();
+ if (__dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0xff) == 0) {
return 0;
}
/*
* add compatible with old device selection method which don't compare subtype
*/
- target_variant_id = board_hardware_id();
- return __dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0);
+ board_dt_data.target_variant_id = board_hardware_id();
+ board_dt_data.platform_variant_id = board_platform_id();
+ return __dev_tree_get_entry_info(table, dt_entry_info, &board_dt_data, 0);
}
/* Function to add the first RAM partition info to the device tree.
@@ -822,12 +852,15 @@
}
offset = ret;
- /* Adding the cmdline to the chosen node */
- ret = fdt_appendprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
- if (ret)
+ if (cmdline)
{
- dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
- return ret;
+ /* Adding the cmdline to the chosen node */
+ ret = fdt_appendprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
+ if (ret)
+ {
+ dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
+ return ret;
+ }
}
if (ramdisk_size) {
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index 0d280f2..284f8e5 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -55,6 +55,11 @@
goto cleanup;
}
pub_key = X509_get_pubkey(x509_certificate);
+ if (pub_key == NULL) {
+ dprintf(CRITICAL, "ERROR: Boot Invalid, PUB_KEY is NULL!\n");
+ goto cleanup;
+ }
+
rsa_key = EVP_PKEY_get1_RSA(pub_key);
if (rsa_key == NULL) {
dprintf(CRITICAL, "ERROR: Boot Invalid, RSA_KEY is NULL!\n");
diff --git a/platform/msm_shared/include/board.h b/platform/msm_shared/include/board.h
index 75fc888..9efde4d 100644
--- a/platform/msm_shared/include/board.h
+++ b/platform/msm_shared/include/board.h
@@ -43,6 +43,7 @@
struct board_data {
uint32_t platform;
+ uint32_t foundry_id;
uint32_t platform_version;
uint32_t platform_hw;
uint32_t platform_subtype;
@@ -79,4 +80,5 @@
SUBTYPE_512MB = 1,
};
+uint32_t board_foundry_id(void);
#endif
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index 1d9b9ad..ef41046 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -98,6 +98,12 @@
DT_OP_FAILURE = -1,
};
+struct board_dt_entry
+{
+ uint32_t target_variant_id;
+ uint32_t platform_variant_id;
+};
+
int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size);
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
int update_device_tree(void *fdt, const char *, void *, unsigned);
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 8207651..1f5b902 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -147,6 +147,10 @@
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x0180)
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x0230)
+/* source pipe opmode bits for flip */
+#define MDSS_MDP_OP_MODE_FLIP_UD BIT(14)
+#define MDSS_MDP_OP_MODE_FLIP_LR BIT(13)
+
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x02E0)
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x02E4)
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index a480d2c..8b7af72 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -195,7 +195,7 @@
uint32_t type;
uint32_t wait_cycle;
uint32_t clk_rate;
- uint32_t rotation;
+ uint32_t orientation;
/* Select pipe type for handoff */
uint32_t pipe_type;
char lowpowerstop;
diff --git a/platform/msm_shared/jtag.c b/platform/msm_shared/jtag.c
index 0430eaf..cf278f8 100644
--- a/platform/msm_shared/jtag.c
+++ b/platform/msm_shared/jtag.c
@@ -2,6 +2,8 @@
* Copyright (C) 2008 The Android Open Source Project
* All rights reserved.
*
+ * Copyright (C) 2008-2014, The Linux Foundation. All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -11,6 +13,9 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
@@ -32,10 +37,11 @@
#define STATUS_OKAY 1
#define STATUS_FAIL 2
#define STATUS_PRINT 3
+#define JTAG_CMD_NUM 256
volatile unsigned _jtag_cmd = 0;
volatile unsigned _jtag_msg = 0;
-unsigned char _jtag_cmd_buffer[128];
+unsigned char _jtag_cmd_buffer[JTAG_CMD_NUM];
unsigned char _jtag_msg_buffer[128];
volatile unsigned _jtag_arg0 = 0;
@@ -82,7 +88,7 @@
if (jtag_cmd_pending()) {
do_cmd((const char *)_jtag_cmd_buffer, _jtag_arg0,
_jtag_arg1, _jtag_arg2);
- for (n = 0; n < 256; n++)
+ for (n = 0; n < JTAG_CMD_NUM; n++)
_jtag_cmd_buffer[n] = 0;
_jtag_arg0 = 0;
_jtag_arg1 = 0;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index ff260d7..6e8fea4 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -127,6 +127,7 @@
{
uint32_t src_size, out_size, stride;
uint32_t fb_off = 0;
+ uint32_t flip_bits = 0;
/* write active region size*/
src_size = (fb->height << 16) + fb->width;
@@ -152,7 +153,15 @@
/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN);
- writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE);
+
+ /* bit(0) is set if hflip is required.
+ * bit(1) is set if vflip is required.
+ */
+ if (pinfo->orientation & 0x1)
+ flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR;
+ if (pinfo->orientation & 0x2)
+ flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD;
+ writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE);
}
static void mdss_vbif_setup()
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 1d68c66..14925f5 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -188,7 +188,7 @@
* Need for 8 bytes alignment
* while reading from shared memory
*/
- unsigned buffer_align;
+ uint32_t foundry_id; /* Used as foundry_id only for v9 and used as an alignment field for v8 */
};
typedef struct {
diff --git a/project/ferrum.mk b/project/ferrum.mk
index 2ffb029..e40bfff 100644
--- a/project/ferrum.mk
+++ b/project/ferrum.mk
@@ -15,11 +15,12 @@
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
#DEFINES += CRYPTO_BAM=1
-#DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
-#DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
-#DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
-#DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
+DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
#Disable thumb mode
ENABLE_THUMB := false
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 0b76b89..22793b2 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -48,3 +48,6 @@
ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
DEFINES += PON_VIB_SUPPORT=1
endif
+
+#enable user force reset feature
+DEFINES += USER_FORCE_RESET_SUPPORT=1
diff --git a/project/msm8994.mk b/project/msm8994.mk
index 5f994d2..bf22317 100644
--- a/project/msm8994.mk
+++ b/project/msm8994.mk
@@ -14,6 +14,7 @@
ENABLE_USB30_SUPPORT := 1
USE_DYNAMIC_SMEM := 1
ENABLE_SMD_SUPPORT := 1
+ENABLE_PWM_SUPPORT := true
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/target/init.c b/target/init.c
index 0d99880..4a896e8 100644
--- a/target/init.c
+++ b/target/init.c
@@ -69,6 +69,11 @@
{
}
+__WEAK uint32_t is_user_force_reset(void)
+{
+ return 0;
+}
+
__WEAK int set_download_mode(enum dload_mode mode)
{
return -1;
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index 2a33157..2385d24 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -168,6 +168,23 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
+#if USER_FORCE_RESET_SUPPORT
+/* Return 1 if it is a force resin triggered by user. */
+uint32_t is_user_force_reset(void)
+{
+ uint8_t poff_reason1 = pm8x41_get_pon_poff_reason1();
+ uint8_t poff_reason2 = pm8x41_get_pon_poff_reason2();
+
+ dprintf(SPEW, "poff_reason1: %d\n", poff_reason1);
+ dprintf(SPEW, "poff_reason2: %d\n", poff_reason2);
+ if (pm8x41_get_is_cold_boot() && (poff_reason1 == KPDPWR_AND_RESIN ||
+ poff_reason2 == STAGE3))
+ return 1;
+ else
+ return 0;
+}
+#endif
+
void target_init(void)
{
uint32_t base_addr;
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 7462e31..3dc17df 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -49,6 +49,7 @@
#include "include/panel_otm1283a_720p_video.h"
#include "include/panel_nt35596_1080p_skuk_video.h"
#include "include/panel_sharp_wqxga_dualdsi_video.h"
+#include "include/panel_jdi_fhd_video.h""
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -67,6 +68,7 @@
OTM1283A_720P_VIDEO_PANEL,
NT35596_1080P_VIDEO_PANEL,
SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+JDI_FHD_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -83,6 +85,7 @@
{"otm1283a_720p_video", OTM1283A_720P_VIDEO_PANEL},
{"nt35596_1080p_video", NT35596_1080P_VIDEO_PANEL},
{"sharp_wqxga_dualdsi_video",SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+ {"jdi_fhd_video", JDI_FHD_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -285,6 +288,26 @@
sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
pinfo->mipi.signature = SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE;
break;
+ case JDI_FHD_VIDEO_PANEL:
+ panelstruct->paneldata = &jdi_fhd_video_panel_data;
+ panelstruct->panelres = &jdi_fhd_video_panel_res;
+ panelstruct->color = &jdi_fhd_video_color;
+ panelstruct->videopanel = &jdi_fhd_video_video_panel;
+ panelstruct->commandpanel = &jdi_fhd_video_command_panel;
+ panelstruct->state = &jdi_fhd_video_state;
+ panelstruct->laneconfig = &jdi_fhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_fhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_fhd_video_reset_seq;
+ panelstruct->backlightinfo = &jdi_fhd_video_backlight;
+ pinfo->mipi.panel_cmds
+ = jdi_fhd_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_FHD_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_fhd_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 635dbfa..cfd665f 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -72,6 +72,7 @@
#define FASTBOOT_MODE 0x77665500
#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1)
+#define PMIC_WLED_SLAVE_ID 3
static void set_sdc_power_ctrl(void);
static uint32_t mmc_pwrctl_base[] =
@@ -280,6 +281,10 @@
}
rpm_smd_init();
+
+ /* QPNP WLED init for display backlight */
+ pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
+ qpnp_wled_init();
}
unsigned board_machtype(void)
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index 3d6d853..e098b17 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -18,6 +18,7 @@
MODULES += \
dev/keys \
dev/pmic/pm8x41 \
+ dev/qpnp_wled \
lib/ptable \
lib/libfdt