Merge "platform: msm_shared: Fix cache flush issues"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 07f87e5..f741419 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -88,6 +88,7 @@
#include "board.h"
#include "scm.h"
#include "mdtp.h"
+#include "fastboot_test.h"
extern bool target_use_signed_kernel(void);
extern void platform_uninit(void);
@@ -168,6 +169,7 @@
static char *target_boot_params = NULL;
static bool boot_reason_alarm;
static bool devinfo_present = true;
+bool boot_into_fastboot = false;
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
@@ -372,6 +374,7 @@
cmdline_final = (unsigned char*) malloc((cmdline_len + 4) & (~3));
ASSERT(cmdline_final != NULL);
+ memset((void *)cmdline_final, 0, sizeof(*cmdline_final));
dst = cmdline_final;
/* Save start ptr for debug print */
@@ -659,14 +662,13 @@
}
#endif
- /* Perform target specific cleanup */
- target_uninit();
-
/* Turn off splash screen if enabled */
#if DISPLAY_SPLASH_SCREEN
target_display_shutdown();
#endif
+ /* Perform target specific cleanup */
+ target_uninit();
dprintf(INFO, "booting linux @ %p, ramdisk @ %p (%d), tags/device tree @ %p\n",
entry, ramdisk, ramdisk_size, (void *)tags_phys);
@@ -980,6 +982,9 @@
page_mask = page_size - 1;
}
+ /* ensure commandline is terminated */
+ hdr->cmdline[BOOT_ARGS_SIZE-1] = 0;
+
kernel_actual = ROUND_TO_PAGE(hdr->kernel_size, page_mask);
ramdisk_actual = ROUND_TO_PAGE(hdr->ramdisk_size, page_mask);
@@ -1034,7 +1039,11 @@
device.is_unlocked,
device.is_tampered);
- if(target_use_signed_kernel() && (!device.is_unlocked))
+ /* Change the condition a little bit to include the test framework support.
+ * We would never reach this point if device is in fastboot mode, even if we did
+ * that means we are in test mode, so execute kernel authentication part for the
+ * tests */
+ if((target_use_signed_kernel() && (!device.is_unlocked)) || boot_into_fastboot)
{
offset = imagesize_actual;
if (check_aboot_addr_range_overlap((uint32_t)image_addr + offset, page_size))
@@ -1051,6 +1060,9 @@
}
verify_signed_bootimg((uint32_t)image_addr, imagesize_actual);
+ /* The purpose of our test is done here */
+ if (boot_into_fastboot && auth_kernel_img)
+ return 0;
} else {
second_actual = ROUND_TO_PAGE(hdr->second_size, page_mask);
#ifdef TZ_SAVE_KERNEL_HASH
@@ -1285,6 +1297,9 @@
return -1;
}
+ /* ensure commandline is terminated */
+ hdr->cmdline[BOOT_ARGS_SIZE-1] = 0;
+
/*
* Update the kernel/ramdisk/tags address if the boot image header
* has default values, these default values come from mkbootimg when
@@ -1944,6 +1959,17 @@
return;
}
+ /* Handle overflow if the input image size is greater than
+ * boot image buffer can hold
+ */
+#if VERIFIED_BOOT
+ if ((target_get_max_flash_size() - (image_actual - sig_actual)) < page_size)
+ {
+ fastboot_fail("booimage: size is greater than boot image buffer can hold");
+ return;
+ }
+#endif
+
/* Verify the boot image
* device & page_size are initialized in aboot_init
*/
@@ -2963,8 +2989,8 @@
return 0;
}
- if ((header->width != fb_display->width) || (header->height != fb_display->height)) {
- dprintf(CRITICAL, "Logo config doesn't match with fb config. Fall back default logo\n");
+ if ((header->width > fb_display->width) || (header->height > fb_display->height)) {
+ dprintf(CRITICAL, "Logo config greater than fb config. Fall back default logo\n");
return -1;
}
@@ -3050,8 +3076,8 @@
fbcon_extract_to_screen(header, (base + LOGO_IMG_HEADER_SIZE));
} else { /* 2 Raw BGR data */
- if ((header->width != fb_display->width) || (header->height != fb_display->height)) {
- dprintf(CRITICAL, "Logo config doesn't match with fb config. Fall back default logo\n");
+ if ((header->width > fb_display->width) || (header->height > fb_display->height)) {
+ dprintf(CRITICAL, "Logo config greater than fb config. Fall back default logo\n");
return -1;
}
@@ -3174,6 +3200,9 @@
{"oem enable-charger-screen", cmd_oem_enable_charger_screen},
{"oem disable-charger-screen", cmd_oem_disable_charger_screen},
{"oem select-display-panel", cmd_oem_select_display_panel},
+#if UNITTEST_FW_SUPPORT
+ {"oem run-tests", cmd_oem_runtests},
+#endif
#endif
};
@@ -3215,7 +3244,6 @@
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
- bool boot_into_fastboot = false;
/* Setup page size information for nv storage */
if (target_is_emmc_boot())
diff --git a/app/aboot/fastboot_test.c b/app/aboot/fastboot_test.c
new file mode 100644
index 0000000..5cad0b5
--- /dev/null
+++ b/app/aboot/fastboot_test.c
@@ -0,0 +1,121 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+ * Neither the name of The Linux Foundation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <stdlib.h>
+#include <debug.h>
+#include "devinfo.h"
+#include "fastboot.h"
+#include "fastboot_test.h"
+#include <app/tests.h>
+#include <target.h>
+#include <boot_device.h>
+#if USE_RPMB_FOR_DEVINFO
+#include <rpmb.h>
+#endif
+/* main function that calls into the tests */
+
+extern void ramdump_table_map();
+extern void kauth_test();
+extern int ufs_get_boot_lun();
+extern int ufs_set_boot_lun(uint32_t bootlunid);
+extern int fastboot_init();
+
+void cmd_oem_runtests()
+{
+ dprintf(INFO, "Running LK tests ... \n");
+
+ // Test boot lun enable for UFS
+ if (!platform_boot_dev_isemmc())
+ {
+ int ret = 0;
+ uint32_t set_lun = 0x2, get_lun;
+ ret = ufs_set_boot_lun(set_lun);
+ if (ret == UFS_SUCCESS)
+ {
+ get_lun = ufs_get_boot_lun();
+ if (get_lun == set_lun)
+ {
+ dprintf(INFO, "UFS Boot LUN En TEST: [ PASS ]\n");
+ set_lun = 0x1; // default is 0x1 LUN A, revert back to 0x1
+ ret = ufs_set_boot_lun(set_lun);
+ }
+ else
+ dprintf(INFO, "UFS Boot LUN En TEST: [ FAIL ]\n");
+ }
+ else
+ dprintf(INFO, "UFS Boot LUN En TEST: [ FAIL ]\n");
+ }
+
+
+#if LPAE
+ ramdump_table_map();
+#endif
+
+#if USE_RPMB_FOR_DEVINFO
+ dprintf(INFO, "Running RPMB test case, please make sure RPMB key is provisioned ...\n");
+ struct device_info *write_info = memalign(PAGE_SIZE, 4096);
+ struct device_info *read_info = memalign(PAGE_SIZE, 4096);
+ if((read_device_info_rpmb((void*) read_info, PAGE_SIZE)) < 0)
+ dprintf(INFO, "RPMB READ TEST : [ FAIL ]\n");
+
+ write_info->is_unlocked = !read_info->is_unlocked;
+
+ if((write_device_info_rpmb((void*) write_info, PAGE_SIZE)) < 0)
+ dprintf(INFO, "RPMB WRITE TEST : [ FAIL ]\n");
+
+ if((read_device_info_rpmb((void*) read_info, PAGE_SIZE)) < 0)
+ dprintf(INFO, "RPMB READ TEST : [ FAIL ]\n");
+
+ if (read_info->is_unlocked == write_info->is_unlocked)
+ dprintf(INFO, "RPMB READ/WRITE TEST: [ PASS ]\n");
+ else
+ dprintf(INFO, "RPMB READ/WRITE TEST: [ FAIL ]\n");
+
+ free(read_info);
+ free(write_info);
+#endif
+
+#if VERIFIED_BOOT
+ if (!boot_linux_from_mmc())
+ dprintf(INFO, "Verifid Boot authentication test: [ PASS ]\n");
+ else
+ dprintf(INFO, "Verifid Boot authentication test: [ FAIL ]\n");
+
+ kauth_test();
+#endif
+
+ if (!thread_tests())
+ dprintf(INFO, "Thread Test: [ PASS ]\n");
+ else
+ dprintf(INFO, "Thread Test: [ FAIL ]\n");
+
+ printf_tests();
+
+ fastboot_okay("");
+}
diff --git a/app/aboot/fastboot_test.h b/app/aboot/fastboot_test.h
new file mode 100644
index 0000000..005bfa7
--- /dev/null
+++ b/app/aboot/fastboot_test.h
@@ -0,0 +1,36 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+ * Neither the name of The Linux Foundation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#ifndef __FASTBOOT_TEST_H__
+#define __FASTBOOT_TEST_H__
+#include <sys/types.h>
+extern void ramdump_table_map();
+void cmd_oem_runtests();
+extern int boot_linux_from_mmc();
+#endif
diff --git a/app/aboot/rules.mk b/app/aboot/rules.mk
index 24bca43..09a5152 100644
--- a/app/aboot/rules.mk
+++ b/app/aboot/rules.mk
@@ -11,6 +11,11 @@
$(LOCAL_DIR)/fastboot.o \
$(LOCAL_DIR)/recovery.o
+ifeq ($(ENABLE_UNITTEST_FW), 1)
+OBJS += \
+ $(LOCAL_DIR)/fastboot_test.o
+endif
+
ifeq ($(ENABLE_MDTP_SUPPORT),1)
OBJS += \
$(LOCAL_DIR)/mdtp.o \
diff --git a/app/mmutest/mmu_test.c b/app/mmutest/mmu_test.c
index 849a9e6..27ed628 100644
--- a/app/mmutest/mmu_test.c
+++ b/app/mmutest/mmu_test.c
@@ -29,6 +29,7 @@
#include <sys/types.h>
#include <debug.h>
#include <arch/arm/mmu.h>
+#include <arch/ops.h>
#include <mmu.h>
#include <string.h>
#include <smem.h>
diff --git a/app/mmutest/rules.mk b/app/mmutest/rules.mk
index 78918a1..5094f65 100644
--- a/app/mmutest/rules.mk
+++ b/app/mmutest/rules.mk
@@ -1,6 +1,6 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
-INCLUDES += -I$(LK_TOP_DIR)/platform/msm_shared/include
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
OBJS += \
$(LOCAL_DIR)/mmu_test.o
diff --git a/app/rules.mk b/app/rules.mk
index e564fe0..0c06ce6 100644
--- a/app/rules.mk
+++ b/app/rules.mk
@@ -3,6 +3,11 @@
MODULES += \
lib/openssl
+ifeq ($(ENABLE_UNITTEST_FW), 1)
+MODULES += \
+ app/tests
+endif
+
OBJS += \
$(LOCAL_DIR)/app.o
diff --git a/app/tests/adc_tests.c b/app/tests/adc_tests.c
deleted file mode 100644
index 5f2d511..0000000
--- a/app/tests/adc_tests.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <pm8x41_adc.h>
-#include <debug.h>
-
-void adc_test()
-{
- uint32_t vadc_chan1;
- uint32_t vadc_chan2;
- uint16_t iusb = 3250000;
- uint16_t ibat = 2500000;
- uint16_t batt_id_chan = 49;
- uint16_t vbat_sns_chan = 6;
-
- /*
- * TEST: Read the voltage on batt_id & vbat_sns channels
- */
- vadc_chan1 = pm8x41_adc_channel_read(batt_id_chan);
- dprintf(INFO, "The channel [%ud] voltage is :%ud\n",batt_id_chan, vadc_chan1);
-
- vadc_chan2 = pm8x41_adc_channel_read(vbat_sns_chan);
- dprintf(INFO, "The channel [%ud] voltage is :%ud\n",vbat_sns_chan, vadc_chan2);
-
- /*
- * TEST: Set the IUSB & IBAT max values
- */
-
- if (!pm8x41_iusb_max_config(iusb))
- dprintf(INFO, "Iusb max current is set\n");
-
- if (!pm8x41_ibat_max_config(ibat))
- dprintf(INFO, "Ibat max current is set\n");
-
-}
diff --git a/app/tests/led_tests.c b/app/tests/led_tests.c
deleted file mode 100644
index 11ef9f2..0000000
--- a/app/tests/led_tests.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2011, The Linux Foundation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of The Linux Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include<dev/pm8921_leds.h>
-#include<dev/pm8921.h>
-
-void led_tests()
-{
-uint32_t duty_us, period_us;
-
- /* 50% Duty cycle */
- duty_us = 500000;
- period_us = 1000000;
-
- /* Configure PM8921_ID_LED_0 from PWM2*/
- pm8921_config_led_current(PM8921_ID_LED_0, 2, PWM2, 1);
-
- /* PWM2 for PM8921_ID_LED_0 is LPG 5
- * Configure and enable lpg5
- */
- pm_set_pwm_config(5, duty_us, period_us, &pmic);
- pm_pwm_channel_enable(5, &pmic);
-
- /* Configure and enable lpg0 for panel backlight*/
- pm_set_pwm_config(0, duty_us, period_us, &pmic);
- pm_pwm_channel_enable(0, &pmic);
-
- mdelay(10000);
-
- /* Configure PM8921_ID_LED_1 also from PWM2*/
- pm8921_config_led_current(PM8921_ID_LED_1, 2, PWM2, 1);
- mdelay(10000);
-
- /* Disable PM8921_ID_LED_0 */
- pm8921_config_led_current(PM8921_ID_LED_0, 2, 2, 0);
-
- /* Turn on GPIO 24 through LPG 0
- * Will be reconfigured during display_init
- */
- panel_backlight_on_pwm();
-
- mdelay(10000);
-
- /* Disable PM8921_ID_LED_1 */
- pm8921_config_led_current(PM8921_ID_LED_1, 2, 2, 0);
-}
diff --git a/app/tests/rules.mk b/app/tests/rules.mk
index f8151ac..ec79a7f 100644
--- a/app/tests/rules.mk
+++ b/app/tests/rules.mk
@@ -5,7 +5,9 @@
OBJS += \
$(LOCAL_DIR)/tests.o \
$(LOCAL_DIR)/thread_tests.o \
- $(LOCAL_DIR)/printf_tests.o \
- $(LOCAL_DIR)/i2c_tests.o \
- $(LOCAL_DIR)/adc_tests.o \
+ $(LOCAL_DIR)/printf_tests.o
+
+ifeq ($(VERIFIED_BOOT),1)
+OBJS += \
$(LOCAL_DIR)/kauth_test.o
+endif
diff --git a/dev/gcdb/display/include/panel_byd_1200p_video.h b/dev/gcdb/display/include/panel_byd_1200p_video.h
new file mode 100644
index 0000000..20e0d75
--- /dev/null
+++ b/dev/gcdb/display/include/panel_byd_1200p_video.h
@@ -0,0 +1,1375 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_BYD_1200P_VIDEO_H_
+
+#define _PANEL_BYD_1200P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config byd_1200p_video_panel_data = {
+ "qcom,mdss_dsi_byd_1200p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution byd_1200p_video_panel_res = {
+ 1200, 1920, 96, 64, 16, 0, 4, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info byd_1200p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char byd_1200p_video_on_cmd0 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x8C, 0x8E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd1 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0x23, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd2 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC7, 0x23, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd3 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xFD, 0x5C, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd4 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xFA, 0x14, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd5 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X83, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd6 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X84, 0X11, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd7 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd8 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd9 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd10 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd11 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd12 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd13 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd14 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd15 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd16 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd17 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd18 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd19 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd20 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd21 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd22 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd23 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd24 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd25 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd26 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd27 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd28 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd29 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd30 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd31 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd32 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd33 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd34 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd35 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd36 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd37 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd38 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd39 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd40 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd41 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd42 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd43 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd44 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd45 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd46 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd47 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd48 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd49 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd50 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd51 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd52 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd53 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd54 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd55 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd56 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd57 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd58 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd59 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd60 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd61 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd62 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd63 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd64 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd65 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd66 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd67 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd68 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd69 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd70 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd71 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XA9, 0X4b, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd72 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X83, 0XBB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd73 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X84, 0X22, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd74 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd75 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd76 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd77 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd78 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd79 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd80 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd81 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd82 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd83 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd84 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd85 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd86 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd87 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd88 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd89 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd90 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd91 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd92 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd93 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd94 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd95 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd96 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd97 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd98 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd99 [] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd100[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd101[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd102[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd103[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd104[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd105[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd106[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd107[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd108[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd109[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd110[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd111[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd112[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd113[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd114[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd115[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd116[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd117[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd118[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd119[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd120[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd121[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd122[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd123[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd124[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd125[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd126[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd127[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd128[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd129[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd130[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd131[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd132[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd133[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd134[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd135[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd136[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd137[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd138[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X83, 0XCC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd139[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0X84, 0X33, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd140[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd141[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd142[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd143[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd144[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd145[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd146[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd147[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd148[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd149[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd150[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd151[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd152[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd153[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd154[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd155[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd156[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd157[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd158[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd159[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd160[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd161[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd162[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd163[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd164[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd165[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd166[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd167[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd168[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd169[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd170[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd171[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd172[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd173[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd174[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd175[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd176[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd177[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd178[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd179[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd180[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd181[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd182[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd183[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd184[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd185[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd186[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd187[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd188[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd189[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd190[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd191[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd192[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd193[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd194[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd195[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd196[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd197[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd198[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd199[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd200[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd201[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd202[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd203[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd204[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x11, 0x00, 0xFF, 0xFF,};
+
+static char byd_1200p_video_on_cmd205[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x29, 0x00, 0xFF, 0xFF,
+};
+
+static struct mipi_dsi_cmd byd_1200p_video_on_command[] = {
+ { 0x8 , byd_1200p_video_on_cmd0, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd1, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd2, 0x10},
+ { 0x8 , byd_1200p_video_on_cmd3, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd4, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd5, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd6, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd7, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd8, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd9, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd10, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd11, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd12, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd13, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd14, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd15, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd16, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd17, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd18, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd19, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd20, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd21, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd22, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd23, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd24, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd25, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd26, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd27, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd28, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd29, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd30, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd31, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd32, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd33, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd34, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd35, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd36, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd37, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd38, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd39, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd40, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd41, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd42, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd43, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd44, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd45, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd46, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd47, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd48, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd49, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd50, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd51, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd52, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd53, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd54, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd55, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd56, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd57, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd58, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd59, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd60, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd61, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd62, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd63, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd64, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd65, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd66, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd67, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd68, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd69, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd70, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd71, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd72, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd73, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd74, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd75, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd76, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd77, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd78, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd79, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd80, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd81, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd82, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd83, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd84, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd85, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd86, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd87, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd88, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd89, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd90, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd91, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd92, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd93, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd94, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd95, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd96, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd97, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd98, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd99, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd100, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd101, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd102, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd103, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd104, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd105, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd106, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd107, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd108, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd109, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd110, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd111, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd112, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd113, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd114, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd115, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd116, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd117, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd118, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd119, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd120, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd121, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd122, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd123, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd124, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd125, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd126, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd127, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd128, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd129, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd130, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd131, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd132, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd133, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd134, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd135, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd136, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd137, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd138, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd139, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd140, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd141, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd142, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd143, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd144, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd145, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd146, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd147, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd148, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd149, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd150, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd151, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd152, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd153, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd154, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd155, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd156, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd157, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd158, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd159, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd160, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd161, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd162, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd163, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd164, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd165, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd166, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd167, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd168, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd169, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd170, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd171, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd172, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd173, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd174, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd175, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd176, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd177, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd178, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd179, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd180, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd181, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd182, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd183, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd184, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd185, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd186, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd187, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd188, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd189, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd190, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd191, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd192, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd193, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd194, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd195, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd196, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd197, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd198, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd199, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd200, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd201, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd202, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd203, 0x00},
+ { 0x8 , byd_1200p_video_on_cmd204, 0xca},
+ { 0x8 , byd_1200p_video_on_cmd205, 0x1f},
+};
+
+#define BYD_1200P_VIDEO_ON_COMMAND 206
+
+
+static char byd_1200p_video_off_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char byd_1200p_video_off_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+
+static struct mipi_dsi_cmd byd_1200p_video_off_command[] = {
+ { 0x4 , byd_1200p_video_off_cmd0, 0x0},
+ { 0x4 , byd_1200p_video_off_cmd1, 0x0}
+};
+
+#define BYD_1200P_VIDEO_OFF_COMMAND 2
+
+static struct command_state byd_1200p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info byd_1200p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info byd_1200p_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration byd_1200p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t byd_1200p_video_timings[] = {
+ 0xE6, 0x38, 0x26, 0x00, 0x68, 0x6e, 0x2A, 0x3c, 0x44, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing byd_1200p_video_timing_info = {
+ 0, 4, 0x02, 0x2d
+};
+
+static struct panel_reset_sequence byd_1200p_video_panel_reset_seq = {
+ { 0, 1, 0, }, { 200, 200, 200, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight byd_1200p_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define BYD_1200P_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_BYD_1200P_VIDEO_H_*/
diff --git a/dev/pmic/fgsram/include/pm_fg_sram.h b/dev/pmic/fgsram/include/pm_fg_sram.h
new file mode 100644
index 0000000..a117e0d
--- /dev/null
+++ b/dev/pmic/fgsram/include/pm_fg_sram.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _PM_FG_SRAM_H_
+#define _PM_FG_SRAM_H_
+
+#include <sys/types.h>
+
+#define FG_MEMIF_INT_RT_STS 0x4410
+#define FG_MEMIF_MEM_INTF_CFG 0x4450
+#define FG_MEMIF_MEM_INTF_CTL 0x4451
+#define FG_MEMIF_IMA_CFG 0x4452
+#define FG_MEMIF_IMA_OPERATION_STS 0x4454
+#define FG_MEMIF_IMA_EXCEPTION_STS 0x4455
+#define FG_MEMIF_MEM_INTF_ADDR_LSB 0x4461
+#define FG_MEMIF_MEM_INTF_ADDR_MSB 0x4462
+#define FG_MEMIF_MEM_INTF_WR_DATA0 0x4463
+#define FG_MEMIF_MEM_INTF_WR_DATA1 0x4464
+#define FG_MEMIF_MEM_INTF_WR_DATA2 0x4465
+#define FG_MEMIF_MEM_INTF_WR_DATA3 0x4466
+#define FG_MEMIF_MEM_INTF_RD_DATA0 0x4467
+#define FG_MEMIF_MEM_INTF_RD_DATA1 0x4468
+#define FG_MEMIF_MEM_INTF_RD_DATA2 0x4469
+#define FG_MEMIF_MEM_INTF_RD_DATA3 0x446A
+#define FG_MEMIF_FG_BEAT_COUNT 0x4457
+#define IACS_SLCT BIT(5)
+#define RIF_MEM_ACCESS_REQ BIT(7)
+#define IACS_RDY BIT(1)
+#define IACS_CLR BIT(2)
+#define BEAT_COUNT_MASK 0x0F
+#define FG_MAX_TRY 10
+#define FG_DATA_MASK 0xffffffff
+#define FG_DATA_MAX_LEN 4
+
+int pmi_fg_sram_read(uint32_t addr, uint32_t *data,int sid, uint8_t offset, uint8_t len);
+
+#endif
diff --git a/dev/pmic/fgsram/pm_fg_sram.c b/dev/pmic/fgsram/pm_fg_sram.c
new file mode 100644
index 0000000..fd4cf14
--- /dev/null
+++ b/dev/pmic/fgsram/pm_fg_sram.c
@@ -0,0 +1,157 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <pm_fg_sram.h>
+#include <pm8x41.h>
+#include <pm8x41_hw.h>
+#include <debug.h>
+#include <bits.h>
+#include <platform/timer.h>
+#include <pm_comm.h>
+
+static int fg_check_addr_mask(int sid,uint32_t addr,uint8_t mask,uint8_t set)
+{
+ uint8_t value;
+ int ret = 1;
+ int try = FG_MAX_TRY;
+
+ udelay(30);
+ while(try)
+ {
+ ret = pm_comm_read_byte_mask(sid, addr, mask, &value, 0);
+ if( !ret && (value == set) )
+ goto err;
+
+ udelay(1000);
+ try--;
+ }
+err:
+ return ret;
+}
+
+int pmi_fg_sram_read(uint32_t addr, uint32_t *data,int sid, uint8_t offset, uint8_t len)
+{
+ uint8_t value;
+ int err = 0;
+ uint8_t start_beat_count, end_beat_count;
+
+ if(offset > 3)
+ {
+ dprintf(INFO,"offset beyond the 4 byte boundary\n");
+ goto err;
+ }
+ /* poll to check if fg memif is available */
+ err = fg_check_addr_mask(sid,FG_MEMIF_MEM_INTF_CFG, RIF_MEM_ACCESS_REQ, 0);
+ if(err)
+ {
+ dprintf(INFO,"Failed to get fg sram access\n");
+ goto err;
+ }
+
+ /* enter into ima mode write 8'hA0 */
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CFG, 0xA0, 0);
+ /* ensure single read access 8'h00 */
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CTL, 0x00, 0);
+
+ /* poll ima is ready */
+ err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+ if(err)
+ {
+ dprintf(INFO,"IACS is not ready cannot enter ima mode\n");
+ goto err;
+ }
+
+ /* write lsb address of the requested data */
+ value = addr & 0xff;
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_LSB, value, 0);
+
+ /* write msb address of the requested data */
+ value = (addr >> 8) & 0xff;
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_MSB, value, 0);
+
+ /* poll until transaction is completed */
+ /* poll ima is ready */
+ err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+ if(err)
+ {
+ dprintf(INFO,"IACS is not ready cannot set address\n");
+ goto err;
+ }
+
+ /* read start beat count */
+ pm_comm_read_byte_mask(sid, FG_MEMIF_FG_BEAT_COUNT, BEAT_COUNT_MASK, &start_beat_count, 0);
+ /* read the data */
+ pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA0, &value, 0);
+ *data = value;
+ pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA1, &value, 0);
+ *data |= value << 8;
+ pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA2, &value, 0);
+ *data |= value << 16;
+ pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA3, &value, 0);
+ *data = value << 24;
+
+ /* poll to check there was no error */
+ err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+ if(err)
+ {
+ dprintf(INFO,"IACS is not ready cannot read\n");
+ goto err;
+ }
+
+ pm_comm_read_byte(sid, FG_MEMIF_IMA_EXCEPTION_STS, &value, 0);
+ err = value;
+ if(!err)
+ {
+ *data = ((*data) >> (offset*8)) & (FG_DATA_MASK >> ((FG_DATA_MAX_LEN - len)*8) );
+ pm_comm_read_byte_mask(sid, FG_MEMIF_FG_BEAT_COUNT, BEAT_COUNT_MASK, &end_beat_count, 0);
+ if(start_beat_count != end_beat_count)
+ err = 1;
+ }
+ else
+ {
+ /* error occured */
+ /*perform iacs clear sequence 1'b1 */
+ pm_comm_read_byte(sid, FG_MEMIF_IMA_CFG, &value, 0);
+ value |= IACS_CLR;
+ pm_comm_write_byte(sid, FG_MEMIF_IMA_CFG, value, 0);
+ /* 8'h04 */
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_MSB, 0x04, 0);
+ /* 8'h00 */
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_WR_DATA3, 0x00, 0);
+ pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA3, &value, 0);
+ /*perform iacs clear sequence 1'b0 */
+ pm_comm_read_byte(sid, FG_MEMIF_IMA_CFG, &value, 0);
+ value &= ~(IACS_CLR);
+ pm_comm_write_byte(sid, FG_MEMIF_IMA_CFG, value, 0);
+ }
+
+err:
+ pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CFG, 0x00, 0);
+
+ return err;
+
+}
diff --git a/dev/pmic/fgsram/rules.mk b/dev/pmic/fgsram/rules.mk
new file mode 100644
index 0000000..261c99a
--- /dev/null
+++ b/dev/pmic/fgsram/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+$(LOCAL_DIR)/pm_fg_sram.o
diff --git a/dev/pmic/pmi8994/pm_app_smbchg.c b/dev/pmic/pmi8994/pm_app_smbchg.c
index 4b9693b..c3a03be 100644
--- a/dev/pmic/pmi8994/pm_app_smbchg.c
+++ b/dev/pmic/pmi8994/pm_app_smbchg.c
@@ -46,6 +46,9 @@
#include <sys/types.h>
#include <target.h>
#include <pm8x41.h>
+#include <bits.h>
+#include <board.h>
+#include <smem.h>
/*===========================================================================
@@ -80,13 +83,15 @@
static bool display_initialized;
static bool charge_in_progress;
static bool display_shutdown_in_prgs;
+static bool pm_app_read_from_sram;
char panel_name[256];
pm_err_flag_type pm_smbchg_get_charger_path(uint32 device_index, pm_smbchg_usb_chgpth_pwr_pth_type* charger_path);
pm_err_flag_type pm_appsbl_chg_config_vbat_low_threshold(uint32 device_index, pm_smbchg_specific_data_type *chg_param_ptr);
static void display_thread_initialize();
-
+static void pm_app_ima_read_voltage(uint32_t *);
+static void pm_app_pmi8994_read_voltage(uint32_t *voltage);
/*===========================================================================
FUNCTION IMPLEMENTATION
@@ -179,6 +184,20 @@
err_flag |= pm_fg_adc_usr_get_calibrated_vbat(device_index, &vbat_adc); //Read calibrated vbatt ADC
if ( err_flag != PM_ERR_FLAG__SUCCESS ) { break;}
+ /* FG_ADC hardware reports values that are off by ~120 to 200 mV, this results in boot up failures
+ * on devices that boot up with battery close to threshold value. If the FG_ADC voltage is less than
+ * threshold then read the voltage from a more accurate source FG SRAM to ascertain the voltage is indeed low.
+ */
+ if (!pm_app_read_from_sram && (vbat_adc <= bootup_threshold))
+ {
+ if (board_pmic_type(PMIC_IS_PMI8996))
+ pm_app_ima_read_voltage(&vbat_adc);
+ else
+ pm_app_pmi8994_read_voltage(&vbat_adc);
+
+ pm_app_read_from_sram = true;
+ }
+
//Check if ADC reading is within limit
if ( vbat_adc >= bootup_threshold) //Compaire it with SW bootup threshold
{
@@ -674,3 +693,160 @@
is_thread_start = true;
}
}
+
+static void pm_app_wait_for_iacs_ready(uint32_t sid)
+{
+ uint8_t iacs;
+ int max_retry = 100;
+
+ udelay(50);
+ pm_comm_read_byte(sid, 0x4454, &iacs, 0);
+ while ((iacs & 0x02) == 0)
+ {
+ max_retry--;
+ pm_comm_read_byte(2, 0x4454, &iacs, 0);
+ mdelay(5);
+ if (!max_retry)
+ {
+ dprintf(CRITICAL, "Error: IACS not ready, shutting down\n");
+ shutdown_device();
+ }
+ }
+}
+
+static int pm_app_check_for_ima_exception(uint32_t sid)
+{
+ uint8_t ima_err_sts;
+ uint8_t ima_exception_sts;
+
+ pm_comm_read_byte(sid, 0x445f, &ima_err_sts, 0);
+ pm_comm_read_byte(sid, 0x4455, &ima_exception_sts, 0);
+
+ if (ima_err_sts != 0 || (ima_exception_sts & 0x1) == 1)
+ {
+ uint8_t ima_hw_sts;
+ pm_comm_read_byte(sid, 0x4456, &ima_hw_sts, 0);
+ dprintf(CRITICAL, "ima_err_sts: %x\tima_exception_sts:%x\tima_hw_sts:%x\n", ima_err_sts, ima_exception_sts, ima_hw_sts);
+ return 1;
+ }
+
+ return 0;
+}
+
+static void pm_app_ima_read_voltage(uint32_t *voltage)
+{
+ uint8_t start_beat_count;
+ uint8_t end_beat_count;
+ uint8_t vbat;
+ uint64_t vbat_adc = 0;
+ uint32_t sid = 2; //sid for pmi8996
+ int max_retry = 5;
+
+retry:
+ //Request IMA access
+ pm_comm_write_byte(sid, 0x4450, 0xA0, 0);
+ // Single read configure
+ pm_comm_write_byte(sid, 0x4451, 0x00, 0);
+
+ pm_app_wait_for_iacs_ready(sid);
+
+ //configure SRAM access
+ pm_comm_write_byte(sid, 0x4461, 0xCC, 0);
+ pm_comm_write_byte(sid, 0x4462, 0x05, 0);
+
+ pm_app_wait_for_iacs_ready(sid);
+
+ pm_comm_read_byte(sid, 0x4457, &start_beat_count, 0);
+
+ //Read the voltage
+ pm_comm_read_byte(sid, 0x4467, &vbat, 0);
+ vbat_adc = vbat;
+ pm_comm_read_byte(sid, 0x4468, &vbat, 0);
+ vbat_adc |= (vbat << 8);
+ pm_comm_read_byte(sid, 0x4469, &vbat, 0);
+ vbat_adc |= (vbat << 16);
+ pm_comm_read_byte(sid, 0x446A, &vbat, 0);
+ vbat_adc |= (vbat << 24);
+
+ pm_app_wait_for_iacs_ready(sid);
+
+ //Look for any errors
+ if(pm_app_check_for_ima_exception(sid))
+ goto err;
+
+ pm_comm_read_byte(sid, 0x4457, &end_beat_count, 0);
+
+ if (start_beat_count != end_beat_count)
+ {
+ max_retry--;
+ if (!max_retry)
+ goto err;
+ goto retry;
+ }
+
+ //Release the ima access
+ pm_comm_write_byte(2, 0x4450, 0x00, 0);
+
+ //extract the byte1 & byte2 and convert to mv
+ vbat_adc = ((vbat_adc & 0x00ffff00) >> 8) * 152587;
+ *voltage = vbat_adc / 1000000;
+ return;
+
+err:
+ dprintf(CRITICAL, "Failed to Read the Voltage from IMA, shutting down\n");
+ shutdown_device();
+}
+
+static void pm_app_pmi8994_read_voltage(uint32_t *voltage)
+{
+ uint8_t val = 0;
+ uint8_t vbat;
+ uint64_t vbat_adc = 0;
+ uint32_t sid = 2; //sid for pmi8994
+ int max_retry = 100;
+
+ pm_comm_read_byte(sid, 0x4440, &val, 0);
+
+ //Request for FG access
+ if ((val & BIT(7)) != 1)
+ pm_comm_write_byte(sid, 0x4440, 0x80, 0);
+
+ pm_comm_read_byte(sid, 0x4410, &val, 0);
+ while((val & 0x1) == 0)
+ {
+ //sleep and retry again, this takes up to 1.5 seconds
+ max_retry--;
+ mdelay(100);
+ pm_comm_read_byte(sid, 0x4410, &val, 0);
+ if (!max_retry)
+ {
+ dprintf(CRITICAL, "Error: Failed to read from Fuel Guage, Shutting down\n");
+ shutdown_device();
+ }
+ }
+
+ //configure single read access
+ pm_comm_write_byte(sid, 0x4441, 0x00, 0);
+ //configure SRAM for voltage shadow
+ pm_comm_write_byte(sid, 0x4442, 0xCC, 0);
+ pm_comm_write_byte(sid, 0x4443, 0x05, 0);
+
+ //Read voltage from SRAM
+ pm_comm_read_byte(sid, 0x444c, &vbat, 0);
+ vbat_adc = vbat;
+ pm_comm_read_byte(sid, 0x444d, &vbat, 0);
+ vbat_adc |= (vbat << 8);
+ pm_comm_read_byte(sid, 0x444e, &vbat, 0);
+ vbat_adc |= (vbat << 16);
+ pm_comm_read_byte(sid, 0x444f, &vbat, 0);
+ vbat_adc |= (vbat << 24);
+
+ //clean up to relase sram access
+ pm_comm_write_byte(sid, 0x4440, 0x00, 0);
+ //extract byte 1 & byte 2
+ vbat_adc = ((vbat_adc & 0x00ffff00) >> 8) * 152587;
+
+ //convert the voltage to mv
+ *voltage = vbat_adc / 1000000;
+}
+
diff --git a/include/platform.h b/include/platform.h
index 9c8e698..156097e 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -66,10 +66,11 @@
int platform_is_msm8909();
int platform_is_msm8992();
int platform_is_msm8956();
+uint32_t platform_is_msm8976_v_1_1();
int boot_device_mask(int);
uint32_t platform_detect_panel();
uint32_t platform_get_max_periph();
int platform_is_msm8996();
-uint64_t platform_get_ddr_start();
bool platform_use_qmp_misc_settings();
+bool platform_is_mdmcalifornium();
#endif
diff --git a/include/target.h b/include/target.h
index f2e2acd..e05613b 100644
--- a/include/target.h
+++ b/include/target.h
@@ -24,6 +24,7 @@
*/
#ifndef __TARGET_H
#define __TARGET_H
+#include <qmp_phy.h>
/* Target helper functions exposed to USB driver */
typedef struct {
@@ -88,6 +89,9 @@
bool target_build_variant_user();
void pmic_reset_configure(uint8_t reset_type);
+struct qmp_reg *target_get_qmp_settings();
+int target_get_qmp_regsize();
+
#if PON_VIB_SUPPORT
uint32_t get_vibration_type();
#endif
diff --git a/platform/mdm9640/acpuclock.c b/platform/mdm9640/acpuclock.c
index 40827eb..99fd7d0 100644
--- a/platform/mdm9640/acpuclock.c
+++ b/platform/mdm9640/acpuclock.c
@@ -35,6 +35,7 @@
#include <platform/clock.h>
#include <platform/iomap.h>
#include <platform/timer.h>
+#include <platform.h>
void clock_config_uart_dm(uint8_t id)
{
@@ -92,7 +93,11 @@
ASSERT(0);
}
- ret = clk_get_set_enable("usb30_pipe_clk", 19200000, 1);
+ if (platform_is_mdmcalifornium())
+ ret = clk_get_set_enable("usb30_pipe_clk_mdmcalifornium", 0, 1);
+ else
+ ret = clk_get_set_enable("usb30_pipe_clk", 19200000, 1);
+
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
@@ -106,6 +111,20 @@
ASSERT(0);
}
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
if(ret)
{
@@ -169,12 +188,85 @@
void clock_bumpup_pipe3_clk()
{
- int ret = 0;
+ int ret =0;
- ret = clk_get_set_enable("usb30_pipe_clk", 125000000, 0);
+ if (platform_is_mdmcalifornium())
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+ else
+ ret = clk_get_set_enable("usb30_pipe_clk", 125000000, true);
+
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
ASSERT(0);
}
}
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+ struct clk *master_clk = NULL;
+
+ master_clk = clk_get("usb30_master_clk");
+ ASSERT(master_clk);
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+ return;
+ }
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ goto deassert_master_clk;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+deassert_master_clk:
+
+ ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+ return;
+ }
+
+}
diff --git a/platform/mdm9640/include/platform/clock.h b/platform/mdm9640/include/platform/clock.h
index e450661..7fdf8a7 100644
--- a/platform/mdm9640/include/platform/clock.h
+++ b/platform/mdm9640/include/platform/clock.h
@@ -35,5 +35,6 @@
void platform_clock_init(void);
void clock_config_uart_dm(uint8_t id);
void clock_usb30_init(void);
+void clock_reset_usb_phy();
#endif
diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
index f92f556..2a21206 100644
--- a/platform/mdm9640/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -170,9 +170,16 @@
#define USB3_AUX_D (CLK_CTL_BASE + 0x5E06C)
#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x5E044)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x5E008)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x5E004)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x5E020)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x5E024)
+
/* USB 3.0 phy */
#define USB3_PHY_BCR (CLK_CTL_BASE + 0x0005E034)
+#define USB_30_BCR (CLK_CTL_BASE + 0x0005E070)
+
/* QUSB2 PHY */
#define QUSB2_PHY_BASE 0x00079000
#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00041028)
@@ -197,5 +204,17 @@
#define APCS_ALIAS0_IPC_INTERRUPT 0xB011008
/* eMMC Display */
#define TLMM_EBI2_EMMC_GPIO_CFG 0x01111000
+
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994)
+
#define EBI2_BOOT_SELECT 0x2
+#define GCC_RX2_USB2_CLKREF_EN 0x01841030
+#define USB3_PHY_STATUS 0x78974
+/* Register for finding out if single ended or differential clock enablement */
+#define TCSR_PHY_CLK_SCHEME_SEL 0x01956044
+
#endif
diff --git a/platform/mdm9640/mdm9640-clock.c b/platform/mdm9640/mdm9640-clock.c
index f6b85fb..0d4c26f 100644
--- a/platform/mdm9640/mdm9640-clock.c
+++ b/platform/mdm9640/mdm9640-clock.c
@@ -276,10 +276,10 @@
},
};
-
static struct branch_clk gcc_usb30_master_clk =
{
.cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
.parent = &usb30_master_clk_src.c,
.c = {
@@ -319,6 +319,19 @@
},
};
+
+static struct branch_clk gcc_usb30_pipe_clk_mdmcalifornium = {
+ .bcr_reg = (uint32_t *) USB3_PIPE_BCR,
+ .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
+ .has_sibling = 1,
+ .halt_check = 0,
+
+ .c = {
+ .dbg_name = "usb30_pipe_clk_mdmcalifornium",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
F( 1000000, cxo, 1, 5, 96),
F_END
@@ -369,6 +382,47 @@
},
};
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
+
static struct clk_lookup msm_clocks_9640[] =
{
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
@@ -380,12 +434,15 @@
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk_mdmcalifornium", gcc_usb30_pipe_clk_mdmcalifornium.c),
CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/mdm9640/platform.c b/platform/mdm9640/platform.c
index 6ccbe19..f69053c 100644
--- a/platform/mdm9640/platform.c
+++ b/platform/mdm9640/platform.c
@@ -156,14 +156,45 @@
return phys_addr;
}
+
+bool platform_is_mdmcalifornium()
+{
+ uint32_t platform_id = board_platform_id();
+ bool ret;
+
+ switch(platform_id)
+ {
+ case MDMCALIFORNIUM1:
+ case MDMCALIFORNIUM2:
+ case MDMCALIFORNIUM3:
+ case MDMCALIFORNIUM4:
+ ret = true;
+ break;
+ default:
+ ret = false;
+ };
+
+ return ret;
+}
+
uint32_t platform_boot_config()
{
uint32_t boot_config;
- if (board_soc_version() >= 0x20000)
+ if (platform_is_mdmcalifornium())
+ boot_config = BOOT_CONFIG_REG_V2;
+ /* Else the platform is 9x45 */
+ else if (board_soc_version() >= 0x20000)
boot_config = BOOT_CONFIG_REG_V2;
else
boot_config = BOOT_CONFIG_REG_V1;
return boot_config;
}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
+
diff --git a/platform/mdmfermium/acpuclock.c b/platform/mdmfermium/acpuclock.c
index 7463222..bd068ad 100644
--- a/platform/mdmfermium/acpuclock.c
+++ b/platform/mdmfermium/acpuclock.c
@@ -37,11 +37,81 @@
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 133330000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ mdelay(20);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ mdelay(20);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ mdelay(20);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ mdelay(20);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
diff --git a/platform/mdmfermium/gpio.c b/platform/mdmfermium/gpio.c
index fba2c76..6f9bc3c 100644
--- a/platform/mdmfermium/gpio.c
+++ b/platform/mdmfermium/gpio.c
@@ -68,10 +68,10 @@
void gpio_config_uart_dm(uint8_t id)
{
/* configure rx gpio */
- gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(9, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio */
- gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ gpio_tlmm_config(8, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
diff --git a/platform/mdmfermium/include/platform/iomap.h b/platform/mdmfermium/include/platform/iomap.h
index 852e5a9..205cd19 100644
--- a/platform/mdmfermium/include/platform/iomap.h
+++ b/platform/mdmfermium/include/platform/iomap.h
@@ -64,6 +64,7 @@
#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x000B3000)
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000D9000)
#define CLK_CTL_BASE 0x1800000
@@ -87,18 +88,18 @@
/* GPLL */
-#define GPLL0_STATUS (CLK_CTL_BASE + 0x21024)
+#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
+#define BLSP1_UART5_APPS_CBCR (CLK_CTL_BASE + 0x603c)
+#define BLSP1_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0x6044)
+#define BLSP1_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0x6048)
+#define BLSP1_UART5_APPS_M (CLK_CTL_BASE + 0x604C)
+#define BLSP1_UART5_APPS_N (CLK_CTL_BASE + 0x6050)
+#define BLSP1_UART5_APPS_D (CLK_CTL_BASE + 0x6054)
/* USB */
#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
diff --git a/platform/mdmfermium/mdmfermium-clock.c b/platform/mdmfermium/mdmfermium-clock.c
index 235d40f..35fbd27 100644
--- a/platform/mdmfermium/mdmfermium-clock.c
+++ b/platform/mdmfermium/mdmfermium-clock.c
@@ -100,8 +100,8 @@
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
.en_mask = BIT(0),
- .status_reg = (void *) GPLL0_STATUS,
- .status_mask = BIT(17),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
.parent = &cxo_clk_src.c,
.c = {
@@ -112,7 +112,7 @@
};
/* UART Clocks */
-static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart5_apps_clk[] =
{
F( 3686400, gpll0, 1, 72, 15625),
F( 7372800, gpll0, 1, 144, 15625),
@@ -132,16 +132,16 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp1_uart5_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP1_UART5_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART5_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART5_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART5_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART5_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart5_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -150,13 +150,13 @@
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp1_uart5_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP1_UART5_APPS_CBCR,
+ .parent = &blsp1_uart5_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp1_uart5_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -219,8 +219,8 @@
/* Clock lookup table */
static struct clk_lookup mdm_clocks_fermium[] =
{
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart5_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart5_core_clk", gcc_blsp1_uart5_apps_clk.c),
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
diff --git a/platform/msm8952/acpuclock.c b/platform/msm8952/acpuclock.c
index e3aaec3..ec37789 100644
--- a/platform/msm8952/acpuclock.c
+++ b/platform/msm8952/acpuclock.c
@@ -132,7 +132,12 @@
}
else if(freq == MMC_CLK_192MHZ)
{
- ret = clk_get_set_enable(clk_name, 192000000, 1);
+ if (platform_is_msm8956() && platform_is_msm8976_v_1_1())
+
+ ret = clk_get_set_enable(clk_name, 186400000, 1);
+ else
+
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
}
else if(freq == MMC_CLK_200MHZ)
{
@@ -140,7 +145,12 @@
}
else if(freq == MMC_CLK_400MHZ)
{
- ret = clk_get_set_enable(clk_name, 384000000, 1);
+ if (platform_is_msm8956() && platform_is_msm8976_v_1_1())
+
+ ret = clk_get_set_enable(clk_name, 372800000, 1);
+ else
+
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
}
else
{
@@ -312,16 +322,28 @@
}
/* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint32_t flags, uint8_t pclk0_m,
+void gcc_dsi_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
+ int dsi0_cfg_rcgr, dsi1_cfg_rcgr = 0;
+
+ dsi0_cfg_rcgr = BIT(8); /* DSI0 can only be sourced from PLL0 */
+
+ /*
+ * DSI1<->PLL1 for 1.) 8956 v1.0 always 2.) Single DSI cases on DSI1
+ * DSI1<->PLL0 for 8956 v1.1 split DSI cases
+ */
+ if (!platform_is_msm8976_v_1_1() || use_dsi1_pll)
+ dsi1_cfg_rcgr = BIT(8);
+ else if (flags == (MMSS_DSI_CLKS_FLAG_DSI0 | MMSS_DSI_CLKS_FLAG_DSI1))
+ dsi1_cfg_rcgr = BIT(8) | BIT(9);
if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
/* Enable DSI0 branch clocks */
/* Set the source for DSI0 byte RCG */
- writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(dsi0_cfg_rcgr, DSI_BYTE0_CFG_RCGR);
/* Set the update RCG bit */
writel(0x1, DSI_BYTE0_CMD_RCGR);
rcg_update_config(DSI_BYTE0_CMD_RCGR);
@@ -331,7 +353,7 @@
/* Configure Pixel clock */
/* Set the source for DSI0 pixel RCG */
- writel(0x100, DSI_PIXEL0_CFG_RCGR);
+ writel(dsi0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
/* Set the MND for DSI0 pixel clock */
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
@@ -355,7 +377,7 @@
/* Enable DSI1 branch clocks */
/* Set the source for DSI1 byte RCG */
- writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(dsi1_cfg_rcgr, DSI_BYTE1_CFG_RCGR);
/* Set the update RCG bit */
writel(0x1, DSI_BYTE1_CMD_RCGR);
rcg_update_config(DSI_BYTE1_CMD_RCGR);
@@ -365,7 +387,7 @@
/* Configure Pixel clock */
/* Set the source for DSI1 pixel RCG */
- writel(0x100, DSI_PIXEL1_CFG_RCGR);
+ writel(dsi1_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
/* Set the MND for DSI1 pixel clock */
writel(pclk0_m, DSI_PIXEL1_M);
writel(pclk0_n, DSI_PIXEL1_N);
diff --git a/platform/msm8952/include/platform/clock.h b/platform/msm8952/include/platform/clock.h
index f6e962a..c9e8cc7 100644
--- a/platform/msm8952/include/platform/clock.h
+++ b/platform/msm8952/include/platform/clock.h
@@ -95,7 +95,7 @@
void mdss_bus_clocks_disable(void);
void mdp_clock_enable(void);
void mdp_clock_disable(void);
-void gcc_dsi_clocks_enable(uint32_t flags, uint8_t pclk0_m,
+void gcc_dsi_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
uint8_t pclk0_n, uint8_t pclk0_d);
void gcc_dsi_clocks_disable(uint32_t flags);
#endif
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index 6a568db..2bf5d7e 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -98,6 +98,7 @@
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
+#define GPLL2_STATUS (CLK_CTL_BASE + 0x4A01C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
diff --git a/platform/msm8952/msm8952-clock.c b/platform/msm8952/msm8952-clock.c
index b87406d..3214895 100644
--- a/platform/msm8952/msm8952-clock.c
+++ b/platform/msm8952/msm8952-clock.c
@@ -39,6 +39,7 @@
/* Mux source select values */
#define cxo_source_val 0
#define gpll0_source_val 1
+#define gpll2_source_val 4
#define gpll4_source_val 2
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 6
@@ -112,6 +113,21 @@
},
};
+static struct pll_vote_clk gpll2_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(2),
+ .status_reg = (void *) GPLL2_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 932000000,
+ .dbg_name = "gpll2_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
static struct pll_vote_clk gpll4_clk_src =
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
@@ -157,6 +173,21 @@
F_END
};
+/* SDCC Clocks for version 8976 v 1.1*/
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_8976_v_1_1[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 10, 1, 4),
+ F( 25000000, gpll0, 16, 1, 2),
+ F( 50000000, gpll0, 16, 0, 0),
+ F(100000000, gpll0, 8, 0, 0),
+ F(177770000, gpll0, 4.5, 0, 0),
+ F(186400000, gpll2, 5, 0, 0),
+ F(372800000, gpll2, 2.5, 0, 0),
+ F_END
+};
+
static struct rcg_clk sdcc1_apps_clk_src =
{
.cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
@@ -594,9 +625,18 @@
mdss_mdp_clk_src.freq_tbl = ftbl_mdp_clk_8956;
}
+void msm8976_v_1_1_sdcc_clock_modify()
+{
+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_8976_v_1_1;
+}
+
void platform_clock_init(void)
{
- if (platform_is_msm8956())
+ if (platform_is_msm8956()) {
msm8956_clock_override();
+ if (platform_is_msm8976_v_1_1())
+ /*freq and GPLL change for 8976 v1.1 */
+ msm8976_v_1_1_sdcc_clock_modify();
+ }
clk_init(msm_clocks_8952, ARRAY_SIZE(msm_clocks_8952));
}
diff --git a/platform/msm8952/platform.c b/platform/msm8952/platform.c
index ec5a1d8..8adaf4c 100644
--- a/platform/msm8952/platform.c
+++ b/platform/msm8952/platform.c
@@ -41,6 +41,7 @@
#include <platform.h>
#include <target/display.h>
+#define MSM8976_SOC_V11 0x10001
#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
#define APPS_SS_SIZE ((APPS_SS_END - APPS_SS_BASE)/MB)
@@ -194,3 +195,14 @@
return ret;
}
+
+uint32_t platform_is_msm8976_v_1_1()
+{
+ uint32_t soc_ver = board_soc_version();
+ uint32_t ret = 0;
+
+ if(soc_ver == MSM8976_SOC_V11)
+ ret = 1;
+
+ return ret;
+}
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index d3ba81a..de4616b 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -80,6 +80,7 @@
#define AHB2_PHY_BASE 0x7416000
#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
+#define GCC_RX2_USB2_CLKREF_EN 0x00388014
/* Clocks */
#define CLK_CTL_BASE 0x300000
@@ -194,7 +195,7 @@
* as device memory, define the start address
* and size in MB
*/
-#define RPMB_SND_RCV_BUF 0x91400000
+#define RPMB_SND_RCV_BUF 0x91A00000
#define RPMB_SND_RCV_BUF_SZ 0x2
#define TCSR_BOOT_MISC_DETECT 0x007B3000
@@ -543,9 +544,4 @@
#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
-#define DDR_START platform_get_ddr_start()
-#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
-#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2200000
-#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x2000000
-#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
#endif
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index 08c0025..79bf7c9 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -68,25 +68,17 @@
/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
{ 0x00000000, 0x00000000, MMU_L2_NS_SECTION_MAPPING, 512, IOMAP_MEMORY},
{ MEMBASE, MEMBASE, MMU_L2_NS_SECTION_MAPPING, (MEMSIZE / MB), LK_MEMORY},
+ { KERNEL_ADDR, KERNEL_ADDR, MMU_L2_NS_SECTION_MAPPING, KERNEL_SIZE, SCRATCH_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, MMU_L2_NS_SECTION_MAPPING, SCRATCH_SIZE, SCRATCH_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, MMU_L2_NS_SECTION_MAPPING, MSM_SHARED_SIZE, COMMON_MEMORY},
{ RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, MMU_L2_NS_SECTION_MAPPING, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
-static mmu_section_t default_mmu_section_table_3gb[] =
-{
-/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
- { 0x40000000, 0x40000000, MMU_L1_NS_SECTION_MAPPING, 1024 , COMMON_MEMORY},
- { 0x80000000, 0x80000000, MMU_L2_NS_SECTION_MAPPING, 88 , COMMON_MEMORY},
-};
-
-
/* Map the ddr for download mode, this region belongs to non-hlos images and pil */
static mmu_section_t dload_mmu_section_table[] =
{
/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
- { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 8, DLOAD_MEMORY},
- { 0x86200000, 0x86200000, MMU_L2_NS_SECTION_MAPPING, 174, DLOAD_MEMORY},
+ { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 189, DLOAD_MEMORY},
};
void platform_early_init(void)
@@ -123,52 +115,11 @@
{
int i;
int table_sz = ARRAY_SIZE(default_mmu_section_table);
- mmu_section_t kernel_mmu_section_table;
- uint64_t ddr_size = smem_get_ddr_size();
- uint32_t kernel_size = 0;
-
- if (ddr_size == MEM_4GB)
- {
- ddr_start = 0x80000000;
- /* As per the memory map when DDR is 4GB first 88 MB is hlos memory
- * use this for loading the kernel
- */
- kernel_size = 88;
- }
- else if (ddr_size == MEM_3GB)
- {
- ddr_start = 0x20000000;
- /* As per memory map wheh DDR is 3GB the first 512 MB is assigned to hlos
- * use this region for loading kernel
- */
- kernel_size = 512;
- }
- else
- {
- dprintf(CRITICAL, "Unsupported memory map\n");
- ASSERT(0);
- }
-
- kernel_mmu_section_table.paddress = ddr_start;
- kernel_mmu_section_table.vaddress = ddr_start;
- kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
- kernel_mmu_section_table.size = kernel_size;
- kernel_mmu_section_table.flags = SCRATCH_MEMORY;
-
- /* Map kernel entry */
- arm_mmu_map_entry(&kernel_mmu_section_table);
/* Map default memory needed for lk , scratch, rpmb & iomap */
for (i = 0 ; i < table_sz; i++)
arm_mmu_map_entry(&default_mmu_section_table[i]);
- /* Map the rest of the DDR for 3GB needed for ramdump */
- if (ddr_size == MEM_3GB)
- {
- for (i = 0 ; i < (int)ARRAY_SIZE(default_mmu_section_table_3gb); i++)
- arm_mmu_map_entry(&default_mmu_section_table_3gb[i]);
- }
-
if (scm_device_enter_dload())
{
/* TZ & Hyp memory can be mapped only while entering the download mode */
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 1265f29..8839a8a 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -400,6 +400,21 @@
return 0;
}
+bool board_pmic_type(uint32_t type)
+{
+ uint8_t i;
+ if (format_major == 0x0 && format_minor >= 0x0B)
+ {
+ for (i = 0; i < SMEM_MAX_PMIC_DEVICES; i++)
+ {
+ if (type == (board.pmic_info_array[i].pmic_type & 0x0000ffff))
+ return true;
+ }
+ }
+
+ return false;
+}
+
uint32_t board_pmic_target(uint8_t num_ent)
{
if (format_major == 0x0 && num_ent < SMEM_MAX_PMIC_DEVICES)
diff --git a/platform/msm_shared/boot_verifier.c b/platform/msm_shared/boot_verifier.c
index 67f28c3..b167d70 100644
--- a/platform/msm_shared/boot_verifier.c
+++ b/platform/msm_shared/boot_verifier.c
@@ -42,11 +42,11 @@
#define ASN1_ENCODED_SHA256_SIZE 0x33
#define ASN1_ENCODED_SHA256_OFFSET 0x13
+#define ASN1_SIGNATURE_BUFFER_SZ mmc_page_size()
static KEYSTORE *oem_keystore;
static KEYSTORE *user_keystore;
static uint32_t dev_boot_state = RED;
-BUF_DMA_ALIGN(keystore_buf, 4096);
char KEYSTORE_PTN_NAME[] = "keystore";
static const char *VERIFIED_FLASH_ALLOWED_PTN[] = {
@@ -118,18 +118,38 @@
len_bytes = (input[pos] & ~(0x80));
pos++;
}
+
while(len_bytes)
{
- /* Shift len by 1 octet */
- len = len << 8;
+ /* Shift len by 1 octet, make sure to check unsigned int overflow */
+ if (len <= (UINT_MAX >> 8))
+ len <<= 8;
+ else
+ {
+ dprintf(CRITICAL, "Error: Length exceeding max size of uintmax\n");
+ return 0;
+ }
/* Read next octet */
- len = len | input[pos];
+ if (pos < (int) ASN1_SIGNATURE_BUFFER_SZ)
+ len = len | input[pos];
+ else
+ {
+ dprintf(CRITICAL, "Error: Pos index exceeding the input buffer size\n");
+ return 0;
+ }
+
pos++; len_bytes--;
}
/* Add number of octets representing sequence id and length */
- len += pos;
+ if ((UINT_MAX - pos) > len)
+ len += pos;
+ else
+ {
+ dprintf(CRITICAL, "Error: Len overflows UINT_MAX value\n");
+ return 0;
+ }
return len;
}
@@ -301,19 +321,12 @@
static void read_oem_keystore()
{
KEYSTORE *ks = NULL;
- uint32_t len = 0;
+ uint32_t len = sizeof(OEM_KEYSTORE);
const unsigned char *input = OEM_KEYSTORE;
if(oem_keystore != NULL)
return;
- len = read_der_message_length((unsigned char *)input);
- if(!len)
- {
- dprintf(CRITICAL, "boot_verifier: oem keystore length is invalid.\n");
- return;
- }
-
ks = d2i_KEYSTORE(NULL, (const unsigned char **) &input, len);
if(ks != NULL)
{
@@ -322,7 +335,7 @@
}
}
-static int read_user_keystore_ptn()
+static int read_user_keystore_ptn(uint8_t *keystore_buf)
{
int index = INVALID_PTN;
unsigned long long ptn = 0;
@@ -346,12 +359,19 @@
unsigned char *input = user_addr;
KEYSTORE *ks = NULL;
uint32_t len = read_der_message_length(input);
+
if(!len)
{
dprintf(CRITICAL, "boot_verifier: user keystore length is invalid.\n");
return;
}
+ if (len > ASN1_SIGNATURE_BUFFER_SZ)
+ {
+ dprintf(CRITICAL, "boot_verifier: user keystore exceeds size signature buffer\n");
+ return;
+ }
+
ks = d2i_KEYSTORE(NULL, (const unsigned char **)&input, len);
if(ks != NULL)
{
@@ -372,11 +392,16 @@
uint32_t boot_verify_keystore_init()
{
+ uint8_t *keystore_buf = NULL;
+
/* Read OEM Keystore */
read_oem_keystore();
+ keystore_buf = memalign(ASN1_SIGNATURE_BUFFER_SZ, CACHE_LINE);
+ ASSERT(keystore_buf);
+
/* Read User Keystore */
- if(!read_user_keystore_ptn())
+ if(!read_user_keystore_ptn(keystore_buf))
read_user_keystore((unsigned char *)keystore_buf);
return dev_boot_state;
}
@@ -386,7 +411,8 @@
bool ret = false;
VERIFIED_BOOT_SIG *sig = NULL;
unsigned char* sig_addr = (unsigned char*)(img_addr + img_size);
- uint32_t sig_len = read_der_message_length(sig_addr);
+ uint32_t sig_len = 0;
+ unsigned char *signature = NULL;
if(dev_boot_state == ORANGE)
{
@@ -395,12 +421,25 @@
return false;
}
+ signature = malloc(ASN1_SIGNATURE_BUFFER_SZ);
+ ASSERT(signature);
+
+ /* Copy the signature from scratch memory to buffer */
+ memcpy(signature, sig_addr, ASN1_SIGNATURE_BUFFER_SZ);
+ sig_len = read_der_message_length(signature);
+
if(!sig_len)
{
dprintf(CRITICAL, "boot_verifier: Error while reading singature length.\n");
goto verify_image_error;
}
+ if (sig_len > ASN1_SIGNATURE_BUFFER_SZ)
+ {
+ dprintf(CRITICAL, "boot_verifier: Signature length exceeds size signature buffer\n");
+ goto verify_image_error;
+ }
+
if((sig = d2i_VERIFIED_BOOT_SIG(NULL, (const unsigned char **) &sig_addr, sig_len)) == NULL)
{
dprintf(CRITICAL,
@@ -411,6 +450,7 @@
ret = verify_image_with_sig(img_addr, img_size, pname, sig, user_keystore);
verify_image_error:
+ free(signature);
if(sig != NULL)
VERIFIED_BOOT_SIG_free(sig);
if(!ret)
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index ad088cb..50042f2 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_pll.h>
#include <clock_lib2.h>
-
+#include <platform/timer.h>
/*=============== CXO clock ops =============*/
int cxo_clk_enable(struct clk *clk)
@@ -55,14 +55,32 @@
{
int rc = 0;
uint32_t cbcr_val;
+ int retry = 100;
struct branch_clk *bclk = to_branch_clk(clk);
cbcr_val = readl(bclk->cbcr_reg);
cbcr_val |= CBCR_BRANCH_ENABLE_BIT;
writel(cbcr_val, bclk->cbcr_reg);
+ /* Some clocks do not need to check the enable status, return
+ * if the halt_check is not set
+ */
+ if (!bclk->halt_check)
+ return rc;
+
/* wait until status shows it is enabled */
- while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT);
+ while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT)
+ {
+ /* Add 100 ms of time out, bail out if the clock is not enable
+ * within 100 ms */
+ if (!retry)
+ {
+ rc = 1;
+ break;
+ }
+ retry--;
+ mdelay(1);
+ }
return rc;
}
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
index f83ee93..c6d651d 100644
--- a/platform/msm_shared/dme.c
+++ b/platform/msm_shared/dme.c
@@ -96,7 +96,7 @@
}
if (resp_upiu->basic_hdr.response != UPIU_QUERY_RESP_SUCCESS)
{
- dprintf(CRITICAL, "%s:%d UPIU Response is not SUCCESS\n", __func__, __LINE__);
+ dprintf(CRITICAL, "%s:%d UPIU Response is not SUCCESS, response code: 0x%x\n", __func__, __LINE__, resp_upiu->basic_hdr.response);
return -UFS_FAILURE;
}
@@ -111,8 +111,9 @@
return -UFS_FAILURE;
}
- *((uint32_t *) buffer) = resp_upiu->flag_value;
+ *((uint32_t *) buffer) = resp_upiu->resv_1[3]; //resv_1[3] contains the data for flag
break;
+ case UPIU_QUERY_OP_WRITE_ATTRIBUTE:
case UPIU_QUERY_OP_TOGGLE_FLAG:
case UPIU_QUERY_OP_CLEAR_FLAG:
case UPIU_QUERY_OP_READ_DESCRIPTOR:
@@ -149,6 +150,9 @@
req_upiu.resp_data_len = query->buf_len;
}
+ if (query->opcode == UPIU_QUERY_OP_WRITE_ATTRIBUTE)
+ req_upiu.data_buffer_addr = query->buf; // attribute is 4 byte value
+
ret = utp_enqueue_upiu(dev, &req_upiu);
if (ret)
goto utp_send_query_upiu_err;
@@ -161,6 +165,47 @@
return ret;
}
+int dme_set_bbootlunen(struct ufs_dev *dev, uint32_t val)
+{
+ int ret = 0;
+ STACKBUF_DMA_ALIGN(value, sizeof(uint32_t));
+ memset((void *)value, 0, sizeof(uint32_t));
+ *value = val;
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_WRITE_ATTRIBUTE,
+ UFS_IDX_bBootLunEn,
+ 0,
+ 0,
+ (addr_t)value,
+ sizeof(uint32_t)};
+ if ((ret = dme_send_query_upiu(dev, &set_query)))
+ {
+ arch_invalidate_cache_range((addr_t) value, sizeof(uint32_t));
+ dprintf(CRITICAL, "%s:%d DME Set Boot Lun Query failed. Value 0x%x\n", __func__, __LINE__, *value);
+ return -UFS_FAILURE;
+ }
+ return UFS_SUCCESS;
+}
+
+int dme_get_bbootlunen(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(value, sizeof(uint32_t));
+ memset((void *)value, 0, sizeof(uint32_t));
+ int ret = 0;
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_READ_ATTRIBUTE,
+ UFS_IDX_bBootLunEn,
+ 0,
+ 0,
+ (addr_t)value,
+ sizeof(uint32_t)};
+ if ((ret = dme_send_query_upiu(dev, &set_query)))
+ {
+ dprintf(CRITICAL, "%s:%d DME Set Boot Lun Query failed\n", __func__, __LINE__);
+ return -UFS_FAILURE;
+ }
+ arch_invalidate_cache_range((addr_t) value, sizeof(uint32_t));
+ return *value;
+}
+
int dme_set_fpurgeenable(struct ufs_dev *dev)
{
STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
@@ -551,6 +596,7 @@
req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_READ_REQ;
break;
case UPIU_QUERY_OP_TOGGLE_FLAG:
+ case UPIU_QUERY_OP_WRITE_ATTRIBUTE:
case UPIU_QUERY_OP_CLEAR_FLAG:
case UPIU_QUERY_OP_SET_FLAG:
req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_WRITE_REQ;
@@ -559,6 +605,13 @@
dprintf(CRITICAL, "%s:%d UPIU query opcode not supported.\n", __func__, __LINE__);
return -UFS_FAILURE;
}
+ if (upiu_data->opcode == UPIU_QUERY_OP_WRITE_ATTRIBUTE)
+ {
+ req_upiu->resv_1[0] = (*(uint32_t *)(upiu_data->data_buffer_addr) >> 24);
+ req_upiu->resv_1[1] = (*(uint32_t *)(upiu_data->data_buffer_addr) >> 16);
+ req_upiu->resv_1[2] = (*(uint32_t *)(upiu_data->data_buffer_addr) >> 8);
+ req_upiu->resv_1[3] = (*(uint32_t *)(upiu_data->data_buffer_addr) & 0xFF);
+ }
return UFS_SUCCESS;
}
diff --git a/platform/msm_shared/include/board.h b/platform/msm_shared/include/board.h
index 4d4c7a9..9a5db02 100644
--- a/platform/msm_shared/include/board.h
+++ b/platform/msm_shared/include/board.h
@@ -90,5 +90,5 @@
uint32_t board_foundry_id(void);
void board_update_boot_dev(uint32_t);
-
+bool board_pmic_type(uint32_t type);
#endif
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
index aa11c54..4930024 100644
--- a/platform/msm_shared/include/dme.h
+++ b/platform/msm_shared/include/dme.h
@@ -73,6 +73,7 @@
#define UFS_IDX_bBootLunEn 0x00
#define UFS_IDX_bCurrentPowerMode 0x01
#define UFS_IDX_bActiveICCLevel 0x03
+#define UFS_IDX_bBootLunID 0x04
#define UFS_IDX_bPurgeStatus 0x06
#define UFS_IDX_bRefClkFreq 0x0a
#define UFS_IDX_bConfigDescrLock 0x0b
@@ -268,4 +269,9 @@
*/
int dme_read_geo_desc(struct ufs_dev *dev);
+/* function to return the boot lun currently booting from */
+int dme_get_bbootlunen(struct ufs_dev *dev);
+
+/* function to set the boot lun to either 0, 1 or 2 */
+int dme_set_bbootlunen(struct ufs_dev *dev, uint32_t val);
#endif
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 54f09ee..5461b49 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -215,7 +215,7 @@
({ \
uint32_t indx = (start) / (size_of); \
uint32_t offset = (start) % (size_of); \
- uint32_t mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
+ unsigned long long mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
uint32_t unpck = array[indx] >> offset; \
uint32_t indx2 = ((start) + (len) - 1) / (size_of); \
if(indx2 > indx) \
diff --git a/platform/msm_shared/include/mmc_wrapper.h b/platform/msm_shared/include/mmc_wrapper.h
index f52a117..fbae494 100644
--- a/platform/msm_shared/include/mmc_wrapper.h
+++ b/platform/msm_shared/include/mmc_wrapper.h
@@ -49,4 +49,6 @@
uint8_t mmc_get_lun(void);
void mmc_read_partition_table(uint8_t arg);
uint32_t mmc_write_protect(const char *name, int set_clr);
+int ufs_set_boot_lun(uint32_t boot_lun_id);
+int ufs_get_boot_lun();
#endif
diff --git a/platform/msm_shared/include/qusb2_phy.h b/platform/msm_shared/include/qusb2_phy.h
index 1d5199a..d3ed338 100644
--- a/platform/msm_shared/include/qusb2_phy.h
+++ b/platform/msm_shared/include/qusb2_phy.h
@@ -32,8 +32,11 @@
void qusb2_phy_reset(void);
+#define QUSB2PHY_PLL_LOCK 0x20
+
#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PLL_TEST (QUSB2_PHY_BASE + 0x00000004)
#define QUSB2PHY_PLL_TUNE (QUSB2_PHY_BASE + 0x00000008)
#define QUSB2PHY_PLL_USER_CTL1 (QUSB2_PHY_BASE + 0x0000000C)
#define QUSB2PHY_PLL_USER_CTL2 (QUSB2_PHY_BASE + 0x00000010)
@@ -42,6 +45,9 @@
#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
#define QUSB2PHY_PORT_TEST2 (QUSB2_PHY_BASE + 0x0000009C)
+#define QUSB2PHY_PLL_PWR_CTL (QUSB2_PHY_BASE + 0x00000018)
+#define QUSB2PHY_PLL_AUTOPGM_CTL1 (QUSB2_PHY_BASE + 0x0000001C)
+#define QUSB2PHY_PLL_STATUS (QUSB2_PHY_BASE + 0x00000038)
#endif
diff --git a/platform/msm_shared/include/upiu.h b/platform/msm_shared/include/upiu.h
index e081909..2c8fee5 100644
--- a/platform/msm_shared/include/upiu.h
+++ b/platform/msm_shared/include/upiu.h
@@ -74,8 +74,8 @@
uint8_t selector;
uint8_t resv_0[2];
uint16_t resp_len;
- uint8_t resv_1[3];
- uint8_t flag_value;
+ // this structure is used for several queries. resv_1 field is reserved for some and used for others
+ uint8_t resv_1[4];
uint8_t resv_2[4];
}__PACKED;
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 0474f37..d336f8b 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -837,7 +837,7 @@
}
writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL);
- if (pinfo->mipi.broadcast)
+ if (pinfo->mipi.dual_dsi)
writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL);
return NO_ERROR;
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 20eb840..7e88b63 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -233,15 +233,22 @@
memcpy((struct mmc_csd *)&card->csd,(struct mmc_csd *)&mmc_csd,
sizeof(struct mmc_csd));
- /* Calculate the wp grp size */
- if (card->ext_csd[MMC_ERASE_GRP_DEF])
- card->wp_grp_size = MMC_HC_ERASE_MULT * card->ext_csd[MMC_HC_ERASE_GRP_SIZE] / MMC_BLK_SZ;
- else
- card->wp_grp_size = (card->csd.wp_grp_size + 1) * (card->csd.erase_grp_size + 1) \
- * (card->csd.erase_grp_mult + 1);
+ if (MMC_CARD_MMC(card)) {
- card->rpmb_size = RPMB_PART_MIN_SIZE * card->ext_csd[RPMB_SIZE_MULT];
- card->rel_wr_count = card->ext_csd[REL_WR_SEC_C];
+ /* Calculate the wp grp size */
+ if (card->ext_csd[MMC_ERASE_GRP_DEF])
+ card->wp_grp_size = MMC_HC_ERASE_MULT * card->ext_csd[MMC_HC_ERASE_GRP_SIZE] / MMC_BLK_SZ;
+ else
+ card->wp_grp_size = (card->csd.wp_grp_size + 1) * (card->csd.erase_grp_size + 1) \
+ * (card->csd.erase_grp_mult + 1);
+
+ card->rpmb_size = RPMB_PART_MIN_SIZE * card->ext_csd[RPMB_SIZE_MULT];
+ card->rel_wr_count = card->ext_csd[REL_WR_SEC_C];
+ }
+ else {
+ card->wp_grp_size = (card->csd.wp_grp_size + 1) * (card->csd.erase_grp_size + 1) \
+ * (card->csd.erase_grp_mult + 1);
+ }
dprintf(SPEW, "Decoded CSD fields:\n");
dprintf(SPEW, "cmmc_structure: %u\n", mmc_csd.cmmc_structure);
@@ -766,7 +773,6 @@
ret = mmc_switch_cmd(host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, value);
if (!ret)
drv_type_changed = true;
-
return drv_type_changed;
}
/*
@@ -1355,11 +1361,13 @@
for (i = 15, j = 0; i >=0 ; i--, j++)
sd_status[i] = swap_endian32(sd_status[j]);
- au_size = UNPACK_BITS(status, MMC_SD_AU_SIZE_BIT, MMC_SD_AU_SIZE_LEN, 32);
+ au_size = UNPACK_BITS(status, MMC_SD_AU_SIZE_BIT, MMC_SD_AU_SIZE_LEN, 4);
/* Card AU size in sectors */
card->ssr.au_size = 1 << (au_size + 4);
- card->ssr.num_aus = UNPACK_BITS(status, MMC_SD_ERASE_SIZE_BIT, MMC_SD_ERASE_SIZE_LEN, 32);
-
+ card->ssr.num_aus = UNPACK_BITS(status, MMC_SD_ERASE_SIZE_BIT, MMC_SD_ERASE_SIZE_LEN, 16);
+ /*if num_aus is 0 then host should assign number of AU erased at a time*/
+ if (!card->ssr.num_aus)
+ card->ssr.num_aus = 0x10;
return 0;
}
@@ -1671,18 +1679,20 @@
card->block_size = MMC_BLK_SZ;
- /* Enable RST_n_FUNCTION */
- if (!card->ext_csd[MMC_EXT_CSD_RST_N_FUNC])
- {
- mmc_return = mmc_switch_cmd(host, card, MMC_SET_BIT, MMC_EXT_CSD_RST_N_FUNC, RST_N_FUNC_ENABLE);
-
- if (mmc_return)
+ if (MMC_CARD_MMC(card)) {
+ /* Enable RST_n_FUNCTION */
+ if (!card->ext_csd[MMC_EXT_CSD_RST_N_FUNC])
{
- dprintf(CRITICAL, "Failed to enable RST_n_FUNCTION\n");
- return mmc_return;
- }
- }
+ mmc_return = mmc_switch_cmd(host, card, MMC_SET_BIT, MMC_EXT_CSD_RST_N_FUNC, RST_N_FUNC_ENABLE);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failed to enable RST_n_FUNCTION\n");
+ return mmc_return;
+ }
+ }
+
+ }
return mmc_return;
}
@@ -2178,7 +2188,10 @@
* As per emmc 4.5 spec section 7.4.27, calculate the erase timeout
* erase_timeout = 300ms * ERASE_TIMEOUT_MULT * num_erase_grps
*/
- erase_timeout = ((uint64_t)300 * 1000 * card->ext_csd[MMC_ERASE_TIMEOUT_MULT] * num_erase_grps);
+ if (MMC_CARD_MMC(card))
+ erase_timeout = ((uint64_t)300 * 1000 * card->ext_csd[MMC_ERASE_TIMEOUT_MULT] * num_erase_grps);
+ else
+ erase_timeout = ((uint64_t)300 * 1000 * num_erase_grps);
/* Send CMD38 to perform erase */
if (mmc_send_erase(dev, erase_timeout))
@@ -2359,15 +2372,17 @@
dprintf(CRITICAL, "card deselect error: %s\n", __func__);
return;
}
+ if(MMC_CARD_MMC(card)){
+ /*CMD5 is reserved in SD card */
+ cmd.cmd_index = CMD5_SLEEP_AWAKE;
+ cmd.argument = (card->rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1B;
- cmd.cmd_index = CMD5_SLEEP_AWAKE;
- cmd.argument = (card->rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP;
- cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
- cmd.resp_type = SDHCI_CMD_RESP_R1B;
-
- /* send command */
- if(sdhci_send_command(&dev->host, &cmd))
- dprintf(CRITICAL, "card sleep error: %s\n", __func__);
+ /* send command */
+ if(sdhci_send_command(&dev->host, &cmd))
+ dprintf(CRITICAL, "card sleep error: %s\n", __func__);
+ }
}
/*
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 10e9955..495767a 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -534,6 +534,41 @@
}
/*
+ * Function : ufs_get_boot_lun
+ * Arg : none
+ * Return type : current boot lun
+ */
+
+int ufs_get_boot_lun()
+{
+ int ret = 0;
+ void *dev;
+ dev = target_mmc_device();
+
+ if (!(platform_boot_dev_isemmc()))
+ ret = dme_get_bbootlunen((struct ufs_dev *)dev);
+ return ret;
+}
+
+
+/*
+ * Function : ufs_set_boot_lun
+ * Arg : boot lun id
+ * Return type : status
+ */
+
+int ufs_set_boot_lun(uint32_t boot_lun_id)
+{
+ int ret = 0;
+ void *dev;
+ dev = target_mmc_device();
+
+ if (!(platform_boot_dev_isemmc()))
+ ret = dme_set_bbootlunen((struct ufs_dev *)dev, boot_lun_id);
+ return ret;
+}
+
+/*
* Function : mmc set LUN for ufs
* Arg : LUN number
* Return type : void
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index 91aed89..a558cea 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -37,6 +37,7 @@
#include <debug.h>
#include <qtimer.h>
#include <platform.h>
+#include <target.h>
#define HS_PHY_COMMON_CTRL 0xEC
#define USE_CORECLK BIT(14)
@@ -107,7 +108,7 @@
{0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
{0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
{0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */
- {0x518, 0x1b}, /* QSERDES_RX_SIGDET_LVL */
+ {0x518, 0x18}, /* QSERDES_RX_SIGDET_LVL */
{0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
/* Tx settings */
@@ -135,6 +136,7 @@
struct qmp_reg qmp_misc_settings_rev2[] =
{
{0x178, 0x01}, /* QSERDES_COM_HSCLK_SEL */
+ {0x518, 0x1B}, /* QSERDES_RX_SIGDET_LVL */
{0xC4, 0x15}, /* USB3PHY_QSERDES_COM_RESCODE_DIV_NUM */
{0x1B8, 0x1F}, /* QSERDES_COM_CMN_MISC2 */
};
@@ -255,12 +257,30 @@
void usb30_qmp_phy_init()
{
int timeout = QMP_PHY_MAX_TIMEOUT;
- uint32_t rev_id = 0;
uint32_t phy_status = 0;
uint32_t qmp_reg_size;
uint32_t i;
- rev_id = platform_get_qmp_rev();
+
+#if USE_TARGET_QMP_SETTINGS
+ struct qmp_reg *target_qmp_settings = NULL;
+ qmp_reg_size = target_get_qmp_regsize();
+ target_qmp_settings = target_get_qmp_settings();
+ if (qmp_reg_size && target_qmp_settings)
+ {
+ for (i = 0 ; i < qmp_reg_size; i++)
+ {
+ /* As per the hw document we need to add a delay of 1 ms after setting
+ * QSERDES_COM_RESETSM_CNTRL2 and before setting QSERDES_COM_CMN_CONFIG */
+ if (i == 7)
+ mdelay(1);
+ writel(target_qmp_settings[i].val, QMP_PHY_BASE + target_qmp_settings[i].off);
+ }
+ goto phy_status;
+ }
+#endif
+
+ uint32_t rev_id = platform_get_qmp_rev();
/* Sequence as per HPG */
writel(0x01, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_DOWN_CONTROL);
@@ -341,12 +361,25 @@
writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
}
- if (rev_id >= 0x20000000)
- phy_status = 0x77c;
- else
- phy_status = 0x728;
+#if USE_TARGET_QMP_SETTINGS
+phy_status:
+#endif
- while ((readl(QMP_PHY_BASE + phy_status) & PHYSTATUS))
+ /* For future targets defined USB3_PHY_STATUS in the iomap.h
+ * Initial version of driver was written thinking phy_status register
+ * address would not change, but the address keeps changing for every chip
+ * so better get the address from iomap amd keep the backward compatibility
+ */
+#if USB3_PHY_STATUS
+ phy_status = USB3_PHY_STATUS;
+#else
+ if (rev_id >= 0x20000000)
+ phy_status = QMP_PHY_BASE + 0x77c;
+ else
+ phy_status = QMP_PHY_BASE + 0x728;
+#endif
+
+ while ((readl(phy_status) & PHYSTATUS))
{
udelay(1);
timeout--;
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index c39d584..d2b6044 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -77,6 +77,7 @@
{0x9590DC2C, 0x56, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x40, 0},
{0x1590aa98, 0x76, 0xFFFFFFFF, 0x0, 0x10000000, 0, 2048, 0x00020000, 0x80, 1},
{0x2690A32C, 0x64, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
+ {0x2690AC98, 0x81676, 0xFFFFFFFF, 0x0, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
diff --git a/platform/msm_shared/qseecom_lk.c b/platform/msm_shared/qseecom_lk.c
index 0c9077b..8543e97 100644
--- a/platform/msm_shared/qseecom_lk.c
+++ b/platform/msm_shared/qseecom_lk.c
@@ -850,6 +850,7 @@
struct qseecom_client_send_data_ireq send_data_req;
struct qseecom_command_scm_resp resp;
void *buf = NULL;
+ void *rsp_buf_temp = NULL;
uint32_t size = 0;
if (req->cmd_req_buf == NULL || req->resp_buf == NULL) {
@@ -859,10 +860,19 @@
}
dprintf(SPEW, "%s called\n", __func__);
- /* Allocate for req or rsp len whichever is higher, both req and rsp point
- * to the same buffer
- */
- size = (req->cmd_req_len > req->resp_len) ? req->cmd_req_len : req->resp_len;
+ if (req->cmd_req_len > (UINT_MAX - req->resp_len)) {
+ dprintf(CRITICAL, "%s:Integer overflow\n", __func__);
+ dprintf(CRITICAL, "req->cmd_req_len: %u\n", req->cmd_req_len);
+ dprintf(CRITICAL, "req->resp_len: %u\n", req->resp_len);
+ return GENERIC_ERROR;
+ }
+
+ if ((req->cmd_req_len + req->resp_len) > (RPMB_SND_RCV_BUF_SZ * 1024 * 1024)) {
+ dprintf(CRITICAL, "%s:Cmd + Rsp len greater than TA buf\n", __func__);
+ dprintf(CRITICAL, "req->cmd_req_len: %u\n", req->cmd_req_len);
+ dprintf(CRITICAL, "req->resp_len: %u\n", req->resp_len);
+ return GENERIC_ERROR;
+ }
/* The req rsp buffer will be xPU protected by TZ during a TZ APP call
* This will still be protected during a listener call and there is a
@@ -878,8 +888,6 @@
return GENERIC_ERROR;
}
- memscpy(buf, ROUNDUP(size, PAGE_SIZE), req->cmd_req_buf, req->cmd_req_len);
-
send_data_req.qsee_cmd_id = QSEE_CLIENT_SEND_DATA_COMMAND;
send_data_req.app_id = app_id;
@@ -888,14 +896,20 @@
*/
send_data_req.req_ptr = (uint32_t)__qseecom_uvirt_to_kphys((uint32_t) buf);
send_data_req.req_len = req->cmd_req_len;
- send_data_req.rsp_ptr = (uint32_t)__qseecom_uvirt_to_kphys((uint32_t) buf);
+ size = ROUNDUP(req->cmd_req_len, PAGE_SIZE);
+ rsp_buf_temp = (uint8_t *)buf + size;
+ send_data_req.rsp_ptr = (uint32_t)__qseecom_uvirt_to_kphys((uint32_t)rsp_buf_temp);
send_data_req.rsp_len = req->resp_len;
+ memscpy(buf, (RPMB_SND_RCV_BUF_SZ * 1024 * 1024), req->cmd_req_buf, req->cmd_req_len);
+ memscpy(rsp_buf_temp, req->resp_len, req->resp_buf, req->resp_len);
+
ret = qseecom_scm_call(SCM_SVC_TZSCHEDULER, 1,
(void *)&send_data_req,
sizeof(send_data_req), (void *)&resp, sizeof(resp));
- memscpy(req->resp_buf, req->resp_len, (void *)send_data_req.rsp_ptr, send_data_req.rsp_len);
+ memscpy(req->cmd_req_buf, req->cmd_req_len, (void *)buf, send_data_req.req_len);
+ memscpy(req->resp_buf, req->resp_len, (void *)rsp_buf_temp, send_data_req.rsp_len);
return ret;
}
@@ -941,6 +955,16 @@
__func__, ret);
goto err;
}
+ dprintf(DEBUG, "Loading cmnlib done\n");
+#if ENABLE_CMNLIB64_LOADING
+ ret = qseecom_load_commonlib_image("cmnlib64");
+ if (ret) {
+ dprintf(CRITICAL, "%s qseecom_load_commonlib_image failed with status:%d\n",
+ __func__, ret);
+ goto err;
+ }
+ dprintf(DEBUG, "Loading cmnlib64 done\n");
+#endif
qseecom.cmnlib_loaded = 1;
}
/* Check if App already exits, if exits increase ref_cnt
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 871bbcc..ced1fea 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -32,6 +32,7 @@
#include <bits.h>
#include <debug.h>
#include <qtimer.h>
+#include <platform.h>
__WEAK int platform_is_msm8994()
{
@@ -43,12 +44,24 @@
return 0;
}
+__WEAK int platform_is_mdmcalifornium()
+{
+ return 0;
+}
+
void qusb2_phy_reset(void)
{
uint32_t val;
/* Default tune value */
uint8_t tune2 = 0xB3;
+ int retry = 100;
+ int se_clock = 1;
+ /* Disable the ref clock before phy reset */
+#if GCC_RX2_USB2_CLKREF_EN
+ writel((readl(GCC_RX2_USB2_CLKREF_EN) & ~0x1), GCC_RX2_USB2_CLKREF_EN);
+ dmb();
+#endif
/* Block Reset */
val = readl(GCC_QUSB2_PHY_BCR) | BIT(0);
writel(val, GCC_QUSB2_PHY_BCR);
@@ -62,7 +75,7 @@
/* set CLAMP_N_EN and stay with disabled USB PHY */
writel(0x23, QUSB2PHY_PORT_POWERDOWN);
- if (platform_is_msm8996())
+ if (platform_is_msm8996() || platform_is_mdmcalifornium())
{
writel(0xF8, QUSB2PHY_PORT_TUNE1);
/* Upper nibble of tune2 register should be updated based on the fuse value.
@@ -77,12 +90,27 @@
tune2 = (tune2 & 0x0f) | (fuse_val << 4);
#endif
writel(tune2, QUSB2PHY_PORT_TUNE2);
- writel(0x93, QUSB2PHY_PORT_TUNE3);
+ writel(0x83, QUSB2PHY_PORT_TUNE3);
writel(0xC0, QUSB2PHY_PORT_TUNE4);
writel(0x30, QUSB2PHY_PLL_TUNE);
writel(0x79, QUSB2PHY_PLL_USER_CTL1);
writel(0x21, QUSB2PHY_PLL_USER_CTL2);
writel(0x14, QUSB2PHY_PORT_TEST2);
+ /* TCSR register bit 0 indicates whether single ended clock
+ * or differential clock configuration is enabled. Based on the
+ * configuration set the PLL_TEST register.
+ */
+#if TCSR_PHY_CLK_SCHEME_SEL
+ se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
+#endif
+ /* By default consider differential clock configuration and if TCSR
+ * register bit 0 is not set then use single ended setting
+ */
+ if (se_clock)
+ writel(0x80, QUSB2PHY_PLL_TEST);
+
+ writel(0x9F, QUSB2PHY_PLL_AUTOPGM_CTL1);
+ writel(0x00, QUSB2PHY_PLL_PWR_CTL);
}
else
{
@@ -102,12 +130,28 @@
/* Wait for tuning params to take effect right before re-enabling power*/
udelay(10);
- /* Disable the PHY */
- writel(0x23, QUSB2PHY_PORT_POWERDOWN);
/* Enable ULPI mode */
if (platform_is_msm8994())
writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2);
/* Enable PHY */
/* set CLAMP_N_EN and USB PHY is enabled*/
writel(0x22, QUSB2PHY_PORT_POWERDOWN);
+ mdelay(10);
+
+#if GCC_RX2_USB2_CLKREF_EN
+ writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN);
+ dmb();
+#endif
+
+ /* Check PLL status */
+ while (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK))
+ {
+ retry--;
+ udelay(100);
+ if (!retry)
+ {
+ dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS));
+ break;
+ }
+ }
}
diff --git a/platform/msm_shared/reboot.c b/platform/msm_shared/reboot.c
index 8f53633..6d97b0c 100644
--- a/platform/msm_shared/reboot.c
+++ b/platform/msm_shared/reboot.c
@@ -71,12 +71,13 @@
uint8_t hard_restart_reason = 0;
/* Read reboot reason and scrub it
- * Bit-5, bit-6 and bit-7 of SOFT_RB_SPARE for hard reset reason
+ * Bit-2 to bit-7 of SOFT_RB_SPARE for hard reset reason
*/
hard_restart_reason = REG_READ(PON_SOFT_RB_SPARE);
- REG_WRITE(PON_SOFT_RB_SPARE, hard_restart_reason & 0x1f);
+ REG_WRITE(PON_SOFT_RB_SPARE, hard_restart_reason & 0x03);
- return hard_restart_reason;
+ /* Extract the bits 5 to 7 and return */
+ return hard_restart_reason & 0xFC;
}
/* Return true if it is triggered by alarm. */
diff --git a/platform/msm_shared/shutdown_detect.c b/platform/msm_shared/shutdown_detect.c
index b7410eb..9bde63d 100644
--- a/platform/msm_shared/shutdown_detect.c
+++ b/platform/msm_shared/shutdown_detect.c
@@ -32,6 +32,7 @@
#include <pm8x41.h>
#include <pm8x41_hw.h>
#include <kernel/timer.h>
+#include <kernel/thread.h>
#include <platform/timer.h>
#include <shutdown_detect.h>
#include <platform.h>
@@ -130,6 +131,7 @@
timer_cancel(&pon_timer);
break;
}
+ thread_sleep(1);
}
}
@@ -150,7 +152,10 @@
* Initialize pon_timer and call long_press_pwrkey_timer_func
* function to check if the power key is last press long enough.
*/
- if (is_pwrkey_pon_reason() && is_pwrkey_time_expired()) {
+ if (is_pwrkey_pon_reason()) {
+ if(!pm8x41_get_pwrkey_is_pressed()){
+ shutdown_device();
+ }
timer_initialize(&pon_timer);
timer_set_oneshot(&pon_timer, 0,(timer_callback)long_press_pwrkey_timer_func, NULL);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index a342f86..312a33d 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -136,6 +136,8 @@
PMIC_IS_PM8019 = 3,
PMIC_IS_PM8026 = 4,
PMIC_IS_PM8110 = 5,
+ PMIC_IS_PMI8994 = 10,
+ PMIC_IS_PMI8996 = 19,
} pm_model_type_bfly;
struct smem_board_info_v3 {
@@ -433,7 +435,11 @@
MDMCALIFORNIUM4 = 285,
MDMCALIFORNIUM5 = 286,
APQ8052 = 289,
- MDMFERMIUM = 290,
+ MDMFERMIUM1 = 290,
+ MDMFERMIUM2 = 296,
+ MDMFERMIUM3 = 297,
+ MDMFERMIUM4 = 298,
+ MDMFERMIUM5 = 299,
APQ8096 = 291,
MSMTITANIUM = 293,
};
diff --git a/project/mdm9640.mk b/project/mdm9640.mk
index 24addd8..2aa002a 100644
--- a/project/mdm9640.mk
+++ b/project/mdm9640.mk
@@ -45,5 +45,9 @@
DEFINES += SMD_SUPPORT=1
endif
+# Reset USB clock from target code
+DEFINES += USB_RESET_FROM_CLK=1
+
# Turn on Werror
CFLAGS += -Werror
+DEFINES += USE_TARGET_QMP_SETTINGS=1
diff --git a/project/mdmfermium.mk b/project/mdmfermium.mk
index 8a7b5f5..96de0cb 100644
--- a/project/mdmfermium.mk
+++ b/project/mdmfermium.mk
@@ -17,6 +17,7 @@
DEFINES += DEVICE_TREE=1
DEFINES += CONTIGUOUS_MEMORY=1
+DEFINES += SPMI_CORE_V2=1
DEFINES += BAM_V170=1
#Disable thumb mode
ENABLE_THUMB := false
diff --git a/project/msm8952.mk b/project/msm8952.mk
index 54d4fa8..7fbfae6 100644
--- a/project/msm8952.mk
+++ b/project/msm8952.mk
@@ -64,8 +64,6 @@
ifeq ($(ENABLE_MDTP_SUPPORT),1)
DEFINES += MDTP_SUPPORT=1
-DEFINES += MDTP_EFUSE_ADDRESS=0x0005C250 # QFPROM_CORR_QC_SPARE_REG_LSB_ADDR
-DEFINES += MDTP_EFUSE_START=0
endif
ENABLE_WDOG_SUPPORT := 0
diff --git a/project/msm8996.mk b/project/msm8996.mk
index f0e618a..586922a 100644
--- a/project/msm8996.mk
+++ b/project/msm8996.mk
@@ -36,10 +36,17 @@
DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80080000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82200000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x82000000
+DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x80080000
+
DEFINES += USB_RESET_FROM_CLK=1
DEFINES += USE_BOOTDEV_CMDLINE=1
DEFINES += USE_RPMB_FOR_DEVINFO=1
DEFINES += ENABLE_WBC=1
+#Enable below flag to compile cmnlib64
+#DEFINES += ENABLE_CMNLIB64_LOADING=1
#Disable thumb mode
ENABLE_THUMB := false
@@ -89,3 +96,9 @@
DEFINES += PLATFORM_USE_QMP_MISC=1
#Use PON register for reboot reason
DEFINES += USE_PON_REBOOT_REG=1
+# Enable unit test FW
+ENABLE_UNITTEST_FW=1
+ifeq ($(ENABLE_UNITTEST_FW),1)
+DEFINES += UNITTEST_FW_SUPPORT=1
+endif
+
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index 565b0b2..62d48ab 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -54,6 +54,7 @@
#include <sdhci_msm.h>
#include <uart_dm.h>
#include <boot_device.h>
+#include <qmp_phy.h>
extern void smem_ptable_init(void);
extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -239,6 +240,7 @@
struct ptable *ptable;
int system_ptn_index = -1;
uint32_t buflen;
+ int ret = -1;
if (!cmdline || !part ) {
dprintf(CRITICAL, "WARN: Invalid input param\n");
@@ -274,6 +276,7 @@
/* Adding command line parameters according to target boot type */
snprintf(*buf, buflen, UBI_CMDLINE);
snprintf(*buf+strlen(*buf), buflen, " root=ubi0:rootfs ubi.mtd=%d", system_ptn_index);
+ ret = 0;
}
else {
buflen = strlen("EXT4_CMDLINE") + sizeof(int) +1;
@@ -291,10 +294,11 @@
return -1;
}
snprintf(*buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
+ ret = 0;
}
}
/*in success case buf will be freed in the calling function of this*/
- return 0;
+ return ret;
}
const char * target_usb_controller()
@@ -372,7 +376,14 @@
void target_usb_phy_reset(void)
{
- usb30_qmp_phy_reset();
+ /* Reset sequence for californium is different from 9x40, use the reset sequence
+ * from clock driver
+ */
+ if (platform_is_mdmcalifornium())
+ clock_reset_usb_phy();
+ else
+ usb30_qmp_phy_reset();
+
qusb2_phy_reset();
}
@@ -394,10 +405,123 @@
uint32_t target_override_pll()
{
- return 1;
+ if (platform_is_mdmcalifornium())
+ return 0;
+ else
+ return 1;
}
uint32_t target_get_hlos_subtype()
{
return board_hlos_subtype();
}
+
+/* QMP settings are different from californium when compared to v2.0/v1.0 hardware.
+ * Use the QMP settings from target code to keep the common driver clean
+ */
+struct qmp_reg qmp_settings[] =
+{
+ {0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+ {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+ {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+ {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+ {0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+ {0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+ {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+ {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */
+ {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+ {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+ {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */
+ {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+ {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+ {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+ {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+ {0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */
+ {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+ {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+ {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+ {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+ {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+ {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+ {0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+ {0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */
+ {0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */
+
+ /* Rx Settings */
+ {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */
+ {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+ {0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+ {0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+ {0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */
+ {0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */
+ {0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */
+
+ /* Tx settings */
+ {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+ {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x294, 0x06}, /* QSERDES_TX_LANE_MODE */
+ {0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */
+
+ /* FLL settings */
+ {0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */
+ {0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */
+ {0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */
+ {0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */
+ {0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */
+
+ /* PCS Settings */
+ {0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */
+ {0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */
+ {0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */
+ {0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */
+ {0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */
+ {0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */
+ {0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */
+ {0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */
+ {0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */
+ {0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+ {0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */
+ {0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */
+ {0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */
+ {0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */
+ {0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */
+ {0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */
+ {0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */
+ {0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
+};
+
+struct qmp_reg *target_get_qmp_settings()
+{
+ if (platform_is_mdmcalifornium())
+ return qmp_settings;
+ else
+ return NULL;
+}
+
+int target_get_qmp_regsize()
+{
+ if (platform_is_mdmcalifornium())
+ return ARRAY_SIZE(qmp_settings);
+ else
+ return 0;
+}
diff --git a/target/mdm9640/keypad.c b/target/mdm9640/keypad.c
index 11ba6e8..2f637f1 100644
--- a/target/mdm9640/keypad.c
+++ b/target/mdm9640/keypad.c
@@ -29,6 +29,8 @@
#include <reg.h>
#include <platform/gpio.h>
#include <platform/iomap.h>
+#include <pm8x41.h>
+#include <platform.h>
/* GPIO that controls the button
* for FASTBOOT.
@@ -43,9 +45,14 @@
{
int ret;
- gpio_tlmm_config(FASTBOOT_KEY_GPIO_ID, 0, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_ENABLE);
+ if (platform_is_mdmcalifornium())
+ ret = pm8x41_resin_status();
+ else
+ {
+ gpio_tlmm_config(FASTBOOT_KEY_GPIO_ID, 0, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_ENABLE);
- ret = gpio_get_state(FASTBOOT_KEY_GPIO_ID);
+ ret = gpio_get_state(FASTBOOT_KEY_GPIO_ID);
+ }
return ret;
}
diff --git a/target/mdmfermium/init.c b/target/mdmfermium/init.c
index 1ccc227..3bfb3c0 100644
--- a/target/mdmfermium/init.c
+++ b/target/mdmfermium/init.c
@@ -118,7 +118,8 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ /*BLSP1 and UART5*/
+ uart_dm_init(5, 0, BLSP1_UART5_BASE);
#endif
}
@@ -190,7 +191,11 @@
switch(platform)
{
- case MDMFERMIUM:
+ case MDMFERMIUM1:
+ case MDMFERMIUM2:
+ case MDMFERMIUM3:
+ case MDMFERMIUM4:
+ case MDMFERMIUM5:
board->baseband = BASEBAND_MDM;
break;
default:
@@ -199,6 +204,13 @@
};
}
+void target_serialno(unsigned char *buf)
+{
+ uint32_t serialno;
+ serialno = board_chip_serial();
+ snprintf((char *)buf, sizeof(uint32_t)+1, "%x", serialno);
+}
+
unsigned check_reboot_mode(void)
{
uint32_t restart_reason = 0;
diff --git a/target/msm8952/mdtp_ui_defs.c b/target/msm8952/mdtp_defs.c
similarity index 77%
rename from target/msm8952/mdtp_ui_defs.c
rename to target/msm8952/mdtp_defs.c
index 668feb2..ebcdafb 100644
--- a/target/msm8952/mdtp_ui_defs.c
+++ b/target/msm8952/mdtp_defs.c
@@ -27,8 +27,15 @@
*
*/
+#include "platform.h"
#include "mdtp_defs.h"
+#define MDTP_EFUSE_ADDRESS_MSM8952 0x0005C250 // QFPROM_CORR_QC_SPARE_REG_LSB_ADDR
+#define MDTP_EFUSE_START_MSM8952 0
+
+#define MDTP_EFUSE_ADDRESS_MSM8956 0x000A4408 // QFPROM_CORR_SPARE_REG18_LSB_ADDR
+#define MDTP_EFUSE_START_MSM8956 0
+
struct mdtp_ui_defs mdtp_ui_defs_msm8952 = {
// Image dimensions
952, // error_msg_width;
@@ -65,3 +72,25 @@
{
return mdtp_ui_defs_msm8952;
}
+
+int mdtp_get_target_efuse(struct mdtp_target_efuse* target_efuse)
+{
+ if (target_efuse == NULL)
+ {
+ dprintf(CRITICAL, "mdtp: mdtp_get_target_efuse: ERROR, target_efuse is NULL\n");
+ return -1;
+ }
+
+ if (platform_is_msm8956())
+ {
+ target_efuse->address = MDTP_EFUSE_ADDRESS_MSM8956;
+ target_efuse->start = MDTP_EFUSE_START_MSM8956;
+ }
+ else
+ {
+ target_efuse->address = MDTP_EFUSE_ADDRESS_MSM8952;
+ target_efuse->start = MDTP_EFUSE_START_MSM8952;
+ }
+
+ return 0;
+}
diff --git a/target/msm8952/rules.mk b/target/msm8952/rules.mk
index 142cd88..045275e 100644
--- a/target/msm8952/rules.mk
+++ b/target/msm8952/rules.mk
@@ -28,6 +28,8 @@
dev/vib \
lib/libfdt \
dev/qpnp_wled \
+ dev/pmic/pmi8994 \
+ dev/pmic/fgsram \
dev/gcdb/display
DEFINES += \
@@ -48,5 +50,5 @@
endif
ifeq ($(ENABLE_MDTP_SUPPORT),1)
OBJS += \
- $(LOCAL_DIR)/mdtp_ui_defs.o
+ $(LOCAL_DIR)/mdtp_defs.o
endif
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index b2585fc..0598833 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -330,15 +330,16 @@
if (!ret)
dprintf(CRITICAL, "Not able to enable master pll\n");
- if (platform_is_msm8956() && pinfo->mipi.dual_dsi) {
+ if (platform_is_msm8956() && pinfo->mipi.dual_dsi &&
+ !platform_is_msm8976_v_1_1()) {
ret = mdss_dsi_pll_config(pinfo->mipi.spll_base,
pinfo->mipi.sctl_base, pll_data);
if (!ret)
dprintf(CRITICAL, "Not able to enable second pll\n");
}
- gcc_dsi_clocks_enable(flags, pll_data->pclk_m, pll_data->pclk_n,
- pll_data->pclk_d);
+ gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
+ pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
gcc_dsi_clocks_disable(flags);
mdp_clock_disable();
diff --git a/target/msm8996/init.c b/target/msm8996/init.c
index 9f49ceb..a60a4dd 100644
--- a/target/msm8996/init.c
+++ b/target/msm8996/init.c
@@ -62,6 +62,11 @@
#include <pm_app_smbchg.h>
#endif
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+
#define CE_INSTANCE 1
#define CE_EE 0
#define CE_FIFO_SIZE 64
@@ -202,6 +207,16 @@
tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
+uint32_t target_is_pwrkey_pon_reason()
+{
+ uint8_t pon_reason = pm8950_get_pon_reason();
+ if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1))))
+ return 1;
+ else
+ return 0;
+}
+
+
void target_sdc_init()
{
struct mmc_config_data config = {0};
@@ -256,6 +271,16 @@
rpm_glink_init();
target_keystatus();
+#if defined(LONG_PRESS_POWER_ON) || defined(PON_VIB_SUPPORT)
+ switch(board_hardware_id())
+ {
+ case HW_PLATFORM_QRD:
+#if LONG_PRESS_POWER_ON
+ shutdown_detect();
+#endif
+ break;
+ }
+#endif
if (target_use_signed_kernel())
target_crypto_init_params();
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index fa207a4..6f06109 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -8,17 +8,22 @@
PLATFORM := msm8996
-MEMBASE := 0x91000000 # SDRAM
+MEMBASE := 0x91600000 # SDRAM
MEMSIZE := 0x00400000 # 4MB
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0x91600000
-SCRATCH_SIZE := 746
+SCRATCH_ADDR := 0x91C00000
+SCRATCH_SIZE := 740
+KERNEL_ADDR := 0x80000000
+KERNEL_SIZE := 88
+
# LPAE supports only 32 virtual address, L1 pt size is 4
L1_PT_SZ := 4
L2_PT_SZ := 3
+DEFINES += PMI_CONFIGURED=1
+
DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
@@ -39,6 +44,8 @@
BASE_ADDR=$(BASE_ADDR) \
TAGS_ADDR=$(TAGS_ADDR) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ KERNEL_SIZE=$(KERNEL_SIZE) \
SCRATCH_ADDR=$(SCRATCH_ADDR) \
SCRATCH_SIZE=$(SCRATCH_SIZE) \
L1_PT_SZ=$(L1_PT_SZ) \