Merge "target: msm8952: enable DSI SSC feature for msm8937" into lk.lnx.1.0-dev.1.0
diff --git a/dev/gcdb/display/include/panel_r69006_1080p_cmd.h b/dev/gcdb/display/include/panel_r69006_1080p_cmd.h
old mode 100644
new mode 100755
index 8aac2c9..4fb01a2
--- a/dev/gcdb/display/include/panel_r69006_1080p_cmd.h
+++ b/dev/gcdb/display/include/panel_r69006_1080p_cmd.h
@@ -66,35 +66,35 @@
/* Panel on/off command information */
/*---------------------------------------------------------------------------*/
static char r69006_1080p_cmd_on_cmd0[] = {
- 0XB0, 0x00, 0x23, 0x80
+ 0xB0, 0x00, 0x23, 0x80
};
static char r69006_1080p_cmd_on_cmd1[] = {
0x06, 0x00, 0x29, 0xC0,
- 0XB3, 0x04, 0x10, 0x00,
+ 0xB3, 0x04, 0x10, 0x00,
0x00, 0x00, 0xFF, 0xFF,
};
static char r69006_1080p_cmd_on_cmd2[] = {
0x03, 0x00, 0x29, 0xC0,
- 0XB4, 0x0c, 0x00, 0xFF,
+ 0xB4, 0x0C, 0x00, 0xFF,
};
static char r69006_1080p_cmd_on_cmd3[] = {
0x04, 0x00, 0x29, 0xC0,
- 0XB6, 0x3b, 0xc3, 0x00,
+ 0xB6, 0x3B, 0xD3, 0x00,
};
static char r69006_1080p_cmd_on_cmd4[] = {
- 0XC0, 0x00, 0x23, 0x80
+ 0xC0, 0x00, 0x23, 0x80
};
static char r69006_1080p_cmd_on_cmd5[] = {
- 0X36, 0x98, 0x15, 0x80
+ 0x36, 0x98, 0x15, 0x80
};
static char r69006_1080p_cmd_on_cmd6[] = {
- 0XCC, 0x04, 0x23, 0x80
+ 0xCC, 0x04, 0x23, 0x80
};
static char r69006_1080p_cmd_on_cmd7[] = {
@@ -125,13 +125,13 @@
static char r69006_1080p_cmd_on_cmd10[] = {
0x07, 0x00, 0x29, 0xC0,
- 0XC3, 0x55, 0x01, 0x00,
+ 0xC3, 0x55, 0x01, 0x00,
0x01, 0x00, 0x00, 0xFF,
};
static char r69006_1080p_cmd_on_cmd11[] = {
0x12, 0x00, 0x29, 0xC0,
- 0XC4, 0x70, 0x00, 0x00,
+ 0xC4, 0x70, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x02, 0x01,
0x00, 0x05, 0x01, 0x00,
@@ -140,31 +140,31 @@
static char r69006_1080p_cmd_on_cmd12[] = {
0x0F, 0x00, 0x29, 0xC0,
- 0xC6, 0x59, 0x07, 0x4a,
- 0x07, 0x4a, 0x01, 0x0E,
+ 0xC6, 0x57, 0x07, 0x4A,
+ 0x07, 0x4A, 0x01, 0x0E,
0x01, 0x02, 0x01, 0x02,
0x09, 0x15, 0x07, 0xFF,
};
static char r69006_1080p_cmd_on_cmd13[] = {
0x1F, 0x00, 0x29, 0xC0,
- 0XC7, 0x00, 0x30, 0x32,
- 0x34, 0x42, 0x4E, 0x56,
- 0x62, 0x44, 0x4A, 0x54,
- 0x62, 0x6B, 0x73, 0x7F,
- 0x08, 0x30, 0x32, 0x34,
- 0x42, 0x4E, 0x56, 0x62,
- 0x44, 0x4A, 0x54, 0x62,
- 0x6B, 0x73, 0x7F, 0xFF,
+ 0xC7, 0x00, 0x13, 0x1E,
+ 0x2A, 0x3A, 0x47, 0x50,
+ 0x5D, 0x40, 0x48, 0x52,
+ 0x5F, 0x67, 0x6F, 0x7A,
+ 0x00, 0x13, 0x1E, 0x2A,
+ 0x3A, 0x47, 0x50, 0x5D,
+ 0x40, 0x48, 0x52, 0x5F,
+ 0x67, 0x6F, 0x7A, 0xFF,
};
static char r69006_1080p_cmd_on_cmd14[] = {
0x14, 0x00, 0x29, 0xC0,
- 0xC8, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xFC, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0xFC, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xFC, 0x00,
+ 0xC8, 0x00, 0x00, 0xFE,
+ 0x01, 0x08, 0xE7, 0x00,
+ 0x00, 0xFD, 0x02, 0x03,
+ 0xA8, 0x00, 0x00, 0xFC,
+ 0xE7, 0xE9, 0xC9, 0x00,
};
static char r69006_1080p_cmd_on_cmd15[] = {
@@ -188,7 +188,7 @@
0xD3, 0x1B, 0x3B, 0xBB,
0xAD, 0xA5, 0x33, 0x33,
0x33, 0x00, 0x80, 0xAD,
- 0xA8, 0x6f, 0x6f, 0x33,
+ 0xA8, 0x5B, 0x5B, 0x33,
0x33, 0x33, 0xF7, 0xF2,
0x1F, 0x7D, 0x7C, 0xFF,
0x0F, 0x99, 0x00, 0xFF,
@@ -202,23 +202,75 @@
static char r69006_1080p_cmd_on_cmd19[] = {
0x0C, 0x00, 0x29, 0xC0,
- 0XD5, 0x66, 0x00, 0x00,
- 0x01, 0x27, 0x01, 0x27,
- 0x00, 0x6D, 0x00, 0x6D,
+ 0xD5, 0x66, 0x00, 0x00,
+ 0x01, 0x33, 0x01, 0x33,
+ 0x00, 0x43, 0x00, 0x43,
};
static char r69006_1080p_cmd_on_cmd20[] = {
- 0xD6, 0x81, 0x23, 0x80
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBE, 0x04, 0xFF, 0xFF,
};
static char r69006_1080p_cmd_on_cmd21[] = {
- 0x11, 0x00, 0x05, 0x80
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xCF, 0x40, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x32,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
};
static char r69006_1080p_cmd_on_cmd22[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xDE, 0x00, 0x00, 0x3F,
+ 0xFF, 0x10, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd23[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE9, 0x00, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd24[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF2, 0x00, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd25[] = {
+ 0xD6, 0x01, 0x23, 0x80
+};
+
+static char r69006_1080p_cmd_on_cmd26[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd27[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x51, 0xff, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd28[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x2c, 0xFF, 0xFF,
+};
+
+static char r69006_1080p_cmd_on_cmd29[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x55, 0x00, 0xFF, 0xFF,
+};
+
+
+static char r69006_1080p_cmd_on_cmd30[] = {
0x29, 0x00, 0x05, 0x80
};
+static char r69006_1080p_cmd_on_cmd31[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+
static struct mipi_dsi_cmd r69006_1080p_cmd_on_command[] = {
{0x4, r69006_1080p_cmd_on_cmd0, 0x00},
{0xc, r69006_1080p_cmd_on_cmd1, 0x00},
@@ -240,12 +292,21 @@
{0x24, r69006_1080p_cmd_on_cmd17, 0x00},
{0x8, r69006_1080p_cmd_on_cmd18, 0x00},
{0x10, r69006_1080p_cmd_on_cmd19, 0x00},
- {0x4, r69006_1080p_cmd_on_cmd20, 0x00},
- {0x4, r69006_1080p_cmd_on_cmd21, 0x78},
- {0x4, r69006_1080p_cmd_on_cmd22, 0x78}
+ {0x8, r69006_1080p_cmd_on_cmd20, 0x00},
+ {0x18, r69006_1080p_cmd_on_cmd21, 0x00},
+ {0xc, r69006_1080p_cmd_on_cmd22, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd23, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd24, 0x00},
+ {0x4, r69006_1080p_cmd_on_cmd25, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd26, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd27, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd28, 0x00},
+ {0x8, r69006_1080p_cmd_on_cmd29, 0x14},
+ {0x4, r69006_1080p_cmd_on_cmd30, 0x14},
+ {0x4, r69006_1080p_cmd_on_cmd31, 0x78}
};
-#define R69006_1080P_CMD_ON_COMMAND 23
+#define R69006_1080P_CMD_ON_COMMAND 32
static char r69006_1080p_cmdoff_cmd0[] = {
@@ -293,7 +354,7 @@
/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t r69006_1080p_cmd_timings[] = {
- 0x7d, 0x25, 0x1d, 0x00, 0x37, 0x33, 0x22, 0x27, 0x1e, 0x03, 0x04, 0x00
+ 0x6E, 0x3F, 0x36, 0x00, 0x5A, 0x4F, 0x38, 0x41, 0x54, 0x03, 0x04, 0x00
};
static struct panel_timing r69006_1080p_cmd_timing_info = {
@@ -314,6 +375,11 @@
1, 1, 4095, 100, 1, "PMIC_8941"
};
+static struct labibb_desc r69006_1080p_cmd_labibb = {
+ 0, 1, 5700000, 5700000, 5700000, 5700000, 3, 3, 1
+};
+
+
#define R69006_1080P_CMD_PANEL_ON_DELAY 32
#define R69006_1080P_CMD_SIGNATURE 0xFFFF
diff --git a/dev/gcdb/display/include/panel_r69006_1080p_video.h b/dev/gcdb/display/include/panel_r69006_1080p_video.h
index e9c5d26..aaf679c 100755
--- a/dev/gcdb/display/include/panel_r69006_1080p_video.h
+++ b/dev/gcdb/display/include/panel_r69006_1080p_video.h
@@ -300,6 +300,10 @@
0, 4, 0x20, 0x2c
};
+static struct labibb_desc r69006_1080p_video_labibb = {
+ 0, 1, 5700000, 5700000, 5700000, 5700000, 3, 3, 1
+};
+
/*---------------------------------------------------------------------------*/
/* Panel reset sequence */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_truly_720p_video.h b/dev/gcdb/display/include/panel_truly_720p_video.h
new file mode 100644
index 0000000..66fb45e
--- /dev/null
+++ b/dev/gcdb/display/include/panel_truly_720p_video.h
@@ -0,0 +1,1049 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_TRULY_720P_VIDEO_H_
+
+#define _PANEL_TRULY_720P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config truly_720p_video_panel_data = {
+ "qcom,mdss_dsi_truly_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution truly_720p_video_panel_res = {
+ 720, 1280, 100, 100, 6, 0, 32, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info truly_720p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char truly_720p_video_on_cmd0[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd1[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb1, 0x78, 0x21, 0xff, };
+
+static char truly_720p_video_on_cmd2[] = {
+0xb6, 0x0f, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd3[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbc, 0x00, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd4[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xbd, 0x02, 0xb0, 0x1e,
+0x1e, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd5[] = {
+0x0b, 0x00, 0x29, 0xc0,
+0xe7, 0xf2, 0xe6, 0xd8,
+0xcc, 0xbf, 0xb2, 0xa5,
+0x99, 0x99, 0x95, 0xff, };
+
+static char truly_720p_video_on_cmd6[] = {
+0x0b, 0x00, 0x29, 0xc0,
+0xe8, 0xf2, 0xe6, 0xd8,
+0xcc, 0xbf, 0xb2, 0xa5,
+0x99, 0x99, 0x95, 0xff, };
+
+static char truly_720p_video_on_cmd7[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x01, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd8[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbc, 0xa0, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd9[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbd, 0xa0, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd10[] = {
+0xca, 0x01, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd11[] = {
+0xc0, 0x0c, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd12[] = {
+0xbe, 0x4e, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb3, 0x38, 0x38, 0xff, };
+
+static char truly_720p_video_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb4, 0x11, 0x11, 0xff, };
+
+static char truly_720p_video_on_cmd15[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb6, 0x05, 0x05, 0xff, };
+
+static char truly_720p_video_on_cmd16[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb9, 0x45, 0x45, 0xff, };
+
+static char truly_720p_video_on_cmd17[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xba, 0x25, 0x25, 0xff, };
+
+static char truly_720p_video_on_cmd18[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc4, 0x11, 0x11, 0xff, };
+
+static char truly_720p_video_on_cmd19[] = {
+0xc6, 0x66, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd20[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x02, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd21[] = {
+0xee, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd22[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb0, 0x00, 0x37, 0x00,
+0x48, 0x00, 0x69, 0x00,
+0x8a, 0x00, 0xab, 0x00,
+0xcb, 0x00, 0xeb, 0x01,
+0x1c, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd23[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb1, 0x01, 0x41, 0x01,
+0x7c, 0x01, 0xaa, 0x01,
+0xf3, 0x02, 0x2d, 0x02,
+0x2e, 0x02, 0x63, 0x02,
+0x9d, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd24[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb2, 0x02, 0xc3, 0x02,
+0xf6, 0x03, 0x19, 0x03,
+0x54, 0x03, 0x85, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd25[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xb3, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd26[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xbc, 0x00, 0x37, 0x00,
+0x48, 0x00, 0x69, 0x00,
+0x8a, 0x00, 0xab, 0x00,
+0xcb, 0x00, 0xeb, 0x01,
+0x1c, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd27[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xbd, 0x01, 0x41, 0x01,
+0x7c, 0x01, 0xaa, 0x01,
+0xf3, 0x02, 0x2d, 0x02,
+0x2e, 0x02, 0x63, 0x02,
+0x9d, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd28[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xbe, 0x02, 0xc3, 0x02,
+0xf6, 0x03, 0x19, 0x03,
+0x54, 0x03, 0x85, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd29[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xbf, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd30[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb4, 0x00, 0xd1, 0x00,
+0xd7, 0x00, 0xe4, 0x00,
+0xf1, 0x00, 0xfe, 0x01,
+0x12, 0x01, 0x26, 0x01,
+0x48, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd31[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb5, 0x01, 0x64, 0x01,
+0x95, 0x01, 0xbd, 0x02,
+0x01, 0x02, 0x36, 0x02,
+0x38, 0x02, 0x6c, 0x02,
+0xa7, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd32[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb6, 0x02, 0xce, 0x03,
+0x04, 0x03, 0x2b, 0x03,
+0x5b, 0x03, 0x89, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd33[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xb7, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd34[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc0, 0x00, 0xd1, 0x00,
+0xd7, 0x00, 0xe4, 0x00,
+0xf1, 0x00, 0xfe, 0x01,
+0x12, 0x01, 0x26, 0x01,
+0x48, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd35[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc1, 0x01, 0x64, 0x01,
+0x95, 0x01, 0xbd, 0x02,
+0x01, 0x02, 0x36, 0x02,
+0x38, 0x02, 0x6c, 0x02,
+0xa7, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd36[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc2, 0x02, 0xce, 0x03,
+0x04, 0x03, 0x2b, 0x03,
+0x5b, 0x03, 0x89, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd37[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc3, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd38[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb8, 0x00, 0x37, 0x00,
+0x45, 0x00, 0x61, 0x00,
+0x7d, 0x00, 0x9a, 0x00,
+0xbb, 0x00, 0xdc, 0x01,
+0x0b, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd39[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xb9, 0x01, 0x31, 0x01,
+0x6e, 0x01, 0x9e, 0x01,
+0xea, 0x02, 0x24, 0x02,
+0x25, 0x02, 0x58, 0x02,
+0x90, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd40[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xba, 0x02, 0xb4, 0x02,
+0xe4, 0x03, 0x04, 0x03,
+0x44, 0x03, 0x7f, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd41[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xbb, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd42[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc4, 0x00, 0x37, 0x00,
+0x45, 0x00, 0x61, 0x00,
+0x7d, 0x00, 0x9a, 0x00,
+0xbb, 0x00, 0xdc, 0x01,
+0x0b, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd43[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc5, 0x01, 0x31, 0x01,
+0x6e, 0x01, 0x9e, 0x01,
+0xea, 0x02, 0x24, 0x02,
+0x25, 0x02, 0x58, 0x02,
+0x90, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd44[] = {
+0x11, 0x00, 0x29, 0xc0,
+0xc6, 0x02, 0xb4, 0x02,
+0xe4, 0x03, 0x04, 0x03,
+0x44, 0x03, 0x7f, 0x03,
+0xb2, 0x03, 0xc1, 0x03,
+0xd1, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd45[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc7, 0x03, 0xe0, 0x03,
+0xe8, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd46[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x06, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd47[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb0, 0x29, 0x2a, 0xff, };
+
+static char truly_720p_video_on_cmd48[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb1, 0x10, 0x12, 0xff, };
+
+static char truly_720p_video_on_cmd49[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb2, 0x14, 0x16, 0xff, };
+
+static char truly_720p_video_on_cmd50[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb3, 0x18, 0x1a, 0xff, };
+
+static char truly_720p_video_on_cmd51[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb4, 0x02, 0x04, 0xff, };
+
+static char truly_720p_video_on_cmd52[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb5, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd53[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb6, 0x34, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd54[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb7, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd55[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb8, 0x34, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd56[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb9, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd57[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xba, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd58[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbb, 0x01, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd59[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbc, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd60[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbd, 0x2e, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd61[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbe, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd62[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xbf, 0x05, 0x03, 0xff, };
+
+static char truly_720p_video_on_cmd63[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc0, 0x1b, 0x19, 0xff, };
+
+static char truly_720p_video_on_cmd64[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc1, 0x17, 0x15, 0xff, };
+
+static char truly_720p_video_on_cmd65[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc2, 0x13, 0x11, 0xff, };
+
+static char truly_720p_video_on_cmd66[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc3, 0x2a, 0x29, 0xff, };
+
+static char truly_720p_video_on_cmd67[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xe5, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd68[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc4, 0x29, 0x2a, 0xff, };
+
+static char truly_720p_video_on_cmd69[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc5, 0x1b, 0x19, 0xff, };
+
+static char truly_720p_video_on_cmd70[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc6, 0x17, 0x15, 0xff, };
+
+static char truly_720p_video_on_cmd71[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc7, 0x13, 0x11, 0xff, };
+
+static char truly_720p_video_on_cmd72[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc8, 0x01, 0x05, 0xff, };
+
+static char truly_720p_video_on_cmd73[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc9, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd74[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xca, 0x34, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd75[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xcb, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd76[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xcc, 0x34, 0x03, 0xff, };
+
+static char truly_720p_video_on_cmd77[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xcd, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd78[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xce, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd79[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xcf, 0x02, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd80[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd0, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd81[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd1, 0x2e, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd82[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd2, 0x34, 0x34, 0xff, };
+
+static char truly_720p_video_on_cmd83[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd3, 0x04, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd84[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd4, 0x10, 0x12, 0xff, };
+
+static char truly_720p_video_on_cmd85[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd5, 0x14, 0x16, 0xff, };
+
+static char truly_720p_video_on_cmd86[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd6, 0x18, 0x1a, 0xff, };
+
+static char truly_720p_video_on_cmd87[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xd7, 0x2a, 0x29, 0xff, };
+
+static char truly_720p_video_on_cmd88[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xe6, 0x2e, 0x2e, 0xff, };
+
+static char truly_720p_video_on_cmd89[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd8, 0x00, 0x00, 0x00,
+0x54, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd90[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd9, 0x00, 0x15, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd91[] = {
+0xe7, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd92[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x03, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd93[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb1, 0x00, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd94[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb0, 0x00, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd95[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb2, 0x05, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd96[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb3, 0x05, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd97[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb4, 0x05, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd98[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb5, 0x05, 0x00, 0x17,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd99[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb6, 0x12, 0x00, 0x19,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd100[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb7, 0x12, 0x00, 0x19,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd101[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb8, 0x12, 0x00, 0x19,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd102[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xb9, 0x12, 0x00, 0x19,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd103[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xba, 0x57, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd104[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xbb, 0x57, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd105[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xbc, 0x75, 0x00, 0x1a,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd106[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xbd, 0x53, 0x00, 0x1a,
+0x00, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd107[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc0, 0x00, 0x34, 0x00,
+0x00, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd108[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc1, 0x00, 0x34, 0x00,
+0x00, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd109[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc2, 0x00, 0x34, 0x00,
+0x00, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd110[] = {
+0x05, 0x00, 0x29, 0xc0,
+0xc3, 0x00, 0x34, 0x00,
+0x00, 0xff, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd111[] = {
+0xc4, 0x20, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd112[] = {
+0xc5, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd113[] = {
+0xc6, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd114[] = {
+0xc7, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd115[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xf0, 0x55, 0xaa, 0x52,
+0x08, 0x05, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd116[] = {
+0xed, 0x30, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd117[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb0, 0x17, 0x06, 0xff, };
+
+static char truly_720p_video_on_cmd118[] = {
+0xb8, 0x08, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd119[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xbd, 0x03, 0x07, 0x00,
+0x03, 0x00, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd120[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb1, 0x17, 0x06, 0xff, };
+
+static char truly_720p_video_on_cmd121[] = {
+0xb9, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd122[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb2, 0x00, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd123[] = {
+0xba, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd124[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb3, 0x17, 0x06, 0xff, };
+
+static char truly_720p_video_on_cmd125[] = {
+0xbb, 0x0a, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd126[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb4, 0x17, 0x06, 0xff, };
+
+static char truly_720p_video_on_cmd127[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb5, 0x17, 0x06, 0xff, };
+
+static char truly_720p_video_on_cmd128[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb6, 0x14, 0x03, 0xff, };
+
+static char truly_720p_video_on_cmd129[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xb7, 0x00, 0x00, 0xff, };
+
+static char truly_720p_video_on_cmd130[] = {
+0xbc, 0x02, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd131[] = {
+0xe5, 0x06, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd132[] = {
+0xe6, 0x06, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd133[] = {
+0xe7, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd134[] = {
+0xe8, 0x06, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd135[] = {
+0xe9, 0x06, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd136[] = {
+0xea, 0x06, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd137[] = {
+0xeb, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd138[] = {
+0xec, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd139[] = {
+0xc0, 0x07, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd140[] = {
+0xc1, 0x80, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd141[] = {
+0xc2, 0xa4, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd142[] = {
+0xc3, 0x05, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd143[] = {
+0xc4, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd144[] = {
+0xc5, 0x02, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd145[] = {
+0xc6, 0x22, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd146[] = {
+0xc7, 0x03, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd147[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc8, 0x05, 0x30, 0xff, };
+
+static char truly_720p_video_on_cmd148[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xc9, 0x01, 0x31, 0xff, };
+
+static char truly_720p_video_on_cmd149[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xca, 0x03, 0x21, 0xff, };
+
+static char truly_720p_video_on_cmd150[] = {
+0x03, 0x00, 0x29, 0xc0,
+0xcb, 0x01, 0x20, 0xff, };
+
+static char truly_720p_video_on_cmd151[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd1, 0x00, 0x05, 0x09,
+0x07, 0x10, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd152[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd2, 0x10, 0x05, 0x0e,
+0x03, 0x10, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd153[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd3, 0x20, 0x00, 0x48,
+0x07, 0x10, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd154[] = {
+0x06, 0x00, 0x29, 0xc0,
+0xd4, 0x30, 0x00, 0x43,
+0x07, 0x10, 0xff, 0xff, };
+
+static char truly_720p_video_on_cmd155[] = {
+0xd0, 0x00, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd156[] = {
+0x04, 0x00, 0x29, 0xc0,
+0xcc, 0x00, 0x00, 0x3e, };
+
+static char truly_720p_video_on_cmd157[] = {
+0x04, 0x00, 0x29, 0xc0,
+0xcd, 0x00, 0x00, 0x3e, };
+
+static char truly_720p_video_on_cmd158[] = {
+0x04, 0x00, 0x29, 0xc0,
+0xce, 0x00, 0x00, 0x02, };
+
+static char truly_720p_video_on_cmd159[] = {
+0x04, 0x00, 0x29, 0xc0,
+0xcf, 0x00, 0x00, 0x02, };
+
+static char truly_720p_video_on_cmd160[] = {
+0x6f, 0x11, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd161[] = {
+0xf3, 0x01, 0x23, 0x80, };
+
+static char truly_720p_video_on_cmd162[] = {
+0x51, 0xff, 0x15, 0x80, };
+
+static char truly_720p_video_on_cmd163[] = {
+0x53, 0x2c, 0x15, 0x80, };
+
+static char truly_720p_video_on_cmd164[] = {
+0x55, 0x03, 0x15, 0x80, };
+
+static char truly_720p_video_on_cmd165[] = {
+0x35, 0x00, 0x15, 0x80, };
+
+static char truly_720p_video_on_cmd166[] = {
+0x11, 0x00, 0x05, 0x80, };
+
+static char truly_720p_video_on_cmd167[] = {
+0x29, 0x00, 0x05, 0x80, };
+
+
+static struct mipi_dsi_cmd truly_720p_video_on_command[] = {
+{ 0xc , truly_720p_video_on_cmd0, 0x00},
+{ 0x8 , truly_720p_video_on_cmd1, 0x00},
+{ 0x4 , truly_720p_video_on_cmd2, 0x00},
+{ 0x8 , truly_720p_video_on_cmd3, 0x00},
+{ 0xc , truly_720p_video_on_cmd4, 0x00},
+{ 0x10 , truly_720p_video_on_cmd5, 0x00},
+{ 0x10 , truly_720p_video_on_cmd6, 0x00},
+{ 0xc , truly_720p_video_on_cmd7, 0x00},
+{ 0x8 , truly_720p_video_on_cmd8, 0x00},
+{ 0x8 , truly_720p_video_on_cmd9, 0x00},
+{ 0x4 , truly_720p_video_on_cmd10, 0x00},
+{ 0x4 , truly_720p_video_on_cmd11, 0x00},
+{ 0x4 , truly_720p_video_on_cmd12, 0x00},
+{ 0x8 , truly_720p_video_on_cmd13, 0x00},
+{ 0x8 , truly_720p_video_on_cmd14, 0x00},
+{ 0x8 , truly_720p_video_on_cmd15, 0x00},
+{ 0x8 , truly_720p_video_on_cmd16, 0x00},
+{ 0x8 , truly_720p_video_on_cmd17, 0x00},
+{ 0x8 , truly_720p_video_on_cmd18, 0x00},
+{ 0x4 , truly_720p_video_on_cmd19, 0x00},
+{ 0xc , truly_720p_video_on_cmd20, 0x00},
+{ 0x4 , truly_720p_video_on_cmd21, 0x00},
+{ 0x18 , truly_720p_video_on_cmd22, 0x00},
+{ 0x18 , truly_720p_video_on_cmd23, 0x00},
+{ 0x18 , truly_720p_video_on_cmd24, 0x00},
+{ 0xc , truly_720p_video_on_cmd25, 0x00},
+{ 0x18 , truly_720p_video_on_cmd26, 0x00},
+{ 0x18 , truly_720p_video_on_cmd27, 0x00},
+{ 0x18 , truly_720p_video_on_cmd28, 0x00},
+{ 0xc , truly_720p_video_on_cmd29, 0x00},
+{ 0x18 , truly_720p_video_on_cmd30, 0x00},
+{ 0x18 , truly_720p_video_on_cmd31, 0x00},
+{ 0x18 , truly_720p_video_on_cmd32, 0x00},
+{ 0xc , truly_720p_video_on_cmd33, 0x00},
+{ 0x18 , truly_720p_video_on_cmd34, 0x00},
+{ 0x18 , truly_720p_video_on_cmd35, 0x00},
+{ 0x18 , truly_720p_video_on_cmd36, 0x00},
+{ 0xc , truly_720p_video_on_cmd37, 0x00},
+{ 0x18 , truly_720p_video_on_cmd38, 0x00},
+{ 0x18 , truly_720p_video_on_cmd39, 0x00},
+{ 0x18 , truly_720p_video_on_cmd40, 0x00},
+{ 0xc , truly_720p_video_on_cmd41, 0x00},
+{ 0x18 , truly_720p_video_on_cmd42, 0x00},
+{ 0x18 , truly_720p_video_on_cmd43, 0x00},
+{ 0x18 , truly_720p_video_on_cmd44, 0x00},
+{ 0xc , truly_720p_video_on_cmd45, 0x00},
+{ 0xc , truly_720p_video_on_cmd46, 0x00},
+{ 0x8 , truly_720p_video_on_cmd47, 0x00},
+{ 0x8 , truly_720p_video_on_cmd48, 0x00},
+{ 0x8 , truly_720p_video_on_cmd49, 0x00},
+{ 0x8 , truly_720p_video_on_cmd50, 0x00},
+{ 0x8 , truly_720p_video_on_cmd51, 0x00},
+{ 0x8 , truly_720p_video_on_cmd52, 0x00},
+{ 0x8 , truly_720p_video_on_cmd53, 0x00},
+{ 0x8 , truly_720p_video_on_cmd54, 0x00},
+{ 0x8 , truly_720p_video_on_cmd55, 0x00},
+{ 0x8 , truly_720p_video_on_cmd56, 0x00},
+{ 0x8 , truly_720p_video_on_cmd57, 0x00},
+{ 0x8 , truly_720p_video_on_cmd58, 0x00},
+{ 0x8 , truly_720p_video_on_cmd59, 0x00},
+{ 0x8 , truly_720p_video_on_cmd60, 0x00},
+{ 0x8 , truly_720p_video_on_cmd61, 0x00},
+{ 0x8 , truly_720p_video_on_cmd62, 0x00},
+{ 0x8 , truly_720p_video_on_cmd63, 0x00},
+{ 0x8 , truly_720p_video_on_cmd64, 0x00},
+{ 0x8 , truly_720p_video_on_cmd65, 0x00},
+{ 0x8 , truly_720p_video_on_cmd66, 0x00},
+{ 0x8 , truly_720p_video_on_cmd67, 0x00},
+{ 0x8 , truly_720p_video_on_cmd68, 0x00},
+{ 0x8 , truly_720p_video_on_cmd69, 0x00},
+{ 0x8 , truly_720p_video_on_cmd70, 0x00},
+{ 0x8 , truly_720p_video_on_cmd71, 0x00},
+{ 0x8 , truly_720p_video_on_cmd72, 0x00},
+{ 0x8 , truly_720p_video_on_cmd73, 0x00},
+{ 0x8 , truly_720p_video_on_cmd74, 0x00},
+{ 0x8 , truly_720p_video_on_cmd75, 0x00},
+{ 0x8 , truly_720p_video_on_cmd76, 0x00},
+{ 0x8 , truly_720p_video_on_cmd77, 0x00},
+{ 0x8 , truly_720p_video_on_cmd78, 0x00},
+{ 0x8 , truly_720p_video_on_cmd79, 0x00},
+{ 0x8 , truly_720p_video_on_cmd80, 0x00},
+{ 0x8 , truly_720p_video_on_cmd81, 0x00},
+{ 0x8 , truly_720p_video_on_cmd82, 0x00},
+{ 0x8 , truly_720p_video_on_cmd83, 0x00},
+{ 0x8 , truly_720p_video_on_cmd84, 0x00},
+{ 0x8 , truly_720p_video_on_cmd85, 0x00},
+{ 0x8 , truly_720p_video_on_cmd86, 0x00},
+{ 0x8 , truly_720p_video_on_cmd87, 0x00},
+{ 0x8 , truly_720p_video_on_cmd88, 0x00},
+{ 0xc , truly_720p_video_on_cmd89, 0x00},
+{ 0xc , truly_720p_video_on_cmd90, 0x00},
+{ 0x4 , truly_720p_video_on_cmd91, 0x00},
+{ 0xc , truly_720p_video_on_cmd92, 0x00},
+{ 0x8 , truly_720p_video_on_cmd93, 0x00},
+{ 0x8 , truly_720p_video_on_cmd94, 0x00},
+{ 0xc , truly_720p_video_on_cmd95, 0x00},
+{ 0xc , truly_720p_video_on_cmd96, 0x00},
+{ 0xc , truly_720p_video_on_cmd97, 0x00},
+{ 0xc , truly_720p_video_on_cmd98, 0x00},
+{ 0xc , truly_720p_video_on_cmd99, 0x00},
+{ 0xc , truly_720p_video_on_cmd100, 0x00},
+{ 0xc , truly_720p_video_on_cmd101, 0x00},
+{ 0xc , truly_720p_video_on_cmd102, 0x00},
+{ 0xc , truly_720p_video_on_cmd103, 0x00},
+{ 0xc , truly_720p_video_on_cmd104, 0x00},
+{ 0xc , truly_720p_video_on_cmd105, 0x00},
+{ 0xc , truly_720p_video_on_cmd106, 0x00},
+{ 0xc , truly_720p_video_on_cmd107, 0x00},
+{ 0xc , truly_720p_video_on_cmd108, 0x00},
+{ 0xc , truly_720p_video_on_cmd109, 0x00},
+{ 0xc , truly_720p_video_on_cmd110, 0x00},
+{ 0x4 , truly_720p_video_on_cmd111, 0x00},
+{ 0x4 , truly_720p_video_on_cmd112, 0x00},
+{ 0x4 , truly_720p_video_on_cmd113, 0x00},
+{ 0x4 , truly_720p_video_on_cmd114, 0x00},
+{ 0xc , truly_720p_video_on_cmd115, 0x00},
+{ 0x4 , truly_720p_video_on_cmd116, 0x00},
+{ 0x8 , truly_720p_video_on_cmd117, 0x00},
+{ 0x4 , truly_720p_video_on_cmd118, 0x00},
+{ 0xc , truly_720p_video_on_cmd119, 0x00},
+{ 0x8 , truly_720p_video_on_cmd120, 0x00},
+{ 0x4 , truly_720p_video_on_cmd121, 0x00},
+{ 0x8 , truly_720p_video_on_cmd122, 0x00},
+{ 0x4 , truly_720p_video_on_cmd123, 0x00},
+{ 0x8 , truly_720p_video_on_cmd124, 0x00},
+{ 0x4 , truly_720p_video_on_cmd125, 0x00},
+{ 0x8 , truly_720p_video_on_cmd126, 0x00},
+{ 0x8 , truly_720p_video_on_cmd127, 0x00},
+{ 0x8 , truly_720p_video_on_cmd128, 0x00},
+{ 0x8 , truly_720p_video_on_cmd129, 0x00},
+{ 0x4 , truly_720p_video_on_cmd130, 0x00},
+{ 0x4 , truly_720p_video_on_cmd131, 0x00},
+{ 0x4 , truly_720p_video_on_cmd132, 0x00},
+{ 0x4 , truly_720p_video_on_cmd133, 0x00},
+{ 0x4 , truly_720p_video_on_cmd134, 0x00},
+{ 0x4 , truly_720p_video_on_cmd135, 0x00},
+{ 0x4 , truly_720p_video_on_cmd136, 0x00},
+{ 0x4 , truly_720p_video_on_cmd137, 0x00},
+{ 0x4 , truly_720p_video_on_cmd138, 0x00},
+{ 0x4 , truly_720p_video_on_cmd139, 0x00},
+{ 0x4 , truly_720p_video_on_cmd140, 0x00},
+{ 0x4 , truly_720p_video_on_cmd141, 0x00},
+{ 0x4 , truly_720p_video_on_cmd142, 0x00},
+{ 0x4 , truly_720p_video_on_cmd143, 0x00},
+{ 0x4 , truly_720p_video_on_cmd144, 0x00},
+{ 0x4 , truly_720p_video_on_cmd145, 0x00},
+{ 0x4 , truly_720p_video_on_cmd146, 0x00},
+{ 0x8 , truly_720p_video_on_cmd147, 0x00},
+{ 0x8 , truly_720p_video_on_cmd148, 0x00},
+{ 0x8 , truly_720p_video_on_cmd149, 0x00},
+{ 0x8 , truly_720p_video_on_cmd150, 0x00},
+{ 0xc , truly_720p_video_on_cmd151, 0x00},
+{ 0xc , truly_720p_video_on_cmd152, 0x00},
+{ 0xc , truly_720p_video_on_cmd153, 0x00},
+{ 0xc , truly_720p_video_on_cmd154, 0x00},
+{ 0x4 , truly_720p_video_on_cmd155, 0x00},
+{ 0x8 , truly_720p_video_on_cmd156, 0x00},
+{ 0x8 , truly_720p_video_on_cmd157, 0x00},
+{ 0x8 , truly_720p_video_on_cmd158, 0x00},
+{ 0x8 , truly_720p_video_on_cmd159, 0x00},
+{ 0x4 , truly_720p_video_on_cmd160, 0x00},
+{ 0x4 , truly_720p_video_on_cmd161, 0x00},
+{ 0x4 , truly_720p_video_on_cmd162, 0x00},
+{ 0x4 , truly_720p_video_on_cmd163, 0x00},
+{ 0x4 , truly_720p_video_on_cmd164, 0x00},
+{ 0x4 , truly_720p_video_on_cmd165, 0xc8},
+{ 0x4 , truly_720p_video_on_cmd166, 0x78},
+{ 0x4 , truly_720p_video_on_cmd167, 0x0a},
+};
+#define TRULY_720P_VIDEO_ON_COMMAND 168
+
+
+static char truly_720p_video_off_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char truly_720p_video_off_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+static struct mipi_dsi_cmd truly_720p_video_off_command[] = {
+{ 0x4 , truly_720p_video_off_cmd0, 0x0},
+{ 0x4 , truly_720p_video_off_cmd1, 0x0}
+};
+#define TRULY_720P_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state truly_720p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info truly_720p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info truly_720p_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration truly_720p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t truly_720p_video_timings[] = {
+ 0x87, 0x2c, 0x12, 0x00, 0x40, 0x44, 0x16, 0x1e, 0x17, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing truly_720p_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+static struct panel_reset_sequence truly_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 200, 200, 200, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight truly_720p_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define TRULY_720P_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_TRULY_720P_VIDEO_H_*/
diff --git a/dev/qpnp_haptic/qpnp_haptic.c b/dev/qpnp_haptic/qpnp_haptic.c
index e472dff..51de2e5 100644
--- a/dev/qpnp_haptic/qpnp_haptic.c
+++ b/dev/qpnp_haptic/qpnp_haptic.c
@@ -65,9 +65,7 @@
#define QPNP_HAP_PWM_CAP_MASK 0x03
#define QPNP_HAP_PWM_CAP_13PF 0x01
#define QPNP_HAP_RATE_CFG1_MASK 0xFF
-#define QPNP_HAP_RATE_CFG1_7_0 0x1C
#define QPNP_HAP_RATE_CFG2_MASK 0x0F
-#define QPNP_HAP_RATE_CFG2_11_8 0x04
#define QPNP_HAP_EN_BRAKE_EN_MASK 0x01
#define QPNP_HAP_EN_BRAKING_EN 0x01
#define QPNP_HAP_BRAKE_VMAX_MASK 0xFF
@@ -87,12 +85,13 @@
/* Turn on vibrator */
void pm_vib_turn_on(void)
{
- uint32_t vib_type = VIB_ERM_TYPE;
- vib_type = get_vibration_type();
+ struct qpnp_hap vib_config = {0};
+
+ get_vibration_type(&vib_config);
/* Configure the ACTUATOR TYPE register as ERM*/
pmic_spmi_reg_mask_write(QPNP_HAP_ACT_TYPE_REG,
QPNP_HAP_ACT_TYPE_MASK,
- VIB_ERM_TYPE == vib_type ? QPNP_HAP_ERM
+ VIB_ERM_TYPE == vib_config.vib_type ? QPNP_HAP_ERM
: QPNP_HAP_LRA);
/* Disable auto resonance for ERM */
@@ -129,9 +128,9 @@
/* Configure RATE_CFG1 and RATE_CFG2 registers for haptic rate. */
pmic_spmi_reg_mask_write(QPNP_HAP_RATE_CFG1_REG,
- QPNP_HAP_RATE_CFG1_MASK, QPNP_HAP_RATE_CFG1_7_0);
+ QPNP_HAP_RATE_CFG1_MASK, vib_config.hap_rate_cfg1);
pmic_spmi_reg_mask_write(QPNP_HAP_RATE_CFG2_REG,
- QPNP_HAP_RATE_CFG2_MASK, QPNP_HAP_RATE_CFG2_11_8);
+ QPNP_HAP_RATE_CFG2_MASK, vib_config.hap_rate_cfg2);
/* Configure BRAKE register, PATTERN1 & PATTERN2 as VMAX. */
pmic_spmi_reg_mask_write(QPNP_HAP_EN_CTL2_REG,
diff --git a/dev/vib/include/vibrator.h b/dev/vib/include/vibrator.h
index 2ec1346..b6aee2f 100644
--- a/dev/vib/include/vibrator.h
+++ b/dev/vib/include/vibrator.h
@@ -32,6 +32,18 @@
#define VIB_LRA_TYPE 0x00
#define VIB_ERM_TYPE 0x01
+/* Only copy the definitions that are required for haptic */
+#define QPNP_HAP_RATE_CFG1_1c 0x1C
+#define QPNP_HAP_RATE_CFG2_04 0x04
+#define QPNP_HAP_RATE_CFG1_41 0x41
+#define QPNP_HAP_RATE_CFG2_03 0x03
+
+struct qpnp_hap{
+ uint8_t hap_rate_cfg1;
+ uint8_t hap_rate_cfg2;
+ uint8_t vib_type;
+};
+
void vib_turn_on(void);
void vib_turn_off(void);
void vib_timed_turn_on(const uint32_t);
diff --git a/include/target.h b/include/target.h
index 1da87f1..17c0c0e 100644
--- a/include/target.h
+++ b/include/target.h
@@ -93,7 +93,7 @@
int target_get_qmp_regsize();
#if PON_VIB_SUPPORT
-uint32_t get_vibration_type();
+void get_vibration_type();
#endif
#if CHECK_BAT_VOLTAGE
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
old mode 100644
new mode 100755
index bce48b9..2bfc931
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -632,7 +632,16 @@
$(LOCAL_DIR)/scm.o \
$(LOCAL_DIR)/qseecom_lk.o \
$(LOCAL_DIR)/dev_tree.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/dload_util.o \
+ $(LOCAL_DIR)/shutdown_detect.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/qmp_usb30_phy.o \
+ $(LOCAL_DIR)/qusb2_phy.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o
endif
ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
index 25c1eff..58fc686 100755
--- a/platform/msmtitanium/acpuclock.c
+++ b/platform/msmtitanium/acpuclock.c
@@ -38,25 +38,171 @@
#define MAX_LOOPS 500
-void hsusb_clock_init(void)
+/*
+ * Disable power collapse using GDSCR:
+ * Globally Distributed Switch Controller Register
+ */
+void clock_usb30_gdsc_enable(void)
{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 133330000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_aux_clk", 19200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_phy_cfg_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret = 1;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_177MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 177770000, 1);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret =0;
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
@@ -64,14 +210,90 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ /* Start the block reset for CE */
+ writel(1, GCC_CRYPTO_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CRYPTO_BCR);
+
+ udelay(2);
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 160000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
@@ -88,3 +310,73 @@
clock_ce_enable(instance);
}
+
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+ struct clk *master_clk = NULL;
+
+ master_clk = clk_get("usb30_master_clk");
+ ASSERT(master_clk);
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+ return;
+ }
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ goto deassert_master_clk;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+
+deassert_master_clk:
+
+ ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+ return;
+ }
+}
diff --git a/platform/msmtitanium/include/platform/clock.h b/platform/msmtitanium/include/platform/clock.h
old mode 100644
new mode 100755
index 4174744..86d1f9b
--- a/platform/msmtitanium/include/platform/clock.h
+++ b/platform/msmtitanium/include/platform/clock.h
@@ -41,4 +41,8 @@
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
+void clock_reset_usb_phy();
#endif
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
index 833520a..64779cb 100755
--- a/platform/msmtitanium/include/platform/iomap.h
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -88,12 +88,12 @@
/* GPLL */
-#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
+#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
-#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x37024)
/* SDCC */
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
@@ -127,6 +127,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
+#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
+#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
+#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
@@ -140,9 +146,56 @@
#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
-#define MSM_USB30_QSCRATCH_BASE 0x070F8800
-#define MSM_USB30_BASE 0x7000000
-#define USB2_PHY_SEL 0x01937000
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x4103C)
+#define MSM_USB30_QSCRATCH_BASE 0x070F8800
+#define MSM_USB30_BASE 0x7000000
+#define USB2_PHY_SEL 0x01937000
+#define QUSB2_PHY_BASE 0X79000
+
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE 0x78000
+
+#define AHB2_PHY_BASE 0x0007e000
+#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
+
+ /* USB3 clocks */
+#define USB_30_BCR (CLK_CTL_BASE + 0x3F070)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x3F078)
+#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x3F000)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x3F004)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x3F008)
+#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x3F00C)
+#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x3F010)
+#define USB30_MASTER_M (CLK_CTL_BASE + 0x3F014)
+#define USB30_MASTER_N (CLK_CTL_BASE + 0x3F018)
+#define USB30_MASTER_D (CLK_CTL_BASE + 0x3F01C)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x3F020)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x3F024)
+#define PC_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x3F038)
+
+#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x3F05C)
+#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x3F060)
+#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x3F044)
+#define USB3_AUX_M (CLK_CTL_BASE + 0x3F064)
+#define USB3_AUX_N (CLK_CTL_BASE + 0x3F068)
+#define USB3_AUX_D (CLK_CTL_BASE + 0x3F06C)
+#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x3F040)
+#define USB3_PHY_BCR (CLK_CTL_BASE + 0x3F034)
+#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x3F03C)
+#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3F080)
+
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994)
+
+/* Dummy macro needed for compilation only */
+#define PLATFORM_QMP_OFFSET 0x0
+
+#define USB3_PHY_STATUS 0x78974
+/* Register for finding out if single ended or differential clock enablement */
+#define TCSR_PHY_CLK_SCHEME_SEL 0x0193F044
/* RPMB send receive buffer needs to be mapped
* as device memory, define the start address
diff --git a/platform/msmtitanium/include/platform/irqs.h b/platform/msmtitanium/include/platform/irqs.h
index db33501..120ea3d 100755
--- a/platform/msmtitanium/include/platform/irqs.h
+++ b/platform/msmtitanium/include/platform/irqs.h
@@ -51,7 +51,7 @@
#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
/* Retrofit universal macro names */
-#define INT_USB_HS USB1_HS_IRQ
+#define INT_USB_HS USB30_EE1_IRQ
#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
old mode 100644
new mode 100755
index 092ca54..ff1e313
--- a/platform/msmtitanium/msmtitanium-clock.c
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -40,6 +40,8 @@
#define cxo_source_val 0
#define gpll0_source_val 1
#define gpll4_source_val 2
+#define gpll6_source_val 1
+#define gpll0_out_main_div2_source_val 4
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 6
#define gpll6_mm_source_val 3
@@ -48,6 +50,12 @@
/* Clock Operations */
+
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -101,8 +109,8 @@
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
.en_mask = BIT(0),
- .status_reg = (void *) GPLL0_STATUS,
- .status_mask = BIT(17),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
.parent = &cxo_clk_src.c,
.c = {
@@ -112,6 +120,21 @@
},
};
+static struct pll_vote_clk gpll0_out_main_div2_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 400000000,
+ .dbg_name = "gpll0_out_main_div2_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
static struct pll_vote_clk gpll4_clk_src =
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
@@ -127,17 +150,32 @@
},
};
+static struct pll_vote_clk gpll6_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(7),
+ .status_reg = (void *) GPLL6_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1080000000,
+ .dbg_name = "gpll6_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F(384000000, gpll4, 3, 0, 0),
F_END
};
@@ -186,12 +224,12 @@
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F_END
};
@@ -238,10 +276,10 @@
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
{
- F( 3686400, gpll0, 1, 72, 15625),
- F( 7372800, gpll0, 1, 144, 15625),
- F(14745600, gpll0, 1, 288, 15625),
- F(16000000, gpll0, 10, 1, 5),
+ F( 3686400, gpll0_out_main_div2, 1, 144, 15625),
+ F( 7372800, gpll0_out_main_div2, 1, 288, 15625),
+ F(14745600, gpll0_out_main_div2, 1, 576, 15625),
+ F(16000000, gpll0_out_main_div2, 5, 1, 5),
F(19200000, cxo, 1, 0, 0),
F(24000000, gpll0, 1, 3, 100),
F(25000000, gpll0, 16, 1, 2),
@@ -253,9 +291,39 @@
F(56000000, gpll0, 1, 7, 100),
F(58982400, gpll0, 1,1152, 15625),
F(60000000, gpll0, 1, 3, 40),
+ F(64000000, gpll0, 12, 1, 2),
F_END
};
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -297,50 +365,117 @@
};
/* USB Clocks */
-static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+static struct branch_clk gcc_pc_noc_usb30_axi_clk =
{
- F(100000000, gpll0, 10, 0, 0),
- F(133330000, gpll0, 6, 0, 0),
+ .cbcr_reg = (uint32_t *) PC_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_pc_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb_clk = {
+ .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_phy_cfg_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(100000000, gpll0, 8, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
F_END
};
-static struct rcg_clk usb_hs_system_clk_src =
-{
- .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
- .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "usb_hs_system_clk",
+ .dbg_name = "usb30_master_clk_src",
.ops = &clk_ops_rcg,
},
};
-static struct branch_clk gcc_usb_hs_system_clk =
+static struct branch_clk gcc_usb30_master_clk =
{
- .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
- .parent = &usb_hs_system_clk_src.c,
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
.c = {
- .dbg_name = "gcc_usb_hs_system_clk",
+ .dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
},
};
-static struct branch_clk gcc_usb_hs_ahb_clk =
-{
- .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.has_sibling = 1,
+ .halt_check = 0,
.c = {
- .dbg_name = "gcc_usb_hs_ahb_clk",
+ .dbg_name = "usb30_pipe_clk",
.ops = &clk_ops_branch,
},
};
+static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR,
+ .m_reg = (uint32_t *) USB3_AUX_M,
+ .n_reg = (uint32_t *) USB3_AUX_N,
+ .d_reg = (uint32_t *) USB3_AUX_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_aux_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_aux_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_usb30_aux_clk = {
+ .cbcr_reg = (uint32_t *) USB3_AUX_CBCR,
+ .parent = &usb30_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -370,6 +505,54 @@
},
};
+static struct reset_clk gcc_usb2a_phy_sleep_clk = {
+ .bcr_reg = (uint32_t) GCC_QUSB2_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F( 60000000, gpll6, 6, 1, 3),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
static struct vote_clk gcc_ce1_ahb_clk = {
.cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
@@ -401,11 +584,21 @@
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
- CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
- CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_pc_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
index 2168570..83d0b3b 100755
--- a/platform/msmtitanium/platform.c
+++ b/platform/msmtitanium/platform.c
@@ -66,6 +66,7 @@
{ APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
{ MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+ { RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
void platform_early_init(void)
@@ -168,3 +169,9 @@
else
return MSM_SHARED_BASE;
}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
diff --git a/project/msmtitanium.mk b/project/msmtitanium.mk
index d1449a5..6cc2ada 100755
--- a/project/msmtitanium.mk
+++ b/project/msmtitanium.mk
@@ -67,6 +67,11 @@
CFLAGS += -Werror
+# Reset USB clock from target code
+DEFINES += USB_RESET_FROM_CLK=1
+
+DEFINES += USE_TARGET_QMP_SETTINGS=1
+
DEFINES += USE_TARGET_HS200_DELAY=1
#Enable the external reboot functions
diff --git a/target/init.c b/target/init.c
index 1d67c69..b8a818b 100644
--- a/target/init.c
+++ b/target/init.c
@@ -240,35 +240,42 @@
}
#if PON_VIB_SUPPORT
-uint32_t get_vibration_type()
+void get_vibration_type(struct qpnp_hap *config)
{
- uint32_t ret = VIB_ERM_TYPE;
uint32_t hw_id = board_hardware_id();
uint32_t platform = board_platform_id();
+
+ config->vib_type = VIB_ERM_TYPE;
+ config->hap_rate_cfg1 = QPNP_HAP_RATE_CFG1_1c;
+ config->hap_rate_cfg2 = QPNP_HAP_RATE_CFG2_04;
switch(hw_id){
case HW_PLATFORM_MTP:
switch(platform){
case MSM8952:
- ret = VIB_ERM_TYPE;
+ config->vib_type = VIB_ERM_TYPE;
break;
case MSM8976:
case MSM8956:
case APQ8056:
- ret = VIB_LRA_TYPE;
+ config->vib_type = VIB_LRA_TYPE;
break;
+ case MSM8937:
+ case APQ8037:
+ config->vib_type = VIB_LRA_TYPE;
+ config->hap_rate_cfg1 = QPNP_HAP_RATE_CFG1_41;
+ config->hap_rate_cfg2 = QPNP_HAP_RATE_CFG2_03;
default:
dprintf(CRITICAL,"Unsupported platform id\n");
break;
}
break;
case HW_PLATFORM_QRD:
- ret = VIB_ERM_TYPE;
+ config->vib_type = VIB_ERM_TYPE;
break;
default:
- dprintf(CRITICAL,"Unsupported platform id\n");
+ dprintf(CRITICAL,"Unsupported hardware id\n");
break;
}
- return ret;
}
#endif
diff --git a/target/msm8952/mdtp_defs.c b/target/msm8952/mdtp_defs.c
index ebcdafb..4518b06 100644
--- a/target/msm8952/mdtp_defs.c
+++ b/target/msm8952/mdtp_defs.c
@@ -36,6 +36,9 @@
#define MDTP_EFUSE_ADDRESS_MSM8956 0x000A4408 // QFPROM_CORR_SPARE_REG18_LSB_ADDR
#define MDTP_EFUSE_START_MSM8956 0
+#define MDTP_EFUSE_ADDRESS_MSM8937 0x000A43B0 // QFPROM_CORR_SPARE_REG18_ROW0_LSB_ADDR
+#define MDTP_EFUSE_START_MSM8937 0
+
struct mdtp_ui_defs mdtp_ui_defs_msm8952 = {
// Image dimensions
952, // error_msg_width;
@@ -86,6 +89,11 @@
target_efuse->address = MDTP_EFUSE_ADDRESS_MSM8956;
target_efuse->start = MDTP_EFUSE_START_MSM8956;
}
+ else if (platform_is_msm8937())
+ {
+ target_efuse->address = MDTP_EFUSE_ADDRESS_MSM8937;
+ target_efuse->start = MDTP_EFUSE_START_MSM8937;
+ }
else
{
target_efuse->address = MDTP_EFUSE_ADDRESS_MSM8952;
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
old mode 100644
new mode 100755
index 241d100..60ade48
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -496,6 +496,7 @@
panelstruct->panelresetseq
= &r69006_1080p_cmd_reset_seq;
panelstruct->backlightinfo = &r69006_1080p_cmd_backlight;
+ pinfo->labibb = &r69006_1080p_cmd_labibb;
pinfo->mipi.panel_on_cmds
= r69006_1080p_cmd_on_command;
pinfo->mipi.num_of_panel_on_cmds
@@ -507,6 +508,8 @@
memcpy(phy_db->timing,
r69006_1080p_cmd_timings, TIMING_SIZE);
pinfo->mipi.signature = R69006_1080P_CMD_SIGNATURE;
+ pinfo->mipi.tx_eot_append = true;
+ pinfo->mipi.rx_eot_ignore = true;
break;
case R69006_1080P_VIDEO_PANEL:
panelstruct->paneldata = &r69006_1080p_video_panel_data;
@@ -521,6 +524,7 @@
panelstruct->panelresetseq
= &r69006_1080p_video_reset_seq;
panelstruct->backlightinfo = &r69006_1080p_video_backlight;
+ pinfo->labibb = &r69006_1080p_video_labibb;
pinfo->mipi.panel_on_cmds
= r69006_1080p_video_on_command;
pinfo->mipi.num_of_panel_on_cmds
diff --git a/target/msmtitanium/init.c b/target/msmtitanium/init.c
index 8a80a8c..ac1b75f 100755
--- a/target/msmtitanium/init.c
+++ b/target/msmtitanium/init.c
@@ -52,6 +52,12 @@
#include <spmi.h>
#include <sdhci_msm.h>
#include <clock.h>
+#include <boot_device.h>
+#include <secapp_loader.h>
+#include <rpmb.h>
+#include <smem.h>
+#include <qmp_phy.h>
+#include <qusb2_phy.h>
#if LONG_PRESS_POWER_ON
#include <shutdown_detect.h>
@@ -62,8 +68,18 @@
#define TLMM_VOL_UP_BTN_GPIO 85
#define FASTBOOT_MODE 0x77665500
+#define RECOVERY_MODE 0x77665502
#define PON_SOFT_RB_SPARE 0x88F
+#define CE1_INSTANCE 1
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
+
struct mmc_device *dev;
static uint32_t mmc_pwrctl_base[] =
@@ -78,7 +94,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(1, 0, BLSP1_UART1_BASE);
+ uart_dm_init(2, 0, BLSP1_UART1_BASE);
#endif
}
@@ -160,7 +176,7 @@
status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
/* Active high signal. */
- return status;
+ return !status;
}
/* Return 1 if vol_down pressed */
@@ -170,6 +186,15 @@
return pm8x41_resin_status();
}
+uint32_t target_is_pwrkey_pon_reason()
+{
+ uint8_t pon_reason = pm8950_get_pon_reason();
+ if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1))))
+ return 1;
+ else
+ return 0;
+}
+
static void target_keystatus()
{
keys_init();
@@ -183,6 +208,11 @@
void target_init(void)
{
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ int ret = 0;
+#endif
+#endif
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
@@ -199,6 +229,53 @@
#if LONG_PRESS_POWER_ON
shutdown_detect();
#endif
+
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
+
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ clock_ce_enable(CE1_INSTANCE);
+
+ /* Initialize Qseecom */
+ ret = qseecom_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to initialize qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Start Qseecom */
+ ret = qseecom_tz_init();
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed to start qseecom, error: %d\n", ret);
+ ASSERT(0);
+ }
+
+ if (rpmb_init() < 0)
+ {
+ dprintf(CRITICAL, "RPMB init failed\n");
+ ASSERT(0);
+ }
+
+ /*
+ * Load the sec app for first time
+ */
+ if (load_sec_app() < 0)
+ {
+ dprintf(CRITICAL, "Failed to load App for verified\n");
+ ASSERT(0);
+ }
+#endif
+#endif
+
+#if SMD_SUPPORT
+ rpm_smd_init();
+#endif
}
void target_serialno(unsigned char *buf)
@@ -221,6 +298,7 @@
/* This is already filled as part of board.c */
}
+/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
uint32_t platform;
@@ -237,6 +315,10 @@
};
}
+unsigned target_baseband()
+{
+ return board_baseband();
+}
int set_download_mode(enum dload_mode mode)
{
int ret = 0;
@@ -272,6 +354,42 @@
return 0;
}
+void target_uninit(void)
+{
+ mmc_put_card_to_sleep(dev);
+ sdhci_mode_disable(&dev->host);
+ if (crypto_initialized())
+ crypto_eng_cleanup();
+
+ if (target_is_ssd_enabled())
+ clock_ce_disable(CE1_INSTANCE);
+
+#if VERIFIED_BOOT
+#if !VBOOT_MOTA
+ if (is_sec_app_loaded())
+ {
+ if (send_milestone_call_to_tz() < 0)
+ {
+ dprintf(CRITICAL, "Failed to unload App for rpmb\n");
+ ASSERT(0);
+ }
+ }
+
+ if (rpmb_uninit() < 0)
+ {
+ dprintf(CRITICAL, "RPMB uninit failed\n");
+ ASSERT(0);
+ }
+
+ clock_ce_disable(CE1_INSTANCE);
+#endif
+#endif
+
+#if SMD_SUPPORT
+ rpm_smd_uninit();
+#endif
+}
+
/* UTMI MUX configuration to connect PHY to SNPS controller:
* Configure primary HS phy mux to use UTMI interface
* (connected to usb30 controller).
@@ -294,16 +412,26 @@
}
}
+void target_usb_phy_reset()
+{
+
+ usb30_qmp_phy_reset();
+ qusb2_phy_reset();
+}
+
/* Initialize target specific USB handlers */
target_usb_iface_t* target_usb30_init()
{
target_usb_iface_t *t_usb_iface;
- t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
+ t_usb_iface = (target_usb_iface_t *) calloc(1, sizeof(target_usb_iface_t));
ASSERT(t_usb_iface);
- t_usb_iface->mux_config = target_usb_phy_mux_configure;
- //t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->mux_config = NULL;
+ t_usb_iface->phy_init = usb30_qmp_phy_init;
+ t_usb_iface->phy_reset = target_usb_phy_reset;
+ t_usb_iface->clock_init = clock_usb30_init;
+ t_usb_iface->vbus_override = 1;
return t_usb_iface;
}
@@ -314,14 +442,200 @@
return "dwc";
}
+/* Do any target specific intialization needed before entering fastboot mode */
+void target_fastboot_init(void)
+{
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(CE1_INSTANCE);
+ target_load_ssd_keystore();
+ }
+}
+
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer = NULL;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(CE1_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(CE1_INSTANCE);
+ free(buffer);
+}
crypto_engine_type board_ce_type(void)
{
return CRYPTO_ENGINE_TYPE_HW;
}
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE1_INSTANCE;
+ ce_params.crypto_base = MSM_CE1_BASE;
+ ce_params.bam_base = MSM_CE1_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
void pmic_reset_configure(uint8_t reset_type)
{
pm8x41_reset_configure(reset_type);
}
+
+uint32_t target_get_pmic()
+{
+ return PMIC_IS_PMI8950;
+}
+
+struct qmp_reg qmp_settings[] =
+{
+ {0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+ {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+ {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+ {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+ {0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+ {0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+ {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+ {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */
+ {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+ {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+ {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ {0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ {0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */
+ {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ {0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+ {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+ {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+ {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+ {0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */
+ {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+ {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+ {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+ {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+ {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+ {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+ {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+ {0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+ {0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */
+ {0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */
+
+ /* Rx Settings */
+ {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ {0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ {0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ {0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */
+ {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ {0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+ {0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+ {0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+ {0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */
+ {0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */
+ {0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */
+
+ /* Tx settings */
+ {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+ {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ {0x294, 0x06}, /* QSERDES_TX_LANE_MODE */
+ {0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */
+
+ /* FLL settings */
+ {0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */
+ {0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */
+ {0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */
+ {0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */
+ {0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */
+
+ /* PCS Settings */
+ {0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */
+ {0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */
+ {0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */
+ {0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */
+ {0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */
+ {0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */
+ {0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */
+ {0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */
+ {0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */
+ {0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+ {0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */
+ {0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */
+ {0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */
+ {0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */
+ {0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */
+ {0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */
+ {0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */
+ {0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
+};
+
+struct qmp_reg *target_get_qmp_settings()
+{
+ return qmp_settings;
+}
+
+int target_get_qmp_regsize()
+{
+ return ARRAY_SIZE(qmp_settings);
+}