Merge "target: msm8226: enable ssd2080m panel for skug"
diff --git a/dev/gcdb/display/include/panel_sharp_qhd_video.h b/dev/gcdb/display/include/panel_sharp_qhd_video.h
new file mode 100755
index 0000000..df8c5a5
--- /dev/null
+++ b/dev/gcdb/display/include/panel_sharp_qhd_video.h
@@ -0,0 +1,190 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SHARP_QHD_VIDEO_H_
+
+#define _PANEL_SHARP_QHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config sharp_qhd_video_panel_data = {
+ "qcom,mdss_dsi_sharp_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution sharp_qhd_video_panel_res = {
+ 540, 960, 48, 80, 32, 0, 3, 15, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info sharp_qhd_video_color = {
+ 24, 2, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char sharp_qhd_video_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd1[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd2[] = {
+0x53, 0x2c, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd3[] = {
+0x51, 0xff, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd4[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd5[] = {
+0xae, 0x03, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd6[] = {
+0x3a, 0x77, 0x15, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_on_command[] = {
+{ 0x4 , sharp_qhd_video_on_cmd0},
+{ 0x4 , sharp_qhd_video_on_cmd1},
+{ 0x4 , sharp_qhd_video_on_cmd2},
+{ 0x4 , sharp_qhd_video_on_cmd3},
+{ 0x4 , sharp_qhd_video_on_cmd4},
+{ 0x4 , sharp_qhd_video_on_cmd5},
+{ 0x4 , sharp_qhd_video_on_cmd6}
+};
+#define SHARP_QHD_VIDEO_ON_COMMAND 7
+
+
+static char sharp_qhd_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_off_command[] = {
+{ 0x4 , sharp_qhd_videooff_cmd0},
+{ 0x4 , sharp_qhd_videooff_cmd1}
+};
+#define SHARP_QHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state sharp_qhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info sharp_qhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info sharp_qhd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 0, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration sharp_qhd_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t sharp_qhd_video_timings[] = {
+ 0x46, 0x1d, 0x20, 0x00, 0x39, 0x3a, 0x21, 0x21, 0x32, 0x03, 0x04, 0x00
+};
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_rotation[] = {
+
+};
+#define SHARP_QHD_VIDEO_ROTATION 0
+
+
+static struct panel_timing sharp_qhd_video_timing_info = {
+ 4, 4, 0x04, 0x1c
+};
+
+static struct panel_reset_sequence sharp_qhd_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight sharp_qhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+
+#endif /*_PANEL_SHARP_QHD_VIDEO_H_*/
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 236aed7..dcd4549 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -203,4 +203,5 @@
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
+void pm8x41_clear_pmic_watchdog(void);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index c8c83ce..9239ce7 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -72,6 +72,7 @@
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
+#define PMIC_WD_RESET_S2_CTL2 0x857
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 915cf52..91f1daa 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -401,3 +401,8 @@
REG_WRITE(DIFF_CLK1_EN_CTL, reg);
}
+
+void pm8x41_clear_pmic_watchdog(void)
+{
+ pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
+}
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 432fbdb..c939bad 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -133,13 +133,13 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp2_uart2_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
@@ -151,13 +151,13 @@
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -287,8 +287,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart7_core_clk", gcc_blsp2_uart2_apps_clk.c),
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 7e6e7d5..33e0090 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -65,6 +65,8 @@
#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+
#define CLK_CTL_BASE 0xFC400000
/* GPLL */
@@ -75,12 +77,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
/* USB */
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 5284d0f..e66208c 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -481,6 +481,83 @@
}
}
+void mmss_clock_auto_pll_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change because
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure S0 AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ if (dual_dsi) {
+ /* Configure Byte 1 clock */
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+ }
+}
+
void mmss_clock_disable(uint32_t dual_dsi)
{
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index f83c2ae..3f6bd14 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -67,6 +67,9 @@
#define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000)
#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI_PIXEL0_M REG_MM(0x2008)
+#define DSI_PIXEL0_N REG_MM(0x200C)
+#define DSI_PIXEL0_D REG_MM(0x2010)
#define DSI0_PHY_PLL_OUT BIT(8)
#define PIXEL_SRC_DIV_1_5 BIT(1)
@@ -80,6 +83,9 @@
#define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020)
#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define DSI_PIXEL1_M REG_MM(0x2028)
+#define DSI_PIXEL1_N REG_MM(0x202C)
+#define DSI_PIXEL1_D REG_MM(0x2030)
#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 7ff5a82..01c0303 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -45,6 +45,7 @@
uint32_t size;
};
+static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask);
extern int target_is_emmc_boot(void);
extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
/* TODO: This function needs to be moved to target layer to check violations
@@ -52,23 +53,32 @@
*/
extern int check_aboot_addr_range_overlap(uint32_t start, uint32_t size);
-struct msm_id
-{
- uint32_t platform_id;
- uint32_t hardware_id;
- uint32_t soc_rev;
-};
-
/* Returns soc version if platform id and hardware id matches
otherwise return 0xFFFFFFFF */
#define INVALID_SOC_REV_ID 0XFFFFFFFF
static uint32_t dev_tree_compatible(void *dtb)
{
int root_offset;
- const void *prop;
- char model[128];
- struct msm_id msm_id;
+ const void *prop = NULL;
+ const char *plat_prop = NULL;
+ const char *board_prop = NULL;
+ char *model = NULL;
+ struct dt_entry cur_dt_entry;
+ struct dt_entry *dt_entry_v2 = NULL;
+ struct board_id *board_data = NULL;
+ struct plat_id *platform_data = NULL;
int len;
+ int len_board_id;
+ int len_plat_id;
+ int min_plat_id_len = 0;
+ uint32_t target_variant_id;
+ uint32_t dtb_ver;
+ uint32_t num_entries = 0;
+ uint32_t i, j, k;
+ uint32_t found = 0;
+ uint32_t msm_data_count;
+ uint32_t board_data_count;
+ uint32_t soc_rev;
root_offset = fdt_path_offset(dtb, "/");
if (root_offset < 0)
@@ -76,49 +86,199 @@
prop = fdt_getprop(dtb, root_offset, "model", &len);
if (prop && len > 0) {
- memcpy(model, prop, MIN((int)sizeof(model), len));
- model[sizeof(model) - 1] = '\0';
+ model = (char *) malloc(sizeof(char) * len);
+ ASSERT(model);
+ strlcpy(model, prop, len);
} else {
model[0] = '\0';
}
- prop = fdt_getprop(dtb, root_offset, "qcom,msm-id", &len);
- if (!prop || len <= 0) {
+ /* Find the board-id prop from DTB , if board-id is present then
+ * the DTB is version 2 */
+ board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
+ if (board_prop)
+ {
+ dtb_ver = DEV_TREE_VERSION_V2;
+ min_plat_id_len = PLAT_ID_SIZE;
+ }
+ else
+ {
+ dtb_ver = DEV_TREE_VERSION_V1;
+ min_plat_id_len = DT_ENTRY_V1_SIZE;
+ }
+
+ /* Get the msm-id prop from DTB */
+ plat_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,msm-id", &len_plat_id);
+ if (!plat_prop || len_plat_id <= 0) {
dprintf(INFO, "qcom,msm-id entry not found\n");
return false;
- } else if (len < (int)sizeof(struct msm_id)) {
- dprintf(INFO, "qcom,msm-id entry size mismatch (%d != %d)\n",
- len, sizeof(struct msm_id));
+ } else if (len_plat_id % min_plat_id_len) {
+ dprintf(INFO, "qcom,msm-id in device tree is (%d) not a multiple of (%d)\n",
+ len_plat_id, min_plat_id_len);
return false;
}
- msm_id.platform_id = fdt32_to_cpu(((const struct msm_id *)prop)->platform_id);
- msm_id.hardware_id = fdt32_to_cpu(((const struct msm_id *)prop)->hardware_id);
- msm_id.soc_rev = fdt32_to_cpu(((const struct msm_id *)prop)->soc_rev);
- dprintf(INFO, "Found an appended flattened device tree (%s - %d %d 0x%x)\n",
- *model ? model : "unknown",
- msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
+ /*
+ * If DTB version is '1' look for <x y z> pair in the DTB
+ * x: platform_id
+ * y: variant_id
+ * z: SOC rev
+ */
+ if (dtb_ver == DEV_TREE_VERSION_V1)
+ {
+ while (len_plat_id)
+ {
+ cur_dt_entry.platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
+ cur_dt_entry.variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
+ cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
+ cur_dt_entry.board_hw_subtype = board_hardware_subtype();
- if (msm_id.platform_id != board_platform_id() ||
- msm_id.hardware_id != board_hardware_id()) {
- dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_soc_version());
- return INVALID_SOC_REV_ID;
+ target_variant_id = board_hardware_id();
+
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
+
+ if (platform_dt_match(&cur_dt_entry, target_variant_id, 0) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ plat_prop += DT_ENTRY_V1_SIZE;
+ len_plat_id -= DT_ENTRY_V1_SIZE;
+ continue;
+ }
+ else
+ {
+ found = 1;
+ break;
+ }
+ }
+ }
+ /*
+ * If DTB Version is '2' then we have split DTB with board & msm data
+ * populated saperately in board-id & msm-id prop respectively.
+ * Extract the data & prepare a look up table
+ */
+ else if (dtb_ver == DEV_TREE_VERSION_V2)
+ {
+ board_data_count = (len_board_id / BOARD_ID_SIZE);
+ msm_data_count = (len_plat_id / PLAT_ID_SIZE);
+
+ /* If we are using dtb v2.0, then we have split board & msm data in the DTB */
+ board_data = (struct board_id *) malloc(sizeof(struct board_id) * (len_board_id / BOARD_ID_SIZE));
+ ASSERT(board_data);
+ platform_data = (struct plat_id *) malloc(sizeof(struct plat_id) * (len_plat_id / PLAT_ID_SIZE));
+ ASSERT(platform_data);
+ i = 0;
+
+ /* Extract board data from DTB */
+ for(i = 0 ; i < board_data_count; i++)
+ {
+ board_data[i].variant_id = fdt32_to_cpu(((struct board_id *)board_prop)->variant_id);
+ board_data[i].platform_subtype = fdt32_to_cpu(((struct board_id *)board_prop)->platform_subtype);
+ len_board_id -= sizeof(struct board_id);
+ board_prop += sizeof(struct board_id);
+ }
+
+ /* Extract platform data from DTB */
+ for(i = 0 ; i < msm_data_count; i++)
+ {
+ platform_data[i].platform_id = fdt32_to_cpu(((struct plat_id *)plat_prop)->platform_id);
+ platform_data[i].soc_rev = fdt32_to_cpu(((struct plat_id *)plat_prop)->soc_rev);
+ len_plat_id -= sizeof(struct plat_id);
+ plat_prop += sizeof(struct plat_id);
+ }
+
+ /* We need to merge board & platform data into dt entry structure */
+ num_entries = msm_data_count * board_data_count;
+ dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+ ASSERT(dt_entry_v2);
+
+ /* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
+ * Then dt entry should look like
+ * <X ,A >;<X, B>;<X, C>;
+ * <Y ,A >;<Y, B>;<Y, C>;
+ * <Z ,A >;<Z, B>;<Z, C>;
+ */
+ i = 0;
+ k = 0;
+ for (i = 0; i < msm_data_count; i++)
+ {
+ for (j = 0; j < board_data_count; j++)
+ {
+ dt_entry_v2[k].platform_id = platform_data[i].platform_id;
+ dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_v2[k].variant_id = board_data[j].variant_id;
+ dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
+ k++;
+ }
+ }
+
+ /* Now find the matching entry in the merged list */
+ if (board_hardware_id() == HW_PLATFORM_QRD)
+ target_variant_id = board_target_id();
+ else
+ target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+
+ for (i=0 ;i < num_entries; i++)
+ {
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+
+ if (platform_dt_match(&dt_entry_v2[i], target_variant_id, 0xff) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
+ dt_entry_v2[i].platform_id,
+ dt_entry_v2[i].variant_id,
+ dt_entry_v2[i].soc_rev,
+ dt_entry_v2[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ continue;
+ }
+ else
+ {
+ /* If found a match, return the cur_dt_entry */
+ found = 1;
+ cur_dt_entry = dt_entry_v2[i];
+ break;
+ }
+ }
}
- dprintf(INFO, "Device tree's msm_id matches the board: <%d %d 0x%x> == <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
+ if (!found)
+ {
+ soc_rev = INVALID_SOC_REV_ID;
+ goto end;
+ }
+ else
+ soc_rev = cur_dt_entry.soc_rev;
+
+ dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.board_hw_subtype,
+ cur_dt_entry.soc_rev,
board_platform_id(),
board_hardware_id(),
+ board_hardware_subtype(),
board_soc_version());
- return msm_id.soc_rev;
+
+end:
+ free(board_data);
+ free(platform_data);
+ free(dt_entry_v2);
+ free(model);
+
+ return soc_rev;
}
/*
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index b88a47d..85aa40d 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -43,6 +43,18 @@
#define DTB_PAD_SIZE 1024
+/*
+ * For DTB V1: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, CDP, rev_1>; (3 * sizeof(uint32_t))
+ * For DTB V2: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, rev_1>; (2 * sizeof(uint32_t))
+ * qcom,board-id = <CDP, subtype_ID>; (2 * sizeof(uint32_t))
+ * The macros below are defined based on these.
+ */
+#define DT_ENTRY_V1_SIZE 0xC
+#define PLAT_ID_SIZE 0x8
+#define BOARD_ID_SIZE 0x8
+
struct dt_entry
{
uint32_t platform_id;
@@ -60,6 +72,18 @@
uint32_t num_entries;
};
+struct plat_id
+{
+ uint32_t platform_id;
+ uint32_t soc_rev;
+};
+
+struct board_id
+{
+ uint32_t variant_id;
+ uint32_t platform_subtype;
+};
+
enum dt_err_codes
{
DT_OP_SUCCESS,
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 5616956..72f2f94 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -64,220 +64,8 @@
return dividend / divisor;
}
-static uint32_t dsi_pll_enable_seq_m(void)
-{
- uint32_t i = 0;
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- if (i != 0)
- writel(0x34, MIPI_DSI_BASE + 0x00270); /* CAL CFG1*/
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- }
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_d(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_f1(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_c(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_e(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-
-
-static uint32_t dsi_pll_enable_seq_8974(void)
-{
- uint32_t rc = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
-
- while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- }
- return rc;
-}
-
-static uint32_t dsi_pll_enable_seq(void)
-{
- uint32_t platformid = board_platform_id();
-
- /* Only one enable seq for 8974 target */
- if (platformid == MSM8974) {
- dsi_pll_enable_seq_8974();
- }
-
- /* 6 enable seq for 8226 target */
- else if (platformid == MSM8826 ||
- platformid == MSM8626 ||
- platformid == MSM8226 ||
- platformid == MSM8926 ||
- platformid == MSM8126 ||
- platformid == MSM8326 ||
- platformid == APQ8026) {
- if (dsi_pll_enable_seq_m()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_f1()) {
- } else if (dsi_pll_enable_seq_c()) {
- } else if (dsi_pll_enable_seq_e()) {
- } else {
- dprintf(CRITICAL, "Not able to enable the pll\n");
- }
- } else {
- dprintf(CRITICAL, "Target not supported in auto PLL\n");
- }
-
-}
-
-int32_t mdss_dsi_auto_pll_config(struct mdss_dsi_pll_config *pd)
+int32_t mdss_dsi_auto_pll_config(uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
{
uint32_t rem, divider;
uint32_t refclk_cfg = 0, frac_n_mode = 0, ref_doubler_en_b = 0;
@@ -299,25 +87,25 @@
return rc;
}
- mdss_dsi_phy_sw_reset(MIPI_DSI_BASE);
+ mdss_dsi_phy_sw_reset(ctl_base);
/* Loop filter resistance value */
- writel(lpfr_lut[i].resistance, MIPI_DSI_BASE + 0x022c);
+ writel(lpfr_lut[i].resistance, ctl_base + 0x022c);
/* Loop filter capacitance values : c1 and c2 */
- writel(0x70, MIPI_DSI_BASE + 0x0230);
- writel(0x15, MIPI_DSI_BASE + 0x0234);
+ writel(0x70, ctl_base + 0x0230);
+ writel(0x15, ctl_base + 0x0234);
- writel(0x02, MIPI_DSI_BASE + 0x0208); /* ChgPump */
+ writel(0x02, ctl_base + 0x0208); /* ChgPump */
/* postDiv1 - calculated in pll config*/
- writel(pd->posdiv1, MIPI_DSI_BASE + 0x0204);
+ writel(pd->posdiv1, ctl_base + 0x0204);
/* postDiv2 - fixed devision 4 */
- writel(0x03, MIPI_DSI_BASE + 0x0224);
+ writel(0x03, ctl_base + 0x0224);
/* postDiv3 - calculated in pll config */
- writel(pd->posdiv3, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
+ writel(pd->posdiv3, ctl_base + 0x0228); /* postDiv3 */
- writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
- writel(0x66, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
- writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+ writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
+ writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
+ writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
if (rem) {
@@ -361,27 +149,25 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(sdm_cfg1 , MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
- writel(sdm_cfg2 , MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
- writel(sdm_cfg3 , MIPI_DSI_BASE + 0x0244); /* SDM CFG3 */
- writel(0x00, MIPI_DSI_BASE + 0x0248); /* SDM CFG4 */
+ writel(sdm_cfg1 , ctl_base + 0x023c); /* SDM CFG1 */
+ writel(sdm_cfg2 , ctl_base + 0x0240); /* SDM CFG2 */
+ writel(sdm_cfg3 , ctl_base + 0x0244); /* SDM CFG3 */
+ writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
udelay(10);
- writel(refclk_cfg, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
- writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
- writel(0x71, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
- writel(pd->directpath, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
- writel(sdm_cfg0, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
+ writel(refclk_cfg, ctl_base + 0x0200); /* REFCLK CFG */
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
+ writel(pd->directpath, ctl_base + 0x0210); /* VREG CFG */
+ writel(sdm_cfg0, ctl_base + 0x0238); /* SDM CFG0 */
- writel(0x0a, MIPI_DSI_BASE + 0x026c); /* CAL CFG0 */
- writel(0x30, MIPI_DSI_BASE + 0x0284); /* CAL CFG6 */
- writel(0x00, MIPI_DSI_BASE + 0x0288); /* CAL CFG7 */
- writel(0x60, MIPI_DSI_BASE + 0x028c); /* CAL CFG8 */
- writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
- writel(cal_cfg10, MIPI_DSI_BASE + 0x0294); /* CAL CFG10 */
- writel(cal_cfg11, MIPI_DSI_BASE + 0x0298); /* CAL CFG11 */
- writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
-
- dsi_pll_enable_seq();
+ writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
+ writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
+ writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
+ writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
+ writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
+ writel(cal_cfg10, ctl_base + 0x0294); /* CAL CFG10 */
+ writel(cal_cfg11, ctl_base + 0x0298); /* CAL CFG11 */
+ writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index ccf164c..00be808 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -86,6 +86,7 @@
$(LOCAL_DIR)/display.o \
$(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 03996f9..4399c60 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -383,8 +383,11 @@
static uint8_t sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd)
{
uint8_t i;
+ uint8_t ret = 0;
+ uint8_t need_reset = 0;
uint32_t retry = 0;
uint32_t int_status;
+ uint32_t trans_complete = 0;
do {
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
@@ -397,6 +400,7 @@
udelay(500);
if (retry == SDHCI_MAX_CMD_RETRY) {
dprintf(CRITICAL, "Error: Command never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -435,12 +439,16 @@
int_status &= SDHCI_INT_STS_TRANS_COMPLETE;
if (int_status & SDHCI_INT_STS_TRANS_COMPLETE)
+ {
+ trans_complete = 1;
break;
+ }
retry++;
udelay(1000);
if (retry == SDHCI_MAX_TRANS_RETRY) {
dprintf(CRITICAL, "Error: Transfer never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -452,20 +460,41 @@
err:
/* Look for errors */
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
- if (int_status & SDHCI_ERR_INT_STAT_MASK) {
- if (sdhci_cmd_err_status(host)) {
- dprintf(CRITICAL, "Error: Command completed with errors\n");
- /* Reset the command & Data line */
- sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 1;
+
+ if (int_status & SDHCI_ERR_INT_STAT_MASK)
+ {
+ /*
+ * As per SDHC spec transfer complete has higher priority than data timeout
+ * If both transfer complete & data timeout are set then we should ignore
+ * data timeout error.
+ * ---------------------------------------------------------------------------
+ * | Transfer complete | Data timeout error | Meaning of the Status |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 0 | Interrupted by another factor |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 1 | Time out occured during transfer|
+ * |--------------------------------------------------------------------------|
+ * | 1 | Don't Care | Command execution complete |
+ * --------------------------------------------------------------------------
+ */
+ if ((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK) && trans_complete)
+ {
+ ret = 0;
}
+ else if (sdhci_cmd_err_status(host))
+ {
+ dprintf(CRITICAL, "Error: Command completed with errors\n");
+ ret = 1;
+ }
+ /* Reset Command & Dat lines on error */
+ need_reset = 1;
}
/* Reset data & command line */
- if (cmd->data_present)
+ if (cmd->data_present || need_reset)
sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 0;
+ return ret;
}
/*
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 4838b6f..0f032dd 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -346,7 +346,9 @@
HW_PLATFORM_RUMI = 15,
HW_PLATFORM_VIRTIO = 16,
HW_PLATFORM_BTS = 19,
+ HW_PLATFORM_RCM = 21,
HW_PLATFORM_DMA = 22,
+ HW_PLATFORM_STP = 23,
HW_PLATFORM_32BITS = 0x7FFFFFFF,
};
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 3aaa70f..3a66d38 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -57,8 +57,33 @@
#define FASTBOOT_MODE 0x77665500
-static void set_sdc_power_ctrl(void);
+enum cdp_subtype
+{
+ CDP_SUBTYPE_SMB349 = 0,
+ CDP_SUBTYPE_9x25_SMB349,
+ CDP_SUBTYPE_9x25_SMB1357,
+ CDP_SUBTYPE_9x35,
+ CDP_SUBTYPE_SMB1357
+};
+enum mtp_subtype
+{
+ MTP_SUBTYPE_SMB349 = 0,
+ MTP_SUBTYPE_9x25_SMB349,
+ MTP_SUBTYPE_9x25_SMB1357,
+ MTP_SUBTYPE_9x35,
+};
+
+enum rcm_subtype
+{
+ RCM_SUBTYPE_SMB349 = 0,
+ RCM_SUBTYPE_9x25_SMB349,
+ RCM_SUBTYPE_9x25_SMB1357,
+ RCM_SUBTYPE_9x35,
+ RCM_SUBTYPE_SMB1357,
+};
+
+static void set_sdc_power_ctrl(void);
static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
@@ -75,7 +100,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(7, 0, BLSP2_UART1_BASE);
#endif
}
@@ -116,6 +141,11 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
+void target_uninit(void)
+{
+ mmc_put_card_to_sleep(dev);
+}
+
/* Do target specific usb initialization */
void target_usb_init(void)
{
@@ -229,37 +259,105 @@
board->target = LINUX_MACHTYPE_UNKNOWN;
}
+void set_cdp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case CDP_SUBTYPE_9x25_SMB349:
+ case CDP_SUBTYPE_9x25_SMB1357:
+ case CDP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case CDP_SUBTYPE_SMB349:
+ case CDP_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "CDP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+
+}
+
+void set_mtp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case MTP_SUBTYPE_9x25_SMB349:
+ case MTP_SUBTYPE_9x25_SMB1357:
+ case MTP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case MTP_SUBTYPE_SMB349:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "MTP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+void set_rcm_baseband(struct board_data *board)
+{
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case RCM_SUBTYPE_9x25_SMB349:
+ case RCM_SUBTYPE_9x25_SMB1357:
+ case RCM_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case RCM_SUBTYPE_SMB349:
+ case RCM_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "RCM platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
uint32_t platform;
uint32_t platform_subtype;
+ uint32_t platform_hardware;
platform = board->platform;
- platform_subtype = board->platform_subtype;
- /*
- * Look for platform subtype if present, else
- * check for platform type to decide on the
- * baseband type
- */
- switch(platform_subtype) {
- case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ platform_hardware = board->platform_hw;
+
+ switch(platform_hardware) {
+ case HW_PLATFORM_SURF:
+ set_cdp_baseband(board);
break;
-
- default:
- dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
- ASSERT(0);
- };
-
- switch(platform) {
- case APQ8084:
+ case HW_PLATFORM_MTP:
+ set_mtp_baseband(board);
+ break;
+ case HW_PLATFORM_RCM:
+ set_rcm_baseband(board);
+ break;
+ case HW_PLATFORM_LIQUID:
board->baseband = BASEBAND_APQ;
break;
default:
- dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ dprintf(CRITICAL, "Platform :%u is not supported\n",
+ platform_hardware);
ASSERT(0);
- }
+ };
}
unsigned target_baseband()
diff --git a/target/apq8084/rules.mk b/target/apq8084/rules.mk
index aa2abf1..ef4c377 100644
--- a/target/apq8084/rules.mk
+++ b/target/apq8084/rules.mk
@@ -9,7 +9,7 @@
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0xFF00000
+SCRATCH_ADDR := 0x10000000
DEFINES += DISPLAY_SPLASH_SCREEN=0
DEFINES += DISPLAY_TYPE_MIPI=1
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index 48b145b..1121591 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -110,5 +110,4 @@
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-int mdss_dsi_auto_pll_config(struct mipi_dsi_panel_config *);
#endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index d33aa95..cc97909 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -462,6 +462,8 @@
dload_util_write_cookie(mode == NORMAL_DLOAD ?
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ pm8x41_clear_pmic_watchdog();
+
return 0;
}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 667d5bc..04e0615 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -54,6 +54,149 @@
.fdbck = 0x1
};
+static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
+{
+ uint32_t i = 0;
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ for (i = 0; (i < 4) && !pll_locked; i++) {
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ if (i != 0)
+ writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ }
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
int target_backlight_ctrl(uint8_t enable)
{
dprintf(SPEW, "target_backlight_ctrl\n");
@@ -66,6 +209,19 @@
return 0;
}
+static void dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ if (dsi_pll_enable_seq_m(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_f1(ctl_base)) {
+ } else if (dsi_pll_enable_seq_c(ctl_base)) {
+ } else if (dsi_pll_enable_seq_e(ctl_base)) {
+ } else {
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ }
+}
+
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
@@ -76,7 +232,8 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(pll_data);
+ mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
mmss_clock_auto_pll_init(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
diff --git a/target/msm8610/include/target/display.h b/target/msm8610/include/target/display.h
index 9f9f609..c6e93c4 100644
--- a/target/msm8610/include/target/display.h
+++ b/target/msm8610/include/target/display.h
@@ -102,7 +102,7 @@
#define msm8610_DSI_FEATURE_ENABLE 0
-#define MIPI_FB_ADDR 0x0D200000
+#define MIPI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 8
#define MIPI_HSYNC_BACK_PORCH_DCLK 40
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 468b6d5..ae2b01e 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -29,6 +29,66 @@
#ifndef _TARGET_COPPER_DISPLAY_H
#define _TARGET_COPPER_DISPLAY_H
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "pm8941_gpios", 19, 2, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 58, 3, 1, 0, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 22, 0, 3000000, 100000, 100, 0, 20, 0, 0},
+{ "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+{ "vdda", 2, 1, 1200000, 100000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+
#define MIPI_FB_ADDR 0x0D200000
#define EDP_FB_ADDR 0x7EF00000
diff --git a/target/msm8974/oem_panel.c b/target/msm8974/oem_panel.c
new file mode 100755
index 0000000..3ea115e
--- /dev/null
+++ b/target/msm8974/oem_panel.c
@@ -0,0 +1,151 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_toshiba_720p_video.h"
+#include "include/panel_sharp_qhd_video.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+TOSHIBA_720P_VIDEO_PANEL,
+SHARP_QHD_VIDEO_PANEL
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel spefic off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static void init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ switch (panel_id) {
+ case TOSHIBA_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &toshiba_720p_video_panel_data;
+ panelstruct->panelres = &toshiba_720p_video_panel_res;
+ panelstruct->color = &toshiba_720p_video_color;
+ panelstruct->videopanel = &toshiba_720p_video_video_panel;
+ panelstruct->commandpanel = &toshiba_720p_video_command_panel;
+ panelstruct->state = &toshiba_720p_video_state;
+ panelstruct->laneconfig = &toshiba_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &toshiba_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &toshiba_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &toshiba_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = toshiba_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TOSHIBA_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ toshiba_720p_video_timings, TIMING_SIZE);
+ break;
+ case SHARP_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &sharp_qhd_video_panel_data;
+ panelstruct->panelres = &sharp_qhd_video_panel_res;
+ panelstruct->color = &sharp_qhd_video_color;
+ panelstruct->videopanel = &sharp_qhd_video_video_panel;
+ panelstruct->commandpanel = &sharp_qhd_video_command_panel;
+ panelstruct->state = &sharp_qhd_video_state;
+ panelstruct->laneconfig = &sharp_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &sharp_qhd_video_backlight;
+ pinfo->mipi.panel_cmds
+ = sharp_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SHARP_QHD_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_qhd_video_timings, TIMING_SIZE);
+ break;
+ }
+}
+
+bool oem_panel_select(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t target_id = board_target_id();
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_SURF:
+ panel_id = TOSHIBA_720P_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_DRAGON:
+ panel_id = SHARP_QHD_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
+ return false;
+ }
+
+ init_panel_data(panelstruct, pinfo, phy_db);
+
+ return true;
+}
diff --git a/target/msm8974/rules.mk b/target/msm8974/rules.mk
index e2acd10..ab9a431 100644
--- a/target/msm8974/rules.mk
+++ b/target/msm8974/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8974
@@ -22,6 +23,7 @@
dev/keys \
dev/pmic/pm8x41 \
dev/panel/msm \
+ dev/gcdb/display \
lib/ptable \
lib/libfdt
@@ -38,4 +40,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 3c0cadd..7b35aa0 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -29,7 +29,9 @@
#include <debug.h>
#include <smem.h>
+#include <err.h>
#include <msm_panel.h>
+#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
@@ -38,15 +40,13 @@
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
static struct msm_fb_panel_data panel;
-static uint8_t display_enable;
+static uint8_t edp_enable;
-extern int msm_display_init(struct msm_fb_panel_data *pdata);
-extern int msm_display_off();
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern void edp_auo_1080p_init(struct edp_panel_data *edp_panel);
+#define HFPLL_LDO_ID 12
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0x00,
@@ -58,38 +58,85 @@
.full_current_scale = 0x19
};
-static int msm8974_backlight_on()
+static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ uint32_t rc = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+
+ while (!(readl(ctl_base + 0x02c0) & 0x01)) {
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(2);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ }
+ return rc;
+}
+
+int target_backlight_ctrl(uint8_t enable)
{
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- uint8_t slave_id = 1, i;
- struct board_pmic_data *pmic_info;
+ uint8_t slave_id = 1;
- if (platform_id == MSM8974AC)
- if ((hardware_id == HW_PLATFORM_MTP)
- || (hardware_id == HW_PLATFORM_LIQUID))
- slave_id = 3;
+ if (enable) {
+ if (platform_id == MSM8974AC)
+ if ((hardware_id == HW_PLATFORM_MTP)
+ || (hardware_id == HW_PLATFORM_LIQUID))
+ slave_id = 3;
- pm8x41_wled_config_slave_id(slave_id);
- pm8x41_wled_config(&wled_ctrl);
- pm8x41_wled_sink_control(1);
- pm8x41_wled_iled_sync_control(1);
- pm8x41_wled_enable(1);
+ pm8x41_wled_config_slave_id(slave_id);
+ pm8x41_wled_config(&wled_ctrl);
+ pm8x41_wled_sink_control(enable);
+ pm8x41_wled_iled_sync_control(enable);
+ }
+ pm8x41_wled_enable(enable);
- return 0;
+ return NO_ERROR;
}
-static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t dual_dsi = panel.panel_info.mipi.dual_dsi;
+ struct mdss_dsi_pll_config *pll_data;
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (panel.panel_info.mipi.dual_dsi &&
- !(panel.panel_info.mipi.broadcast))
+ !(panel.panel_info.mipi.broadcast)) {
mdss_dsi_uniphy_pll_config(MIPI_DSI1_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT, dual_dsi);
+ dsi_pll_enable_seq(MIPI_DSI1_BASE);
+ }
+ mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
@@ -97,34 +144,18 @@
mdp_gdsc_ctrl(enable);
}
- return 0;
-}
-
-static int msm8974_mdss_sharp_dsi_panel_clock(uint8_t enable)
-{
- if (enable) {
- mdp_gdsc_ctrl(enable);
- mdp_clock_init();
- mdss_sharp_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT);
- } else if (!target_cont_splash_screen()) {
- /* Add here for continuous splash */
- mmss_clock_disable();
- mdp_clock_disable();
- mdp_gdsc_ctrl(enable);
- }
-
- return 0;
+ return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
-static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
- uint32_t rst_gpio = 19;
+ uint32_t rst_gpio = reset_gpio.pin_id;
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- struct pm8x41_gpio gpio_param = {
+ struct pm8x41_gpio resetgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
@@ -138,65 +169,53 @@
dprintf(SPEW, "platform_id: %u, rst_gpio: %u\n",
platform_id, rst_gpio);
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
if (enable) {
- gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength, enable_gpio.pin_state);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- mdelay(5);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[0]);
+ mdelay(resetseq->sleep[0]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[1]);
+ mdelay(resetseq->sleep[1]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[2]);
+ mdelay(resetseq->sleep[2]);
} else {
- gpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ resetgpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
}
+ return NO_ERROR;
}
-static int msm8974_mipi_panel_power(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable)
{
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
- struct pm8x41_ldo ldo2 = LDO(PM8x41_LDO2, NLDO_TYPE);
- struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
- struct pm8x41_ldo ldo22 = LDO(PM8x41_LDO22, PLDO_TYPE);
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
- if (enable) {
+ dprintf(SPEW, "Setting %s\n",
+ ldo_entry_array[ldocounter].ldo_id);
- /* Enable backlight */
- msm8974_backlight_on();
-
- /* Turn on LDO8 for lcd1 mipi vdd */
- dprintf(SPEW, " Setting LDO22\n");
- pm8x41_ldo_set_voltage(&ldo22, 3000000);
- pm8x41_ldo_control(&ldo22, enable);
-
- dprintf(SPEW, " Setting LDO12\n");
- /* Turn on LDO23 for lcd1 mipi vddio */
- pm8x41_ldo_set_voltage(&ldo12, 1800000);
- pm8x41_ldo_control(&ldo12, enable);
-
- dprintf(SPEW, " Setting LDO2\n");
- /* Turn on LDO2 for vdda_mipi_dsi */
- pm8x41_ldo_set_voltage(&ldo2, 1200000);
- pm8x41_ldo_control(&ldo2, enable);
-
- dprintf(SPEW, " Panel Reset \n");
- /* Panel Reset */
- msm8974_mdss_mipi_panel_reset(enable);
- dprintf(SPEW, " Panel Reset Done\n");
- } else {
- msm8974_mdss_mipi_panel_reset(enable);
- pm8x41_wled_enable(enable);
- pm8x41_ldo_control(&ldo2, enable);
- pm8x41_ldo_control(&ldo22, enable);
-
+ /* Set voltage during power on */
+ if (enable) {
+ pm8x41_ldo_set_voltage(&ldo_entry,
+ ldo_entry_array[ldocounter].ldo_voltage);
+ pm8x41_ldo_control(&ldo_entry, enable);
+ } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
}
- return 0;
+ return NO_ERROR;
}
static int msm8974_mdss_edp_panel_clock(int enable)
@@ -256,40 +275,7 @@
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
- uint32_t soc_ver = board_soc_version();
-
- dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
-
switch (hw_id) {
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_FLUID:
- case HW_PLATFORM_SURF:
- mipi_toshiba_video_720p_init(&(panel.panel_info));
- panel.clk_func = msm8974_mdss_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
- case HW_PLATFORM_DRAGON:
- mipi_sharp_video_qhd_init(&(panel.panel_info));
- wled_ctrl.ovp = 0x0; /* 35V */
- wled_ctrl.full_current_scale = 0x14; /* 20mA */
- wled_ctrl.max_duty_cycle = 0; /* 26ns */
- panel.clk_func = msm8974_mdss_sharp_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
panel.clk_func = msm8974_mdss_edp_panel_clock;
@@ -297,21 +283,30 @@
panel.fb.base = (void *)EDP_FB_ADDR;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
+
+ if (msm_display_init(&panel)) {
+ dprintf(CRITICAL, "edp init failed!\n");
+ return;
+ }
+
+ edp_enable = 1;
break;
default:
- return;
- };
-
- if (msm_display_init(&panel)) {
- dprintf(CRITICAL, "Display init failed!\n");
- return;
+ gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ break;
}
-
- display_enable = 1;
}
void display_shutdown(void)
{
- if (display_enable)
- msm_display_off();
+ uint32_t hw_id = board_hardware_id();
+ switch (hw_id) {
+ case HW_PLATFORM_LIQUID:
+ if (edp_enable)
+ msm_display_off();
+ break;
+ default:
+ gcdb_display_shutdown();
+ break;
+ }
}