dev : qpnp_wled : Fix configuration of avdd_trim registers
Update the sequence to configure the trim register and the OVP
register based on predetermined values mapped to the target voltage.
Change-Id: Iaf53f2cafca0a4f62eb06e89468b53ca18e5202c
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
index 64e85e0..d90ca0b 100644
--- a/dev/qpnp_wled/include/qpnp_wled.h
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -47,8 +47,11 @@
#define QPNP_WLED_VLOOP_COMP_RES(b) (b + 0x55)
#define QPNP_WLED_VLOOP_COMP_GM(b) (b + 0x56)
#define QPNP_WLED_PSM_CTRL(b) (b + 0x5B)
-#define QPNP_WLED_TEST4(b) (b + 0xE5)
+#define QPNP_WLED_TEST4(b) (b + 0xE5)
+#define QPNP_WLED_CTRL_SPARE_REG(b) (b + 0xDF)
+#define QPNP_WLED_REF_7P7_TRIM_REG(b) (b + 0xF2)
+#define QPNP_WLED_7P7_TRIM_MASK 0xF
#define QPNP_WLED_EN_MASK 0x7F
#define QPNP_WLED_EN_SHIFT 7
#define QPNP_WLED_FDBK_OP_MASK 0xF8
@@ -183,6 +186,19 @@
#define PWRDN_DLY2_MASK 0x3
+#define NUM_SUPPORTED_AVDD_VOLTAGES 6
+
+/* Supported values 7900, 7600, 7300, 6400, 6100, 5800 */
+#if TARGET_QPNP_WLED_AVDD_DEFAULT_VOLTAGE_MV
+#define QPNP_WLED_AVDD_DEFAULT_VOLTAGE_MV TARGET_QPNP_WLED_AVDD_DEFAULT_VOLTAGE_MV
+#else
+#define QPNP_WLED_AVDD_DEFAULT_VOLTAGE_MV 7600
+#endif
+
+#define QPNP_WLED_AVDD_MIN_TRIM_VALUE 0x0
+#define QPNP_WLED_AVDD_MAX_TRIM_VALUE 0xF
+#define QPNP_WLED_AVDD_SET_BIT BIT(4)
+
/* output feedback mode */
enum qpnp_wled_fdbk_op {
QPNP_WLED_FDBK_AUTO,
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
index 3aa41f8..ad2f5d5 100644
--- a/dev/qpnp_wled/qpnp_wled.c
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -34,6 +34,18 @@
#include <pm8x41_wled.h>
#include <qtimer.h>
+static int qpnp_wled_avdd_target_voltages[NUM_SUPPORTED_AVDD_VOLTAGES] = {
+ 7900, 7600, 7300, 6400, 6100, 5800,
+};
+
+static uint8_t qpnp_wled_ovp_reg_settings[NUM_SUPPORTED_AVDD_VOLTAGES] = {
+ 0x0, 0x0, 0x1, 0x2, 0x2, 0x3,
+};
+
+static int qpnp_wled_avdd_trim_adjustments[NUM_SUPPORTED_AVDD_VOLTAGES] = {
+ 3, 0, -2, 7, 3, 3,
+};
+
static int fls(uint16_t n)
{
int i = 0;
@@ -311,6 +323,44 @@
reg |= temp;
pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
+ if (wled->disp_type_amoled) {
+ for (i = 0; i < NUM_SUPPORTED_AVDD_VOLTAGES; i++) {
+ if (QPNP_WLED_AVDD_DEFAULT_VOLTAGE_MV == qpnp_wled_avdd_target_voltages[i])
+ break;
+ }
+ if (i == NUM_SUPPORTED_AVDD_VOLTAGES)
+ {
+ dprintf(CRITICAL, "Invalid avdd target voltage specified \n");
+ return ERR_NOT_VALID;
+ }
+ /* Update WLED_OVP register based on desired target voltage */
+ reg = qpnp_wled_ovp_reg_settings[i];
+ pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
+ /* Update WLED_TRIM register based on desired target voltage */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
+ reg += qpnp_wled_avdd_trim_adjustments[i];
+ if ((int8_t)reg < QPNP_WLED_AVDD_MIN_TRIM_VALUE)
+ reg = QPNP_WLED_AVDD_MIN_TRIM_VALUE;
+ else if((int8_t)reg > QPNP_WLED_AVDD_MAX_TRIM_VALUE)
+ reg = QPNP_WLED_AVDD_MAX_TRIM_VALUE;
+
+ rc = qpnp_wled_sec_access(wled, wled->ctrl_base);
+ if (rc)
+ return rc;
+
+ temp = pm8x41_wled_reg_read(
+ QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
+ temp &= ~QPNP_WLED_7P7_TRIM_MASK;
+ temp |= (reg & QPNP_WLED_7P7_TRIM_MASK);
+ pm8x41_wled_reg_write(QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base), temp);
+ /* Write to spare to avoid reconfiguration in HLOS */
+ reg = pm8x41_wled_reg_read(
+ QPNP_WLED_CTRL_SPARE_REG(wled->ctrl_base));
+ reg |= QPNP_WLED_AVDD_SET_BIT;
+ pm8x41_wled_reg_write(QPNP_WLED_CTRL_SPARE_REG(wled->ctrl_base), reg);
+ }
+
/* Configure the MODULATION register */
if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_1200_KHZ) {
wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_1200_KHZ;