Merge "target: Fix pll locking sequence for MSM8974"
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 8a5eaff..512657f 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -206,4 +206,5 @@
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
+void pm8x41_clear_pmic_watchdog(void);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 672514a..a1c2e6d 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -78,6 +78,7 @@
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
+#define PMIC_WD_RESET_S2_CTL2 0x857
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 2c14d3b..035c442 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -474,3 +474,8 @@
return batt_is_broken;
}
+
+void pm8x41_clear_pmic_watchdog(void)
+{
+ pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
+}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index d673ee0..f7a82f3 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -844,9 +844,15 @@
/* Run the clock @ 400 Mhz */
if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card))
{
- clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
/* Save the timing value, before changing the clock */
MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ /*
+ * Set the MCI_CLK divider before changing the sdcc core
+ * core clk to ensure card receives no more than 200 MHZ
+ * clock frequency
+ */
+ sdhci_msm_set_mci_clk(host);
+ clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
}
else
{
@@ -993,6 +999,10 @@
/* Save the timing value, before changing the clock */
MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+ /*
+ * Enable HS400 mode
+ */
+ sdhci_msm_set_mci_clk(host);
/* 7. Execute Tuning for hs400 mode */
if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
@@ -1691,7 +1701,16 @@
else
cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK;
- cmd.argument = blk_addr;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = blk_addr * card->block_size;
+ else
+ cmd.argument = blk_addr;
+
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_READ;
@@ -1763,7 +1782,16 @@
else
cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK;
- cmd.argument = blk_addr;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = blk_addr * card->block_size;
+ else
+ cmd.argument = blk_addr;
+
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_WRITE;
@@ -1825,7 +1853,15 @@
else
cmd.cmd_index = CMD32_ERASE_WR_BLK_START;
- cmd.argument = erase_start;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = erase_start * card->block_size;
+ else
+ cmd.argument = erase_start;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
@@ -1860,7 +1896,15 @@
else
cmd.cmd_index = CMD33_ERASE_WR_BLK_END;
- cmd.argument = erase_end;
+ /*
+ * Standard emmc cards use byte mode addressing
+ * convert the block address to byte address before
+ * sending the command
+ */
+ if (card->type == MMC_TYPE_STD_MMC)
+ cmd.argument = erase_end * card->block_size;
+ else
+ cmd.argument = erase_end;
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 632de53..98f1da0 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -172,7 +172,8 @@
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/shutdown_detect.o
endif
ifeq ($(PLATFORM),apq8084)
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 547f4ec..9c4e8ed 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -264,13 +264,6 @@
REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
- /*
- * SDHC spec does not have matching UHS mode
- * So we use Vendor specific registers to enable
- * HS400 mode
- */
- sdhci_msm_set_mci_clk(host);
-
/* Run the clock back */
sdhci_clk_supply(host, clk_val);
}
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index f551a7a..c92a34f 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -29,6 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include <debug.h>
+#include <kernel/thread.h>
#include <reg.h>
#include <sys/types.h>
#include <platform/iomap.h>
@@ -339,6 +340,8 @@
}
}
+ //We need to make sure the DM_NO_CHARS_FOR_TX&DM_TF are are programmed atmoically.
+ enter_critical_section();
/* We are here. FIFO is ready to be written. */
/* Write number of characters to be written */
writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
@@ -366,6 +369,7 @@
tx_char_left = num_of_chars - (i + 1) * 4;
tx_data = tx_data + num_chars_written;
}
+ exit_critical_section();
return MSM_BOOT_UART_DM_E_SUCCESS;
}
diff --git a/project/msm8610.mk b/project/msm8610.mk
index 3f7dcbb..5bcad33 100644
--- a/project/msm8610.mk
+++ b/project/msm8610.mk
@@ -10,6 +10,9 @@
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
+#enable power on vibrator feature
+ENABLE_PON_VIB_SUPPORT := true
+
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
DEFINES += WITH_DEBUG_LOG_BUF=1
@@ -29,6 +32,10 @@
#is with the linker and file a bug report.
ENABLE_THUMB := false
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 286ef41..2a41004 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -519,6 +519,8 @@
dload_util_write_cookie(mode == NORMAL_DLOAD ?
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ pm8x41_clear_pmic_watchdog();
+
return 0;
}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index fb6d24c..d085765 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -49,11 +49,14 @@
#include <partition_parser.h>
#include <platform/clock.h>
#include <platform/timer.h>
+#include <shutdown_detect.h>
+#include <vibrator.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
#define TLMM_VOL_UP_BTN_GPIO 72
+#define VIBRATE_TIME 250
enum target_subtype {
HW_PLATFORM_SUBTYPE_SKUAA = 1,
@@ -163,11 +166,19 @@
target_keystatus();
target_sdc_init();
+
+ shutdown_detect();
+
+ /* turn on vibrator to indicate that phone is booting up to end user */
+ vib_timed_turn_on(VIBRATE_TIME);
}
void target_uninit(void)
{
mmc_put_card_to_sleep(dev);
+
+ /* wait for the vibrator timer is expried */
+ wait_vib_timeout();
}
#define SSD_CE_INSTANCE 1
@@ -425,3 +436,21 @@
{
return dev;
}
+
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "shutdown failed\n");
+
+ ASSERT(0);
+}
diff --git a/target/msm8610/rules.mk b/target/msm8610/rules.mk
index 909e673..7ffcfe1 100644
--- a/target/msm8610/rules.mk
+++ b/target/msm8610/rules.mk
@@ -25,6 +25,7 @@
dev/pmic/pm8x41 \
dev/panel/msm \
dev/gcdb/display \
+ dev/vib \
lib/libfdt
DEFINES += \