Merge "target: msm8226: add a delay to fix fastboot reboot enumeration."
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index d1805bc..9ed4110 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -207,7 +207,7 @@
}
}
-static void clock_ce_enable(uint8_t instance)
+void clock_ce_enable(uint8_t instance)
{
int ret;
char clk_name[64];
@@ -253,7 +253,7 @@
udelay(1);
}
-static void clock_ce_disable(uint8_t instance)
+void clock_ce_disable(uint8_t instance)
{
struct clk *ahb_clk;
struct clk *cclk;
@@ -295,6 +295,7 @@
ce_async_reset(instance);
clock_ce_enable(instance);
+
}
void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index 1bb371b..6906ed2 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -72,5 +72,7 @@
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
void mdp_gdsc_ctrl(uint8_t enable);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
#endif
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 5e91af2..86f154d 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -100,6 +100,14 @@
#define MPM2_MPM_PS_HOLD 0xFC4AB000
#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
+/* CE 1 */
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
+#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
+#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
+#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
+#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
+#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
+
/* CE 2 */
#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
#define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090)
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index cb7981b..9f1e590 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -334,6 +334,59 @@
},
};
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(5),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(3),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(4),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+
struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
@@ -491,6 +544,12 @@
CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
CLK_LOOKUP("ce2_src_clk", ce2_clk_src.c),
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+
+
CLK_LOOKUP("blsp2_ahb_clk", gcc_blsp2_ahb_clk.c),
CLK_LOOKUP("blsp2_qup5_i2c_apps_clk", gcc_blsp2_qup5_i2c_apps_clk.c),
diff --git a/target/msm8226/meminfo.c b/target/msm8226/meminfo.c
index 3b92733..e5a53d2 100644
--- a/target/msm8226/meminfo.c
+++ b/target/msm8226/meminfo.c
@@ -35,8 +35,6 @@
#include <platform/iomap.h>
#include <dev_tree.h>
-#define MB (1024*1024)
-
/* Funtion to add the ram partition entries into device tree.
* The function assumes that all the entire fixed memory regions should
* be listed in the first bank of the passed in ddr regions.
@@ -56,14 +54,6 @@
if((ram_ptable.parts[i].category == SDRAM) &&
(ram_ptable.parts[i].type == SYS_MEMORY))
{
- if (ram_ptable.parts[i].start == 0x0)
- {
- /* Ensure that the size for this segment is > 1MB */
- ASSERT(ram_ptable.parts[i].size > 1*MB);
-
- ram_ptable.parts[i].start += 1*MB;
- ram_ptable.parts[i].size -= 1*MB;
- }
/* Pass along all other usable memory regions to Linux */
ret = dev_tree_add_mem_info(fdt,