target: Fix pll locking sequence for MSM8974
This change fixes several issues related to pll locking
sequence for MSM8974 target.
* Reduce the pll locking time
* Separate the pll locking sequence to BDD format.
* Update pll lock detect configuration register based on
suggestion.
Change-Id: Ie37b50abf89a23340e7a932abd9b015d259ee08b
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 62cabf0..8e4a762 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -199,10 +199,9 @@
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t ctl_base)
{
- writel(0x04, ctl_base + 0x0264); /* LKDetect CFG2 */
+ writel(0x0c, ctl_base + 0x0264); /* LKDetect CFG2 */
udelay(100);
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
- mdelay(1);
+ writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
}
void mdss_dsi_uniphy_pll_sw_reset(uint32_t ctl_base)
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 270a300..b8dc850 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -58,40 +58,76 @@
.full_current_scale = 0x19
};
-static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
+static uint32_t dsi_pll_lock_status(uint32_t ctl_base)
{
- uint32_t rc = 0;
+ uint32_t counter, status;
+ udelay(100);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+
+ status = readl(ctl_base + 0x02c0) & 0x01;
+ for (counter = 0; counter < 5 && !status; counter++) {
+ udelay(100);
+ status = readl(ctl_base + 0x02c0) & 0x01;
+ }
+
+ return status;
+}
+
+static uint32_t dsi_pll_enable_seq_b(uint32_t ctl_base)
+{
mdss_dsi_uniphy_pll_sw_reset(ctl_base);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(1);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(200);
writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(500);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(500);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ return dsi_pll_lock_status(ctl_base);
+}
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+{
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(250);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(500);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(500);
+
+ return dsi_pll_lock_status(ctl_base);
+}
+
+static void dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ uint32_t counter, status;
+
+ for (counter = 0; counter < 3; counter++) {
+ status = dsi_pll_enable_seq_b(ctl_base);
+ if (status)
+ break;
+ status = dsi_pll_enable_seq_d(ctl_base);
+ if (status)
+ break;
+ status = dsi_pll_enable_seq_d(ctl_base);
+ if(status)
+ break;
}
- return rc;
+
+ if (!status)
+ dprintf(CRITICAL, "Pll lock sequence failed\n");
}
static int msm8974_wled_backlight_ctrl(uint8_t enable)