Merge "[target/msm7630]: Add code to dynamically configure page table entries."
diff --git a/arch/arm/crt0.S b/arch/arm/crt0.S
index d5b4a32..3a3d776 100644
--- a/arch/arm/crt0.S
+++ b/arch/arm/crt0.S
@@ -20,6 +20,10 @@
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
+#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+
.text
.globl _start
_start:
@@ -144,6 +148,11 @@
strlt r2, [r0], #4
blt .L__bss_loop
+#ifdef ARM_CPU_CORTEX_A8
+ DSB
+ ISB
+#endif
+
bl kmain
b .
diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index 9ddd57f..e49d529 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -188,7 +188,7 @@
MCR p15, 0x0, r1, c15, c15, 0x2 //; write R1 to PVR0F2
//;WCP15_PVR2F0 r2
- MCR p15, 0x2, r2, c15, c15, 0x2 //; write R2 to PVR2F0
+ MCR p15, 0x2, r2, c15, c15, 0x0 //; write R2 to PVR2F0
//;WCP15_PVR2F1 r3
MCR p15, 0x2, r3, c15, c15, 0x1 //; write R3 to PVR2F1
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 085fa9e..73e465e 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -91,11 +91,72 @@
SMEM_BOARD_INFO_LOCATION = 137,
+ SMEM_USABLE_RAM_PARTITION_TABLE = 402,
+
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
- SMEM_LAST_VALID_TYPE = SMEM_BOARD_INFO_LOCATION,
+ SMEM_LAST_VALID_TYPE = SMEM_USABLE_RAM_PARTITION_TABLE,
} smem_mem_type_t;
/* Note: buf MUST be 4byte aligned, and max_len MUST be a multiple of 4. */
unsigned smem_read_alloc_entry(smem_mem_type_t type, void *buf, int max_len);
+/* SMEM RAM Partition */
+enum {
+ DEFAULT_ATTRB = ~0x0,
+ READ_ONLY = 0x0,
+ READWRITE,
+};
+
+enum {
+ DEFAULT_CATEGORY = ~0x0,
+ SMI = 0x0,
+ EBI1,
+ EBI2,
+ QDSP6,
+ IRAM,
+ IMEM,
+ EBI0_CS0,
+ EBI0_CS1,
+ EBI1_CS0,
+ EBI1_CS1,
+};
+
+enum {
+ DEFAULT_DOMAIN = 0x0,
+ APPS_DOMAIN,
+ MODEM_DOMAIN,
+ SHARED_DOMAIN,
+};
+
+struct smem_ram_ptn {
+ char name[16];
+ unsigned start;
+ unsigned size;
+
+ /* RAM Partition attribute: READ_ONLY, READWRITE etc. */
+ unsigned attr;
+
+ /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
+ unsigned category;
+
+ /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
+ unsigned domain;
+
+ /* reserved for future expansion without changing version number */
+ unsigned reserved1, reserved2, reserved3, reserved4, reserved5;
+} __attribute__ ((__packed__));
+
+struct smem_ram_ptable {
+#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
+#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
+ unsigned magic[2];
+ unsigned version;
+ unsigned reserved1;
+ unsigned len;
+ struct smem_ram_ptn parts[32];
+ unsigned buf;
+} __attribute__ ((__packed__));
+
+
+
#endif /* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index de4422d..60d0e26 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -133,3 +133,24 @@
}
}
+/* RAM Partition table from SMEM */
+int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable)
+{
+ unsigned i;
+
+ i = smem_read_alloc_entry(SMEM_USABLE_RAM_PARTITION_TABLE,
+ smem_ram_ptable, sizeof(struct smem_ram_ptable));
+ if (i != 0)
+ return 0;
+
+ if (smem_ram_ptable->magic[0] != _SMEM_RAM_PTABLE_MAGIC_1 ||
+ smem_ram_ptable->magic[1] != _SMEM_RAM_PTABLE_MAGIC_2)
+ return 0;
+
+ dprintf(INFO, "smem ram ptable found: ver: %d len: %d\n",
+ smem_ram_ptable->version, smem_ram_ptable->len);
+
+ return 1;
+}
+
+
diff --git a/target/msm7630_surf/atags.c b/target/msm7630_surf/atags.c
index 93cecd7..b5264ec 100644
--- a/target/msm7630_surf/atags.c
+++ b/target/msm7630_surf/atags.c
@@ -30,100 +30,70 @@
#include <debug.h>
#include <smem.h>
-#define EBI1_SIZE_60M 0x03C00000
-#define EBI1_ADDR_2M 0x00200000
-#define EBI0_SIZE_14M 0x00E00000
-#define EBI0_ADDR_114M 0x07200000
-#define EBI0_SIZE_8M 0x00800000
-#define EBI0_ADDR_120M 0x07800000
-#define EBI1_SIZE_128M 0x08000000
#define EBI1_ADDR_128M 0x08000000
-#define EBI1_ADDR_1G 0x40000000
+#define SIZE_1M 0x00100000
-static int msm7x30_lpddr1 = -1;
-static int target_is_msm7x30_lpddr1(void);
-int target_is_emmc_boot(void);
-int target_is_msm7x30_lpddr1(void)
-{
- struct smem_board_info_v4 board_info_v4;
- unsigned int board_info_len = 0;
- unsigned smem_status;
- char *build_type;
- unsigned format = 0;
-
- if (msm7x30_lpddr1 != -1)
- {
- return msm7x30_lpddr1;
- }
-
- smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
- &format, sizeof(format), 0);
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for offset entry\n");
- }
-
- if ((format == 3) || (format == 4))
- {
- if (format == 4)
- board_info_len = sizeof(board_info_v4);
- else
- board_info_len = sizeof(board_info_v4.board_info_v3);
-
- smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
- &board_info_v4, board_info_len);
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for Hardware Platform\n");
- }
- }
-
- msm7x30_lpddr1 = 1;
-
- build_type = (char *)(board_info_v4.board_info_v3.build_id) + 8;
- if (*build_type == 'A')
- {
- msm7x30_lpddr1 = 0;
- }
-
- return msm7x30_lpddr1;
-}
+static int scratch_addr = -1;
+int smem_ram_ptable_init(struct smem_ram_ptable *);
unsigned* target_atag_mem(unsigned* ptr)
{
- /* ATAG_MEM for 51MB + [6MB if nand boot] + 128MB setup */
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = EBI1_SIZE_60M;
- *ptr++ = EBI1_ADDR_2M;
+ struct smem_ram_ptable ram_ptable;
+ unsigned i = 0;
- /* Reclaim EFS partition used in EMMC for NAND boot */
- if (target_is_emmc_boot())
+ if (smem_ram_ptable_init(&ram_ptable))
{
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = EBI0_SIZE_8M;
- *ptr++ = EBI0_ADDR_120M;
+ for (i = 0; i < ram_ptable.len; i++)
+ {
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].start != 0x0)
+ && (!(ram_ptable.parts[i].size < SIZE_1M)))
+ {
+ /* ATAG_MEM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ *ptr++ = ram_ptable.parts[i].size;
+ *ptr++ = ram_ptable.parts[i].start;
+ }
+ }
}
else
{
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = EBI0_SIZE_14M;
- *ptr++ = EBI0_ADDR_114M;
+ dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
+ ASSERT(0);
}
- /* ATAG_MEM */
- *ptr++ = 4;
- *ptr++ = 0x54410002;
- *ptr++ = EBI1_SIZE_128M;
- *ptr++ = (target_is_msm7x30_lpddr1()) ? EBI1_ADDR_128M : EBI1_ADDR_1G;
-
return ptr;
}
void *target_get_scratch_address(void)
{
- return (void *)((target_is_msm7x30_lpddr1()) ? EBI1_ADDR_128M : EBI1_ADDR_1G);
+ struct smem_ram_ptable ram_ptable;
+ unsigned i = 0;
+
+ if (smem_ram_ptable_init(&ram_ptable))
+ {
+ for (i = 0; i < ram_ptable.len; i++)
+ {
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].start != 0x0))
+ {
+ if (ram_ptable.parts[i].size >= FASTBOOT_BUF_SIZE)
+ {
+ scratch_addr = ram_ptable.parts[i].start;
+ break;
+ }
+ }
+ }
+ }
+ else
+ {
+ dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
+ ASSERT(0);
+ }
+
+ return (void *)((scratch_addr == -1) ? EBI1_ADDR_128M : scratch_addr);
}
diff --git a/target/msm7630_surf/rules.mk b/target/msm7630_surf/rules.mk
index 6f2e5db..a5647aa 100644
--- a/target/msm7630_surf/rules.mk
+++ b/target/msm7630_surf/rules.mk
@@ -7,12 +7,13 @@
MEMBASE := 0x00000000 # EBI
MEMSIZE := 0x00100000 # 1MB
-BASE_ADDR := 0x00200000
+BASE_ADDR := 0x00200000
-TAGS_ADDR := BASE_ADDR+0x00000100
-KERNEL_ADDR := BASE_ADDR+0x00008000
-RAMDISK_ADDR := BASE_ADDR+0x01000000
-SCRATCH_ADDR := 0x08008000
+TAGS_ADDR := BASE_ADDR+0x00000100
+KERNEL_ADDR := BASE_ADDR+0x00008000
+RAMDISK_ADDR := BASE_ADDR+0x01000000
+SCRATCH_ADDR := 0x08008000
+FASTBOOT_BUF_SIZE := 0x07800000
KEYS_USE_GPIO_KEYPAD := 1
@@ -29,7 +30,8 @@
TAGS_ADDR=$(TAGS_ADDR) \
KERNEL_ADDR=$(KERNEL_ADDR) \
RAMDISK_ADDR=$(RAMDISK_ADDR) \
- SCRATCH_ADDR=$(SCRATCH_ADDR)
+ SCRATCH_ADDR=$(SCRATCH_ADDR) \
+ FASTBOOT_BUF_SIZE=$(FASTBOOT_BUF_SIZE)
OBJS += \