platform: msm_shared: do phy reset as part of init sequence
The 20 nm DSI PHY init sequence was missing the phy software
reset which may result in display corruption during bootup.
Fix this by adding phy software reset to the init sequence.
Change-Id: I237b1a3d827dc71bbe94a2a3f0a53cf4180b3973
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 845c495..df45ba6 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -277,8 +277,7 @@
int rdbk_len);
int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
struct mdss_dsi_pll_config *pd);
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t spll_base,
- struct mdss_dsi_pll_config *pd);
+void mdss_dsi_auto_pll_20nm_config(struct msm_panel_info *pinfo);
void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index e6f326f..890f253 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -281,9 +281,16 @@
}
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t spll_base,
- struct mdss_dsi_pll_config *pd)
+void mdss_dsi_auto_pll_20nm_config(struct msm_panel_info *pinfo)
{
+ struct mdss_dsi_pll_config *pd = pinfo->mipi.dsi_pll_config;
+ uint32_t pll_base = pinfo->mipi.pll_base;
+ uint32_t spll_base = pinfo->mipi.spll_base;
+
+ mdss_dsi_phy_sw_reset(pinfo->mipi.ctl_base);
+ if (pinfo->mipi.dual_dsi)
+ mdss_dsi_phy_sw_reset(pinfo->mipi.sctl_base);
+
/*
* For 20nm PHY, the DSI PLL which is not powered on to drive a panel
* drains some current in its reset state.
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 8b3b977..96754b7 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -421,8 +421,7 @@
goto clks_disable;
}
- mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_base,
- pinfo->mipi.spll_base, pll_data);
+ mdss_dsi_auto_pll_20nm_config(pinfo);
if (!dsi_pll_20nm_enable_seq(pinfo->mipi.pll_base)) {
ret = ERROR;