platform: msm8994: support selectively enabling DSI branch clocks
Add support to configure DSI0 or DSI1 branch clocks as part of the
existing clock API. This enables configuring either one of them
independently or both of them together to support dual-dsi use cases.
Change-Id: Icbaa34c6fc7d275a9a49ac6a4afb9c6194fd5e4c
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index e170046..6b77ea0 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -448,41 +448,39 @@
clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
}
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags,
uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
- /* Configure Byte clock -autopll- This will not change because
- byte clock does not need any divider*/
- writel(0x100, DSI_BYTE0_CFG_RCGR);
- writel(0x1, DSI_BYTE0_CMD_RCGR);
- writel(0x1, DSI_BYTE0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ /* Enable DSI0 branch clocks */
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
- /* Configure Pixel clock */
- writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
- writel(pclk0_m, DSI_PIXEL0_M);
- writel(pclk0_n, DSI_PIXEL0_N);
- writel(pclk0_d, DSI_PIXEL0_D);
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
- /* Configure ESC clock */
- ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
- if(ret)
- {
- dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
- ASSERT(0);
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
- if (dual_dsi) {
- /* Configure Byte 1 clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
+ /* Enable DSI1 branch clocks */
writel(0x100, DSI_BYTE1_CFG_RCGR);
writel(0x1, DSI_BYTE1_CMD_RCGR);
writel(0x1, DSI_BYTE1_CBCR);
- /* Configure Pixel clock */
writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);
@@ -491,7 +489,6 @@
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
- /* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
if(ret)
{
@@ -501,15 +498,15 @@
}
}
-void mmss_dsi_clock_disable(uint32_t dual_dsi)
+void mmss_dsi_clock_disable(uint32_t flags)
{
- /* Disable ESC clock */
- clk_disable(clk_get("mdss_esc0_clk"));
- writel(0x0, DSI_BYTE0_CBCR);
- writel(0x0, DSI_PIXEL0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_BYTE0_CBCR);
+ writel(0x0, DSI_PIXEL0_CBCR);
+ }
- if (dual_dsi) {
- /* Disable ESC clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
clk_disable(clk_get("mdss_esc1_clk"));
writel(0x0, DSI_BYTE1_CBCR);
writel(0x0, DSI_PIXEL1_CBCR);
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index c50fef7..578e56e 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -100,6 +100,9 @@
#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
+#define MMSS_DSI_CLKS_FLAG_DSI0 BIT(0)
+#define MMSS_DSI_CLKS_FLAG_DSI1 BIT(1)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 171f3d6..89579d8 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -266,7 +266,17 @@
{
uint32_t ret;
struct mdss_dsi_pll_config *pll_data;
- uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ uint32_t flags;
+
+ if (pinfo->dest == DISPLAY_2) {
+ flags = MMSS_DSI_CLKS_FLAG_DSI1;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI0;
+ } else {
+ flags = MMSS_DSI_CLKS_FLAG_DSI0;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI1;
+ }
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
@@ -286,13 +296,13 @@
mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
- mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
- mmss_dsi_clock_disable(dual_dsi);
+ mmss_dsi_clock_disable(flags);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);