Merge "target: msm8994: Disable default splash on DB8094"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 9482806..de8948e 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -493,7 +493,10 @@
if (boot_dev_buf)
free(boot_dev_buf);
- dprintf(INFO, "cmdline: %s\n", cmdline_final ? cmdline_final : "");
+ if (cmdline_final)
+ dprintf(INFO, "cmdline: %s\n", cmdline_final);
+ else
+ dprintf(INFO, "cmdline is NULL\n");
return cmdline_final;
}
@@ -1080,7 +1083,7 @@
imagesize_actual = (page_size + kernel_actual + ramdisk_actual);
#endif
- if (check_aboot_addr_range_overlap(image_addr, imagesize_actual))
+ if (check_aboot_addr_range_overlap((uint32_t) image_addr, imagesize_actual))
{
dprintf(CRITICAL, "Boot image buffer address overlaps with aboot addresses.\n");
return -1;
@@ -1103,7 +1106,7 @@
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
#ifdef TZ_SAVE_KERNEL_HASH
- aboot_save_boot_hash_mmc(image_addr, imagesize_actual);
+ aboot_save_boot_hash_mmc((uint32_t) image_addr, imagesize_actual);
#endif /* TZ_SAVE_KERNEL_HASH */
/* Move kernel, ramdisk and device tree to correct address */
@@ -2166,10 +2169,10 @@
void cmd_flash_mmc(const char *arg, void *data, unsigned sz)
{
sparse_header_t *sparse_header;
- /* 8 Byte Magic + 2048 Byte xml + Encrypted Data */
- unsigned int *magic_number = (unsigned int *) data;
#ifdef SSD_ENABLE
+ /* 8 Byte Magic + 2048 Byte xml + Encrypted Data */
+ unsigned int *magic_number = (unsigned int *) data;
int ret=0;
uint32 major_version=0;
uint32 minor_version=0;
@@ -2841,7 +2844,7 @@
#endif
target_crypto_init_params();
- hash_find(image_addr, image_size, (unsigned char *)&digest, auth_algo);
+ hash_find((unsigned char *) image_addr, image_size, (unsigned char *)&digest, auth_algo);
save_kernel_hash_cmd(digest);
dprintf(INFO, "aboot_save_boot_hash_mmc: imagesize_actual size %d bytes.\n", (int) image_size);
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index cff176f..646d575 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -97,7 +97,6 @@
static uint32_t calculate_div3(uint8_t bpp, uint8_t num_of_lanes)
{
- uint32_t ret = NO_ERROR;
pll_data.pclk_m = 0x1; /* M = 1, N= 1 */
pll_data.pclk_n = 0xFF; /* ~ (N-M) = 0xff */
pll_data.pclk_d = 0xFF; /* ~N = 0xFF */
@@ -138,6 +137,7 @@
}
pll_data.posdiv3--; /* Register needs one value less */
+ return NO_ERROR;
}
static uint32_t calculate_dec_frac_start()
@@ -165,13 +165,11 @@
dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
+ return NO_ERROR;
}
static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
{
- uint8_t counter = 0;
- uint32_t temprate = 0;
-
/* If half bitclock is more than VCO min value */
if (pll_data.halfbit_clock > VCO_MIN_CLOCK) {
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 2066e4d..7d97842 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -30,11 +30,13 @@
#include <debug.h>
#include <err.h>
#include <smem.h>
+#include <clock.h>
#include <msm_panel.h>
#include <string.h>
#include <stdlib.h>
#include <board.h>
#include <mdp5.h>
+#include <qtimer.h>
#include <platform/gpio.h>
#include <mipi_dsi.h>
@@ -199,6 +201,7 @@
char *default_str;
int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+ char *sctl_string;
panel_name += strspn(panel_name, " ");
@@ -254,7 +257,12 @@
arg_size = prefix_string_len + dsi_id_len + panel_node_len +
LK_OVERRIDE_PANEL_LEN + 1;
- arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
+ if (!strcmp(panelstruct.paneldata->panel_destination, "DISPLAY_2"))
+ sctl_string = DSI_0_STRING;
+ else
+ sctl_string = DSI_1_STRING;
+
+ arg_size += strlen(sctl_string) + slave_panel_node_len;
if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
@@ -277,12 +285,11 @@
pbuf += panel_node_len;
buf_size -= panel_node_len;
- strlcpy(pbuf, DSI_1_STRING, buf_size);
- pbuf += DSI_1_STRING_LEN;
- buf_size -= DSI_1_STRING_LEN;
+ strlcpy(pbuf, sctl_string, buf_size);
+ pbuf += strlen(sctl_string);
+ buf_size -= strlen(sctl_string);
strlcpy(pbuf, slave_panel_node, buf_size);
}
-end:
return ret;
}
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 3b112e3..f18ecea 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -43,9 +43,6 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
-#define DSI_1_STRING ":1:"
-#define DSI_1_STRING_LEN 3
-
/*---------------------------------------------------------------------------*/
/* API */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index ca392ff..6250427 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -42,6 +42,11 @@
#define LK_OVERRIDE_PANEL "1:"
#define LK_OVERRIDE_PANEL_LEN 2
+#define DSI_0_STRING ":0:"
+#define DSI_0_STRING_LEN 3
+#define DSI_1_STRING ":1:"
+#define DSI_1_STRING_LEN 3
+
#define NO_PANEL_CONFIG "none"
#define SIM_VIDEO_PANEL "sim_video_panel"
#define SIM_DUALDSI_VIDEO_PANEL "sim_dualdsi_video_panel"
@@ -61,7 +66,7 @@
/*---------------------------------------------------------------------------*/
/*GPIO pin structure to define reset pin, enable pin, te pin, etc. */
-typedef struct gpio_pin{
+struct gpio_pin{
char *pin_source;
uint32_t pin_id;
@@ -72,7 +77,7 @@
};
/*LDO entry structure for different LDO entries. */
-typedef struct ldo_entry{
+struct ldo_entry{
char *ldo_name;
uint32_t ldo_id;
uint32_t ldo_type;
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index c21383e..e20b76a 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -39,7 +39,7 @@
#define TOTAL_RESET_GPIO_CTRL 5
/*---------------------------------------------------------------------------*/
-/* panel type
+/* panel type */
/*---------------------------------------------------------------------------*/
enum {
PANEL_TYPE_UNKNOWN,
@@ -53,7 +53,7 @@
/*---------------------------------------------------------------------------*/
/*Panel Configuration */
-typedef struct panel_config{
+struct panel_config{
char *panel_node_id;
char *panel_controller;
@@ -78,7 +78,7 @@
char *slave_panel_node_id;
};
-typedef struct panel_resolution{
+struct panel_resolution{
uint16_t panel_width;
uint16_t panel_height;
@@ -100,7 +100,7 @@
uint16_t invert_hsync_polarity;
};
-typedef struct color_info{
+struct color_info{
uint8_t color_format;
uint8_t color_order;
uint8_t underflow_color;
@@ -109,12 +109,12 @@
uint8_t pixel_alignment;
};
-typedef struct command_state {
+struct command_state {
uint8_t oncommand_state;
uint8_t offcommand_state;
};
-typedef struct videopanel_info {
+struct videopanel_info {
uint8_t hsync_pulse;
uint8_t hfp_power_mode;
uint8_t hbp_power_mode;
@@ -126,7 +126,7 @@
uint32_t bllp_eof_power;
};
-typedef struct commandpanel_info {
+struct commandpanel_info {
uint8_t techeck_enable;
uint8_t tepin_select;
uint8_t teusing_tepin;
@@ -141,7 +141,7 @@
uint32_t cmdmode_idletime;
};
-typedef struct lane_configuration {
+struct lane_configuration {
uint8_t dsi_lanes;
uint8_t dsi_lanemap;
uint8_t lane0_state;
@@ -150,7 +150,7 @@
uint8_t lane3_state;
};
-typedef struct panel_timing {
+struct panel_timing {
uint8_t dsi_mdp_trigger;
uint8_t dsi_dma_trigger;
uint8_t tclk_post;
@@ -163,13 +163,13 @@
BL_DCS,
};
-typedef struct panel_reset_sequence {
+struct panel_reset_sequence {
uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
uint8_t pin_direction;
};
-typedef struct backlight {
+struct backlight {
uint16_t bl_interface_type;
uint16_t bl_min_level;
uint16_t bl_max_level;
@@ -178,7 +178,7 @@
char *bl_pmic_model;
};
-typedef struct fb_compression {
+struct fb_compression {
uint32_t enabled;
uint32_t comp_ratio;
uint32_t comp_mode;
@@ -196,6 +196,10 @@
uint32_t lossy_mode_thd;
uint32_t lossy_rgb_thd;
uint32_t lossy_mode_idx;
+
+ uint32_t slice_height;
+ uint32_t pred_mode;
+ uint32_t max_pred_err;
};
#endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
index ea638cf..528cb26 100755
--- a/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
+++ b/dev/gcdb/display/include/panel_hx8379a_truly_fwvga_video.h
@@ -44,7 +44,7 @@
/*---------------------------------------------------------------------------*/
static struct panel_config hx8379a_truly_fwvga_video_panel_data = {
"qcom,mdss_dsi_hx8379a_truly_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ""
};
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_jdi_1080p_video.h b/dev/gcdb/display/include/panel_jdi_1080p_video.h
index bcee0c1..2dbc2ba 100755
--- a/dev/gcdb/display/include/panel_jdi_1080p_video.h
+++ b/dev/gcdb/display/include/panel_jdi_1080p_video.h
@@ -47,7 +47,7 @@
static struct panel_config jdi_1080p_video_panel_data = {
"qcom,mdss_dsi_jdi_1080p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, ""
};
/*---------------------------------------------------------------------------*/
@@ -90,11 +90,11 @@
static struct mipi_dsi_cmd jdi_1080p_video_on_command[] = {
-{ 0x4 , jdi_1080p_video_on_cmd0},
-{ 0x4 , jdi_1080p_video_on_cmd1},
-{ 0x4 , jdi_1080p_video_on_cmd2},
-{ 0x4 , jdi_1080p_video_on_cmd3},
-{ 0x4 , jdi_1080p_video_on_cmd4}
+{ 0x4 , jdi_1080p_video_on_cmd0, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd1, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd2, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd3, 0x0},
+{ 0x4 , jdi_1080p_video_on_cmd4, 0x0}
};
#define JDI_1080P_VIDEO_ON_COMMAND 5
@@ -110,8 +110,8 @@
static struct mipi_dsi_cmd jdi_1080p_video_off_command[] = {
-{ 0x4 , jdi_1080p_videooff_cmd0},
-{ 0x4 , jdi_1080p_videooff_cmd1}
+{ 0x4 , jdi_1080p_videooff_cmd0, 0},
+{ 0x4 , jdi_1080p_videooff_cmd1, 0}
};
#define JDI_1080P_VIDEO_OFF_COMMAND 2
@@ -152,14 +152,6 @@
0xe7, 0x36, 0x24, 0x00, 0x66, 0x6a, 0x2a, 0x3a, 0x2d, 0x03, 0x04, 0x00
};
-
-
-static struct mipi_dsi_cmd jdi_1080p_video_rotation[] = {
-
-};
-#define JDI_1080P_VIDEO_ROTATION 0
-
-
static struct panel_timing jdi_1080p_video_timing_info = {
0x0, 0x04, 0x04, 0x1b
};
diff --git a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
index 5f5e5d3..8c9cbce 100644
--- a/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_4k_dualdsi_video.h
@@ -159,7 +159,7 @@
};
static struct fb_compression jdi_4k_dualdsi_video_fbc = {
- 1, 2, 1, 1, 2, 1, 1, 1, 1200, 5, 91, 0x200, 192, 4, 3
+ 1, 2, 1, 1, 2, 1, 1, 1, 1200, 5, 91, 0x200, 192, 4, 3, 0, 0, 0
};
#endif /*_PANEL_JDI_4K_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
new file mode 100644
index 0000000..846a56d
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_cmd.h
@@ -0,0 +1,261 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_CMD_H_
+#define _PANEL_NT35597_WQXGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_cmd_panel_data = {
+ "qcom,dsi_nt35597_wqxga_cmd", /* panel_node_id */
+ "dsi:1:", /* panel_controller */
+ "qcom,mdss-dsi-panel", /* panel_compatible */
+ 11, /* panel_interface */
+ 1, /* panel_type */
+ "DISPLAY_1", /* panel_destination */
+ 0, /* panel_orientation */
+ 0, /* panel_clockrate */
+ 60, /* panel_framerate */
+ 0, /* panel_channelid */
+ 0, /* dsi_virtualchannel_id */
+ 0, /* panel_broadcast_mode */
+ 0, /* panel_lp11_init */
+ 0, /* panel_init_delay */
+ 0, /* dsi_stream */
+ 0, /* interleave_mode */
+ 0, /* panel_bitclock_freq */
+ 0, /* panel_operating_mode */
+ 0, /* panel_with_enable_gpio */
+ 0, /* mode_gpio_state */
+ 0, /* slave_panel_node_id */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_cmd_panel_res = {
+ 1440, /* panel_width */
+ 2560, /* panel_height */
+ 152, /* hfront_porch */
+ 160, /* hback_porch */
+ 12, /* hpulse_width */
+ 0, /* hsync_skew */
+ 10, /* vfront_porch */
+ 9, /* vback_porch */
+ 1, /* vpulse_width */
+ 0, /* hleft_border */
+ 0, /* hright_border */
+ 0, /* vtop_border */
+ 0, /* vbottom_border */
+ 0, /* hactive_res */
+ 0, /* uint16_t vactive_res */
+ 0, /* invert_data_polarity */
+ 0, /* invert_vsync_polarity */
+ 0, /* invert_hsync_polarity */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_cmd_color = {
+ 24, /* color_format */
+ 0, /* color_order */
+ 0xff, /* underflow_color */
+ 0, /* border_color */
+ 0, /* pixel_packing */
+ 0, /* pixel_alignment */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_cmd_on_cmd0[] = {
+ 0xff, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd1[] = {
+ 0xbb, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd2[] = {
+ 0x06, 0x00, 0x39, 0x80,
+ 0x3b, 0x03, 0x09, 0x0a,
+ 0x98, 0xa0,
+};
+
+static char nt35597_wqxga_cmd_on_cmd3[] = {
+ 0xe5, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_cmd_on_cmd4[] = {
+ 0xc0, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd5[] = {
+ 0xfb, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_cmd_on_cmd6[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_cmd_on_cmd7[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_cmd_on_command[] = {
+ {0x4, nt35597_wqxga_cmd_on_cmd0, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd1, 0x00},
+ {0xA, nt35597_wqxga_cmd_on_cmd2, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd3, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd4, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd5, 0x00},
+ {0x4, nt35597_wqxga_cmd_on_cmd6, 0x78},
+ {0x4, nt35597_wqxga_cmd_on_cmd7, 0x78}
+};
+
+#define NT35597_WQXGA_CMD_ON_COMMAND 8
+
+
+static char nt35597_wqxga_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_cmd_off_command[] = {
+ {0x4, nt35597_wqxga_cmdoff_cmd0, 0x02},
+ {0x4, nt35597_wqxga_cmdoff_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_CMD_OFF_COMMAND 2
+
+
+static struct command_state nt35597_wqxga_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_cmd_command_panel = {
+ //1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+ 0, /* techeck_enable*/
+ 0, /* tepin_select */
+ 0, /* teusing_tepin */
+ 0, /* autorefresh_enable */
+ 0, /* autorefresh_framenumdiv */
+ 0x2c, /* tevsync_rdptr_irqline */
+ 0, /* tevsync_continue_lines */
+ 0, /* tevsync_startline_divisor */
+ 0, /* tepercent_variance */
+ 0, /* tedcs_command */
+ 0, /* disable_eotafter_hsxfer */
+ 0, /* cmdmode_idletime */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_cmd_video_panel = {
+ 0, /* hsync_pulse */
+ 0, /* hfp_power_mode */
+ 0, /* hbp_power_mode */
+ 0, /* hsa_power_mode */
+ 1, /* bllp_eof_power_mode */
+ 1, /* bllp_power_mode */
+ 1, /* traffic_mode */
+ 0, /* dma_delayafter_vsync */
+ 0x9, /* bllp_eof_power */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_cmd_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_cmd_timings[] = {
+ 0xC4, 0x2E, 0x20, 0x00, 0x5C, 0x5E, 0x24, 0x32, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35597_wqxga_cmd_timing_info = {
+ 0x00, /* dsi_mdp_trigger */
+ 0x04, /* dsi_dma_trigger */
+ 0x03, /* tclk_post */
+ 0x25 /* tclk_pre */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_cmd_reset_seq = {
+ {1, 0, 1, }, {10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_cmd_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+static struct fb_compression nt35597_wqxga_cmd_fbc = {
+ 1, /* enabled */
+ 3, /* comp_ratio */
+ 1, /* comp_mode */
+ 1, /* qerr_enable */
+ 2, /* cd_bias */
+ 1, /* pat_enable */
+ 1, /* vlc_enable */
+ 1, /* bflc_enable */
+ 900, /* line_x_budget */
+ 5, /* block_x_budget */
+ 59, /* block_budget */
+ 0x200, /* lossless_mode_thd */
+ 192, /* lossy_mode_thd */
+ 4, /* lossy_rgb_thd */
+ 3, /* lossy_mode_idx */
+ 4, /* slice_height */
+ 1, /* pred_mode */
+ 2, /* max_pred_err */
+};
+
+#endif /*_PANEL_NT35597_WQXGA_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
new file mode 100644
index 0000000..8d93e2a
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_video.h
@@ -0,0 +1,249 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_VIDEO_H_
+#define _PANEL_NT35597_WQXGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_video_panel_data = {
+ "qcom,dsi_nt35597_wqxga_video", /* panel_node_id */
+ "dsi:1:", /* panel_controller */
+ "qcom,mdss-dsi-panel", /* panel_compatible */
+ 10, /* panel_interface */
+ 0, /* panel_type */
+ "DISPLAY_1", /* panel_destination */
+ 0, /* panel_orientation */
+ 0, /* panel_clockrate */
+ 60, /* panel_framerate */
+ 0, /* panel_channelid */
+ 0, /* dsi_virtualchannel_id */
+ 0, /* panel_broadcast_mode */
+ 0, /* panel_lp11_init */
+ 0, /* panel_init_delay */
+ 0, /* dsi_stream */
+ 0, /* interleave_mode */
+ 0, /* panel_bitclock_freq */
+ 0, /* panel_operating_mode */
+ 0, /* panel_with_enable_gpio */
+ 0, /* mode_gpio_state */
+ 0, /* slave_panel_node_id */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_video_panel_res = {
+ 1440, /* panel_width */
+ 2560, /* panel_height */
+ 152, /* hfront_porch */
+ 160, /* hback_porch */
+ 12, /* hpulse_width */
+ 0, /* hsync_skew */
+ 10, /* vfront_porch */
+ 9, /* vback_porch */
+ 1, /* vpulse_width */
+ 0, /* hleft_border */
+ 0, /* hright_border */
+ 0, /* vtop_border */
+ 0, /* vbottom_border */
+ 0, /* hactive_res */
+ 0, /* uint16_t vactive_res */
+ 0, /* invert_data_polarity */
+ 0, /* invert_vsync_polarity */
+ 0, /* invert_hsync_polarity */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_video_color = {
+ 24, /* color_format */
+ 0, /* color_order */
+ 0xff, /* underflow_color */
+ 0, /* border_color */
+ 0, /* pixel_packing */
+ 0, /* pixel_alignment */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_video_on_cmd0[] = {
+ 0xff, 0x10, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd1[] = {
+ 0xbb, 0x03, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd2[] = {
+ 0x06, 0x00, 0x39, 0x80,
+ 0x3b, 0x03, 0x09, 0x0a,
+ 0x98, 0xa0,
+};
+
+static char nt35597_wqxga_video_on_cmd3[] = {
+ 0xe5, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_video_on_cmd4[] = {
+ 0xc0, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd5[] = {
+ 0xfb, 0x01, 0x15, 0x80,
+};
+
+static char nt35597_wqxga_video_on_cmd6[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_video_on_cmd7[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_video_on_command[] = {
+ {0x4, nt35597_wqxga_video_on_cmd0, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd1, 0x00},
+ {0xA, nt35597_wqxga_video_on_cmd2, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd3, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd4, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd5, 0x00},
+ {0x4, nt35597_wqxga_video_on_cmd6, 0x78},
+ {0x4, nt35597_wqxga_video_on_cmd7, 0x78}
+};
+
+#define NT35597_WQXGA_VIDEO_ON_COMMAND 8
+
+
+static char nt35597_wqxga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_video_off_command[] = {
+ {0x4, nt35597_wqxga_videooff_cmd0, 0x02},
+ {0x4, nt35597_wqxga_videooff_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35597_wqxga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_video_video_panel = {
+ 0, /* hsync_pulse */
+ 0, /* hfp_power_mode */
+ 0, /* hbp_power_mode */
+ 0, /* hsa_power_mode */
+ 1, /* bllp_eof_power_mode */
+ 1, /* bllp_power_mode */
+ 1, /* traffic_mode */
+ 0, /* dma_delayafter_vsync */
+ 0x9, /* bllp_eof_power */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_video_timings[] = {
+ 0xC4, 0x2E, 0x20, 0x00, 0x5C, 0x5E, 0x24, 0x32, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35597_wqxga_video_timing_info = {
+ 0x00, /* dsi_mdp_trigger */
+ 0x04, /* dsi_dma_trigger */
+ 0x03, /* tclk_post */
+ 0x25 /* tclk_pre */
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_video_reset_seq = {
+ {1, 0, 1, }, {10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_video_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+static struct fb_compression nt35597_wqxga_video_fbc = {
+ 1, /* enabled */
+ 3, /* comp_ratio */
+ 1, /* comp_mode */
+ 1, /* qerr_enable */
+ 2, /* cd_bias */
+ 1, /* pat_enable */
+ 1, /* vlc_enable */
+ 1, /* bflc_enable */
+ 900, /* line_x_budget */
+ 5, /* block_x_budget */
+ 59, /* block_budget */
+ 0x200, /* lossless_mode_thd */
+ 192, /* lossy_mode_thd */
+ 4, /* lossy_rgb_thd */
+ 3, /* lossy_mode_idx */
+ 4, /* slice_height */
+ 1, /* pred_mode */
+ 2, /* max_pred_err */
+};
+
+#endif /*_PANEL_nt35597_wqxga_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index c09da68..9ecd88a 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -33,19 +33,19 @@
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
+#include <mdp5.h>
#include <sys/types.h>
#include <platform/iomap.h>
#include <err.h>
#include <reg.h>
-#include <mdp5.h>
#include <string.h>
-
/*---------------------------------------------------------------------------*/
/* Panel Header */
/*---------------------------------------------------------------------------*/
#include "panel_display.h"
#include "include/panel.h"
+#include "target/display.h"
/*---------------------------------------------------------------------------*/
/* Panel Init */
@@ -178,6 +178,10 @@
pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+ pinfo->fbc.slice_height = pstruct->fbcinfo.slice_height;
+ pinfo->fbc.pred_mode = pstruct->fbcinfo.pred_mode;
+ pinfo->fbc.max_pred_err = pstruct->fbcinfo.max_pred_err;
+
} else {
pinfo->fbc.comp_ratio = 1;
}
@@ -311,6 +315,8 @@
uint8_t lane_en = 0;
uint8_t ystride = pinfo->bpp / 8;
uint32_t panel_width = pinfo->xres;
+ uint32_t final_xres, final_yres, final_width;
+ uint32_t final_height;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -324,22 +330,32 @@
if (pinfo->mipi.data_lane3)
lane_en |= (1 << 3);
- ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- panel_width, (pinfo->yres),
+ final_xres = panel_width;
+ final_width = panel_width + pinfo->lcdc.xres_pad;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+ final_xres /= pinfo->fbc.comp_ratio;
+ final_width /= pinfo->fbc.comp_ratio;
+ dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
+ final_width);
+ }
+ final_yres = pinfo->yres;
+ final_height = pinfo->yres + pinfo->lcdc.yres_pad;
+
+ ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+ final_xres, final_yres,
pinfo->mipi.dst_format,
ystride, lane_en,
pinfo->mipi.interleave_mode,
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
- ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- panel_width, (pinfo->yres),
- pinfo->mipi.dst_format,
- ystride, lane_en,
- pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ pinfo->mipi.dst_format,
+ ystride, lane_en,
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI1_BASE);
return ret;
}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 3c99289..8860f00 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -52,7 +52,7 @@
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
-typedef struct panel_struct{
+struct panel_struct{
struct panel_config *paneldata;
struct panel_resolution *panelres;
struct color_info *color;
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 3129ba4..d1fac29 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -247,7 +247,6 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
diff --git a/platform/apq8084/platform.c b/platform/apq8084/platform.c
index 923588d..cf13b5a 100644
--- a/platform/apq8084/platform.c
+++ b/platform/apq8084/platform.c
@@ -167,8 +167,3 @@
/* Using 1-1 mapping on this platform. */
return phys_addr;
}
-
-int boot_device_mask(int val)
-{
- return ((val & 0x3E) >> 1);
-}
diff --git a/platform/init.c b/platform/init.c
index 095f6e2..4783eba 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -130,3 +130,8 @@
{
return 0;
}
+
+__WEAK int boot_device_mask(int val)
+{
+ return ((val & 0x3E) >> 1);
+}
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 4429c0a..fec3f86 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -176,7 +176,6 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200)
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index b47fede..e199906 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -167,8 +167,6 @@
#define DSI1_PHY_BASE DSI0_PHY_BASE
#define DSI0_PLL_BASE (0x1AC8300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
-
/* MDP */
#define MDP_BASE 0x1A00000
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index 014e6ae..e58525f 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -159,8 +159,6 @@
#define DSI1_PHY_BASE (0x1AA0500)
#define DSI0_PLL_BASE (0x1A98300)
#define DSI1_PLL_BASE DSI0_PLL_BASE
-#define DSIPHY_PLL_CTRL(x) REG_DSI(DSI0_PLL_BASE + (x) * 4)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0x1A00000)
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 8463a77..0b1e4cf 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -224,7 +224,6 @@
#define DSI1_PHY_BASE (0xFD923100)
#define DSI0_PLL_BASE (0xFD922A00)
#define DSI1_PLL_BASE (0xFD923000)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define EDP_BASE (0xFD923400)
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
diff --git a/platform/msm8994/include/platform/gpio.h b/platform/msm8994/include/platform/gpio.h
index bce399b..154fbdf 100644
--- a/platform/msm8994/include/platform/gpio.h
+++ b/platform/msm8994/include/platform/gpio.h
@@ -57,4 +57,7 @@
void gpio_config_uart_dm(uint8_t id);
void gpio_config_blsp_i2c(uint8_t, uint8_t);
+void gpio_set(uint32_t gpio, uint32_t dir);
+void gpio_tlmm_config(uint32_t gpio, uint8_t func, uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable);
#endif
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index db20bf9..1774aa5 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -240,7 +240,6 @@
#define DSI1_PHY_BASE (0xFD9A0500)
#define DSI0_PLL_BASE (0xFD998300)
#define DSI1_PLL_BASE (0xFD9A0300)
-#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
#define MDP_BASE (0xfd900000)
@@ -256,68 +255,251 @@
#define MDP_PP_1_BASE REG_MDP(0x71800)
#define REG_MDP(off) (MDP_BASE + (off))
+
+#ifdef MDP_HW_REV
+#undef MDP_HW_REV
+#endif
#define MDP_HW_REV REG_MDP(0x1000)
+
+#ifdef MDP_INTR_EN
+#undef MDP_INTR_EN
+#endif
#define MDP_INTR_EN REG_MDP(0x1010)
+
+#ifdef MDP_INTR_CLEAR
+#undef MDP_INTR_CLEAR
+#endif
#define MDP_INTR_CLEAR REG_MDP(0x1018)
+
+#ifdef MDP_HIST_INTR_EN
+#undef MDP_HIST_INTR_EN
+#endif
#define MDP_HIST_INTR_EN REG_MDP(0x101C)
+#ifdef MDP_DISP_INTF_SEL
+#undef MDP_DISP_INTF_SEL
+#endif
#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
+
+#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
+#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
+#endif
#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
+
+#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
+#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
+#endif
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
+
+#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
+#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
+#endif
#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
+#ifdef MDP_INTF_0_TIMING_ENGINE_EN
+#undef MDP_INTF_0_TIMING_ENGINE_EN
+#endif
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
+
+#ifdef MDP_INTF_1_TIMING_ENGINE_EN
+#undef MDP_INTF_1_TIMING_ENGINE_EN
+#endif
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
+#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
-#define MDP_CTL_0_BASE REG_MDP(0x2000)
-#define MDP_CTL_1_BASE REG_MDP(0x2200)
+#ifdef MDP_CTL_0_BASE
+#undef MDP_CTL_0_BASE
+#endif
+#define MDP_CTL_0_BASE REG_MDP(0x2000)
+#ifdef MDP_CTL_1_BASE
+#undef MDP_CTL_1_BASE
+#endif
+#define MDP_CTL_1_BASE REG_MDP(0x2200)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_EN
+#undef MDP_REG_SPLIT_DISPLAY_EN
+#endif
#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
+#endif
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
+
+#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
+#endif
#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
-/* can not find following two registers */
-#define MDP_REG_PPB0_CNTL REG_MDP(0x1420)
-#define MDP_REG_PPB0_CONFIG REG_MDP(0x1424)
-
+#ifdef MDP_INTF_0_BASE
+#undef MDP_INTF_0_BASE
+#endif
#define MDP_INTF_0_BASE REG_MDP(0x6b000)
+
+#ifdef MDP_INTF_1_BASE
+#undef MDP_INTF_1_BASE
+#endif
#define MDP_INTF_1_BASE REG_MDP(0x6b800)
+
+#ifdef MDP_INTF_2_BASE
+#undef MDP_INTF_2_BASE
+#endif
#define MDP_INTF_2_BASE REG_MDP(0x6c000)
-
+#ifdef MDP_CLK_CTRL0
+#undef MDP_CLK_CTRL0
+#endif
#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
+
+#ifdef MDP_CLK_CTRL1
+#undef MDP_CLK_CTRL1
+#endif
#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
+
+#ifdef MDP_CLK_CTRL2
+#undef MDP_CLK_CTRL2
+#endif
#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
+
+#ifdef MDP_CLK_CTRL3
+#undef MDP_CLK_CTRL3
+#endif
#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
+
+#ifdef MDP_CLK_CTRL4
+#undef MDP_CLK_CTRL4
+#endif
#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
+
+#ifdef MDP_CLK_CTRL5
+#undef MDP_CLK_CTRL5
+#endif
#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
+
+#ifdef MDP_CLK_CTRL6
+#undef MDP_CLK_CTRL6
+#endif
#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
+
+#ifdef MDP_CLK_CTRL7
+#undef MDP_CLK_CTRL7
+#endif
#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
+#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
+#undef MMSS_MDP_SMP_ALLOC_W_BASE
+#endif
#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
+
+#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
+#undef MMSS_MDP_SMP_ALLOC_R_BASE
+#endif
#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
+#ifdef MDP_QOS_REMAPPER_CLASS_0
+#undef MDP_QOS_REMAPPER_CLASS_0
+#endif
#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
+
+#ifdef MDP_QOS_REMAPPER_CLASS_1
+#undef MDP_QOS_REMAPPER_CLASS_1
+#endif
#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
+#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
+#undef VBIF_VBIF_DDR_FORCE_CLK_ON
+#endif
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
+
+#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
+#undef VBIF_VBIF_DDR_OUT_MAX_BURST
+#endif
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
+
+#ifdef VBIF_VBIF_DDR_ARB_CTRL
+#undef VBIF_VBIF_DDR_ARB_CTRL
+#endif
#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
+
+#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
+#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
+#endif
#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
+
+#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
+#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
+#endif
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
+
+#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
+#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
+#endif
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
+
+#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
+#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
+#endif
#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
+
+#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
+#undef VBIF_VBIF_DDR_OUT_AX_AOOO
+#endif
#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
+#undef VBIF_VBIF_IN_RD_LIM_CONF0
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
+#undef VBIF_VBIF_IN_RD_LIM_CONF1
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
+#undef VBIF_VBIF_IN_RD_LIM_CONF2
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8)
+
+#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
+#undef VBIF_VBIF_IN_RD_LIM_CONF3
+#endif
#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
+#undef VBIF_VBIF_IN_WR_LIM_CONF0
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
+#undef VBIF_VBIF_IN_WR_LIM_CONF1
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
+#undef VBIF_VBIF_IN_WR_LIM_CONF2
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8)
+
+#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
+#undef VBIF_VBIF_IN_WR_LIM_CONF3
+#endif
#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC)
+
+#ifdef VBIF_VBIF_ABIT_SHORT
+#undef VBIF_VBIF_ABIT_SHORT
+#endif
#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070)
+
+#ifdef VBIF_VBIF_ABIT_SHORT_CONF
+#undef VBIF_VBIF_ABIT_SHORT_CONF
+#endif
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074)
+
+#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
+#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
+#endif
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8)
#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 5ee2d5c..358db25 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -158,24 +158,6 @@
F_END
};
-static struct rcg_clk blsp2_uart2_apps_clk_src =
-{
- .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
-
- .set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
- .current_freq = &rcg_dummy_freq,
-
- .c = {
- .dbg_name = "blsp1_uart2_apps_clk",
- .ops = &clk_ops_rcg_mnd,
- },
-};
-
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -194,17 +176,6 @@
},
};
-static struct branch_clk gcc_blsp2_uart2_apps_clk =
-{
- .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
- .parent = &blsp2_uart2_apps_clk_src.c,
-
- .c = {
- .dbg_name = "gcc_blsp2_uart2_apps_clk",
- .ops = &clk_ops_branch,
- },
-};
-
static struct branch_clk gcc_blsp1_uart2_apps_clk =
{
.cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
@@ -227,17 +198,6 @@
},
};
-static struct vote_clk gcc_blsp2_ahb_clk = {
- .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
- .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
- .en_mask = BIT(15),
-
- .c = {
- .dbg_name = "gcc_blsp2_ahb_clk",
- .ops = &clk_ops_vote,
- },
-};
-
/* USB Clocks */
static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
{
@@ -708,7 +668,7 @@
};
static struct branch_clk mdss_mdp_lut_clk = {
- .cbcr_reg = MDP_LUT_CBCR,
+ .cbcr_reg = (uint32_t *) MDP_LUT_CBCR,
.parent = &mdss_mdp_clk_src.c,
.has_sibling = 1,
@@ -719,7 +679,7 @@
};
static struct branch_clk mdss_vsync_clk = {
- .cbcr_reg = MDSS_VSYNC_CBCR,
+ .cbcr_reg = (uint32_t *) MDSS_VSYNC_CBCR,
.parent = &vsync_clk_src.c,
.has_sibling = 0,
@@ -746,7 +706,7 @@
};
static struct branch_clk mdss_edpaux_clk = {
- .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .cbcr_reg = (uint32_t *) MDSS_EDPAUX_CBCR,
.parent = &edpaux_clk_src.c,
.has_sibling = 0,
@@ -811,7 +771,7 @@
};
static struct branch_clk mmss_misc_ahb_clk = {
- .cbcr_reg = MMSS_MISC_AHB_CBCR,
+ .cbcr_reg = (uint32_t *) MMSS_MISC_AHB_CBCR,
.has_sibling = 1,
.c = {
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 80f4ad3..560a021 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -180,8 +180,3 @@
else
return ((addr_t)BS_INFO_ADDR2);
}
-
-int boot_device_mask(int val)
-{
- return ((val & 0x3E) >> 1);
-}
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 8e17def..07f1a12 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -98,6 +98,7 @@
#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
+#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12900)
#define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x12B00)
#define MDP_CTL_0_BASE REG_MDP(0x600)
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 0741851..2a244ca 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -35,49 +35,27 @@
#define PASS 0
#define FAIL 1
-/**********************************************************
- DSI register offset
- **********************************************************/
+/*
+ * DSI register offsets defined here are only used for non-MDSS targets.
+ * For MDSS targets, all offset definitions are picked up from corresponding
+ * target files.
+ */
+#if (DISPLAY_TYPE_MDSS == 0)
#define DSI_CLKOUT_TIMING_CTRL REG_DSI(0x0C0)
#define DSI_SOFT_RESET REG_DSI(0x114)
-#define DSI_CAL_CTRL REG_DSI(0x0F4)
-
#define DSIPHY_SW_RESET REG_DSI(0x128)
#define DSIPHY_PLL_RDY REG_DSI(0x280)
-#define DSIPHY_REGULATOR_CAL_PWR_CFG REG_DSI(0x518)
-
#define DSI_CLK_CTRL REG_DSI(0x118)
#define DSI_TRIG_CTRL REG_DSI(0x080)
-#define DSI_CTRL REG_DSI(0x000)
#define DSI_COMMAND_MODE_DMA_CTRL REG_DSI(0x038)
-#define DSI_COMMAND_MODE_MDP_CTRL REG_DSI(0x03C)
-#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL REG_DSI(0x040)
-#define DSI_DMA_CMD_OFFSET REG_DSI(0x044)
-#define DSI_DMA_CMD_LENGTH REG_DSI(0x048)
-#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL REG_DSI(0x054)
-#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL REG_DSI(0x058)
-#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL REG_DSI(0x05C)
-#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL REG_DSI(0x060)
#define DSI_ERR_INT_MASK0 REG_DSI(0x108)
#define DSI_INT_CTRL REG_DSI(0x10C)
-
-#define DSI_VIDEO_MODE_ACTIVE_H REG_DSI(0x020)
-#define DSI_VIDEO_MODE_ACTIVE_V REG_DSI(0x024)
-#define DSI_VIDEO_MODE_TOTAL REG_DSI(0x028)
-#define DSI_VIDEO_MODE_HSYNC REG_DSI(0x02C)
-#define DSI_VIDEO_MODE_VSYNC REG_DSI(0x030)
-#define DSI_VIDEO_MODE_VSYNC_VPOS REG_DSI(0x034)
-
-#define DSI_MISR_CMD_CTRL REG_DSI(0x09C)
-#define DSI_MISR_VIDEO_CTRL REG_DSI(0x0A0)
-#define DSI_EOT_PACKET_CTRL REG_DSI(0x0C8)
-#define DSI_VIDEO_MODE_CTRL REG_DSI(0x00C)
-#define DSI_CAL_STRENGTH_CTRL REG_DSI(0x100)
#define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C)
+#define DSI_DMA_CMD_OFFSET REG_DSI(0x044)
+#define DSI_DMA_CMD_LENGTH REG_DSI(0x048)
+#define DSI_CTRL REG_DSI(0x000)
#define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090)
-#define DSI_HS_TIMER_CTRL REG_DSI(0x0B8)
-
-#define DSI_LANE_CTRL REG_DSI(0x0A8)
+#endif
#define DSI_VIDEO_MODE_DONE_MASK BIT(17)
#define DSI_VIDEO_MODE_DONE_AK BIT(16)
@@ -202,8 +180,8 @@
};
struct mipi_dsi_cmd {
- int size;
- char *payload;
+ uint32_t size;
+ uint8_t *payload;
int wait;
};
@@ -261,7 +239,7 @@
int mipi_dsi_on();
int mipi_dsi_off(struct msm_panel_info *pinfo);
-int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count);
-int mipi_dsi_cmds_rx(char **rp, int len);
+int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count, char dual_dsi);
+int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len);
#endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 1d0d17b..677e707 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -133,6 +133,10 @@
uint32_t lossy_mode_thd;
uint32_t lossy_rgb_thd;
uint32_t lossy_mode_idx;
+
+ uint32_t slice_height;
+ uint32_t pred_mode;
+ uint32_t max_pred_err;
};
/* intf timing settings */
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 5509bc8..63b824d 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -621,39 +621,46 @@
uint32_t mode = 0;
uint32_t budget_ctl = 0;
uint32_t lossy_mode = 0;
- uint32_t xres;
struct fbc_panel_info *fbc;
- uint32_t enc_mode;
+ uint32_t enc_mode, width;
fbc = &pinfo->fbc;
- xres = pinfo->xres;
if (!pinfo->fbc.enabled)
return;
- if (pinfo->mipi.dual_dsi)
- xres /= 2;
-
/* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
- mode = ((xres) << 16) | (enc_mode) << 9 | ((fbc->comp_mode) << 8) |
- ((fbc->qerr_enable) << 7) | ((fbc->cd_bias) << 4) |
- ((fbc->pat_enable) << 3) | ((fbc->vlc_enable) << 2) |
- ((fbc->bflc_enable) << 1) | 1;
+ width = pinfo->xres;
+ if (enc_mode)
+ width = (pinfo->xres/fbc->comp_ratio);
- dprintf(SPEW, "xres = %d, comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
- xres, fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
+ if (pinfo->mipi.dual_dsi)
+ width /= 2;
+
+ mode = ((width) << 16) | ((fbc->slice_height) << 11) |
+ ((fbc->pred_mode) << 10) | (enc_mode) << 9 |
+ ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) |
+ ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) |
+ ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1;
+
+ dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \
+ comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
+ width, fbc->slice_height, fbc->pred_mode, enc_mode,
+ fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
budget_ctl = ((fbc->line_x_budget) << 12) |
((fbc->block_x_budget) << 8) | fbc->block_budget;
- lossy_mode = ((fbc->lossless_mode_thd) << 16) |
+ lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) |
((fbc->lossy_mode_thd) << 8) |
((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
+ dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n",
+ mode, budget_ctl, lossy_mode);
writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 9211dd3..08b675f 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -35,6 +35,7 @@
#include <string.h>
#include <debug.h>
#include <target/display.h>
+#include <mdp5.h>
#include <platform/iomap.h>
#include <platform/clock.h>
#include <platform/timer.h>
@@ -78,7 +79,7 @@
if (ret && ret != panel_signature)
goto exit_read_signature;
- ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1);
+ ret = mdss_dsi_cmds_tx(&read_ddb_start_cmd, 1, 0);
if (ret)
goto exit_read_signature;
if (!mdss_dsi_cmds_rx(&lp, 1, 1))
@@ -98,24 +99,27 @@
return ret;
}
-int mdss_dual_dsi_cmd_dma_trigger_for_panel()
+static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi)
{
uint32_t ReadValue;
uint32_t count = 0;
int status = 0;
+ uint32_t ctl_base = dual_dsi ? MIPI_DSI1_BASE : MIPI_DSI0_BASE;
#if (DISPLAY_TYPE_MDSS == 1)
writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL);
writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER);
dsb();
- writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL);
- writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER);
- dsb();
+ if (dual_dsi) {
+ writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL);
+ writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER);
+ dsb();
+ }
- ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
+ ReadValue = readl(ctl_base + INT_CTRL) & 0x00000001;
while (ReadValue != 0x00000001) {
- ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001;
+ ReadValue = readl(ctl_base + INT_CTRL) & 0x00000001;
count++;
if (count > 0xffff) {
status = FAIL;
@@ -125,57 +129,31 @@
}
}
- writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001),
- MIPI_DSI1_BASE + INT_CTRL);
+ writel((readl(ctl_base + INT_CTRL) | 0x01000001),
+ ctl_base + INT_CTRL);
dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
#endif
return status;
}
-int dsi_cmd_dma_trigger_for_panel()
-{
- unsigned long ReadValue;
- unsigned long count = 0;
- int status = 0;
-
- writel(0x03030303, DSI_INT_CTRL);
- writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
- dsb();
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- while (ReadValue != 0x00000001) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
- count++;
- if (count > 0xffff) {
- status = FAIL;
- dprintf(CRITICAL,
- "Panel CMD: command mode dma test failed\n");
- return status;
- }
- }
-
- writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
- dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
- return status;
-}
-
-int mdss_dsi_wait4_video_done()
+static int mdss_dsi_wait4_video_done()
{
unsigned long read;
unsigned long count = 0;
int status = 0;
/* If video mode is not enabled, return here */
- if ((readl(DSI_CTRL) & BIT(1)) == 0)
+ if ((readl(MIPI_DSI0_BASE + CTRL) & BIT(1)) == 0)
return 0;
- read = readl(DSI_INT_CTRL);
+ read = readl(MIPI_DSI0_BASE + INT_CTRL);
/* Enable VIDEO MODE DONE MASK and clear the interrupt */
read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK;
- writel(read, DSI_INT_CTRL);
+ writel(read, MIPI_DSI0_BASE + INT_CTRL);
dsb();
- read = readl(DSI_INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT;
- while (!read) {
- read = readl(DSI_INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT;
+ do {
+ read = readl(MIPI_DSI0_BASE + INT_CTRL) &
+ DSI_VIDEO_MODE_DONE_STAT;
count++;
if (count > 0xffff) {
status = FAIL;
@@ -183,33 +161,34 @@
"Panel CMD: Did not recieve video mode done interrupt\n");
return status;
}
- }
+ } while (!read);
- writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
+ writel((readl(MIPI_DSI0_BASE + INT_CTRL) | 0x01000001),
+ MIPI_DSI0_BASE + INT_CTRL);
dprintf(SPEW, "Panel wait_4_video_done: Recieved video mode done ack\n");
/* Skip BLLP 4ms */
mdelay(4);
return status;
-
}
-int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
+int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count, char dual_dsi)
{
int ret = 0;
+#if (DISPLAY_TYPE_MDSS == 1)
struct mipi_dsi_cmd *cm;
int i = 0;
- char pload[256];
+ uint8_t pload[256];
uint32_t off;
+ uint32_t size;
-#if (DISPLAY_TYPE_MDSS == 1)
- /* Align pload at 8 byte boundry */
- off = pload;
+ /* Align pload at 8 byte boundary */
+ off = (uint32_t) pload;
off &= 0x07;
if (off)
off = 8 - off;
- off += pload;
+ off += (uint32_t) pload;
cm = cmds;
for (i = 0; i < count; i++) {
@@ -218,13 +197,22 @@
if (ret)
goto wait4video_error;
- memcpy((void *)off, (cm->payload), cm->size);
+ /* The payload size has to be a multiple of 4 */
+ size = cm->size;
+ size &= 0x03;
+ if (size)
+ size = 4 - size;
+ size += cm->size;
+ memcpy((uint8_t *)off, (cm->payload), size);
writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET);
- writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
- writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET);
- writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build
+
+ writel(size, MIPI_DSI0_BASE + DMA_CMD_LENGTH);
+ if (dual_dsi) {
+ writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET);
+ writel(size, MIPI_DSI1_BASE + DMA_CMD_LENGTH);
+ }
dsb();
- ret += mdss_dual_dsi_cmd_dma_trigger_for_panel();
+ ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi);
if (cm->wait)
mdelay(cm->wait);
else
@@ -288,101 +276,7 @@
return rdbk_len;
}
-int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
-{
- int ret = 0;
- struct mipi_dsi_cmd *cm;
- int i = 0;
- char pload[256];
- uint32_t off;
-
- /* Align pload at 8 byte boundry */
- off = pload;
- off &= 0x07;
- if (off)
- off = 8 - off;
- off += pload;
-
- cm = cmds;
- for (i = 0; i < count; i++) {
- /* Wait for VIDEO_MODE_DONE */
- ret = mdss_dsi_wait4_video_done();
- if (ret)
- goto mipi_cmds_error;
-
- memcpy((void *)off, (cm->payload), cm->size);
- writel(off, DSI_DMA_CMD_OFFSET);
- writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
- dsb();
- ret += dsi_cmd_dma_trigger_for_panel();
- dsb();
- if (cm->wait)
- mdelay(cm->wait);
- else
- udelay(80);
- cm++;
- }
-mipi_cmds_error:
- return ret;
-}
-
-/*
- * mipi_dsi_cmd_rx: can receive at most 16 bytes
- * per transaction since it only have 4 32bits reigsters
- * to hold data.
- * therefore Maximum Return Packet Size need to be set to 16.
- * any return data more than MRPS need to be break down
- * to multiple transactions.
- */
-int mipi_dsi_cmds_rx(char **rp, int len)
-{
- uint32_t *lp, data;
- char *dp;
- int i, off, cnt;
- int rlen, res;
-
- if (len <= 2)
- rlen = 4; /* short read */
- else
- rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
-
- if (rlen > MIPI_DSI_REG_LEN) {
- return 0;
- }
-
- res = rlen & 0x03;
-
- rlen += res; /* 4 byte align */
- lp = (uint32_t *) (*rp);
-
- cnt = rlen;
- cnt += 3;
- cnt >>= 2;
-
- if (cnt > 4)
- cnt = 4; /* 4 x 32 bits registers only */
-
- off = 0x068; /* DSI_RDBK_DATA0 */
- off += ((cnt - 1) * 4);
-
- for (i = 0; i < cnt; i++) {
- data = (uint32_t) readl(MIPI_DSI_BASE + off);
- *lp++ = ntohl(data); /* to network byte order */
- off -= 4;
- }
-
- if (len > 2) {
- /*First 4 bytes + paded bytes will be header next len bytes would be payload */
- for (i = 0; i < len; i++) {
- dp = *rp;
- dp[i] = dp[4 + res + i];
- }
- }
-
- return len;
-}
-
-static int mipi_dsi_cmd_bta_sw_trigger(void)
+static int mdss_dsi_cmd_bta_sw_trigger(void)
{
uint32_t data;
int cnt = 0;
@@ -522,12 +416,10 @@
writel(((read_val & ~BIT(1)) | BIT(2)),
MIPI_DSI1_BASE + CTRL);
}
- mdss_dual_dsi_cmds_tx(pinfo->mipi.panel_off_cmds,
- pinfo->mipi.num_of_panel_off_cmds);
- } else {
- mipi_dsi_cmds_tx(pinfo->mipi.panel_off_cmds,
- pinfo->mipi.num_of_panel_off_cmds);
}
+ mdss_dsi_cmds_tx(pinfo->mipi.panel_off_cmds,
+ pinfo->mipi.num_of_panel_off_cmds,
+ pinfo->mipi.broadcast);
}
#endif
}
@@ -539,140 +431,29 @@
uint32_t ctrl_mode = 0;
#if (DISPLAY_TYPE_MDSS == 1)
- if (pinfo->panel_on_cmds) {
+ if (!pinfo->panel_on_cmds)
+ goto end;
- ctrl_mode = readl(MIPI_DSI0_BASE + CTRL);
- if (broadcast) {
- /* Enable command mode before sending the commands. */
- writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
- writel(ctrl_mode | 0x04, MIPI_DSI1_BASE + CTRL);
- status = mdss_dual_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds);
- writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
- writel(ctrl_mode, MIPI_DSI1_BASE + CTRL);
+ ctrl_mode = readl(MIPI_DSI0_BASE + CTRL);
- } else {
- /* Enable command mode before sending the commands. */
- writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
- status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds);
- writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
- if (!status && target_panel_auto_detect_enabled())
- status =
- mdss_dsi_read_panel_signature(pinfo->signature);
- dprintf(SPEW, "Read panel signature status = 0x%x \n", status);
- }
- }
+ /* Enable command mode before sending the commands. */
+ writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
+ if (broadcast)
+ writel(ctrl_mode | 0x04, MIPI_DSI1_BASE + CTRL);
+ status = mdss_dsi_cmds_tx(pinfo->panel_on_cmds,
+ pinfo->num_of_panel_on_cmds, broadcast);
+ writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
+ if (broadcast)
+ writel(ctrl_mode, MIPI_DSI1_BASE + CTRL);
+
+ if (!broadcast && !status && target_panel_auto_detect_enabled())
+ status = mdss_dsi_read_panel_signature(pinfo->signature);
+
+end:
#endif
return status;
}
-int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
-{
- uint8_t DMA_STREAM1 = 0; // for mdp display processor path
- uint8_t EMBED_MODE1 = 1; // from frame buffer
- uint8_t POWER_MODE2 = 1; // from frame buffer
- uint8_t PACK_TYPE1; // long packet
- uint8_t VC1 = 0;
- uint8_t DT1 = 0; // non embedded mode
- uint8_t WC1 = 0; // for non embedded mode only
- int status = 0;
- uint8_t DLNx_EN;
-
- switch (pinfo->num_of_lanes) {
- default:
- case 1:
- DLNx_EN = 1; // 1 lane
- break;
- case 2:
- DLNx_EN = 3; // 2 lane
- break;
- case 3:
- DLNx_EN = 7; // 3 lane
- break;
- case 4:
- DLNx_EN = 0x0F; /* 4 lanes */
- break;
- }
-
- PACK_TYPE1 = pinfo->pack;
-
- writel(0x0001, DSI_SOFT_RESET);
- writel(0x0000, DSI_SOFT_RESET);
-
- writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
-
- writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
- // build
- writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
- | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- DSI_COMMAND_MODE_DMA_CTRL);
-
- if (pinfo->panel_on_cmds)
- status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds);
-
- return status;
-}
-
-void mipi_dsi_shutdown(void)
-{
- if(!target_cont_splash_screen())
- {
- mdp_shutdown();
- writel(0x01010101, DSI_INT_CTRL);
- writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
-
- writel(0, DSI_CLK_CTRL);
- writel(0, DSI_CTRL);
- writel(0, DSIPHY_PLL_CTRL(0));
- }
- else
- {
- /* To keep the splash screen displayed till kernel driver takes
- control, do not turn off the video mode engine and clocks.
- Only disabling the MIPI DSI IRQs */
- writel(0x01010101, DSI_INT_CTRL);
- writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
- }
-}
-
-int mipi_config(struct msm_fb_panel_data *panel)
-{
- int ret = NO_ERROR;
- struct msm_panel_info *pinfo;
- struct mipi_dsi_panel_config mipi_pinfo;
-
- if (!panel)
- return ERR_INVALID_ARGS;
-
- pinfo = &(panel->panel_info);
- mipi_pinfo.mode = pinfo->mipi.mode;
- mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
- mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db;
- mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
- mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds;
- mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
- mipi_pinfo.pack = 1;
-
- /* Enable MMSS_AHB_ARB_MATER_PORT_E for
- arbiter master0 and master 1 request */
-#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610)
- writel(0x00001800, MMSS_SFPB_GPREG);
-#endif
-
- mipi_dsi_phy_init(&mipi_pinfo);
-
- ret += mipi_dsi_panel_initialize(&mipi_pinfo);
-
- if (pinfo->rotate && panel->rotate)
- pinfo->rotate();
-
- return ret;
-}
-
int mdss_dsi_video_mode_config(uint16_t disp_width,
uint16_t disp_height,
uint16_t img_width,
@@ -926,12 +707,12 @@
unsigned long ReadValue;
unsigned long count = 0;
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
+ ReadValue = readl(MIPI_DSI0_BASE + INT_CTRL) & 0x00010000;
mdelay(10);
while (ReadValue != 0x00010000) {
- ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
+ ReadValue = readl(MIPI_DSI0_BASE + INT_CTRL) & 0x00010000;
count++;
if (count > 0xffff) {
dprintf(CRITICAL, "Video lane test failed\n");
@@ -948,8 +729,8 @@
if(!target_cont_splash_screen())
{
mdss_dsi_panel_shutdown(pinfo);
- writel(0, DSI_CLK_CTRL);
- writel(0, DSI_CTRL);
+ writel(0, MIPI_DSI0_BASE + CLK_CTRL);
+ writel(0x1F1, MIPI_DSI0_BASE + CTRL);
}
writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
@@ -959,9 +740,241 @@
return NO_ERROR;
}
+#if (DISPLAY_TYPE_MDSS == 0)
+static int dsi_cmd_dma_trigger_for_panel()
+{
+ unsigned long ReadValue;
+ unsigned long count = 0;
+ int status = 0;
+
+ writel(0x03030303, DSI_INT_CTRL);
+ writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
+ dsb();
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ while (ReadValue != 0x00000001) {
+ ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
+ count++;
+ if (count > 0xffff) {
+ status = FAIL;
+ dprintf(CRITICAL,
+ "Panel CMD: command mode dma test failed\n");
+ return status;
+ }
+ }
+
+ writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
+ dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
+ return status;
+}
+
+int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
+{
+ int ret = 0;
+ struct mipi_dsi_cmd *cm;
+ int i = 0;
+ char pload[256];
+ uint32_t off;
+
+ /* Align pload at 8 byte boundry */
+ off = pload;
+ off &= 0x07;
+ if (off)
+ off = 8 - off;
+ off += pload;
+
+ cm = cmds;
+ for (i = 0; i < count; i++) {
+ /* Wait for VIDEO_MODE_DONE */
+ ret = mdss_dsi_wait4_video_done();
+ if (ret)
+ goto mipi_cmds_error;
+
+ memcpy((void *)off, (cm->payload), cm->size);
+ writel(off, DSI_DMA_CMD_OFFSET);
+ writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
+ dsb();
+ ret += dsi_cmd_dma_trigger_for_panel();
+ dsb();
+ if (cm->wait)
+ mdelay(cm->wait);
+ else
+ udelay(80);
+ cm++;
+ }
+mipi_cmds_error:
+ return ret;
+}
+
+/*
+ * mipi_dsi_cmd_rx: can receive at most 16 bytes
+ * per transaction since it only have 4 32bits reigsters
+ * to hold data.
+ * therefore Maximum Return Packet Size need to be set to 16.
+ * any return data more than MRPS need to be break down
+ * to multiple transactions.
+ */
+int mipi_dsi_cmds_rx(char **rp, int len)
+{
+ uint32_t *lp, data;
+ char *dp;
+ int i, off, cnt;
+ int rlen, res;
+
+ if (len <= 2)
+ rlen = 4; /* short read */
+ else
+ rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
+
+ if (rlen > MIPI_DSI_REG_LEN) {
+ return 0;
+ }
+
+ res = rlen & 0x03;
+
+ rlen += res; /* 4 byte align */
+ lp = (uint32_t *) (*rp);
+
+ cnt = rlen;
+ cnt += 3;
+ cnt >>= 2;
+
+ if (cnt > 4)
+ cnt = 4; /* 4 x 32 bits registers only */
+
+ off = 0x068; /* DSI_RDBK_DATA0 */
+ off += ((cnt - 1) * 4);
+
+ for (i = 0; i < cnt; i++) {
+ data = (uint32_t) readl(MIPI_DSI_BASE + off);
+ *lp++ = ntohl(data); /* to network byte order */
+ off -= 4;
+ }
+
+ if (len > 2) {
+ /*First 4 bytes + paded bytes will be header next len bytes would be payload */
+ for (i = 0; i < len; i++) {
+ dp = *rp;
+ dp[i] = dp[4 + res + i];
+ }
+ }
+
+ return len;
+}
+
+static int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
+{
+ uint8_t DMA_STREAM1 = 0; // for mdp display processor path
+ uint8_t EMBED_MODE1 = 1; // from frame buffer
+ uint8_t POWER_MODE2 = 1; // from frame buffer
+ uint8_t PACK_TYPE1; // long packet
+ uint8_t VC1 = 0;
+ uint8_t DT1 = 0; // non embedded mode
+ uint8_t WC1 = 0; // for non embedded mode only
+ int status = 0;
+ uint8_t DLNx_EN;
+
+ switch (pinfo->num_of_lanes) {
+ default:
+ case 1:
+ DLNx_EN = 1; // 1 lane
+ break;
+ case 2:
+ DLNx_EN = 3; // 2 lane
+ break;
+ case 3:
+ DLNx_EN = 7; // 3 lane
+ break;
+ case 4:
+ DLNx_EN = 0x0F; /* 4 lanes */
+ break;
+ }
+
+ PACK_TYPE1 = pinfo->pack;
+
+ writel(0x0001, DSI_SOFT_RESET);
+ writel(0x0000, DSI_SOFT_RESET);
+
+ writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
+ writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
+ // trigger 0x4; dma stream1
+
+ writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
+ // build
+ writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
+ | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
+ DSI_COMMAND_MODE_DMA_CTRL);
+
+ if (pinfo->panel_on_cmds)
+ status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds,
+ pinfo->num_of_panel_on_cmds);
+
+ return status;
+}
+#endif
+
+void mipi_dsi_shutdown(void)
+{
+#if (DISPLAY_TYPE_MDSS == 0)
+ if(!target_cont_splash_screen())
+ {
+ mdp_shutdown();
+ writel(0x01010101, DSI_INT_CTRL);
+ writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
+
+ writel(0, DSI_CLK_CTRL);
+ writel(0, DSI_CTRL);
+ writel(0, DSIPHY_PLL_CTRL(0));
+ }
+ else
+ {
+ /* To keep the splash screen displayed till kernel driver takes
+ control, do not turn off the video mode engine and clocks.
+ Only disabling the MIPI DSI IRQs */
+ writel(0x01010101, DSI_INT_CTRL);
+ writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
+ }
+#endif
+}
+
int mipi_cmd_trigger()
{
+#if (DISPLAY_TYPE_MDSS == 0)
writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
-
+#endif
return NO_ERROR;
}
+
+int mipi_config(struct msm_fb_panel_data *panel)
+{
+ int ret = NO_ERROR;
+#if (DISPLAY_TYPE_MDSS == 0)
+ struct msm_panel_info *pinfo;
+ struct mipi_dsi_panel_config mipi_pinfo;
+
+ if (!panel)
+ return ERR_INVALID_ARGS;
+
+ pinfo = &(panel->panel_info);
+ mipi_pinfo.mode = pinfo->mipi.mode;
+ mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
+ mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db;
+ mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
+ mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds;
+ mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
+ mipi_pinfo.pack = 1;
+
+ /* Enable MMSS_AHB_ARB_MATER_PORT_E for
+ arbiter master0 and master 1 request */
+#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610)
+ writel(0x00001800, MMSS_SFPB_GPREG);
+#endif
+
+ mipi_dsi_phy_init(&mipi_pinfo);
+
+ ret += mipi_dsi_panel_initialize(&mipi_pinfo);
+
+ if (pinfo->rotate && panel->rotate)
+ pinfo->rotate();
+#endif
+ return ret;
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 9fd69a4..ffcb407 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -91,6 +91,7 @@
}
}
+#if (DISPLAY_TYPE_MDSS == 0)
int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mipi_dsi_phy_ctrl *pd;
@@ -202,6 +203,7 @@
}
return 0;
}
+#endif
void mdss_dsi_phy_sw_reset(uint32_t ctl_base)
{
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 3d944b6..11259f5 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -95,16 +95,16 @@
int ret = NO_ERROR;
switch (panel_id) {
case TOSHIBA_720P_VIDEO_PANEL:
- ret = mipi_dsi_cmds_tx(toshiba_720p_video_rotation,
- TOSHIBA_720P_VIDEO_ROTATION);
+ ret = mdss_dsi_cmds_tx(toshiba_720p_video_rotation,
+ TOSHIBA_720P_VIDEO_ROTATION, 0);
break;
case NT35590_720P_CMD_PANEL:
- ret = mipi_dsi_cmds_tx(nt35590_720p_cmd_rotation,
- NT35590_720P_CMD_ROTATION);
+ ret = mdss_dsi_cmds_tx(nt35590_720p_cmd_rotation,
+ NT35590_720P_CMD_ROTATION, 0);
break;
case NT35590_720P_VIDEO_PANEL:
- ret = mipi_dsi_cmds_tx(nt35590_720p_video_rotation,
- NT35590_720P_VIDEO_ROTATION);
+ ret = mdss_dsi_cmds_tx(nt35590_720p_video_rotation,
+ NT35590_720P_VIDEO_ROTATION, 0);
break;
}
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index 93837f9..c7c8c2d 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -216,10 +216,9 @@
int target_ldo_ctrl(uint8_t enable)
{
- /*
- * The PMIC regulators needed for display are enabled in SBL.
- * There is no access to the regulators is LK.
- */
+ if (enable)
+ regulator_enable(); /* L2, L6, and L17 */
+
return NO_ERROR;
}
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
index b9d5dfe..35643a0 100644
--- a/target/msm8994/include/target/display.h
+++ b/target/msm8994/include/target/display.h
@@ -34,31 +34,6 @@
/*---------------------------------------------------------------------------*/
#include <display_resource.h>
-/*---------------------------------------------------------------------------*/
-/* GPIO configuration */
-/*---------------------------------------------------------------------------*/
-static struct gpio_pin reset_gpio = {
- "msmgpio", 78, 3, 1, 0, 1
-};
-
-static struct gpio_pin lcd_reg_en = { /* boost regulator */
- "pm8994_gpios", 14, 3, 1, 0, 1
-};
-
-static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
- "pmi8994_gpios", 2, 3, 1, 0, 1
-};
-
-/*---------------------------------------------------------------------------*/
-/* LDO configuration */
-/*---------------------------------------------------------------------------*/
-static struct ldo_entry ldo_entry_array[] = {
- { "vdd", 14, 0, 1800000, 100000, 100, 0, 20, 0, 0},
- { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
- { "vdda", 2, 1, 1250000, 100000, 100, 0, 0, 0, 0},
- { "vcca", 28, 1, 1000000, 10000, 100, 0, 0, 0, 0},
-};
-
#define TOTAL_LDO_DEFINED 3
/*---------------------------------------------------------------------------*/
@@ -107,3 +82,16 @@
#define PWM_BL_LPG_CHAN_ID 4 /* lpg_out<3> */
#endif
+
+/*---------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------*/
+int target_display_pre_on();
+int target_display_pre_off();
+int target_display_post_on();
+int target_display_post_off();
+int target_cont_splash_screen();
+void target_force_cont_splash_disable(uint8_t override);
+uint8_t target_panel_auto_detect_enabled();
+
+
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 9c54490..925fcde 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -61,6 +61,8 @@
#include <pm8x41_wled.h>
#include <qpnp_wled.h>
+#include "target/display.h"
+
#define CE_INSTANCE 2
#define CE_EE 1
#define CE_FIFO_SIZE 64
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index 0c7d02b..7264474 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -28,11 +28,13 @@
*/
#include <debug.h>
+#include <string.h>
#include <err.h>
#include <smem.h>
#include <msm_panel.h>
#include <board.h>
#include <mipi_dsi.h>
+#include <qtimer.h>
#include "include/panel.h"
#include "panel_display.h"
@@ -46,6 +48,8 @@
#include "include/panel_jdi_4k_dualdsi_video.h"
#include "include/panel_jdi_1080p_video.h"
#include "include/panel_hx8379a_truly_fwvga_video.h"
+#include "include/panel_nt35597_wqxga_video.h"
+#include "include/panel_nt35597_wqxga_cmd.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -57,6 +61,8 @@
JDI_4K_DUALDSI_VIDEO_PANEL,
JDI_1080P_VIDEO_PANEL,
HX8379A_TRULY_FWVGA_VIDEO_PANEL,
+NOVATEK_WQXGA_VIDEO_PANEL,
+NOVATEK_WQXGA_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -71,6 +77,8 @@
{"jdi_4k_dualdsi_video", JDI_4K_DUALDSI_VIDEO_PANEL},
{"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
{"hx8379a_truly_fwvga_video", HX8379A_TRULY_FWVGA_VIDEO_PANEL},
+ {"nt35597_wqxga_video", NOVATEK_WQXGA_VIDEO_PANEL},
+ {"nt35597_wqxga_cmd", NOVATEK_WQXGA_CMD_PANEL},
};
static uint32_t panel_id;
@@ -271,6 +279,65 @@
pinfo->mipi.broadcast = 0;
memcpy(phy_db->timing,
hx8379a_truly_fwvga_video_timings, TIMING_SIZE);
+ case NOVATEK_WQXGA_VIDEO_PANEL:
+ dprintf(ALWAYS, " Novatek 35597 panel selected\n");
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 0;
+ panelstruct->paneldata = &nt35597_wqxga_video_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &nt35597_wqxga_video_panel_res;
+ panelstruct->color = &nt35597_wqxga_video_color;
+ panelstruct->videopanel = &nt35597_wqxga_video_video_panel;
+ panelstruct->commandpanel = &nt35597_wqxga_video_command_panel;
+ panelstruct->state = &nt35597_wqxga_video_state;
+ panelstruct->laneconfig = &nt35597_wqxga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35597_wqxga_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35597_wqxga_video_reset_seq;
+ panelstruct->backlightinfo = &nt35597_wqxga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = nt35597_wqxga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = NT35597_WQXGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = nt35597_wqxga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = NT35597_WQXGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ nt35597_wqxga_video_timings, TIMING_SIZE);
+ memcpy(&panelstruct->fbcinfo, &nt35597_wqxga_video_fbc,
+ sizeof(struct fb_compression));
+ break;
+ case NOVATEK_WQXGA_CMD_PANEL:
+ dprintf(ALWAYS, " Novatek 35597 command mode panel selected\n");
+ pan_type = PANEL_TYPE_DSI;
+ pinfo->lcd_reg_en = 1;
+ panelstruct->paneldata = &nt35597_wqxga_cmd_panel_data;
+ panelstruct->paneldata->panel_with_enable_gpio = 0;
+ panelstruct->panelres = &nt35597_wqxga_cmd_panel_res;
+ panelstruct->color = &nt35597_wqxga_cmd_color;
+ panelstruct->videopanel = &nt35597_wqxga_cmd_video_panel;
+ panelstruct->commandpanel = &nt35597_wqxga_cmd_command_panel;
+ panelstruct->state = &nt35597_wqxga_cmd_state;
+ panelstruct->laneconfig = &nt35597_wqxga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35597_wqxga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &nt35597_wqxga_cmd_reset_seq;
+ panelstruct->backlightinfo = &nt35597_wqxga_cmd_backlight;
+ pinfo->mipi.panel_on_cmds
+ = nt35597_wqxga_cmd_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = NT35597_WQXGA_CMD_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = nt35597_wqxga_cmd_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = NT35597_WQXGA_CMD_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ nt35597_wqxga_cmd_timings, TIMING_SIZE);
+ memcpy(&panelstruct->fbcinfo, &nt35597_wqxga_cmd_fbc,
+ sizeof(struct fb_compression));
break;
default:
case UNKNOWN_PANEL:
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 171f3d6..7e6cdea 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -28,6 +28,7 @@
*/
#include <debug.h>
+#include <string.h>
#include <smem.h>
#include <err.h>
#include <msm_panel.h>
@@ -39,12 +40,16 @@
#include <mdp5.h>
#include <scm.h>
#include <endian.h>
+#include <regulator.h>
+#include <qtimer.h>
+#include <arch/defines.h>
#include <platform/gpio.h>
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
#include "include/panel.h"
#include "include/display_resource.h"
+#include "gcdb_display.h"
#define HFPLL_LDO_ID 12
@@ -57,6 +62,21 @@
#define PMIC_WLED_SLAVE_ID 3
#define PMIC_MPP_SLAVE_ID 2
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 78, 3, 1, 0, 1
+};
+
+static struct gpio_pin lcd_reg_en = { /* boost regulator */
+ "pm8994_gpios", 14, 3, 1, 0, 1
+};
+
+static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
+ "pmi8994_gpios", 2, 3, 1, 0, 1
+};
+
static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
{
mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
@@ -363,12 +383,8 @@
bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
{
- int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
- bool ret = true;
+ return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
- ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
-
- return ret;
}
void target_display_init(const char *panel_name)
@@ -384,7 +400,7 @@
panel_name);
return;
}
- if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR)) {
+ if (gcdb_display_init(panel_name, MDP_REV_50, (void *)MIPI_FB_ADDR)) {
target_force_cont_splash_disable(true);
msm_display_off();
}
diff --git a/target/target_display.c b/target/target_display.c
index 4b07cc8..a16a46e 100644
--- a/target/target_display.c
+++ b/target/target_display.c
@@ -30,6 +30,8 @@
#include <debug.h>
#include <platform.h>
+#include "include/msm_panel.h"
+
__WEAK int mdp_lcdc_config(void)
{
return 0;