Merge "platform: msm_shared: Correct the USB function prototype to avoid compiler warning."
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 8a5eaff..512657f 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -206,4 +206,5 @@
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
+void pm8x41_clear_pmic_watchdog(void);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 672514a..a1c2e6d 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -78,6 +78,7 @@
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
+#define PMIC_WD_RESET_S2_CTL2 0x857
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 2c14d3b..035c442 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -474,3 +474,8 @@
return batt_is_broken;
}
+
+void pm8x41_clear_pmic_watchdog(void)
+{
+ pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 62cabf0..834b335 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -199,9 +199,9 @@
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t ctl_base)
{
- writel(0x04, ctl_base + 0x0264); /* LKDetect CFG2 */
+ writel(0x0c, ctl_base + 0x0264); /* LKDetect CFG2 */
udelay(100);
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
+ writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
mdelay(1);
}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 632de53..98f1da0 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -172,7 +172,8 @@
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/scm.o \
- $(LOCAL_DIR)/gpio.o
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/shutdown_detect.o
endif
ifeq ($(PLATFORM),apq8084)
diff --git a/project/msm8610.mk b/project/msm8610.mk
index 3f7dcbb..5bcad33 100644
--- a/project/msm8610.mk
+++ b/project/msm8610.mk
@@ -10,6 +10,9 @@
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
+#enable power on vibrator feature
+ENABLE_PON_VIB_SUPPORT := true
+
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
DEFINES += WITH_DEBUG_LOG_BUF=1
@@ -29,6 +32,10 @@
#is with the linker and file a bug report.
ENABLE_THUMB := false
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 286ef41..2a41004 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -519,6 +519,8 @@
dload_util_write_cookie(mode == NORMAL_DLOAD ?
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ pm8x41_clear_pmic_watchdog();
+
return 0;
}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index fb6d24c..d085765 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -49,11 +49,14 @@
#include <partition_parser.h>
#include <platform/clock.h>
#include <platform/timer.h>
+#include <shutdown_detect.h>
+#include <vibrator.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
#define TLMM_VOL_UP_BTN_GPIO 72
+#define VIBRATE_TIME 250
enum target_subtype {
HW_PLATFORM_SUBTYPE_SKUAA = 1,
@@ -163,11 +166,19 @@
target_keystatus();
target_sdc_init();
+
+ shutdown_detect();
+
+ /* turn on vibrator to indicate that phone is booting up to end user */
+ vib_timed_turn_on(VIBRATE_TIME);
}
void target_uninit(void)
{
mmc_put_card_to_sleep(dev);
+
+ /* wait for the vibrator timer is expried */
+ wait_vib_timeout();
}
#define SSD_CE_INSTANCE 1
@@ -425,3 +436,21 @@
{
return dev;
}
+
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "shutdown failed\n");
+
+ ASSERT(0);
+}
diff --git a/target/msm8610/rules.mk b/target/msm8610/rules.mk
index 909e673..7ffcfe1 100644
--- a/target/msm8610/rules.mk
+++ b/target/msm8610/rules.mk
@@ -25,6 +25,7 @@
dev/pmic/pm8x41 \
dev/panel/msm \
dev/gcdb/display \
+ dev/vib \
lib/libfdt
DEFINES += \
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 270a300..b8dc850 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -58,40 +58,76 @@
.full_current_scale = 0x19
};
-static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
+static uint32_t dsi_pll_lock_status(uint32_t ctl_base)
{
- uint32_t rc = 0;
+ uint32_t counter, status;
+ udelay(100);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+
+ status = readl(ctl_base + 0x02c0) & 0x01;
+ for (counter = 0; counter < 5 && !status; counter++) {
+ udelay(100);
+ status = readl(ctl_base + 0x02c0) & 0x01;
+ }
+
+ return status;
+}
+
+static uint32_t dsi_pll_enable_seq_b(uint32_t ctl_base)
+{
mdss_dsi_uniphy_pll_sw_reset(ctl_base);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(1);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(200);
writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(500);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
+ udelay(500);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ return dsi_pll_lock_status(ctl_base);
+}
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+{
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(250);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(500);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(500);
+
+ return dsi_pll_lock_status(ctl_base);
+}
+
+static void dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ uint32_t counter, status;
+
+ for (counter = 0; counter < 3; counter++) {
+ status = dsi_pll_enable_seq_b(ctl_base);
+ if (status)
+ break;
+ status = dsi_pll_enable_seq_d(ctl_base);
+ if (status)
+ break;
+ status = dsi_pll_enable_seq_d(ctl_base);
+ if(status)
+ break;
}
- return rc;
+
+ if (!status)
+ dprintf(CRITICAL, "Pll lock sequence failed\n");
}
static int msm8974_wled_backlight_ctrl(uint8_t enable)