commit f91907f2b723d8d76e6060d1986447410aece457
author Kinson Chik <kchik@codeaurora.org> Fri Jul 15 10:06:48 2011 -0700
committer Kinson Chik <kchik@codeaurora.org> Thu Jul 21 16:50:38 2011 -0700
tree c4c85ea93bbcc1a7ea0059310b3ee9b233638eba
parent 46d28982b2e31247797bef47dedcbd2d36eeb572

msm8960: Optimize delays for display splash

Change-Id: Icd997a82764173a73919fdefc1a987cf423a7998

platform/msm_shared/mipi_dsi.c

diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index ee878f9..d5e9ff6 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -150,7 +150,6 @@
     struct mipi_dsi_phy_ctrl *pd;
 
     writel(0x00000001, DSI_PHY_SW_RESET);
-    mdelay(50);
     writel(0x00000000, DSI_PHY_SW_RESET);
 
     pd = (pinfo->dsi_phy_config);
@@ -215,7 +214,6 @@
     int status = 0;
 
     writel(0x03030303, DSI_INT_CTRL);
-    mdelay(10);
     writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
     ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
     while (ReadValue != 0x00000001) {
@@ -247,7 +245,7 @@
         writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
         writel(cm->size, DSI_DMA_CMD_LENGTH);   // reg 0x48 for this build
         ret += dsi_cmd_dma_trigger_for_panel();
-        mdelay(10);
+        udelay(80);
         cm++;
     }
     return ret;
@@ -778,7 +776,7 @@
 void mipi_dsi_shutdown(void)
 {
     writel(0x00000000, MDP_DSI_VIDEO_EN);
-    mdelay(60);
+    mdelay(10);
     writel(0x00000000, MDP_INTR_ENABLE);
     writel(0x00000003, MDP_OVERLAYPROC0_CFG);
     writel(0x01010101, DSI_INT_CTRL);

target/msm8960/panel.c

diff --git a/target/msm8960/panel.c b/target/msm8960/panel.c
index 59f534b..8e49321 100644
--- a/target/msm8960/panel.c
+++ b/target/msm8960/panel.c
@@ -105,7 +105,7 @@
 
     /* DSI1_DSIPHY_CAL_HW_TRIGGER */
     writel(0x01, MIPI_DSI_BASE + 0x0528);
-    mdelay(50);
+
     /* DSI1_DSIPHY_CAL_HW_TRIGGER */
     writel(0x00, MIPI_DSI_BASE + 0x0528);
 
@@ -125,8 +125,7 @@
         struct mipi_dsi_phy_ctrl *pd;
     uint32_t i, off = 0;
 
-        writel(0x0001, MIPI_DSI_BASE + 0x128);/* start phy sw reset */
-    mdelay(100);
+    writel(0x0001, MIPI_DSI_BASE + 0x128);/* start phy sw reset */
     writel(0x0000, MIPI_DSI_BASE + 0x128);/* end phy w reset */
     writel(0x0003, MIPI_DSI_BASE + 0x500);/* regulator_ctrl_0 */
     writel(0x0001, MIPI_DSI_BASE + 0x504);/* regulator_ctrl_1 */