Revert "bootloadker/lk: Changes for adding new target msm7627_7x to build system"
This reverts commit ce64f5195f76bce5823e9c39fe1e50d69f669d2c.
diff --git a/project/msm7627_7x_ffa.mk b/project/msm7627_7x_ffa.mk
deleted file mode 100644
index aeef472..0000000
--- a/project/msm7627_7x_ffa.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# top level project rules for the msm7627_ffa project
-#
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-TARGET := msm7627_7x_ffa
-
-MODULES += app/aboot
-
-#DEFINES += WITH_DEBUG_DCC=1
-#DEFINES += WITH_DEBUG_UART=1
-#DEFINES += WITH_DEBUG_FBCON=1
diff --git a/project/msm7627_7x_ffa_nandwrite.mk b/project/msm7627_7x_ffa_nandwrite.mk
deleted file mode 100644
index 3e8b7d2..0000000
--- a/project/msm7627_7x_ffa_nandwrite.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# top level project rules for the msm7627_ffa_nandwrite project
-#
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-TARGET := msm7627_7x_ffa
-
-MODULES += app/nandwrite
-
-DEFINES += WITH_DEBUG_JTAG=1
-DEFINES += ENABLE_NANDWRITE=1
-#DEFINES += WITH_DEBUG_DCC=1
-#DEFINES += WITH_DEBUG_UART=1
-#DEFINES += WITH_DEBUG_FBCON=1
-
diff --git a/project/msm7627_7x_surf.mk b/project/msm7627_7x_surf.mk
deleted file mode 100644
index 2de4131..0000000
--- a/project/msm7627_7x_surf.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# top level project rules for the msm7627_surf project
-#
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-TARGET := msm7627_7x_surf
-
-MODULES += app/aboot
-
-#DEFINES += WITH_DEBUG_DCC=1
-#DEFINES += WITH_DEBUG_UART=1
-DEFINES += WITH_DEBUG_FBCON=1
diff --git a/project/msm7627_7x_surf_nandwrite.mk b/project/msm7627_7x_surf_nandwrite.mk
deleted file mode 100644
index 86962dc..0000000
--- a/project/msm7627_7x_surf_nandwrite.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# top level project rules for the msm7627_surf_nandwrite project
-#
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-TARGET := msm7627_7x_surf
-
-MODULES += app/nandwrite
-
-DEFINES += WITH_DEBUG_JTAG=1
-DEFINES += ENABLE_NANDWRITE=1
-#DEFINES += WITH_DEBUG_DCC=1
-#DEFINES += WITH_DEBUG_UART=1
-#DEFINES += WITH_DEBUG_FBCON=1
-
diff --git a/target/msm7627_7x_ffa/atags.c b/target/msm7627_7x_ffa/atags.c
deleted file mode 100644
index 9029ad2..0000000
--- a/target/msm7627_7x_ffa/atags.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Code Aurora nor
- * the names of its contributors may be used to endorse or promote
- * products derived from this software without specific prior written
- * permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-unsigned* target_atag_mem(unsigned* ptr)
-{
- return ptr;
-}
diff --git a/target/msm7627_7x_ffa/init.c b/target/msm7627_7x_ffa/init.c
deleted file mode 100644
index 6c9ea7d..0000000
--- a/target/msm7627_7x_ffa/init.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2009, Google Inc.
- * All rights reserved.
- * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google, Inc. nor the names of its contributors
- * may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <debug.h>
-#include <dev/keys.h>
-#include <dev/gpio_keypad.h>
-#include <lib/ptable.h>
-#include <dev/flash.h>
-#include <smem.h>
-
-#define LINUX_MACHTYPE 1007015
-
-#define VARIABLE_LENGTH 0x10101010
-#define DIFF_START_ADDR 0xF0F0F0F0
-#define NUM_PAGES_PER_BLOCK 0x40
-
-static struct ptable flash_ptable;
-
-/* for these partitions, start will be offset by either what we get from
- * smem, or from the above offset if smem is not useful. Also, we should
- * probably have smem_ptable code populate our flash_ptable.
- *
- * When smem provides us with a full partition table, we can get rid of
- * this altogether.
- *
- */
-static struct ptentry board_part_list[] = {
- {
- .start = 0,
- .length = 40 /* 5MB */,
- .name = "boot",
- },
- {
- .start = 40,
- .length =760 /* 95MB */,
- .name = "system",
- },
- {
- .start = 800,
- .length = 40 /* 5MB */,
- .name = "cache",
- },
- {
- .start = 840,
- .length = VARIABLE_LENGTH,
- .name = "userdata",
- },
- {
- .start = DIFF_START_ADDR,
- .length = 12 /* 1.5MB */,
- .name = "persist",
- },
- {
- .start = DIFF_START_ADDR,
- .length = 40 /* 5MB */,
- .name = "recovery",
- },
-};
-static int num_parts = sizeof(board_part_list)/sizeof(struct ptentry);
-
-void smem_ptable_init(void);
-unsigned smem_get_apps_flash_start(void);
-
-void keypad_init(void);
-
-int target_is_emmc_boot(void);
-
-void target_init(void)
-{
- unsigned offset;
- struct flash_info *flash_info;
- unsigned total_num_of_blocks;
- bool start_addr_changed = false;
- unsigned next_ptr_start_adr = 0;
- int i;
-
- dprintf(INFO, "target_init()\n");
-
-#if (!ENABLE_NANDWRITE)
- keys_init();
- keypad_init();
-#endif
-
- if (target_is_emmc_boot())
- return;
-
- ptable_init(&flash_ptable);
- smem_ptable_init();
-
- flash_init();
- flash_info = flash_get_info();
- ASSERT(flash_info);
-
- offset = smem_get_apps_flash_start();
- if (offset == 0xffffffff)
- while(1);
-
- total_num_of_blocks = (flash_info->block_size)/NUM_PAGES_PER_BLOCK;
-
- for (i = 0; i < num_parts; i++) {
- struct ptentry *ptn = &board_part_list[i];
- unsigned len = ptn->length;
-
- if(len == VARIABLE_LENGTH)
- {
- start_addr_changed = true;
- unsigned length_for_prt = 0;
- unsigned j;
- for (j = i+1; j < num_parts; j++)
- {
- struct ptentry *temp_ptn = &board_part_list[j];
- ASSERT(temp_ptn->length != VARIABLE_LENGTH);
- length_for_prt += temp_ptn->length;
- }
- len = (total_num_of_blocks - 1) - (offset + ptn->start + length_for_prt);
- ASSERT(len >= 0);
- next_ptr_start_adr = ptn->start + len;
- }
- if((ptn->start == DIFF_START_ADDR) && (start_addr_changed))
- {
- ASSERT(next_ptr_start_adr);
- ptn->start = next_ptr_start_adr;
- next_ptr_start_adr = ptn->start + ptn->length;
- }
- ptable_add(&flash_ptable, ptn->name, offset + ptn->start,
- len, ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
- }
-
- smem_add_modem_partitions(&flash_ptable);
-
- ptable_dump(&flash_ptable);
- flash_set_ptable(&flash_ptable);
-}
-
-unsigned board_machtype(void)
-{
- return LINUX_MACHTYPE;
-}
-
-void reboot_device(unsigned reboot_reason)
-{
- reboot(reboot_reason);
-}
-
-unsigned check_reboot_mode(void)
-{
- unsigned mode[2] = {0, 0};
- unsigned int mode_len = sizeof(mode);
- unsigned smem_status;
-
- smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
- &mode, mode_len );
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for reboot mode\n");
- return 0;
- }
- return mode[0];
-}
-
-void target_battery_charging_enable(unsigned enable, unsigned disconnect)
-{
-}
diff --git a/target/msm7627_7x_ffa/keypad.c b/target/msm7627_7x_ffa/keypad.c
deleted file mode 100644
index 7550ed5..0000000
--- a/target/msm7627_7x_ffa/keypad.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2009, Google Inc.
- * All rights reserved.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google, Inc. nor the names of its contributors
- * may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <dev/keys.h>
-#include <dev/gpio_keypad.h>
-
-#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
-
-/* don't turn this on without updating the ffa support */
-#define SCAN_FUNCTION_KEYS 0
-
-static unsigned int halibut_row_gpios[] = {
- 31, 32, 33, 34, 35, 41
-#if SCAN_FUNCTION_KEYS
- , 42
-#endif
-};
-
-static unsigned int halibut_col_gpios[] = { 36, 37, 38, 39, 40 };
-
-#define KEYMAP_INDEX(row, col) ((row)*ARRAY_SIZE(halibut_col_gpios) + (col))
-
-static const unsigned short halibut_keymap[ARRAY_SIZE(halibut_col_gpios) * ARRAY_SIZE(halibut_row_gpios)] = {
- //[KEYMAP_INDEX(0, 0)] = KEY_5,
- //[KEYMAP_INDEX(0, 1)] = KEY_9,
- [KEYMAP_INDEX(0, 2)] = KEY_1,
- [KEYMAP_INDEX(0, 3)] = KEY_SEND,
- [KEYMAP_INDEX(0, 4)] = KEY_LEFT,
-
- [KEYMAP_INDEX(1, 0)] = KEY_3,
- [KEYMAP_INDEX(1, 1)] = KEY_RIGHT,
- [KEYMAP_INDEX(1, 2)] = KEY_VOLUMEUP,
- //[KEYMAP_INDEX(1, 3)] = KEY_SHARP,
- [KEYMAP_INDEX(1, 4)] = KEY_6,
-
- [KEYMAP_INDEX(2, 0)] = KEY_HOME, /* A */
- [KEYMAP_INDEX(2, 1)] = KEY_BACK, /* B */
- [KEYMAP_INDEX(2, 2)] = KEY_0,
- [KEYMAP_INDEX(2, 3)] = KEY_SHARP,
- [KEYMAP_INDEX(2, 4)] = KEY_9,
-
- [KEYMAP_INDEX(3, 0)] = KEY_UP,
- [KEYMAP_INDEX(3, 1)] = KEY_CENTER,
- [KEYMAP_INDEX(3, 2)] = KEY_4,
- //[KEYMAP_INDEX(3, 3)] = KEY_MUTE, /* SPKR */
- [KEYMAP_INDEX(3, 4)] = KEY_2,
-
- [KEYMAP_INDEX(4, 0)] = KEY_VOLUMEDOWN,
- [KEYMAP_INDEX(4, 1)] = KEY_SOUND,
- [KEYMAP_INDEX(4, 2)] = KEY_DOWN,
- [KEYMAP_INDEX(4, 3)] = KEY_8,
- [KEYMAP_INDEX(4, 4)] = KEY_5,
-
- //[KEYMAP_INDEX(5, 0)] = KEY_VOLUMEDOWN,
- [KEYMAP_INDEX(5, 1)] = KEY_STAR,
- [KEYMAP_INDEX(5, 2)] = KEY_SOFT2,
- [KEYMAP_INDEX(5, 3)] = KEY_MENU,
- [KEYMAP_INDEX(5, 4)] = KEY_7,
-
-#if SCAN_FUNCTION_KEYS
- [KEYMAP_INDEX(6, 0)] = KEY_F5,
- [KEYMAP_INDEX(6, 1)] = KEY_F4,
- [KEYMAP_INDEX(6, 2)] = KEY_F3,
- [KEYMAP_INDEX(6, 3)] = KEY_F2,
- [KEYMAP_INDEX(6, 4)] = KEY_F1
-#endif
-};
-
-static struct gpio_keypad_info halibut_keypad_info = {
- .keymap = halibut_keymap,
- .output_gpios = halibut_row_gpios,
- .input_gpios = halibut_col_gpios,
- .noutputs = ARRAY_SIZE(halibut_row_gpios),
- .ninputs = ARRAY_SIZE(halibut_col_gpios),
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
- .flags = GPIOKPF_DRIVE_INACTIVE,
-};
-
-void keypad_init(void)
-{
- gpio_keypad_init(&halibut_keypad_info);
-}
diff --git a/target/msm7627_7x_ffa/panel.c b/target/msm7627_7x_ffa/panel.c
deleted file mode 100644
index c2b56a1..0000000
--- a/target/msm7627_7x_ffa/panel.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright 2007, Google Inc. */
-
-#include <debug.h>
-#include <dev/gpio.h>
-#include <kernel/thread.h>
-#include <platform/mddi.h>
-
-#define MDDI_CLIENT_CORE_BASE 0x108000
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define SPI_BLOCK_BASE 0x120000
-#define I2C_BLOCK_BASE 0x130000
-#define PWM_BLOCK_BASE 0x140000
-#define GPIO_BLOCK_BASE 0x150000
-#define SYSTEM_BLOCK1_BASE 0x160000
-#define SYSTEM_BLOCK2_BASE 0x170000
-
-
-#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
-#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
-#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
-#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
-#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
-#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
-#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
-#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
-#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
-#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
-#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
-#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
-#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
-#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
-#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
-#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
-#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
-#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
-#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
-#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
-#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
-#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
-
-
-#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
-#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
-#define START (LCD_CONTROL_BLOCK_BASE|0x08)
-#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
-#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
-#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
-#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
-#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
-#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
-#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
-#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
-
-#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
-#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
-#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
-#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
-#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
-#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
-#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
-#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
-#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
-#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
-#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
-#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
-#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
-#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
-#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
-#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
-#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
-#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
-#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
-#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
-#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
-#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
-
-#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
-
-#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
-#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
-#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
-
-
-#define SSICTL (SPI_BLOCK_BASE|0x00)
-#define SSITIME (SPI_BLOCK_BASE|0x04)
-#define SSITX (SPI_BLOCK_BASE|0x08)
-#define SSIRX (SPI_BLOCK_BASE|0x0C)
-#define SSIINTC (SPI_BLOCK_BASE|0x10)
-#define SSIINTS (SPI_BLOCK_BASE|0x14)
-#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
-#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
-#define SSIID (SPI_BLOCK_BASE|0x20)
-
-
-#define I2CSETUP (I2C_BLOCK_BASE|0x00)
-#define I2CCTRL (I2C_BLOCK_BASE|0x04)
-
-
-#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
-#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
-#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
-#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
-#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
-#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
-#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
-#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
-#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
-#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
-#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
-#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
-#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
-#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
-#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
-#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
-#define TIMERITCR (PWM_BLOCK_BASE|0x60)
-#define TIMERITOP (PWM_BLOCK_BASE|0x64)
-#define PWMCR (PWM_BLOCK_BASE|0x68)
-#define PWMID (PWM_BLOCK_BASE|0x6C)
-#define PWMMON (PWM_BLOCK_BASE|0x70)
-
-
-#define GPIODATA (GPIO_BLOCK_BASE|0x00)
-#define GPIODIR (GPIO_BLOCK_BASE|0x04)
-#define GPIOIS (GPIO_BLOCK_BASE|0x08)
-#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
-#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
-#define GPIOIE (GPIO_BLOCK_BASE|0x14)
-#define GPIORIS (GPIO_BLOCK_BASE|0x18)
-#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
-#define GPIOIC (GPIO_BLOCK_BASE|0x20)
-#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
-#define GPIOPC (GPIO_BLOCK_BASE|0x28)
-
-#define GPIOID (GPIO_BLOCK_BASE|0x30)
-
-
-#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
-#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
-#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
-#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
-#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
-
-struct init_table {
- unsigned int reg;
- unsigned int val;
-};
-
-static struct init_table toshiba_480x640_init_table[] = {
- { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
- { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
- { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
- { 0, 14 }, // wait_ms(14);
- { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
- { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
- { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
- { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
- { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
- { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
- { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
- { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
- { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
- { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
- { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
- { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
- { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
- { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
- { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
- { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
- //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
-#if 0
- { PWM0OFF, 0x00001387 }, // SURF 100% backlight
- { PWM0OFF, 0x00000000 }, // FFA 100% backlight
-#endif
- { PWM0OFF, 0x000009C3 }, // 50% BL
- { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
- { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
- //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
- { PWM1OFF, 0x00001387 },
- { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
- { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
- { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
- { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
- { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
- { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
-
- { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
- { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
- { SSITX, 0x00080036 }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Memory access control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BB }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Display mode setup(2)
- { SSITX, 0x0008003A }, // # Command setting of SPI block
- { SSITX, 0x00000160 }, // # RGB Interface data format
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BF }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Drivnig method
- { SSITX, 0x000800B1 }, // # Command setting of SPI block
- { SSITX, 0x0000015D }, // # Booster operation setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B2 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Booster mode setup
- { SSITX, 0x000800B3 }, // # Command setting of SPI block
- { SSITX, 0x00000122 }, // # Booster frequencies setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B4 }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
- { SSITX, 0x000800B5 }, // # Command setting of SPI block
- { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B6 }, // # Command setting of SPI block
- { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
- { SSITX, 0x000800B7 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # Configure an external display signal
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B9 }, // # Command setting of SPI block
- { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
- { SSITX, 0x000800BD }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # ASW signal control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BE }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { SSITX, 0x000800C0 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C1 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
- { SSITX, 0x000800C2 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C3 }, // # Command setting of SPI block
- { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C4 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C5 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C6 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C7 }, // # Command setting of SPI block
- { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000143 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C8 }, // # Command setting of SPI block
- { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
- { SSITX, 0x000800C9 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CA }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EC }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D0 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D1 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D2 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D3 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D4 }, // # Command setting of SPI block
- { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000016E }, //
- { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
- { SSITX, 0x000800D5 }, // # Command setting of SPI block
- { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800ED }, // # Command setting of SPI block
- { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D6 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D7 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D8 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D9 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DE }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DF }, // # Command setting of SPI block
- { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000013F }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E0 }, // # Command setting of SPI block
- { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x000800E2 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E3 }, // # Command setting of SPI block
- { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E4 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
- { SSITX, 0x00000103 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E5 }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E6 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E7 }, // # Command setting of SPI block
- { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E8 }, // # Command setting of SPI block
- { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
-
-
- { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
- { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
- { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
- { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
- { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
- { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000001 }, // # Oscillator start
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 10 }, // wait_ms(10);
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
- { ASY_DATB, 0x80000000 }, //
- { ASY_DATC, 0x80000000 }, //
- { ASY_DATD, 0x80000000 }, //
- { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
- { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
- { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00004005 }, // # LCD driver control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 20 }, // wait_ms(20);
- { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000000 }, // # LTPS I/F control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
-
- { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
-
- /******************************/
-
- { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
-
- { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
- { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
- { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
- { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
- { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
- { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
- { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
- { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
- { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
- { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
- { HSW, 0x00000003 }, // LCD.HSW
- { HDE_START, 0x00000007 }, // LCD.HDE_START
- { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
- { VCYCLE, 0x00000285 }, // LCD.VCYCLE
- { VSW, 0x00000001 }, // LCD.VSW
- { VDE_START, 0x00000003 }, // LCD.VDE_START
- { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
-
- { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
-
- { 0, 10 }, // wait_ms( 10 );
- { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
- { SSITX, 0x00000180 }, // Display data setup
- { SSITX, 0x0008003B }, // Command setting of SPI block
- { SSITX, 0x00000100 }, // Quad Data configuration - VGA
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B0 }, // Command setting of SPI block
- { SSITX, 0x00000116 }, // Power supply ON/OFF control
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B8 }, // Command setting of SPI block
- { SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
- { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
- { SSITX, 0x00000029 }, // Display on (Command only)
-
- { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
-
- { 0, 0 }
-};
-
-static void _panel_init(struct init_table *init_table)
-{
- unsigned n;
-
- dprintf(INFO, "panel_init()\n");
-
- n = 0;
- while (init_table[n].reg != 0 || init_table[n].val != 0) {
- if (init_table[n].reg != 0)
- mddi_remote_write(init_table[n].val, init_table[n].reg);
- else
- thread_sleep(init_table[n].val);//mdelay(init_table[n].val);
- n++;
- }
-
- dprintf(INFO, "panel_init() done\n");
-}
-
-void panel_init(struct mddi_client_caps *client_caps)
-{
- switch(client_caps->manufacturer_name) {
- case 0xd263: // Toshiba
- dprintf(INFO, "Found Toshiba panel\n");
- _panel_init(toshiba_480x640_init_table);
- break;
- case 0x4474: //??
- if (client_caps->product_code == 0xc065)
- dprintf(INFO, "Found WVGA panel\n");
- break;
- }
-}
-
-void panel_poweron(void)
-{
- gpio_set(88, 0);
- gpio_config(88, GPIO_OUTPUT);
- thread_sleep(1); //udelay(10);
- gpio_set(88, 1);
- thread_sleep(10); //mdelay(10);
-
- //mdelay(1000); // uncomment for second stage boot
-}
-
-void panel_backlight(int on)
-{}
diff --git a/target/msm7627_7x_ffa/rules.mk b/target/msm7627_7x_ffa/rules.mk
deleted file mode 100755
index 148ffdd..0000000
--- a/target/msm7627_7x_ffa/rules.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
-
-PLATFORM := msm7k
-
-MEMBASE := 0x00000000 # SMI
-MEMSIZE := 0x00100000 # 1MB
-
-BASE_ADDR := 0x00200000
-
-TAGS_ADDR := BASE_ADDR+0x00000100
-KERNEL_ADDR := BASE_ADDR+0x00008000
-RAMDISK_ADDR := BASE_ADDR+0x01000000
-SCRATCH_ADDR := BASE_ADDR+0x00001000
-
-KEYS_USE_GPIO_KEYPAD := 1
-
-DEFINES += DISPLAY_TYPE_MDDI=0
-
-MODULES += \
- dev/keys \
- lib/ptable
-
-DEFINES += \
- SDRAM_SIZE=$(MEMSIZE) \
- MEMBASE=$(MEMBASE) \
- BASE_ADDR=$(BASE_ADDR) \
- TAGS_ADDR=$(TAGS_ADDR) \
- KERNEL_ADDR=$(KERNEL_ADDR) \
- RAMDISK_ADDR=$(RAMDISK_ADDR) \
- SCRATCH_ADDR=$(SCRATCH_ADDR)
-
-
-OBJS += \
- $(LOCAL_DIR)/init.o \
- $(LOCAL_DIR)/keypad.o \
- $(LOCAL_DIR)/atags.o \
- $(LOCAL_DIR)/panel.o
diff --git a/target/msm7627_7x_ffa/tools/makefile b/target/msm7627_7x_ffa/tools/makefile
deleted file mode 100644
index f01f7ad..0000000
--- a/target/msm7627_7x_ffa/tools/makefile
+++ /dev/null
@@ -1,39 +0,0 @@
-#Makefile to generate appsboot.mbn
-
-ifeq ($(BOOTLOADER_OUT),.)
-APPSBOOTHEADER_DIR := $(BUILDDIR)
-else
-APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../../
-endif
-
-SRC_DIR := target/$(TARGET)/tools
-COMPILER := gcc
-
-ifeq ($(EMMC_BOOT), 1)
- APPSBOOTHDR_FILES := EMMCBOOT.MBN emmc_appsboothd.mbn
-else
- ifeq ($(BUILD_NANDWRITE), 1)
- APPSBOOTHDR_FILES :=
- else
- APPSBOOTHDR_FILES := appsboot.mbn appsboothd.mbn
- endif
-endif
-
-APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
-
-appsboot.mbn: $(OUTBIN)
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.mbn
-
-appsboothd.mbn: mkheader $(OUTBIN)
- $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
-
-EMMCBOOT.MBN: $(OUTBIN)
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
-
-emmc_appsboothd.mbn: mkheader $(OUTBIN)
- $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn unified-boot
-
-mkheader: $(SRC_DIR)/mkheader.c
- ${COMPILER} $(SRC_DIR)/mkheader.c -o $(SRC_DIR)/mkheader
-
diff --git a/target/msm7627_7x_ffa/tools/mkheader.c b/target/msm7627_7x_ffa/tools/mkheader.c
deleted file mode 100644
index 9b03907..0000000
--- a/target/msm7627_7x_ffa/tools/mkheader.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2007, Google Inc. */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-
-#include <sys/stat.h>
-
-int main(int argc, char *argv[])
-{
- struct stat s;
- unsigned size, base;
- int unified_boot = 0;
- unsigned unified_boot_magic[20];
- unsigned non_unified_boot_magic[10];
- unsigned magic_len = 0;
- unsigned *magic;
- int fd;
-
- if(argc < 3) {
- fprintf(stderr,"usage: mkheader <bin> <hdr>\n");
- return -1;
- }
-
- if (argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
- unified_boot = 1;
- }
- }
-
- if(stat(argv[1], &s)) {
- perror("cannot stat binary");
- return -1;
- }
-
- if(unified_boot) {
- magic = unified_boot_magic;
- magic_len = sizeof(unified_boot_magic);
- } else {
- magic = non_unified_boot_magic;
- magic_len = sizeof(non_unified_boot_magic);
- }
-
- size = s.st_size;
- base = 0;
-
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000002; /* nand */
- magic[2] = 0x00000000;
- magic[3] = base;
- magic[4] = size;
- magic[5] = size;
- magic[6] = size + base;
- magic[7] = 0x00000000;
- magic[8] = size + base;
- magic[9] = 0x00000000;
-
- if (unified_boot == 1)
- {
- magic[10] = 0x33836685; /* cookie magic number */
- magic[11] = 0x00000001; /* cookie version */
- magic[12] = 0x00000002; /* file formats */
- magic[13] = 0x00000000;
- magic[14] = 0x00500000; /* 5M for boot.img */
- magic[15] = 0x00000000;
- magic[16] = 0x00000000;
- magic[17] = 0x00000000;
- magic[18] = 0x00000000;
- magic[19] = 0x00000000;
- }
-
- fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
- perror("cannot open header for writing");
- return -1;
- }
- if(write(fd, magic, magic_len) != magic_len) {
- perror("cannot write header");
- close(fd);
- unlink(argv[2]);
- return -1;
- }
- close(fd);
-
- return 0;
-}
diff --git a/target/msm7627_7x_surf/atags.c b/target/msm7627_7x_surf/atags.c
deleted file mode 100644
index 9029ad2..0000000
--- a/target/msm7627_7x_surf/atags.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Code Aurora nor
- * the names of its contributors may be used to endorse or promote
- * products derived from this software without specific prior written
- * permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-unsigned* target_atag_mem(unsigned* ptr)
-{
- return ptr;
-}
diff --git a/target/msm7627_7x_surf/init.c b/target/msm7627_7x_surf/init.c
deleted file mode 100644
index 9014e2d..0000000
--- a/target/msm7627_7x_surf/init.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2009, Google Inc.
- * All rights reserved.
- * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google, Inc. nor the names of its contributors
- * may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <debug.h>
-#include <dev/keys.h>
-#include <dev/gpio_keypad.h>
-#include <lib/ptable.h>
-#include <dev/flash.h>
-#include <smem.h>
-
-#define LINUX_MACHTYPE 1007014
-
-#define VARIABLE_LENGTH 0x10101010
-#define DIFF_START_ADDR 0xF0F0F0F0
-#define NUM_PAGES_PER_BLOCK 0x40
-
-static struct ptable flash_ptable;
-
-/* for these partitions, start will be offset by either what we get from
- * smem, or from the above offset if smem is not useful. Also, we should
- * probably have smem_ptable code populate our flash_ptable.
- *
- * When smem provides us with a full partition table, we can get rid of
- * this altogether.
- *
- */
-static struct ptentry board_part_list[] = {
- {
- .start = 0,
- .length = 40 /* 5MB */,
- .name = "boot",
- },
- {
- .start = 40,
- .length =760 /* 95MB */,
- .name = "system",
- },
- {
- .start = 800,
- .length = 8,
- .name = "splash",
- },
- {
- .start = 808,
- .length = 40 /* 5MB */,
- .name = "cache",
- },
- {
- .start = 848,
- .length = VARIABLE_LENGTH,
- .name = "userdata",
- },
- {
- .start = DIFF_START_ADDR,
- .length = 12 /* 1.5MB */,
- .name = "persist",
- },
- {
- .start = DIFF_START_ADDR,
- .length = 40 /* 5MB */,
- .name = "recovery",
- },
-};
-static int num_parts = sizeof(board_part_list)/sizeof(struct ptentry);
-
-void smem_ptable_init(void);
-unsigned smem_get_apps_flash_start(void);
-
-void keypad_init(void);
-
-int target_is_emmc_boot(void);
-
-void target_init(void)
-{
- unsigned offset;
- struct flash_info *flash_info;
- unsigned total_num_of_blocks;
- bool start_addr_changed = false;
- unsigned next_ptr_start_adr = 0;
- int i;
-
- dprintf(INFO, "target_init()\n");
-
-#if (!ENABLE_NANDWRITE)
- keys_init();
- keypad_init();
-#endif
-
- if (target_is_emmc_boot())
- return;
-
- ptable_init(&flash_ptable);
- smem_ptable_init();
-
- flash_init();
- flash_info = flash_get_info();
- ASSERT(flash_info);
-
- offset = smem_get_apps_flash_start();
- if (offset == 0xffffffff)
- while(1);
-
- total_num_of_blocks = (flash_info->block_size)/NUM_PAGES_PER_BLOCK;
-
- for (i = 0; i < num_parts; i++) {
- struct ptentry *ptn = &board_part_list[i];
- unsigned len = ptn->length;
-
- if(len == VARIABLE_LENGTH)
- {
- start_addr_changed = true;
- unsigned length_for_prt = 0;
- unsigned j;
- for (j = i+1; j < num_parts; j++)
- {
- struct ptentry *temp_ptn = &board_part_list[j];
- ASSERT(temp_ptn->length != VARIABLE_LENGTH);
- length_for_prt += temp_ptn->length;
- }
- len = (total_num_of_blocks - 1) - (offset + ptn->start + length_for_prt);
- ASSERT(len >= 0);
- next_ptr_start_adr = ptn->start + len;
- }
- if((ptn->start == DIFF_START_ADDR) && (start_addr_changed))
- {
- ASSERT(next_ptr_start_adr);
- ptn->start = next_ptr_start_adr;
- next_ptr_start_adr = ptn->start + ptn->length;
- }
- ptable_add(&flash_ptable, ptn->name, offset + ptn->start,
- len, ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
- }
-
- smem_add_modem_partitions(&flash_ptable);
-
- ptable_dump(&flash_ptable);
- flash_set_ptable(&flash_ptable);
-}
-
-unsigned board_machtype(void)
-{
- return LINUX_MACHTYPE;
-}
-
-void reboot_device(unsigned reboot_reason)
-{
- reboot(reboot_reason);
-}
-
-unsigned check_reboot_mode(void)
-{
- unsigned mode[2] = {0, 0};
- unsigned int mode_len = sizeof(mode);
- unsigned smem_status;
-
- smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
- &mode, mode_len );
- if(smem_status)
- {
- dprintf(CRITICAL, "ERROR: unable to read shared memory for reboot mode\n");
- return 0;
- }
- return mode[0];
-}
-
-void target_battery_charging_enable(unsigned enable, unsigned disconnect)
-{
-}
diff --git a/target/msm7627_7x_surf/keypad.c b/target/msm7627_7x_surf/keypad.c
deleted file mode 100644
index c44b06d..0000000
--- a/target/msm7627_7x_surf/keypad.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2009, Google Inc.
- * All rights reserved.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google, Inc. nor the names of its contributors
- * may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <dev/keys.h>
-#include <dev/gpio_keypad.h>
-
-#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
-
-/* don't turn this on without updating the ffa support */
-#define SCAN_FUNCTION_KEYS 0
-
-static unsigned int halibut_row_gpios[] = {
- 31, 32, 33, 34, 35, 41
-#if SCAN_FUNCTION_KEYS
- , 42
-#endif
-};
-
-static unsigned int halibut_col_gpios[] = { 36, 37, 38, 39, 40 };
-
-#define KEYMAP_INDEX(row, col) ((row)*ARRAY_SIZE(halibut_col_gpios) + (col))
-
-static const unsigned short halibut_keymap[ARRAY_SIZE(halibut_col_gpios) * ARRAY_SIZE(halibut_row_gpios)] = {
- [KEYMAP_INDEX(0, 0)] = KEY_5,
- [KEYMAP_INDEX(0, 1)] = KEY_9,
- [KEYMAP_INDEX(0, 2)] = KEY_SOFT1,
- [KEYMAP_INDEX(0, 3)] = KEY_6,
- [KEYMAP_INDEX(0, 4)] = KEY_LEFT,
-
- [KEYMAP_INDEX(1, 0)] = KEY_0,
- [KEYMAP_INDEX(1, 1)] = KEY_RIGHT,
- [KEYMAP_INDEX(1, 2)] = KEY_1,
- [KEYMAP_INDEX(1, 3)] = KEY_SHARP,
- [KEYMAP_INDEX(1, 4)] = KEY_SEND,
-
- [KEYMAP_INDEX(2, 0)] = KEY_VOLUMEUP,
- [KEYMAP_INDEX(2, 1)] = KEY_HOME, /* FA */
- [KEYMAP_INDEX(2, 2)] = KEY_F8, /* QCHT */
- [KEYMAP_INDEX(2, 3)] = KEY_F6, /* R+ */
- [KEYMAP_INDEX(2, 4)] = KEY_F7, /* R- */
-
- [KEYMAP_INDEX(3, 0)] = KEY_UP,
- [KEYMAP_INDEX(3, 1)] = KEY_CLEAR,
- [KEYMAP_INDEX(3, 2)] = KEY_4,
- [KEYMAP_INDEX(3, 3)] = KEY_MUTE, /* SPKR */
- [KEYMAP_INDEX(3, 4)] = KEY_2,
-
- [KEYMAP_INDEX(4, 0)] = KEY_SOFT2, /* SOFT2 */
- [KEYMAP_INDEX(4, 1)] = KEY_CENTER, /* KEY_CENTER */
- [KEYMAP_INDEX(4, 2)] = KEY_DOWN,
- [KEYMAP_INDEX(4, 3)] = KEY_BACK, /* FB */
- [KEYMAP_INDEX(4, 4)] = KEY_8,
-
- [KEYMAP_INDEX(5, 0)] = KEY_VOLUMEDOWN,
- [KEYMAP_INDEX(5, 1)] = KEY_STAR, /* KEY_STAR */
- [KEYMAP_INDEX(5, 2)] = KEY_MAIL, /* MESG */
- [KEYMAP_INDEX(5, 3)] = KEY_3,
- [KEYMAP_INDEX(5, 4)] = KEY_7,
-
-#if SCAN_FUNCTION_KEYS
- [KEYMAP_INDEX(6, 0)] = KEY_F5,
- [KEYMAP_INDEX(6, 1)] = KEY_F4,
- [KEYMAP_INDEX(6, 2)] = KEY_F3,
- [KEYMAP_INDEX(6, 3)] = KEY_F2,
- [KEYMAP_INDEX(6, 4)] = KEY_F1
-#endif
-};
-
-static struct gpio_keypad_info halibut_keypad_info = {
- .keymap = halibut_keymap,
- .output_gpios = halibut_row_gpios,
- .input_gpios = halibut_col_gpios,
- .noutputs = ARRAY_SIZE(halibut_row_gpios),
- .ninputs = ARRAY_SIZE(halibut_col_gpios),
- .settle_time = 5 /* msec */,
- .poll_time = 20 /* msec */,
- .flags = GPIOKPF_DRIVE_INACTIVE,
-};
-
-void keypad_init(void)
-{
- gpio_keypad_init(&halibut_keypad_info);
-}
diff --git a/target/msm7627_7x_surf/panel.c b/target/msm7627_7x_surf/panel.c
deleted file mode 100644
index c2b56a1..0000000
--- a/target/msm7627_7x_surf/panel.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright 2007, Google Inc. */
-
-#include <debug.h>
-#include <dev/gpio.h>
-#include <kernel/thread.h>
-#include <platform/mddi.h>
-
-#define MDDI_CLIENT_CORE_BASE 0x108000
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define SPI_BLOCK_BASE 0x120000
-#define I2C_BLOCK_BASE 0x130000
-#define PWM_BLOCK_BASE 0x140000
-#define GPIO_BLOCK_BASE 0x150000
-#define SYSTEM_BLOCK1_BASE 0x160000
-#define SYSTEM_BLOCK2_BASE 0x170000
-
-
-#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
-#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
-#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
-#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
-#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
-#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
-#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
-#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
-#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
-#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
-#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
-#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
-#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
-#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
-#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
-#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
-#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
-#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
-#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
-#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
-#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
-#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
-
-
-#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
-#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
-#define START (LCD_CONTROL_BLOCK_BASE|0x08)
-#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
-#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
-#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
-#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
-#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
-#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
-#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
-#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
-
-#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
-#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
-#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
-#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
-#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
-#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
-#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
-#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
-#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
-#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
-#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
-#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
-#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
-#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
-#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
-#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
-#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
-#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
-#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
-#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
-#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
-#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
-
-#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
-
-#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
-#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
-#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
-
-
-#define SSICTL (SPI_BLOCK_BASE|0x00)
-#define SSITIME (SPI_BLOCK_BASE|0x04)
-#define SSITX (SPI_BLOCK_BASE|0x08)
-#define SSIRX (SPI_BLOCK_BASE|0x0C)
-#define SSIINTC (SPI_BLOCK_BASE|0x10)
-#define SSIINTS (SPI_BLOCK_BASE|0x14)
-#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
-#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
-#define SSIID (SPI_BLOCK_BASE|0x20)
-
-
-#define I2CSETUP (I2C_BLOCK_BASE|0x00)
-#define I2CCTRL (I2C_BLOCK_BASE|0x04)
-
-
-#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
-#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
-#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
-#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
-#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
-#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
-#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
-#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
-#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
-#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
-#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
-#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
-#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
-#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
-#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
-#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
-#define TIMERITCR (PWM_BLOCK_BASE|0x60)
-#define TIMERITOP (PWM_BLOCK_BASE|0x64)
-#define PWMCR (PWM_BLOCK_BASE|0x68)
-#define PWMID (PWM_BLOCK_BASE|0x6C)
-#define PWMMON (PWM_BLOCK_BASE|0x70)
-
-
-#define GPIODATA (GPIO_BLOCK_BASE|0x00)
-#define GPIODIR (GPIO_BLOCK_BASE|0x04)
-#define GPIOIS (GPIO_BLOCK_BASE|0x08)
-#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
-#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
-#define GPIOIE (GPIO_BLOCK_BASE|0x14)
-#define GPIORIS (GPIO_BLOCK_BASE|0x18)
-#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
-#define GPIOIC (GPIO_BLOCK_BASE|0x20)
-#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
-#define GPIOPC (GPIO_BLOCK_BASE|0x28)
-
-#define GPIOID (GPIO_BLOCK_BASE|0x30)
-
-
-#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
-#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
-#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
-#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
-#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
-
-struct init_table {
- unsigned int reg;
- unsigned int val;
-};
-
-static struct init_table toshiba_480x640_init_table[] = {
- { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
- { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
- { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
- { 0, 14 }, // wait_ms(14);
- { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
- { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
- { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
- { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
- { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
- { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
- { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
- { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
- { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
- { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
- { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
- { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
- { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
- { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
- { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
- { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
- //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
-#if 0
- { PWM0OFF, 0x00001387 }, // SURF 100% backlight
- { PWM0OFF, 0x00000000 }, // FFA 100% backlight
-#endif
- { PWM0OFF, 0x000009C3 }, // 50% BL
- { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
- { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
- //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
- { PWM1OFF, 0x00001387 },
- { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
- { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
- { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
- { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
- { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
- { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
-
- { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
- { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
- { SSITX, 0x00080036 }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Memory access control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BB }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Display mode setup(2)
- { SSITX, 0x0008003A }, // # Command setting of SPI block
- { SSITX, 0x00000160 }, // # RGB Interface data format
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BF }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Drivnig method
- { SSITX, 0x000800B1 }, // # Command setting of SPI block
- { SSITX, 0x0000015D }, // # Booster operation setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B2 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Booster mode setup
- { SSITX, 0x000800B3 }, // # Command setting of SPI block
- { SSITX, 0x00000122 }, // # Booster frequencies setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B4 }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
- { SSITX, 0x000800B5 }, // # Command setting of SPI block
- { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B6 }, // # Command setting of SPI block
- { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
- { SSITX, 0x000800B7 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # Configure an external display signal
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B9 }, // # Command setting of SPI block
- { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
- { SSITX, 0x000800BD }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # ASW signal control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BE }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { SSITX, 0x000800C0 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C1 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
- { SSITX, 0x000800C2 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C3 }, // # Command setting of SPI block
- { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C4 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C5 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C6 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C7 }, // # Command setting of SPI block
- { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000143 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C8 }, // # Command setting of SPI block
- { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
- { SSITX, 0x000800C9 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CA }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EC }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D0 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D1 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D2 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D3 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D4 }, // # Command setting of SPI block
- { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000016E }, //
- { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
- { SSITX, 0x000800D5 }, // # Command setting of SPI block
- { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800ED }, // # Command setting of SPI block
- { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D6 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D7 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D8 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D9 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DE }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DF }, // # Command setting of SPI block
- { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000013F }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E0 }, // # Command setting of SPI block
- { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x000800E2 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E3 }, // # Command setting of SPI block
- { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E4 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
- { SSITX, 0x00000103 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E5 }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E6 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E7 }, // # Command setting of SPI block
- { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E8 }, // # Command setting of SPI block
- { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
-
-
- { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
- { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
- { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
- { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
- { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
- { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000001 }, // # Oscillator start
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 10 }, // wait_ms(10);
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
- { ASY_DATB, 0x80000000 }, //
- { ASY_DATC, 0x80000000 }, //
- { ASY_DATD, 0x80000000 }, //
- { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
- { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
- { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00004005 }, // # LCD driver control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 20 }, // wait_ms(20);
- { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000000 }, // # LTPS I/F control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
-
- { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
-
- /******************************/
-
- { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
-
- { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
- { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
- { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
- { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
- { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
- { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
- { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
- { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
- { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
- { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
- { HSW, 0x00000003 }, // LCD.HSW
- { HDE_START, 0x00000007 }, // LCD.HDE_START
- { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
- { VCYCLE, 0x00000285 }, // LCD.VCYCLE
- { VSW, 0x00000001 }, // LCD.VSW
- { VDE_START, 0x00000003 }, // LCD.VDE_START
- { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
-
- { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
-
- { 0, 10 }, // wait_ms( 10 );
- { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
- { SSITX, 0x00000180 }, // Display data setup
- { SSITX, 0x0008003B }, // Command setting of SPI block
- { SSITX, 0x00000100 }, // Quad Data configuration - VGA
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B0 }, // Command setting of SPI block
- { SSITX, 0x00000116 }, // Power supply ON/OFF control
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B8 }, // Command setting of SPI block
- { SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
- { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
- { SSITX, 0x00000029 }, // Display on (Command only)
-
- { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
-
- { 0, 0 }
-};
-
-static void _panel_init(struct init_table *init_table)
-{
- unsigned n;
-
- dprintf(INFO, "panel_init()\n");
-
- n = 0;
- while (init_table[n].reg != 0 || init_table[n].val != 0) {
- if (init_table[n].reg != 0)
- mddi_remote_write(init_table[n].val, init_table[n].reg);
- else
- thread_sleep(init_table[n].val);//mdelay(init_table[n].val);
- n++;
- }
-
- dprintf(INFO, "panel_init() done\n");
-}
-
-void panel_init(struct mddi_client_caps *client_caps)
-{
- switch(client_caps->manufacturer_name) {
- case 0xd263: // Toshiba
- dprintf(INFO, "Found Toshiba panel\n");
- _panel_init(toshiba_480x640_init_table);
- break;
- case 0x4474: //??
- if (client_caps->product_code == 0xc065)
- dprintf(INFO, "Found WVGA panel\n");
- break;
- }
-}
-
-void panel_poweron(void)
-{
- gpio_set(88, 0);
- gpio_config(88, GPIO_OUTPUT);
- thread_sleep(1); //udelay(10);
- gpio_set(88, 1);
- thread_sleep(10); //mdelay(10);
-
- //mdelay(1000); // uncomment for second stage boot
-}
-
-void panel_backlight(int on)
-{}
diff --git a/target/msm7627_7x_surf/rules.mk b/target/msm7627_7x_surf/rules.mk
deleted file mode 100644
index bcf1ddf..0000000
--- a/target/msm7627_7x_surf/rules.mk
+++ /dev/null
@@ -1,41 +0,0 @@
-LOCAL_DIR := $(GET_LOCAL_DIR)
-
-INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
-
-PLATFORM := msm7k
-
-MEMBASE := 0x00000000 # SMI
-MEMSIZE := 0x00100000 # 1MB
-
-BASE_ADDR := 0x00200000
-
-TAGS_ADDR := BASE_ADDR+0x00000100
-KERNEL_ADDR := BASE_ADDR+0x00008000
-RAMDISK_ADDR := BASE_ADDR+0x01000000
-SCRATCH_ADDR := BASE_ADDR+0x00001000
-
-KEYS_USE_GPIO_KEYPAD := 1
-
-DEFINES += DISPLAY_TYPE_MDDI=0
-DEFINES += DISPLAY_TYPE_LCDC=1
-DEFINES += DISPLAY_SPLASH_SCREEN=0
-
-MODULES += \
- dev/keys \
- lib/ptable
-
-DEFINES += \
- SDRAM_SIZE=$(MEMSIZE) \
- MEMBASE=$(MEMBASE) \
- BASE_ADDR=$(BASE_ADDR) \
- TAGS_ADDR=$(TAGS_ADDR) \
- KERNEL_ADDR=$(KERNEL_ADDR) \
- RAMDISK_ADDR=$(RAMDISK_ADDR) \
- SCRATCH_ADDR=$(SCRATCH_ADDR)
-
-
-OBJS += \
- $(LOCAL_DIR)/init.o \
- $(LOCAL_DIR)/keypad.o \
- $(LOCAL_DIR)/atags.o \
- $(LOCAL_DIR)/panel.o
diff --git a/target/msm7627_7x_surf/tools/makefile b/target/msm7627_7x_surf/tools/makefile
deleted file mode 100644
index 09bc134..0000000
--- a/target/msm7627_7x_surf/tools/makefile
+++ /dev/null
@@ -1,38 +0,0 @@
-#Makefile to generate appsboot.mbn
-
-ifeq ($(BOOTLOADER_OUT),.)
-APPSBOOTHEADER_DIR := $(BUILDDIR)
-else
-APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../../
-endif
-
-SRC_DIR := target/$(TARGET)/tools
-COMPILER := gcc
-
-ifeq ($(EMMC_BOOT), 1)
- APPSBOOTHDR_FILES := EMMCBOOT.MBN emmc_appsboothd.mbn
-else
- ifeq ($(BUILD_NANDWRITE), 1)
- APPSBOOTHDR_FILES :=
- else
- APPSBOOTHDR_FILES := appsboot.mbn appsboothd.mbn
- endif
-endif
-
-APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
-
-appsboot.mbn: $(OUTBIN)
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.mbn
-
-appsboothd.mbn: mkheader $(OUTBIN)
- $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
-
-EMMCBOOT.MBN: $(OUTBIN)
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
- cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
-
-emmc_appsboothd.mbn: mkheader $(OUTBIN)
- $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn unified-boot
-
-mkheader: $(SRC_DIR)/mkheader.c
- ${COMPILER} $(SRC_DIR)/mkheader.c -o $(SRC_DIR)/mkheader
diff --git a/target/msm7627_7x_surf/tools/mkheader.c b/target/msm7627_7x_surf/tools/mkheader.c
deleted file mode 100644
index 9b03907..0000000
--- a/target/msm7627_7x_surf/tools/mkheader.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2007, Google Inc. */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-
-#include <sys/stat.h>
-
-int main(int argc, char *argv[])
-{
- struct stat s;
- unsigned size, base;
- int unified_boot = 0;
- unsigned unified_boot_magic[20];
- unsigned non_unified_boot_magic[10];
- unsigned magic_len = 0;
- unsigned *magic;
- int fd;
-
- if(argc < 3) {
- fprintf(stderr,"usage: mkheader <bin> <hdr>\n");
- return -1;
- }
-
- if (argc == 4) {
- if(!strcmp("unified-boot",argv[3])) {
- unified_boot = 1;
- }
- }
-
- if(stat(argv[1], &s)) {
- perror("cannot stat binary");
- return -1;
- }
-
- if(unified_boot) {
- magic = unified_boot_magic;
- magic_len = sizeof(unified_boot_magic);
- } else {
- magic = non_unified_boot_magic;
- magic_len = sizeof(non_unified_boot_magic);
- }
-
- size = s.st_size;
- base = 0;
-
- magic[0] = 0x00000005; /* appsbl */
- magic[1] = 0x00000002; /* nand */
- magic[2] = 0x00000000;
- magic[3] = base;
- magic[4] = size;
- magic[5] = size;
- magic[6] = size + base;
- magic[7] = 0x00000000;
- magic[8] = size + base;
- magic[9] = 0x00000000;
-
- if (unified_boot == 1)
- {
- magic[10] = 0x33836685; /* cookie magic number */
- magic[11] = 0x00000001; /* cookie version */
- magic[12] = 0x00000002; /* file formats */
- magic[13] = 0x00000000;
- magic[14] = 0x00500000; /* 5M for boot.img */
- magic[15] = 0x00000000;
- magic[16] = 0x00000000;
- magic[17] = 0x00000000;
- magic[18] = 0x00000000;
- magic[19] = 0x00000000;
- }
-
- fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if(fd < 0) {
- perror("cannot open header for writing");
- return -1;
- }
- if(write(fd, magic, magic_len) != magic_len) {
- perror("cannot write header");
- close(fd);
- unlink(argv[2]);
- return -1;
- }
- close(fd);
-
- return 0;
-}