Merge "platform: msm_shared: Add new chip-ids for MSM8x10."
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index c9f763e..f5495f9 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -51,6 +51,7 @@
#include <malloc.h>
#include <boot_stats.h>
#include <sha.h>
+#include <platform/iomap.h>
#if DEVICE_TREE
#include <libfdt.h>
@@ -97,7 +98,12 @@
#define DEFAULT_ERASE_SIZE 4096
#define MAX_PANEL_BUF_SIZE 64
+#if UFS_SUPPORT
+static const char *emmc_cmdline = " androidboot.bootdevice=msm_sdcc.1";
+static const char *ufs_cmdline = " androidboot.bootdevice=msm_ufs.1";
+#else
static const char *emmc_cmdline = " androidboot.emmc=true";
+#endif
static const char *usb_sn_cmdline = " androidboot.serialno=";
static const char *androidboot_mode = " androidboot.mode=";
static const char *display_cmdline = " mdss_mdp.panel=";
@@ -191,11 +197,39 @@
*ptr += sizeof(struct atag_ptbl_entry) / sizeof(unsigned);
}
+#if UFS_SUPPORT
+char* get_boot_dev_cmdline()
+{
+ const char *boot_device;
+ uint32_t val = 0;
+
+ val = target_get_boot_device();
+ switch(val)
+ {
+ case BOOT_DEFAULT:
+ case BOOT_EMMC:
+ boot_device = emmc_cmdline;
+ break;
+ case BOOT_UFS:
+ boot_device = ufs_cmdline;
+ break;
+ default:
+ dprintf(CRITICAL,"ERROR: Unexpected boot_device val=%x",val);
+ ASSERT(0);
+ };
+
+ return boot_device;
+}
+#endif
+
unsigned char *update_cmdline(const char * cmdline)
{
int cmdline_len = 0;
int have_cmdline = 0;
unsigned char *cmdline_final = NULL;
+#if UFS_SUPPORT
+ const char *boot_dev_cmdline = NULL;
+#endif
int pause_at_bootup = 0;
bool gpt_exists = partition_gpt_exists();
@@ -204,7 +238,12 @@
have_cmdline = 1;
}
if (target_is_emmc_boot()) {
+#if UFS_SUPPORT
+ boot_dev_cmdline = get_boot_dev_cmdline();
+ cmdline_len += strlen(boot_dev_cmdline);
+#else
cmdline_len += strlen(emmc_cmdline);
+#endif
}
cmdline_len += strlen(usb_sn_cmdline);
@@ -287,7 +326,11 @@
while ((*dst++ = *src++));
}
if (target_is_emmc_boot()) {
+#if UFS_SUPPORT
+ src = boot_dev_cmdline;
+#else
src = emmc_cmdline;
+#endif
if (have_cmdline) --dst;
have_cmdline = 1;
while ((*dst++ = *src++));
@@ -585,6 +628,7 @@
{
/* Authorized kernel */
device.is_tampered = 0;
+ auth_kernel_img = 1;
}
#if USE_PCOM_SECBOOT
@@ -1194,6 +1238,7 @@
unsigned long long ptn = 0;
unsigned long long size;
int index = INVALID_PTN;
+ uint32_t blocksize;
index = partition_get_index("aboot");
ptn = partition_get_offset(index);
@@ -1206,7 +1251,9 @@
memcpy(info, dev, sizeof(device_info));
- if(mmc_write((ptn + size - 512), 512, (void *)info_buf))
+ blocksize = mmc_get_device_blocksize();
+
+ if(mmc_write((ptn + size - blocksize), blocksize, (void *)info_buf))
{
dprintf(CRITICAL, "ERROR: Cannot write device info\n");
return;
@@ -1219,6 +1266,7 @@
unsigned long long ptn = 0;
unsigned long long size;
int index = INVALID_PTN;
+ uint32_t blocksize;
index = partition_get_index("aboot");
ptn = partition_get_offset(index);
@@ -1229,7 +1277,9 @@
size = partition_get_size(index);
- if(mmc_read((ptn + size - 512), (void *)info_buf, 512))
+ blocksize = mmc_get_device_blocksize();
+
+ if(mmc_read((ptn + size - blocksize), (void *)info_buf, blocksize))
{
dprintf(CRITICAL, "ERROR: Cannot read device info\n");
return;
@@ -1616,12 +1666,16 @@
{
unsigned int chunk;
unsigned int chunk_data_sz;
+ uint32_t *fill_buf = NULL;
+ uint32_t fill_val;
+ uint32_t chunk_blk_cnt = 0;
sparse_header_t *sparse_header;
chunk_header_t *chunk_header;
uint32_t total_blocks = 0;
unsigned long long ptn = 0;
unsigned long long size = 0;
int index = INVALID_PTN;
+ int i;
index = partition_get_index(arg);
ptn = partition_get_offset(index);
@@ -1704,6 +1758,47 @@
data += chunk_data_sz;
break;
+ case CHUNK_TYPE_FILL:
+ if(chunk_header->total_sz != (sparse_header->chunk_hdr_sz +
+ sizeof(uint32_t)))
+ {
+ fastboot_fail("Bogus chunk size for chunk type FILL");
+ return;
+ }
+
+ fill_buf = (uint32_t *)memalign(CACHE_LINE, ROUNDUP(sparse_header->blk_sz, CACHE_LINE));
+ if (!fill_buf)
+ {
+ fastboot_fail("Malloc failed for: CHUNK_TYPE_FILL");
+ return;
+ }
+
+ fill_val = *(uint32_t *)data;
+ data = (char *) data + sizeof(uint32_t);
+ chunk_blk_cnt = chunk_data_sz / sparse_header->blk_sz;
+
+ for (i = 0; i < (sparse_header->blk_sz / sizeof(fill_val)); i++)
+ {
+ fill_buf[i] = fill_val;
+ }
+
+ for (i = 0; i < chunk_blk_cnt; i++)
+ {
+ if(mmc_write(ptn + ((uint64_t)total_blocks*sparse_header->blk_sz),
+ sparse_header->blk_sz,
+ fill_buf))
+ {
+ fastboot_fail("flash write failure");
+ free(fill_buf);
+ return;
+ }
+
+ total_blocks++;
+ }
+
+ free(fill_buf);
+ break;
+
case CHUNK_TYPE_DONT_CARE:
total_blocks += chunk_header->chunk_sz;
break;
@@ -1719,6 +1814,7 @@
break;
default:
+ dprintf(CRITICAL, "Unkown chunk type: %x\n",chunk_header->chunk_type);
fastboot_fail("Unknown chunk type");
return;
}
@@ -1845,11 +1941,7 @@
|| !strcmp(ptn->name, "userdata")
|| !strcmp(ptn->name, "persist")
|| !strcmp(ptn->name, "recoveryfs")) {
- if (flash_ecc_bch_enabled())
- /* Spare data bytes for 8 bit ECC increased by 4 */
- extra = ((page_size >> 9) * 20);
- else
- extra = ((page_size >> 9) * 16);
+ extra = 1;
} else
sz = ROUND_TO_PAGE(sz, page_mask);
@@ -2167,10 +2259,10 @@
unsigned reboot_mode = 0;
bool boot_into_fastboot = false;
- /* Setup page size information for nand/emmc reads */
+ /* Setup page size information for nv storage */
if (target_is_emmc_boot())
{
- page_size = 2048;
+ page_size = mmc_page_size();
page_mask = page_size - 1;
}
else
diff --git a/arch/arm/crt0.S b/arch/arm/crt0.S
index 7f1ad16..d58e234 100644
--- a/arch/arm/crt0.S
+++ b/arch/arm/crt0.S
@@ -50,8 +50,8 @@
/* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */
bic r0, r0, #(1<<15| 1<<13 | 1<<12)
bic r0, r0, #(1<<2 | 1<<0)
- /* enable alignment faults */
- orr r0, r0, #(1<<1)
+ /* disable alignment faults */
+ bic r0, r0, #(1<<1)
/* Write SCTLR */
mcr p15, 0, r0, c1, c0, 0
#ifdef ENABLE_TRUSTZONE
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index a1b8184..1fa8bd5 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -225,7 +225,11 @@
fbimg = &default_fbimg;
fbimg->header.width = SPLASH_IMAGE_HEIGHT;
fbimg->header.height = SPLASH_IMAGE_WIDTH;
+#if DISPLAY_TYPE_MIPI
fbimg->image = (unsigned char *)imageBuffer_rgb888;
+#else
+ fbimg->image = (unsigned char *)imageBuffer;
+#endif
}
fbcon_putImage(fbimg, flag);
@@ -305,7 +309,7 @@
for (i = 0; i < header->width; i++)
{
memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
- fbimg->Image + (i * header->height * bytes_per_bpp),
+ fbimg->image + (i * header->height * bytes_per_bpp),
header->height * bytes_per_bpp);
}
}
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 1d50e89..d4d1cb0 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -76,8 +76,8 @@
{
uint32_t ret = NO_ERROR;
- ret = target_panel_reset(enable, &reset_gpio,
- &enable_gpio, panelstruct.panelresetseq);
+ ret = target_panel_reset(enable, panelstruct.panelresetseq,
+ &panel.panel_info);
return ret;
}
@@ -110,8 +110,7 @@
dprintf(CRITICAL, "Backlight enable failed \n");
return ret;
}
- ret = target_ldo_ctrl(enable, ldo_entry_array,
- TOTAL_LDO_DEFINED);
+ ret = target_ldo_ctrl(enable);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed \n");
return ret;
@@ -138,8 +137,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable, ldo_entry_array,
- TOTAL_LDO_DEFINED);
+ ret = target_ldo_ctrl(enable);
if (ret) {
dprintf(CRITICAL, "ldo control disable failed \n");
return ret;
@@ -154,9 +152,15 @@
{
char *dsi_id = panelstruct.paneldata->panel_controller;
char *panel_node = panelstruct.paneldata->panel_node_id;
+ uint16_t dsi_id_len = 0;
bool ret = true;
- if (buf_size < (strlen(panel_node) + MAX_DSI_STREAM_LEN +
+ if (dsi_id == NULL || panel_node == NULL)
+ return false;
+
+ dsi_id_len = strlen(dsi_id);
+
+ if (buf_size < (strlen(panel_node) + dsi_id_len +
MAX_PANEL_FORMAT_STRING + 1) ||
!strlen(panel_node) ||
!strlen(dsi_id))
@@ -171,8 +175,8 @@
buf_size -= MAX_PANEL_FORMAT_STRING;
strlcpy(pbuf, dsi_id, buf_size);
- pbuf += MAX_DSI_STREAM_LEN;
- buf_size -= MAX_DSI_STREAM_LEN;
+ pbuf += dsi_id_len;
+ buf_size -= dsi_id_len;
strlcpy(pbuf, panel_node, buf_size);
}
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 6d647b2..16dd2c0 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -43,8 +43,6 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
-#define MAX_DSI_STREAM_LEN 6
-
#define MAX_PANEL_FORMAT_STRING 2
/*---------------------------------------------------------------------------*/
@@ -53,12 +51,9 @@
int target_backlight_ctrl(uint8_t enable);
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
-int target_panel_reset(uint8_t enable,
- struct gpio_pin *resetgpio,
- struct gpio_pin *enablegpio,
- struct panel_reset_sequence *resetseq);
-int target_ldo_ctrl(uint8_t enable, struct ldo_entry ldo_entry_array[],
- uint8_t totalldo);
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo);
+int target_ldo_ctrl(uint8_t enable);
void gcdb_display_init(unsigned int rev, void *base);
void gcdb_display_shutdown();
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 8a762bd..f7f1f7f 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -64,6 +64,7 @@
uint32_t panel_bitclock_freq;
uint32_t panel_operating_mode;
uint32_t panel_with_enable_gpio;
+ uint8_t mode_gpio_state;
};
typedef struct panel_resolution{
diff --git a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
new file mode 100644
index 0000000..acda031
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
@@ -0,0 +1,252 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8379A_WVGA_VIDEO_H_
+
+#define _PANEL_HX8379A_WVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config hx8379a_wvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379a_wvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379a_wvga_video_panel_res = {
+ 480, 800, 94, 100, 40, 0, 6, 6, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379a_wvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379a_wvga_video_on_cmd0[] = {
+0x04, 0x00, 0x39, 0xC0,
+0xB9, 0xFF, 0x83, 0x79,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd1[] = {
+0x03, 0x00, 0x39, 0xC0,
+0xBA, 0x51, 0x93, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd2[] = {
+0x14, 0x00, 0x39, 0xC0,
+0xB1, 0x00, 0x50, 0x44,
+0xEA, 0x8D, 0x08, 0x11,
+0x11, 0x11, 0x27, 0x2F,
+0x9A, 0x1A, 0x42, 0x0B,
+0x6E, 0xF1, 0x00, 0xE6,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd3[] = {
+0x0E, 0x00, 0x39, 0xC0,
+0xB2, 0x00, 0x00, 0x3C,
+0x08, 0x04, 0x19, 0x22,
+0x00, 0xFF, 0x08, 0x04,
+0x19, 0x20, 0xFF, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd4[] = {
+0x20, 0x00, 0x39, 0xC0,
+0xB4, 0x80, 0x08, 0x00,
+0x32, 0x10, 0x03, 0x32,
+0x13, 0x70, 0x32, 0x10,
+0x08, 0x37, 0x01, 0x28,
+0x07, 0x37, 0x08, 0x35,
+0x08, 0x3D, 0x44, 0x08,
+0x00, 0x40, 0x08, 0x28,
+0x08, 0x30, 0x30, 0x04,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd5[] = {
+0x30, 0x00, 0x39, 0xC0,
+0xD5, 0x00, 0x00, 0x0A,
+0x00, 0x01, 0x05, 0x00,
+0x03, 0x00, 0x88, 0x88,
+0x88, 0x88, 0x23, 0x01,
+0x67, 0x45, 0x02, 0x13,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x54, 0x76,
+0x10, 0x32, 0x31, 0x20,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd6[] = {
+0x24, 0x00, 0x39, 0xC0,
+0xE0, 0x79, 0x05, 0x0F,
+0x14, 0x26, 0x20, 0x3F,
+0x2A, 0x43, 0x04, 0x0C,
+0x11, 0x15, 0x17, 0x15,
+0x15, 0x10, 0x13, 0x05,
+0x0F, 0x14, 0x26, 0x20,
+0x3F, 0x2A, 0x43, 0x04,
+0x0C, 0x11, 0x15, 0x17,
+0x15, 0x15, 0x10, 0x13,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd7[] = {
+0xcc, 0x02, 0x23, 0x80 };
+
+
+static char hx8379a_wvga_video_on_cmd8[] = {
+0x05, 0x00, 0x39, 0xC0,
+0xB6, 0x00, 0x9C, 0x00,
+0x9C, 0xFF, 0xFF, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd9[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char hx8379a_wvga_video_on_cmd10[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8379a_wvga_video_on_command[] = {
+{ 0x8 , hx8379a_wvga_video_on_cmd0},
+{ 0x8 , hx8379a_wvga_video_on_cmd1},
+{ 0x18 , hx8379a_wvga_video_on_cmd2},
+{ 0x14 , hx8379a_wvga_video_on_cmd3},
+{ 0x24 , hx8379a_wvga_video_on_cmd4},
+{ 0x34 , hx8379a_wvga_video_on_cmd5},
+{ 0x28 , hx8379a_wvga_video_on_cmd6},
+{ 0x4 , hx8379a_wvga_video_on_cmd7},
+{ 0xc , hx8379a_wvga_video_on_cmd8},
+{ 0x4 , hx8379a_wvga_video_on_cmd9},
+{ 0x4 , hx8379a_wvga_video_on_cmd10}
+};
+#define HX8379A_WVGA_VIDEO_ON_COMMAND 11
+
+
+static char hx8379a_wvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char hx8379a_wvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8379a_wvga_video_off_command[] = {
+{ 0x4 , hx8379a_wvga_videooff_cmd0},
+{ 0x4 , hx8379a_wvga_videooff_cmd1}
+};
+#define HX8379A_WVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379a_wvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info hx8379a_wvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info hx8379a_wvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration hx8379a_wvga_video_lane_config = {
+ 2, 1, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379a_wvga_video_timings[] = {
+ 0x78, 0x1B, 0x11, 0x00, 0x3E, 0x43, 0x16, 0x1E, 0x1D, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379a_wvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379a_wvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight hx8379a_wvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_HX8379A_WVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
index 36a88bc..75b8493 100644
--- a/dev/gcdb/display/include/panel_hx8394a_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -148,13 +148,13 @@
static char hx8394a_720p_video_on_cmd11[] = {
0x23, 0x00, 0x39, 0xC0,
-0xe0, 0x01, 0x05, 0x07,
-0x25, 0x35, 0x3f, 0x0b,
-0x32, 0x04, 0x09, 0x0e,
+0xe0, 0x01, 0x0b, 0x10,
+0x25, 0x35, 0x3f, 0x15,
+0x36, 0x04, 0x09, 0x0e,
0x10, 0x13, 0x10, 0x14,
-0x16, 0x1b, 0x01, 0x05,
-0x07, 0x25, 0x35, 0x3f,
-0x0b, 0x32, 0x04, 0x09,
+0x16, 0x1b, 0x01, 0x0b,
+0x10, 0x25, 0x35, 0x3f,
+0x15, 0x36, 0x04, 0x09,
0x0e, 0x10, 0x13, 0x10,
0x14, 0x16, 0x1b, 0xFF, };
diff --git a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
new file mode 100755
index 0000000..7fa9098
--- /dev/null
+++ b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
@@ -0,0 +1,686 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_OTM8018B_FWVGA_VIDEO_H_
+
+#define _PANEL_OTM8018B_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config otm8018b_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_otm8018b_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution otm8018b_fwvga_video_panel_res = {
+ 480, 854, 80, 54, 8, 0, 12, 16, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info otm8018b_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char otm8018b_fwvga_video_on_cmd0[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd1[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xff, 0x80, 0x09, 0x01,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd2[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd3[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xff, 0x80, 0x09, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd4[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd5[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xd6, 0x48, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd6[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x03, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd7[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xff, 0x01, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd8[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd9[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC0, 0x10, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd10[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x82, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd11[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0xA3, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd12[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC5, 0x96, 0x87, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd14[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd15[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD8, 0x74, 0x72, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd16[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd17[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xD9, 0x56, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd18[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd19[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xE1, 0x00, 0x06, 0x0A,
+0x07, 0x03, 0x16, 0x08,
+0x0A, 0x04, 0x06, 0x07,
+0x08, 0x0F, 0x23, 0x22,
+0x05, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd20[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd21[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xE2, 0x00, 0x06, 0x0A,
+0x07, 0x03, 0x16, 0x08,
+0x0A, 0x04, 0x06, 0x07,
+0x08, 0x0F, 0x23, 0x22,
+0x05, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd22[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x81, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd23[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x77, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd24[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd25[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0xEA, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd26[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA1, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd27[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x08, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd28[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x89, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd29[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x08, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd30[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x81, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd31[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x83, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd32[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x92, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd33[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0x01, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd34[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB1, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd35[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0xA9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd36[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x92, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd37[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB3, 0x45, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd38[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd39[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB3, 0x02, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd40[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd41[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0x58, 0x00,
+0x14, 0x16, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd42[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd43[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x30, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd44[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd45[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0x44, 0x00,
+0x00, 0x00, 0x03, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd46[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA6, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd47[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xC1, 0x01, 0x00, 0x00,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd48[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd49[] = {
+0x0D, 0x00, 0x29, 0xC0,
+0xCE, 0x87, 0x03, 0x00,
+0x85, 0x03, 0x00, 0x86,
+0x03, 0x00, 0x84, 0x03,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd50[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd51[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x38, 0x03, 0x03,
+0x58, 0x00, 0x00, 0x00,
+0x38, 0x02, 0x03, 0x59,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd52[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd53[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x38, 0x01, 0x03,
+0x5A, 0x00, 0x00, 0x00,
+0x38, 0x00, 0x03, 0x5B,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd54[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd55[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x30, 0x00, 0x03,
+0x5C, 0x00, 0x00, 0x00,
+0x30, 0x01, 0x03, 0x5D,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd56[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd57[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x30, 0x02, 0x03,
+0x5E, 0x00, 0x00, 0x00,
+0x30, 0x03, 0x03, 0x5F,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd58[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC7, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd59[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd60[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd61[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd62[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd63[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd64[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd65[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCB, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd66[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd67[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCB, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd68[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x84, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd69[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCC, 0x0C, 0x0A, 0x10,
+0x0E, 0x03, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd70[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x9E, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd71[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCC, 0x0B, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd72[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd73[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xCC, 0x09, 0x0F, 0x0D,
+0x01, 0x02, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd74[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd75[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCC, 0x0D, 0x0F, 0x09,
+0x0B, 0x02, 0x01, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd76[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xCE, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd77[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCC, 0x0E, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd78[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd79[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xCC, 0x10, 0x0A, 0x0C,
+0x04, 0x03, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd80[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd81[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xff, 0xff, 0xff, 0xff,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd82[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char otm8018b_fwvga_video_on_cmd83[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd otm8018b_fwvga_video_on_command[] = {
+{ 0x8 , otm8018b_fwvga_video_on_cmd0},
+{ 0x8 , otm8018b_fwvga_video_on_cmd1},
+{ 0x8 , otm8018b_fwvga_video_on_cmd2},
+{ 0x8 , otm8018b_fwvga_video_on_cmd3},
+{ 0x8 , otm8018b_fwvga_video_on_cmd4},
+{ 0x8 , otm8018b_fwvga_video_on_cmd5},
+{ 0x8 , otm8018b_fwvga_video_on_cmd6},
+{ 0x8 , otm8018b_fwvga_video_on_cmd7},
+{ 0x8 , otm8018b_fwvga_video_on_cmd8},
+{ 0x8 , otm8018b_fwvga_video_on_cmd9},
+{ 0x8 , otm8018b_fwvga_video_on_cmd10},
+{ 0x8 , otm8018b_fwvga_video_on_cmd11},
+{ 0x8 , otm8018b_fwvga_video_on_cmd12},
+{ 0x8 , otm8018b_fwvga_video_on_cmd13},
+{ 0x8 , otm8018b_fwvga_video_on_cmd14},
+{ 0x8 , otm8018b_fwvga_video_on_cmd15},
+{ 0x8 , otm8018b_fwvga_video_on_cmd16},
+{ 0x8 , otm8018b_fwvga_video_on_cmd17},
+{ 0x8 , otm8018b_fwvga_video_on_cmd18},
+{ 0x18 , otm8018b_fwvga_video_on_cmd19},
+{ 0x8 , otm8018b_fwvga_video_on_cmd20},
+{ 0x18 , otm8018b_fwvga_video_on_cmd21},
+{ 0x8 , otm8018b_fwvga_video_on_cmd22},
+{ 0x8 , otm8018b_fwvga_video_on_cmd23},
+{ 0x8 , otm8018b_fwvga_video_on_cmd24},
+{ 0x8 , otm8018b_fwvga_video_on_cmd25},
+{ 0x8 , otm8018b_fwvga_video_on_cmd26},
+{ 0x8 , otm8018b_fwvga_video_on_cmd27},
+{ 0x8 , otm8018b_fwvga_video_on_cmd28},
+{ 0x8 , otm8018b_fwvga_video_on_cmd29},
+{ 0x8 , otm8018b_fwvga_video_on_cmd30},
+{ 0x8 , otm8018b_fwvga_video_on_cmd31},
+{ 0x8 , otm8018b_fwvga_video_on_cmd32},
+{ 0x8 , otm8018b_fwvga_video_on_cmd33},
+{ 0x8 , otm8018b_fwvga_video_on_cmd34},
+{ 0x8 , otm8018b_fwvga_video_on_cmd35},
+{ 0x8 , otm8018b_fwvga_video_on_cmd36},
+{ 0x8 , otm8018b_fwvga_video_on_cmd37},
+{ 0x8 , otm8018b_fwvga_video_on_cmd38},
+{ 0x8 , otm8018b_fwvga_video_on_cmd39},
+{ 0x8 , otm8018b_fwvga_video_on_cmd40},
+{ 0xc , otm8018b_fwvga_video_on_cmd41},
+{ 0x8 , otm8018b_fwvga_video_on_cmd42},
+{ 0x8 , otm8018b_fwvga_video_on_cmd43},
+{ 0x8 , otm8018b_fwvga_video_on_cmd44},
+{ 0xc , otm8018b_fwvga_video_on_cmd45},
+{ 0x8 , otm8018b_fwvga_video_on_cmd46},
+{ 0x8 , otm8018b_fwvga_video_on_cmd47},
+{ 0x8 , otm8018b_fwvga_video_on_cmd48},
+{ 0x14 , otm8018b_fwvga_video_on_cmd49},
+{ 0x8 , otm8018b_fwvga_video_on_cmd50},
+{ 0x14 , otm8018b_fwvga_video_on_cmd51},
+{ 0x8 , otm8018b_fwvga_video_on_cmd52},
+{ 0x14 , otm8018b_fwvga_video_on_cmd53},
+{ 0x8 , otm8018b_fwvga_video_on_cmd54},
+{ 0x14 , otm8018b_fwvga_video_on_cmd55},
+{ 0x8 , otm8018b_fwvga_video_on_cmd56},
+{ 0x14 , otm8018b_fwvga_video_on_cmd57},
+{ 0x8 , otm8018b_fwvga_video_on_cmd58},
+{ 0x8 , otm8018b_fwvga_video_on_cmd59},
+{ 0x8 , otm8018b_fwvga_video_on_cmd60},
+{ 0x8 , otm8018b_fwvga_video_on_cmd61},
+{ 0x8 , otm8018b_fwvga_video_on_cmd62},
+{ 0x8 , otm8018b_fwvga_video_on_cmd63},
+{ 0x8 , otm8018b_fwvga_video_on_cmd64},
+{ 0xc , otm8018b_fwvga_video_on_cmd65},
+{ 0x8 , otm8018b_fwvga_video_on_cmd66},
+{ 0xc , otm8018b_fwvga_video_on_cmd67},
+{ 0x8 , otm8018b_fwvga_video_on_cmd68},
+{ 0xc , otm8018b_fwvga_video_on_cmd69},
+{ 0x8 , otm8018b_fwvga_video_on_cmd70},
+{ 0x8 , otm8018b_fwvga_video_on_cmd71},
+{ 0x8 , otm8018b_fwvga_video_on_cmd72},
+{ 0xc , otm8018b_fwvga_video_on_cmd73},
+{ 0x8 , otm8018b_fwvga_video_on_cmd74},
+{ 0xc , otm8018b_fwvga_video_on_cmd75},
+{ 0x8 , otm8018b_fwvga_video_on_cmd76},
+{ 0x8 , otm8018b_fwvga_video_on_cmd77},
+{ 0x8 , otm8018b_fwvga_video_on_cmd78},
+{ 0xc , otm8018b_fwvga_video_on_cmd79},
+{ 0x8 , otm8018b_fwvga_video_on_cmd80},
+{ 0x8 , otm8018b_fwvga_video_on_cmd81},
+{ 0x4 , otm8018b_fwvga_video_on_cmd82},
+{ 0x4 , otm8018b_fwvga_video_on_cmd83}
+};
+#define OTM8018B_FWVGA_VIDEO_ON_COMMAND 84
+
+
+static char otm8018b_fwvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char otm8018b_fwvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd otm8018b_fwvga_video_off_command[] = {
+{ 0x4 , otm8018b_fwvga_videooff_cmd0},
+{ 0x4 , otm8018b_fwvga_videooff_cmd1}
+};
+#define OTM8018B_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state otm8018b_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info otm8018b_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info otm8018b_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration otm8018b_fwvga_video_lane_config = {
+ 2, 1, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t otm8018b_fwvga_video_timings[] = {
+ 0x72, 0x19, 0x11, 0x00, 0x3C, 0x46, 0x14, 0x1C, 0x1C, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing otm8018b_fwvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence otm8018b_fwvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight otm8018b_fwvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_OTM8018B_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_sharp_qhd_video.h b/dev/gcdb/display/include/panel_sharp_qhd_video.h
new file mode 100755
index 0000000..df8c5a5
--- /dev/null
+++ b/dev/gcdb/display/include/panel_sharp_qhd_video.h
@@ -0,0 +1,190 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SHARP_QHD_VIDEO_H_
+
+#define _PANEL_SHARP_QHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config sharp_qhd_video_panel_data = {
+ "qcom,mdss_dsi_sharp_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution sharp_qhd_video_panel_res = {
+ 540, 960, 48, 80, 32, 0, 3, 15, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info sharp_qhd_video_color = {
+ 24, 2, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char sharp_qhd_video_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd1[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd2[] = {
+0x53, 0x2c, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd3[] = {
+0x51, 0xff, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd4[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd5[] = {
+0xae, 0x03, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd6[] = {
+0x3a, 0x77, 0x15, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_on_command[] = {
+{ 0x4 , sharp_qhd_video_on_cmd0},
+{ 0x4 , sharp_qhd_video_on_cmd1},
+{ 0x4 , sharp_qhd_video_on_cmd2},
+{ 0x4 , sharp_qhd_video_on_cmd3},
+{ 0x4 , sharp_qhd_video_on_cmd4},
+{ 0x4 , sharp_qhd_video_on_cmd5},
+{ 0x4 , sharp_qhd_video_on_cmd6}
+};
+#define SHARP_QHD_VIDEO_ON_COMMAND 7
+
+
+static char sharp_qhd_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_off_command[] = {
+{ 0x4 , sharp_qhd_videooff_cmd0},
+{ 0x4 , sharp_qhd_videooff_cmd1}
+};
+#define SHARP_QHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state sharp_qhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info sharp_qhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info sharp_qhd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 0, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration sharp_qhd_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t sharp_qhd_video_timings[] = {
+ 0x46, 0x1d, 0x20, 0x00, 0x39, 0x3a, 0x21, 0x21, 0x32, 0x03, 0x04, 0x00
+};
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_rotation[] = {
+
+};
+#define SHARP_QHD_VIDEO_ROTATION 0
+
+
+static struct panel_timing sharp_qhd_video_timing_info = {
+ 4, 4, 0x04, 0x1c
+};
+
+static struct panel_reset_sequence sharp_qhd_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight sharp_qhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+
+#endif /*_PANEL_SHARP_QHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
new file mode 100755
index 0000000..66c2b5a
--- /dev/null
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -0,0 +1,492 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SSD2080M_720P_VIDEO_H_
+
+#define _PANEL_SSD2080M_720P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config ssd2080m_720p_video_panel_data = {
+ "qcom,mdss_dsi_ssd2080m_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution ssd2080m_720p_video_panel_res = {
+ 720, 1280, 80, 24, 14, 0, 12, 16, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info ssd2080m_720p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char ssd2080m_720p_video_on_cmd0[] = {
+0xFF, 0x01, 0x15, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd1[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC6, 0x63, 0x00, 0x81,
+0x31, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd2[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xCB, 0xE7, 0x80, 0x73,
+0x33, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd3[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xEC, 0xD2, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB3, 0x04, 0x9F, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd5[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xB2, 0x16, 0x1E, 0x10,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd6[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB4, 0x00, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd7[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x04, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd8[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xC2, 0xBE, 0x00, 0x58,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd9[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xC3, 0x01, 0x22, 0x11,
+0x21, 0x0E, 0x80, 0x80,
+0x24, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd10[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xB6, 0x09, 0x16, 0x42,
+0x01, 0x13, 0x00, 0x00,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd11[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xB7, 0x24, 0x26, 0x43,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd12[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB8, 0x16, 0x08, 0x25,
+0x44, 0x08, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd13[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xB9, 0x06, 0x08, 0x07,
+0x09, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd14[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBA, 0x0E, 0x10, 0x0A,
+0x0C, 0x16, 0x05, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd15[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBB, 0xA1, 0xA1, 0xA1,
+0xA1, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd16[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBC, 0x0F, 0x11, 0x0B,
+0x0D, 0x16, 0x05, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd17[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBD, 0xA1, 0xA1, 0xA1,
+0xA1, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd18[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xE6, 0xFF, 0xFF, 0x0F,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd19[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC7, 0x3F, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd20[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xB5, 0x47, 0x00, 0x00,
+0x08, 0x00, 0x01, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd21[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xC4, 0xDF, 0x72, 0x12,
+0x12, 0x66, 0xE3, 0x99,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd22[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD0, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd23[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD1, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd24[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD2, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd25[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD3, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd26[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD4, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd27[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD5, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd28[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD6, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd29[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD7, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd30[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD8, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd31[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD9, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd32[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xDA, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd33[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xDB, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd34[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCC, 0x10, 0x00, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd35[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCE, 0x4E, 0x55, 0xA5,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd36[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xE0, 0x01, 0x02, 0x02,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd37[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xF6, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd38[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xF7, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd39[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE1, 0x90, 0x00, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd40[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xDE, 0x95, 0xCF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd41[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x46, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd42[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC5, 0x77, 0x47, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd43[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xED, 0x00, 0x20, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd44[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd45[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd46[] = {
+0x53, 0x2c, 0x15, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd ssd2080m_720p_video_on_command[] = {
+{ 0x4 , ssd2080m_720p_video_on_cmd0},
+{ 0xc , ssd2080m_720p_video_on_cmd1},
+{ 0xc , ssd2080m_720p_video_on_cmd2},
+{ 0x8 , ssd2080m_720p_video_on_cmd3},
+{ 0x8 , ssd2080m_720p_video_on_cmd4},
+{ 0x8 , ssd2080m_720p_video_on_cmd5},
+{ 0x8 , ssd2080m_720p_video_on_cmd6},
+{ 0x8 , ssd2080m_720p_video_on_cmd7},
+{ 0x8 , ssd2080m_720p_video_on_cmd8},
+{ 0x10 , ssd2080m_720p_video_on_cmd9},
+{ 0xc , ssd2080m_720p_video_on_cmd10},
+{ 0x8 , ssd2080m_720p_video_on_cmd11},
+{ 0xc , ssd2080m_720p_video_on_cmd12},
+{ 0x10 , ssd2080m_720p_video_on_cmd13},
+{ 0x10 , ssd2080m_720p_video_on_cmd14},
+{ 0x10 , ssd2080m_720p_video_on_cmd15},
+{ 0x10 , ssd2080m_720p_video_on_cmd16},
+{ 0x10 , ssd2080m_720p_video_on_cmd17},
+{ 0x8 , ssd2080m_720p_video_on_cmd18},
+{ 0x8 , ssd2080m_720p_video_on_cmd19},
+{ 0xc , ssd2080m_720p_video_on_cmd20},
+{ 0xc , ssd2080m_720p_video_on_cmd21},
+{ 0xc , ssd2080m_720p_video_on_cmd22},
+{ 0xc , ssd2080m_720p_video_on_cmd23},
+{ 0xc , ssd2080m_720p_video_on_cmd24},
+{ 0xc , ssd2080m_720p_video_on_cmd25},
+{ 0xc , ssd2080m_720p_video_on_cmd26},
+{ 0xc , ssd2080m_720p_video_on_cmd27},
+{ 0xc , ssd2080m_720p_video_on_cmd28},
+{ 0xc , ssd2080m_720p_video_on_cmd29},
+{ 0xc , ssd2080m_720p_video_on_cmd30},
+{ 0xc , ssd2080m_720p_video_on_cmd31},
+{ 0xc , ssd2080m_720p_video_on_cmd32},
+{ 0xc , ssd2080m_720p_video_on_cmd33},
+{ 0x8 , ssd2080m_720p_video_on_cmd34},
+{ 0x8 , ssd2080m_720p_video_on_cmd35},
+{ 0x8 , ssd2080m_720p_video_on_cmd36},
+{ 0xc , ssd2080m_720p_video_on_cmd37},
+{ 0xc , ssd2080m_720p_video_on_cmd38},
+{ 0x8 , ssd2080m_720p_video_on_cmd39},
+{ 0x8 , ssd2080m_720p_video_on_cmd40},
+{ 0x8 , ssd2080m_720p_video_on_cmd41},
+{ 0x8 , ssd2080m_720p_video_on_cmd42},
+{ 0x8 , ssd2080m_720p_video_on_cmd43},
+{ 0x4 , ssd2080m_720p_video_on_cmd44},
+{ 0x4 , ssd2080m_720p_video_on_cmd45},
+{ 0x4 , ssd2080m_720p_video_on_cmd46}
+};
+#define SSD2080M_720P_VIDEO_ON_COMMAND 47
+
+
+static char ssd2080m_720p_videooff_cmd0[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd1[] = {
+0x53, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd2[] = {
+0xc2, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd3[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xcf, 0x40, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_videooff_cmd4[] = {
+0xde, 0x84, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd5[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xcb, 0x22, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_videooff_cmd6[] = {
+0xc3, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd ssd2080m_720p_video_off_command[] = {
+{ 0x4 , ssd2080m_720p_videooff_cmd0},
+{ 0x4 , ssd2080m_720p_videooff_cmd1},
+{ 0x4 , ssd2080m_720p_videooff_cmd2},
+{ 0x8 , ssd2080m_720p_videooff_cmd3},
+{ 0x4 , ssd2080m_720p_videooff_cmd4},
+{ 0x8 , ssd2080m_720p_videooff_cmd5},
+{ 0x4 , ssd2080m_720p_videooff_cmd6}
+};
+#define SSD2080M_720P_VIDEO_OFF_COMMAND 7
+
+
+static struct command_state ssd2080m_720p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info ssd2080m_720p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info ssd2080m_720p_video_video_panel = {
+ 1, 0, 0, 0, 1, 0, 2, 0, 0x8
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration ssd2080m_720p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t ssd2080m_720p_video_timings[] = {
+ 0xA8, 0x1F, 0x17, 0x00, 0x2F, 0x2D, 0x1C, 0x21, 0x29, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing ssd2080m_720p_video_timing_info = {
+ 0, 4, 0x20, 0x2F
+};
+
+static struct panel_reset_sequence ssd2080m_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight ssd2080m_720p_video_backlight = {
+ 1, 1, 4095, 100, 1, "bl_ctrl_wled"
+};
+
+
+#endif /*_PANEL_SSD2080M_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_cmd.h b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
new file mode 100644
index 0000000..e088b8d
--- /dev/null
+++ b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
@@ -0,0 +1,320 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_TRULY_WVGA_CMD_H_
+
+#define _PANEL_TRULY_WVGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config truly_wvga_cmd_panel_data = {
+ "qcom,mdss_dsi_truly_wvga_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 11, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution truly_wvga_cmd_panel_res = {
+ 480, 800, 160, 40, 8, 0, 12, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info truly_wvga_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char truly_wvga_cmd_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd1[] = {
+0xb0, 0x04, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd2[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xb3, 0x02, 0x00, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd3[] = {
+0xbd, 0x00, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xc0, 0x18, 0x66, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd5[] = {
+0x10, 0x00, 0x29, 0xC0,
+0xc1, 0x23, 0x31, 0x99,
+0x21, 0x20, 0x00, 0x30,
+0x28, 0x0c, 0x0c, 0x00,
+0x00, 0x00, 0x21, 0x01,
+ };
+
+
+static char truly_wvga_cmd_on_cmd6[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xc2, 0x00, 0x06, 0x06,
+0x01, 0x03, 0x00, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd7[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc8, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd8[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc9, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd9[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xca, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd10[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xd0, 0x29, 0x03, 0xce,
+0xa6, 0x00, 0x43, 0x20,
+0x10, 0x01, 0x00, 0x01,
+0x01, 0x00, 0x03, 0x01,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd11[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xd1, 0x18, 0x0C, 0x23,
+0x03, 0x75, 0x02, 0x50,
+ };
+
+
+static char truly_wvga_cmd_on_cmd12[] = {
+0xd3, 0x11, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xd5, 0x2a, 0x2a, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xde, 0x01, 0x51, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd15[] = {
+0xe6, 0x51, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd16[] = {
+0xfa, 0x03, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd17[] = {
+0xd6, 0x28, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd18[] = {
+0x36, 0x41, 0x15, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd19[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2a, 0x00, 0x00, 0x01,
+0xdf, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd20[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2b, 0x00, 0x00, 0x03,
+0x1f, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd21[] = {
+0x35, 0x00, 0x15, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd22[] = {
+0x03, 0x00, 0x39, 0xC0,
+0x44, 0x00, 0x50, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd23[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd24[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_cmd_on_command[] = {
+{ 0x4 , truly_wvga_cmd_on_cmd0},
+{ 0x4 , truly_wvga_cmd_on_cmd1},
+{ 0x8 , truly_wvga_cmd_on_cmd2},
+{ 0x4 , truly_wvga_cmd_on_cmd3},
+{ 0x8 , truly_wvga_cmd_on_cmd4},
+{ 0x14 , truly_wvga_cmd_on_cmd5},
+{ 0xc , truly_wvga_cmd_on_cmd6},
+{ 0x20 , truly_wvga_cmd_on_cmd7},
+{ 0x20 , truly_wvga_cmd_on_cmd8},
+{ 0x20 , truly_wvga_cmd_on_cmd9},
+{ 0x18 , truly_wvga_cmd_on_cmd10},
+{ 0xc , truly_wvga_cmd_on_cmd11},
+{ 0x4 , truly_wvga_cmd_on_cmd12},
+{ 0x8 , truly_wvga_cmd_on_cmd13},
+{ 0x8 , truly_wvga_cmd_on_cmd14},
+{ 0x4 , truly_wvga_cmd_on_cmd15},
+{ 0x4 , truly_wvga_cmd_on_cmd16},
+{ 0x4 , truly_wvga_cmd_on_cmd17},
+{ 0x4 , truly_wvga_cmd_on_cmd18},
+{ 0xc , truly_wvga_cmd_on_cmd19},
+{ 0xc , truly_wvga_cmd_on_cmd20},
+{ 0x4 , truly_wvga_cmd_on_cmd21},
+{ 0x8 , truly_wvga_cmd_on_cmd22},
+{ 0x4 , truly_wvga_cmd_on_cmd23},
+{ 0x4 , truly_wvga_cmd_on_cmd24}
+};
+#define TRULY_WVGA_CMD_ON_COMMAND 25
+
+
+static char truly_wvga_cmdoff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmdoff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_cmd_off_command[] = {
+{ 0x4 , truly_wvga_cmdoff_cmd0},
+{ 0x4 , truly_wvga_cmdoff_cmd1}
+};
+#define TRULY_WVGA_CMD_OFF_COMMAND 2
+
+
+static struct command_state truly_wvga_cmd_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info truly_wvga_cmd_command_panel = {
+ 1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info truly_wvga_cmd_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration truly_wvga_cmd_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t truly_wvga_cmd_timings[] = {
+ 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing truly_wvga_cmd_timing_info = {
+ 2, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence truly_wvga_cmd_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight truly_wvga_cmd_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_TRULY_WVGA_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_video.h b/dev/gcdb/display/include/panel_truly_wvga_video.h
new file mode 100644
index 0000000..ee1ab28
--- /dev/null
+++ b/dev/gcdb/display/include/panel_truly_wvga_video.h
@@ -0,0 +1,325 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_TRULY_WVGA_VIDEO_H_
+
+#define _PANEL_TRULY_WVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config truly_wvga_video_panel_data = {
+ "qcom,mdss_dsi_truly_wvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution truly_wvga_video_panel_res = {
+ 480, 800, 160, 40, 8, 0, 12, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info truly_wvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char truly_wvga_video_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_video_on_cmd1[] = {
+0xb0, 0x04, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd2[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xb3, 0x02, 0x00, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd3[] = {
+0xbd, 0x00, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xc0, 0x18, 0x66, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd5[] = {
+0x10, 0x00, 0x29, 0xC0,
+0xc1, 0x23, 0x31, 0x99,
+0x21, 0x20, 0x00, 0x30,
+0x28, 0x0c, 0x0c, 0x00,
+0x00, 0x00, 0x21, 0x01,
+ };
+
+
+static char truly_wvga_video_on_cmd6[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xc2, 0x00, 0x06, 0x06,
+0x01, 0x03, 0x00, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd7[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc8, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd8[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc9, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd9[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xca, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd10[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xd0, 0x29, 0x03, 0xce,
+0xa6, 0x00, 0x43, 0x20,
+0x10, 0x01, 0x00, 0x01,
+0x01, 0x00, 0x03, 0x01,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd11[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xd1, 0x18, 0x0C, 0x23,
+0x03, 0x75, 0x02, 0x50,
+ };
+
+
+static char truly_wvga_video_on_cmd12[] = {
+0xd3, 0x11, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xd5, 0x2a, 0x2a, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xde, 0x01, 0x51, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd15[] = {
+0xe6, 0x51, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd16[] = {
+0xfa, 0x03, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd17[] = {
+0xd6, 0x28, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd18[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2a, 0x00, 0x00, 0x01,
+0xdf, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd19[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2b, 0x00, 0x00, 0x03,
+0x1f, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd20[] = {
+0x35, 0x00, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd21[] = {
+0x03, 0x00, 0x39, 0xC0,
+0x44, 0x00, 0x50, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd22[] = {
+0x36, 0xc1, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd23[] = {
+0x3a, 0x77, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd24[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_video_on_cmd25[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_video_on_command[] = {
+{ 0x4 , truly_wvga_video_on_cmd0},
+{ 0x4 , truly_wvga_video_on_cmd1},
+{ 0x8 , truly_wvga_video_on_cmd2},
+{ 0x4 , truly_wvga_video_on_cmd3},
+{ 0x8 , truly_wvga_video_on_cmd4},
+{ 0x14 , truly_wvga_video_on_cmd5},
+{ 0xc , truly_wvga_video_on_cmd6},
+{ 0x20 , truly_wvga_video_on_cmd7},
+{ 0x20 , truly_wvga_video_on_cmd8},
+{ 0x20 , truly_wvga_video_on_cmd9},
+{ 0x18 , truly_wvga_video_on_cmd10},
+{ 0xc , truly_wvga_video_on_cmd11},
+{ 0x4 , truly_wvga_video_on_cmd12},
+{ 0x8 , truly_wvga_video_on_cmd13},
+{ 0x8 , truly_wvga_video_on_cmd14},
+{ 0x4 , truly_wvga_video_on_cmd15},
+{ 0x4 , truly_wvga_video_on_cmd16},
+{ 0x4 , truly_wvga_video_on_cmd17},
+{ 0xc , truly_wvga_video_on_cmd18},
+{ 0xc , truly_wvga_video_on_cmd19},
+{ 0x4 , truly_wvga_video_on_cmd20},
+{ 0x8 , truly_wvga_video_on_cmd21},
+{ 0x4 , truly_wvga_video_on_cmd22},
+{ 0x4 , truly_wvga_video_on_cmd23},
+{ 0x4 , truly_wvga_video_on_cmd24},
+{ 0x4 , truly_wvga_video_on_cmd25}
+};
+#define TRULY_WVGA_VIDEO_ON_COMMAND 26
+
+
+static char truly_wvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_video_off_command[] = {
+{ 0x4 , truly_wvga_videooff_cmd0},
+{ 0x4 , truly_wvga_videooff_cmd1}
+};
+#define TRULY_WVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state truly_wvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info truly_wvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info truly_wvga_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration truly_wvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t truly_wvga_video_timings[] = {
+ 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing truly_wvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence truly_wvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight truly_wvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_TRULY_WVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index da69f20..21936f5 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -112,6 +112,7 @@
pinfo->mipi.stream = pstruct->paneldata->dsi_stream;
pinfo->mipi.dual_dsi = (pstruct->paneldata->panel_operating_mode
& 0x1);
+ pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state;
pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
/* Video Panel configuration */
diff --git a/dev/gcdb/display/rules.mk b/dev/gcdb/display/rules.mk
index 438c6c7..71e35f2 100755
--- a/dev/gcdb/display/rules.mk
+++ b/dev/gcdb/display/rules.mk
@@ -5,5 +5,4 @@
OBJS += \
$(LOCAL_DIR)/gcdb_display.o \
$(LOCAL_DIR)/panel_display.o \
- $(LOCAL_DIR)/oem_panel.o \
$(LOCAL_DIR)/gcdb_autopll.o
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 236aed7..dcd4549 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -203,4 +203,5 @@
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
+void pm8x41_clear_pmic_watchdog(void);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index c8c83ce..9239ce7 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -72,6 +72,7 @@
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
+#define PMIC_WD_RESET_S2_CTL2 0x857
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 915cf52..91f1daa 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -401,3 +401,8 @@
REG_WRITE(DIFF_CLK1_EN_CTL, reg);
}
+
+void pm8x41_clear_pmic_watchdog(void)
+{
+ pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
+}
diff --git a/include/dev/flash.h b/include/dev/flash.h
index 9fa10bc..6c2402d 100644
--- a/include/dev/flash.h
+++ b/include/dev/flash.h
@@ -68,7 +68,7 @@
int flash_erase(struct ptentry *ptn);
int flash_read_ext(struct ptentry *ptn, unsigned extra_per_page,
unsigned offset, void *data, unsigned bytes);
-int flash_write(struct ptentry *ptn, unsigned extra_per_page, const void *data,
+int flash_write(struct ptentry *ptn, unsigned write_extra_bytes, const void *data,
unsigned bytes);
static inline int flash_read(struct ptentry *ptn, unsigned offset, void *data,
diff --git a/include/endian.h b/include/endian.h
index 34bef6e..fe41a6c 100644
--- a/include/endian.h
+++ b/include/endian.h
@@ -49,6 +49,15 @@
#endif
// define a macro that unconditionally swaps
+#define SWAP_64(x) \
+ ((((x) & 0xff00000000000000ull) >> 56) \
+ | (((x) & 0x00ff000000000000ull) >> 40) \
+ | (((x) & 0x0000ff0000000000ull) >> 24) \
+ | (((x) & 0x000000ff00000000ull) >> 8) \
+ | (((x) & 0x00000000ff000000ull) << 8) \
+ | (((x) & 0x0000000000ff0000ull) << 24) \
+ | (((x) & 0x000000000000ff00ull) << 40) \
+ | (((x) & 0x00000000000000ffull) << 56))
#define SWAP_32(x) \
(((uint32_t)(x) << 24) | (((uint32_t)(x) & 0xff00) << 8) |(((uint32_t)(x) & 0x00ff0000) >> 8) | ((uint32_t)(x) >> 24))
#define SWAP_16(x) \
@@ -56,19 +65,25 @@
// standard swap macros
#if BYTE_ORDER == BIG_ENDIAN
+#define LE64(val) SWAP_64(val)
#define LE32(val) SWAP_32(val)
#define LE16(val) SWAP_16(val)
+#define BE64(val) (val)
#define BE32(val) (val)
#define BE16(val) (val)
#else
+#define LE64(val) (val)
#define LE32(val) (val)
#define LE16(val) (val)
+#define BE64(val) SWAP_64(val)
#define BE32(val) SWAP_32(val)
#define BE16(val) SWAP_16(val)
#endif
+#define LE64SWAP(var) (var) = LE64(var);
#define LE32SWAP(var) (var) = LE32(var);
#define LE16SWAP(var) (var) = LE16(var);
+#define BE64SWAP(var) (var) = BE64(var);
#define BE32SWAP(var) (var) = BE32(var);
#define BE16SWAP(var) (var) = BE16(var);
diff --git a/include/target.h b/include/target.h
index 45f1605..c973a61 100644
--- a/include/target.h
+++ b/include/target.h
@@ -48,8 +48,17 @@
void target_fastboot_init(void);
void target_load_ssd_keystore(void);
bool target_is_ssd_enabled(void);
-struct mmc_device *target_mmc_device();
+void *target_mmc_device();
bool target_display_panel_node(char *pbuf, uint16_t buf_size);
+uint32_t target_get_boot_device();
+
+/* Boot device */
+enum boot_device
+{
+ BOOT_DEFAULT=0,
+ BOOT_EMMC=2,
+ BOOT_UFS=4,
+};
#endif
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 432fbdb..c939bad 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -133,13 +133,13 @@
F_END
};
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp2_uart2_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
@@ -151,13 +151,13 @@
},
};
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
{
- .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
.c = {
- .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
},
};
@@ -287,8 +287,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
- CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart7_core_clk", gcc_blsp2_uart2_apps_clk.c),
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 7e6e7d5..d1ca7a9 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -31,6 +31,11 @@
#define MSM_SHARED_BASE 0x0FA00000
+#define SYSTEM_IMEM_BASE 0xFE800000
+
+#define MSM_IOMAP_BASE 0xF9000000
+#define MSM_IOMAP_END 0xFEFFFFFF
+
#define MSM_SHARED_IMEM_BASE 0xFE805000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
@@ -65,6 +70,8 @@
#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+
#define CLK_CTL_BASE 0xFC400000
/* GPLL */
@@ -75,12 +82,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
/* USB */
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
@@ -112,6 +119,8 @@
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
+#define UFS_BASE (0xFC590000 + 0x00004000)
+
#define SPMI_BASE 0xFC4C0000
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
@@ -138,4 +147,9 @@
#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+/* Boot config */
+#define SEC_CTRL_CORE_BASE 0xFC4B8000
+#define BOOT_CONFIG_OFFSET 0x00006034
+#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET)
+
#endif
diff --git a/platform/apq8084/include/platform/irqs.h b/platform/apq8084/include/platform/irqs.h
index 8b25b0c..33e1a12 100644
--- a/platform/apq8084/include/platform/irqs.h
+++ b/platform/apq8084/include/platform/irqs.h
@@ -45,6 +45,8 @@
#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
+#define UFS_IRQ (GIC_SPI_START + 28)
+
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
#define USB2_IRQ (GIC_SPI_START + 141)
diff --git a/platform/apq8084/platform.c b/platform/apq8084/platform.c
index 1e4bc85..85aba7e 100644
--- a/platform/apq8084/platform.c
+++ b/platform/apq8084/platform.c
@@ -37,6 +37,30 @@
#include <smem.h>
#include <board.h>
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ /* IMEM needs a seperate entry in the table as it's length is only 0x8000. */
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
void platform_early_init(void)
{
board_init();
@@ -58,3 +82,78 @@
qtimer_uninit();
}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ ram_partition ptn_entry;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 5284d0f..e66208c 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -481,6 +481,83 @@
}
}
+void mmss_clock_auto_pll_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change because
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure S0 AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ if (dual_dsi) {
+ /* Configure Byte 1 clock */
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+ }
+}
+
void mmss_clock_disable(uint32_t dual_dsi)
{
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index f83c2ae..3f6bd14 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -67,6 +67,9 @@
#define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000)
#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI_PIXEL0_M REG_MM(0x2008)
+#define DSI_PIXEL0_N REG_MM(0x200C)
+#define DSI_PIXEL0_D REG_MM(0x2010)
#define DSI0_PHY_PLL_OUT BIT(8)
#define PIXEL_SRC_DIV_1_5 BIT(1)
@@ -80,6 +83,9 @@
#define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020)
#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define DSI_PIXEL1_M REG_MM(0x2028)
+#define DSI_PIXEL1_N REG_MM(0x202C)
+#define DSI_PIXEL1_D REG_MM(0x2030)
#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
diff --git a/platform/msm8974/platform.c b/platform/msm8974/platform.c
index be35f84..b4e0a7b 100644
--- a/platform/msm8974/platform.c
+++ b/platform/msm8974/platform.c
@@ -87,11 +87,32 @@
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+/* Check for 8974 chip */
+int platform_is_8974()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case APQ8074:
+ case MSM8274:
+ case MSM8674:
+ case MSM8974:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
addr_t get_bs_info_addr()
{
uint32_t soc_ver = board_soc_version();
- if (soc_ver < BOARD_SOC_VERSION2)
+ if (platform_is_8974() && (soc_ver < BOARD_SOC_VERSION2))
return ((addr_t)BS_INFO_ADDR_V1);
else
return ((addr_t)BS_INFO_ADDR_V2);
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 7ff5a82..ef81891 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -45,6 +45,9 @@
uint32_t size;
};
+static struct dt_mem_node_info mem_node;
+
+static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask);
extern int target_is_emmc_boot(void);
extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
/* TODO: This function needs to be moved to target layer to check violations
@@ -52,23 +55,32 @@
*/
extern int check_aboot_addr_range_overlap(uint32_t start, uint32_t size);
-struct msm_id
-{
- uint32_t platform_id;
- uint32_t hardware_id;
- uint32_t soc_rev;
-};
-
/* Returns soc version if platform id and hardware id matches
otherwise return 0xFFFFFFFF */
#define INVALID_SOC_REV_ID 0XFFFFFFFF
static uint32_t dev_tree_compatible(void *dtb)
{
int root_offset;
- const void *prop;
- char model[128];
- struct msm_id msm_id;
+ const void *prop = NULL;
+ const char *plat_prop = NULL;
+ const char *board_prop = NULL;
+ char *model = NULL;
+ struct dt_entry cur_dt_entry;
+ struct dt_entry *dt_entry_v2 = NULL;
+ struct board_id *board_data = NULL;
+ struct plat_id *platform_data = NULL;
int len;
+ int len_board_id;
+ int len_plat_id;
+ int min_plat_id_len = 0;
+ uint32_t target_variant_id;
+ uint32_t dtb_ver;
+ uint32_t num_entries = 0;
+ uint32_t i, j, k;
+ uint32_t found = 0;
+ uint32_t msm_data_count;
+ uint32_t board_data_count;
+ uint32_t soc_rev;
root_offset = fdt_path_offset(dtb, "/");
if (root_offset < 0)
@@ -76,49 +88,199 @@
prop = fdt_getprop(dtb, root_offset, "model", &len);
if (prop && len > 0) {
- memcpy(model, prop, MIN((int)sizeof(model), len));
- model[sizeof(model) - 1] = '\0';
+ model = (char *) malloc(sizeof(char) * len);
+ ASSERT(model);
+ strlcpy(model, prop, len);
} else {
model[0] = '\0';
}
- prop = fdt_getprop(dtb, root_offset, "qcom,msm-id", &len);
- if (!prop || len <= 0) {
+ /* Find the board-id prop from DTB , if board-id is present then
+ * the DTB is version 2 */
+ board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
+ if (board_prop)
+ {
+ dtb_ver = DEV_TREE_VERSION_V2;
+ min_plat_id_len = PLAT_ID_SIZE;
+ }
+ else
+ {
+ dtb_ver = DEV_TREE_VERSION_V1;
+ min_plat_id_len = DT_ENTRY_V1_SIZE;
+ }
+
+ /* Get the msm-id prop from DTB */
+ plat_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,msm-id", &len_plat_id);
+ if (!plat_prop || len_plat_id <= 0) {
dprintf(INFO, "qcom,msm-id entry not found\n");
return false;
- } else if (len < (int)sizeof(struct msm_id)) {
- dprintf(INFO, "qcom,msm-id entry size mismatch (%d != %d)\n",
- len, sizeof(struct msm_id));
+ } else if (len_plat_id % min_plat_id_len) {
+ dprintf(INFO, "qcom,msm-id in device tree is (%d) not a multiple of (%d)\n",
+ len_plat_id, min_plat_id_len);
return false;
}
- msm_id.platform_id = fdt32_to_cpu(((const struct msm_id *)prop)->platform_id);
- msm_id.hardware_id = fdt32_to_cpu(((const struct msm_id *)prop)->hardware_id);
- msm_id.soc_rev = fdt32_to_cpu(((const struct msm_id *)prop)->soc_rev);
- dprintf(INFO, "Found an appended flattened device tree (%s - %d %d 0x%x)\n",
- *model ? model : "unknown",
- msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
+ /*
+ * If DTB version is '1' look for <x y z> pair in the DTB
+ * x: platform_id
+ * y: variant_id
+ * z: SOC rev
+ */
+ if (dtb_ver == DEV_TREE_VERSION_V1)
+ {
+ while (len_plat_id)
+ {
+ cur_dt_entry.platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
+ cur_dt_entry.variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
+ cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
+ cur_dt_entry.board_hw_subtype = board_hardware_subtype();
- if (msm_id.platform_id != board_platform_id() ||
- msm_id.hardware_id != board_hardware_id()) {
- dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_soc_version());
- return INVALID_SOC_REV_ID;
+ target_variant_id = board_hardware_id();
+
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
+
+ if (platform_dt_match(&cur_dt_entry, target_variant_id, 0) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ plat_prop += DT_ENTRY_V1_SIZE;
+ len_plat_id -= DT_ENTRY_V1_SIZE;
+ continue;
+ }
+ else
+ {
+ found = 1;
+ break;
+ }
+ }
+ }
+ /*
+ * If DTB Version is '2' then we have split DTB with board & msm data
+ * populated saperately in board-id & msm-id prop respectively.
+ * Extract the data & prepare a look up table
+ */
+ else if (dtb_ver == DEV_TREE_VERSION_V2)
+ {
+ board_data_count = (len_board_id / BOARD_ID_SIZE);
+ msm_data_count = (len_plat_id / PLAT_ID_SIZE);
+
+ /* If we are using dtb v2.0, then we have split board & msm data in the DTB */
+ board_data = (struct board_id *) malloc(sizeof(struct board_id) * (len_board_id / BOARD_ID_SIZE));
+ ASSERT(board_data);
+ platform_data = (struct plat_id *) malloc(sizeof(struct plat_id) * (len_plat_id / PLAT_ID_SIZE));
+ ASSERT(platform_data);
+ i = 0;
+
+ /* Extract board data from DTB */
+ for(i = 0 ; i < board_data_count; i++)
+ {
+ board_data[i].variant_id = fdt32_to_cpu(((struct board_id *)board_prop)->variant_id);
+ board_data[i].platform_subtype = fdt32_to_cpu(((struct board_id *)board_prop)->platform_subtype);
+ len_board_id -= sizeof(struct board_id);
+ board_prop += sizeof(struct board_id);
+ }
+
+ /* Extract platform data from DTB */
+ for(i = 0 ; i < msm_data_count; i++)
+ {
+ platform_data[i].platform_id = fdt32_to_cpu(((struct plat_id *)plat_prop)->platform_id);
+ platform_data[i].soc_rev = fdt32_to_cpu(((struct plat_id *)plat_prop)->soc_rev);
+ len_plat_id -= sizeof(struct plat_id);
+ plat_prop += sizeof(struct plat_id);
+ }
+
+ /* We need to merge board & platform data into dt entry structure */
+ num_entries = msm_data_count * board_data_count;
+ dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+ ASSERT(dt_entry_v2);
+
+ /* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
+ * Then dt entry should look like
+ * <X ,A >;<X, B>;<X, C>;
+ * <Y ,A >;<Y, B>;<Y, C>;
+ * <Z ,A >;<Z, B>;<Z, C>;
+ */
+ i = 0;
+ k = 0;
+ for (i = 0; i < msm_data_count; i++)
+ {
+ for (j = 0; j < board_data_count; j++)
+ {
+ dt_entry_v2[k].platform_id = platform_data[i].platform_id;
+ dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_v2[k].variant_id = board_data[j].variant_id;
+ dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
+ k++;
+ }
+ }
+
+ /* Now find the matching entry in the merged list */
+ if (board_hardware_id() == HW_PLATFORM_QRD)
+ target_variant_id = board_target_id();
+ else
+ target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+
+ for (i=0 ;i < num_entries; i++)
+ {
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+
+ if (platform_dt_match(&dt_entry_v2[i], target_variant_id, 0xff) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
+ dt_entry_v2[i].platform_id,
+ dt_entry_v2[i].variant_id,
+ dt_entry_v2[i].soc_rev,
+ dt_entry_v2[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ continue;
+ }
+ else
+ {
+ /* If found a match, return the cur_dt_entry */
+ found = 1;
+ cur_dt_entry = dt_entry_v2[i];
+ break;
+ }
+ }
}
- dprintf(INFO, "Device tree's msm_id matches the board: <%d %d 0x%x> == <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
+ if (!found)
+ {
+ soc_rev = INVALID_SOC_REV_ID;
+ goto end;
+ }
+ else
+ soc_rev = cur_dt_entry.soc_rev;
+
+ dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.board_hw_subtype,
+ cur_dt_entry.soc_rev,
board_platform_id(),
board_hardware_id(),
+ board_hardware_subtype(),
board_soc_version());
- return msm_id.soc_rev;
+
+end:
+ free(board_data);
+ free(platform_data);
+ free(dt_entry_v2);
+ free(model);
+
+ return soc_rev;
}
/*
@@ -391,7 +553,6 @@
ret);
}
-
ret = fdt_appendprop_u32(fdt, offset, "reg", size);
if (ret)
@@ -403,37 +564,172 @@
return ret;
}
-/* Function to add the subsequent RAM partition info to the device tree. */
-int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t addr, uint32_t size)
+static int dev_tree_query_memory_cell_sizes(void *fdt, struct dt_mem_node_info *mem_node, uint32_t mem_node_offset)
{
- static int mem_info_cnt = 0;
- int ret;
+ int len;
+ uint32_t *valp;
+ int ret;
+ uint32_t offset;
- if (!mem_info_cnt)
+ mem_node->offset = mem_node_offset;
+
+ /* Get offset of the root node */
+ ret = fdt_path_offset(fdt, "/");
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Could not find memory node.\n");
+ return ret;
+ }
+
+ offset = ret;
+
+ /* Find the #address-cells size. */
+ valp = (uint32_t*)fdt_getprop(fdt, offset, "#address-cells", &len);
+ if (len <= 0)
+ {
+ if (len == -FDT_ERR_NOTFOUND)
+ {
+ /* Property not found.
+ * Assume standard sizes.
+ */
+ mem_node->addr_cell_size = 2;
+ dprintf(CRITICAL, "Using default #addr_cell_size: %u\n", mem_node->addr_cell_size);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Error finding the #address-cells property\n");
+ return len;
+ }
+ }
+ else
+ mem_node->addr_cell_size = fdt32_to_cpu(*valp);
+
+ /* Find the #size-cells size. */
+ valp = (uint32_t*)fdt_getprop(fdt, offset, "#size-cells", &len);
+ if (len <= 0)
+ {
+ if (len == -FDT_ERR_NOTFOUND)
+ {
+ /* Property not found.
+ * Assume standard sizes.
+ */
+ mem_node->size_cell_size = 1;
+ dprintf(CRITICAL, "Using default #size_cell_size: %u\n", mem_node->size_cell_size);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Error finding the #size-cells property\n");
+ return len;
+ }
+ }
+ else
+ mem_node->size_cell_size = fdt32_to_cpu(*valp);
+
+ return 0;
+}
+
+static void dev_tree_update_memory_node(uint32_t offset)
+{
+ mem_node.offset = offset;
+ mem_node.addr_cell_size = 1;
+ mem_node.size_cell_size = 1;
+}
+
+/* Function to add the subsequent RAM partition info to the device tree. */
+int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint64_t addr, uint64_t size)
+{
+ int ret = 0;
+
+ if(smem_get_ram_ptable_version() >= 1)
+ {
+ ret = dev_tree_query_memory_cell_sizes(fdt, &mem_node, offset);
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Could not find #address-cells and #size-cells properties: ret %d\n", ret);
+ return ret;
+ }
+
+ }
+ else
+ {
+ dev_tree_update_memory_node(offset);
+ }
+
+ if (!(mem_node.mem_info_cnt))
{
/* Replace any other reg prop in the memory node. */
- ret = fdt_setprop_u32(fdt, offset, "reg", addr);
- mem_info_cnt = 1;
+
+ /* cell_size is the number of 32 bit words used to represent an address/length in the device tree.
+ * memory node in DT can be either 32-bit(cell-size = 1) or 64-bit(cell-size = 2).So when updating
+ * the memory node in the device tree, we write one word or two words based on cell_size = 1 or 2.
+ */
+
+ if(mem_node.addr_cell_size == 2)
+ {
+ ret = fdt_setprop_u32(fdt, mem_node.offset, "reg", addr >> 32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not set prop reg for memory node\n");
+ return ret;
+ }
+
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
+ }
+ else
+ {
+ ret = fdt_setprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not set prop reg for memory node\n");
+ return ret;
+ }
+ }
+
+ mem_node.mem_info_cnt = 1;
}
else
{
/* Append the mem info to the reg prop for subsequent nodes. */
- ret = fdt_appendprop_u32(fdt, offset, "reg", addr);
+ if(mem_node.addr_cell_size == 2)
+ {
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", addr >> 32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
+ }
+
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
}
- if (ret)
+ if(mem_node.size_cell_size == 2)
{
- dprintf(CRITICAL, "Failed to add the memory information addr: %d\n",
- ret);
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", size>>32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
}
-
- ret = fdt_appendprop_u32(fdt, offset, "reg", size);
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)size);
if (ret)
{
dprintf(CRITICAL, "Failed to add the memory information size: %d\n",
ret);
+ return ret;
}
return ret;
diff --git a/platform/msm_shared/dme.c b/platform/msm_shared/dme.c
new file mode 100644
index 0000000..bc564f2
--- /dev/null
+++ b/platform/msm_shared/dme.c
@@ -0,0 +1,390 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <string.h>
+#include <reg.h>
+#include <arch/defines.h>
+#include <sys/types.h>
+#include <stdlib.h>
+#include <endian.h>
+#include <ufs.h>
+#include <dme.h>
+#include <uic.h>
+#include <utp.h>
+
+int dme_send_linkstartup_req(struct ufs_dev *dev)
+{
+ struct uic_cmd cmd;
+
+ cmd.uiccmd = UICCMDR_DME_LINKSTARTUP;
+ cmd.num_args = UICCMD_NO_ARGS;
+ cmd.timeout_msecs = DME_LINK_START_TIMEOUT;
+
+ if (uic_send_cmd(dev, &cmd) || cmd.gen_err_code == UICCMD_FAILURE)
+ goto dme_send_linkstartup_req_err;
+
+ return UFS_SUCCESS;
+
+dme_send_linkstartup_req_err:
+ dprintf(CRITICAL, "DME_LINKSTARTUP command failed.\n");
+ return -UFS_FAILURE;
+}
+
+int dme_get_req(struct ufs_dev *dev, struct dme_get_req_type *req)
+{
+ struct uic_cmd cmd;
+
+ cmd.uiccmd = UICCMDR_DME_GET;
+ cmd.num_args = UICCMD_ONE_ARGS;
+ cmd.uiccmdarg1 = req->attribute << 16 | req->index;
+ cmd.timeout_msecs = INFINITE_TIME;
+
+ if (uic_send_cmd(dev, &cmd) || cmd.gen_err_code == UICCMD_FAILURE)
+ goto dme_get_req_err;
+
+ /* Return the result. */
+ *(req->mibval) = cmd.uiccmdarg3;
+
+ return UFS_SUCCESS;
+
+dme_get_req_err:
+ dprintf(CRITICAL, "DME_GET command failed.\n");
+ return -UFS_FAILURE;
+}
+
+static int dme_get_query_resp(struct ufs_dev *dev,
+ struct upiu_req_build_type *req_upiu,
+ addr_t buffer,
+ size_t buf_len)
+{
+ struct upiu_trans_mgmt_query_hdr *resp_upiu;
+
+ resp_upiu = (struct upiu_trans_mgmt_query_hdr *) req_upiu->resp_ptr;
+
+ if (resp_upiu->opcode != req_upiu->opcode)
+ return -UFS_FAILURE;
+ if (resp_upiu->basic_hdr.response != UPIU_QUERY_RESP_SUCCESS)
+ return -UFS_FAILURE;
+
+ switch (resp_upiu->opcode)
+ {
+ case UPIU_QUERY_OP_READ_FLAG:
+ case UPIU_QUERY_OP_SET_FLAG:
+ if (buf_len < sizeof(uint32_t))
+ {
+ dprintf(CRITICAL, "Insufficient buffer space.\n");
+ return -UFS_FAILURE;
+ }
+
+ *((uint32_t *) buffer) = resp_upiu->flag_value;
+ break;
+ case UPIU_QUERY_OP_TOGGLE_FLAG:
+ case UPIU_QUERY_OP_CLEAR_FLAG:
+ case UPIU_QUERY_OP_READ_DESCRIPTOR:
+ break;
+ default: dprintf(CRITICAL, "UPIU query opcode not supported.\n");
+ return -UFS_FAILURE;
+ }
+
+ return UFS_SUCCESS;
+}
+
+static int dme_send_query_upiu(struct ufs_dev *dev, struct utp_query_req_upiu_type *query)
+{
+ struct upiu_trans_mgmt_query_hdr resp_upiu;
+ struct upiu_req_build_type req_upiu;
+ int ret;
+
+ memset(&req_upiu, 0, sizeof(req_upiu));
+
+ req_upiu.opcode = query->opcode;
+ req_upiu.selector = query->selector;
+ req_upiu.index = query->index;
+ req_upiu.idn = query->idn;
+ req_upiu.trans_type = UPIU_TYPE_QUERY_REQ;
+ req_upiu.dd = UTRD_NO_DATA_TRANSFER;
+ req_upiu.resp_ptr = (struct upiu_basic_hdr *) &resp_upiu;
+ req_upiu.resp_len = sizeof(resp_upiu);
+ req_upiu.resp_data_ptr = query->buf;
+ req_upiu.timeout_msecs = UTP_GENERIC_CMD_TIMEOUT;
+
+ if (query->opcode == UPIU_QUERY_OP_READ_DESCRIPTOR)
+ {
+ req_upiu.resp_data_len = query->buf_len;
+ }
+
+ ret = utp_enqueue_upiu(dev, &req_upiu);
+ if (ret)
+ goto utp_send_query_upiu_err;
+
+ ret = dme_get_query_resp(dev, &req_upiu, query->buf, query->buf_len);
+ if (ret)
+ goto utp_send_query_upiu_err;
+
+utp_send_query_upiu_err:
+ return ret;
+}
+
+int dme_set_fdeviceinit(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(result, sizeof(uint32_t));
+ uint32_t try_again = DME_FDEVICEINIT_RETRIES;
+ struct utp_query_req_upiu_type read_query = {UPIU_QUERY_OP_READ_FLAG,
+ UFS_IDX_fDeviceInit,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+ struct utp_query_req_upiu_type set_query = {UPIU_QUERY_OP_SET_FLAG,
+ UFS_IDX_fDeviceInit,
+ 0,
+ 0,
+ (addr_t) result,
+ sizeof(uint32_t)};
+
+
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ arch_invalidate_cache_range((addr_t) result, sizeof(uint32_t));
+
+ if (*result == 1)
+ goto utp_set_fdeviceinit_done;
+
+ do
+ {
+ try_again--;
+
+ if (dme_send_query_upiu(dev, &set_query))
+ return -UFS_FAILURE;
+
+ if (dme_send_query_upiu(dev, &read_query))
+ return -UFS_FAILURE;
+
+ if (*result == 1)
+ break;
+ } while (try_again);
+
+utp_set_fdeviceinit_done:
+ return UFS_SUCCESS;
+}
+
+int dme_read_string_desc(struct ufs_dev *dev, uint8_t index, struct ufs_string_desc *desc)
+{
+ struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
+ UFS_DESC_IDN_STRING,
+ index,
+ 0,
+ (addr_t) desc,
+ sizeof(struct ufs_string_desc)};
+
+ if (dme_send_query_upiu(dev, &query))
+ return -UFS_FAILURE;
+
+ if (desc->desc_len != 0)
+ return UFS_SUCCESS;
+
+ return -UFS_FAILURE;
+}
+
+static uint32_t dme_parse_serial_no(struct ufs_string_desc *desc)
+{
+ uint32_t serial_no=0;
+ uint16_t *ptr;
+ int index=0,len=0;
+
+ if(desc->desc_len <= 0)
+ return -UFS_FAILURE;
+
+ ptr = desc->serial_num;
+ len = (desc->desc_len-2)/2;
+
+ for(index=0; index<len; index++)
+ {
+ serial_no += *ptr;
+ ptr++;
+ }
+
+ return serial_no;
+}
+
+int dme_read_device_desc(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(dev_desc, sizeof(struct ufs_dev_desc));
+ STACKBUF_DMA_ALIGN(desc, sizeof(struct ufs_string_desc));
+ struct ufs_dev_desc *device_desc = dev_desc;
+ struct ufs_string_desc *str_desc = desc;
+ struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
+ UFS_DESC_IDN_DEVICE,
+ 0,
+ 0,
+ (addr_t) dev_desc,
+ sizeof(struct ufs_dev_desc)};
+
+ if (dme_send_query_upiu(dev, &query))
+ return -UFS_FAILURE;
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) device_desc, sizeof(struct ufs_dev_desc));
+
+ /* Store all relevant data */
+ dev->num_lus = device_desc->num_lu;
+
+ /* Get serial number for the device based on the string index. */
+ if (dme_read_string_desc(dev, device_desc->serial_num, desc))
+ return -UFS_FAILURE;
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) str_desc, sizeof(struct ufs_string_desc));
+
+ dev->serial_num = dme_parse_serial_no(str_desc);
+
+ return UFS_SUCCESS;
+}
+
+int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index, uint64_t *capacity)
+{
+ STACKBUF_DMA_ALIGN(unit_desc, sizeof(struct ufs_unit_desc));
+ struct ufs_unit_desc *desc = unit_desc;
+ struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
+ UFS_DESC_IDN_UNIT,
+ index,
+ 0,
+ (addr_t) unit_desc,
+ sizeof(struct ufs_unit_desc)};
+
+ if (dme_send_query_upiu(dev, &query))
+ return -UFS_FAILURE;
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) desc, sizeof(struct ufs_unit_desc));
+
+ *capacity = BE64(desc->logical_blk_cnt) * dev->block_size;
+
+ return UFS_SUCCESS;
+}
+
+int dme_read_config_desc(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(desc, sizeof(struct ufs_config_desc));
+ struct ufs_config_desc *config_desc = desc;
+ struct utp_query_req_upiu_type query = {UPIU_QUERY_OP_READ_DESCRIPTOR,
+ UFS_DESC_IDN_CONFIGURATION,
+ 0,
+ 0,
+ (addr_t) config_desc,
+ sizeof(struct ufs_config_desc)};
+
+ if (dme_send_query_upiu(dev, &query))
+ return -UFS_FAILURE;
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) config_desc, sizeof(struct ufs_config_desc));
+
+ return UFS_SUCCESS;
+}
+
+int dme_send_nop_query(struct ufs_dev *dev)
+{
+ struct upiu_req_build_type req_upiu;
+ struct upiu_basic_hdr resp_upiu;
+ int ret;
+ unsigned try_again;
+
+ ret = UFS_SUCCESS;
+ try_again = DME_NOP_NUM_RETRIES;
+
+ memset(&req_upiu, 0 , sizeof(struct upiu_req_build_type));
+
+ req_upiu.trans_type = UPIU_TYPE_NOP_OUT;
+ req_upiu.flags = 0;
+ req_upiu.query_mgmt_func = 0;
+ req_upiu.cmd_type = UTRD_DEV_MGMT_FUNC;
+ req_upiu.dd = UTRD_NO_DATA_TRANSFER;
+ req_upiu.resp_ptr = &resp_upiu;
+ req_upiu.resp_len = sizeof(struct upiu_basic_hdr);
+ req_upiu.timeout_msecs = DME_NOP_QUERY_TIMEOUT;
+
+ while (try_again)
+ {
+ try_again--;
+
+ ret = utp_enqueue_upiu(dev, &req_upiu);
+
+ if (ret == -UFS_RETRY)
+ {
+ continue;
+ }
+ else if (ret == -UFS_FAILURE)
+ {
+ dprintf(CRITICAL, "sending nop out failed.\n");
+ goto upiu_send_nop_out_err;
+ }
+
+ /* Check response UPIU */
+ if (resp_upiu.trans_type != UPIU_TYPE_NOP_IN)
+ {
+ dprintf(CRITICAL, "Command failed. command = %x. Invalid response.\n", req_upiu.trans_type);
+ ret = -UFS_FAILURE;
+ goto upiu_send_nop_out_err;
+ }
+ else
+ break;
+ }
+
+upiu_send_nop_out_err:
+ return ret;
+}
+
+int utp_build_query_req_upiu(struct upiu_trans_mgmt_query_hdr *req_upiu,
+ struct upiu_req_build_type *upiu_data)
+{
+ req_upiu->opcode = upiu_data->opcode;
+ req_upiu->idn = upiu_data->idn;
+ req_upiu->index = upiu_data->index;
+ req_upiu->selector = upiu_data->selector;
+ req_upiu->resp_len = BE16(upiu_data->resp_data_len);
+
+ switch (upiu_data->opcode)
+ {
+ case UPIU_QUERY_OP_READ_FLAG:
+ case UPIU_QUERY_OP_READ_DESCRIPTOR:
+ req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_READ_REQ;
+ break;
+ case UPIU_QUERY_OP_TOGGLE_FLAG:
+ case UPIU_QUERY_OP_CLEAR_FLAG:
+ case UPIU_QUERY_OP_SET_FLAG:
+ req_upiu->basic_hdr.query_task_mgmt_func = UPIU_QUERY_FUNC_STD_WRITE_REQ;
+ break;
+ default: dprintf(CRITICAL, "UPIU query opcode not supported.\n");
+ return -UFS_FAILURE;
+ }
+
+ return UFS_SUCCESS;
+}
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index b88a47d..1d9b9ad 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -43,6 +43,18 @@
#define DTB_PAD_SIZE 1024
+/*
+ * For DTB V1: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, CDP, rev_1>; (3 * sizeof(uint32_t))
+ * For DTB V2: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, rev_1>; (2 * sizeof(uint32_t))
+ * qcom,board-id = <CDP, subtype_ID>; (2 * sizeof(uint32_t))
+ * The macros below are defined based on these.
+ */
+#define DT_ENTRY_V1_SIZE 0xC
+#define PLAT_ID_SIZE 0x8
+#define BOARD_ID_SIZE 0x8
+
struct dt_entry
{
uint32_t platform_id;
@@ -60,6 +72,26 @@
uint32_t num_entries;
};
+struct plat_id
+{
+ uint32_t platform_id;
+ uint32_t soc_rev;
+};
+
+struct board_id
+{
+ uint32_t variant_id;
+ uint32_t platform_subtype;
+};
+
+struct dt_mem_node_info
+{
+ uint32_t offset;
+ uint32_t mem_info_cnt;
+ uint32_t addr_cell_size;
+ uint32_t size_cell_size;
+};
+
enum dt_err_codes
{
DT_OP_SUCCESS,
@@ -68,7 +100,7 @@
int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size);
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
-int update_device_tree(void *, const char *, void *, unsigned);
-int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t size, uint32_t addr);
+int update_device_tree(void *fdt, const char *, void *, unsigned);
+int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint64_t size, uint64_t addr);
void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags);
#endif
diff --git a/platform/msm_shared/include/dme.h b/platform/msm_shared/include/dme.h
new file mode 100644
index 0000000..c93e23a
--- /dev/null
+++ b/platform/msm_shared/include/dme.h
@@ -0,0 +1,247 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DME_H_
+#define _DME_H_
+
+#include <sys/types.h>
+#include <upiu.h>
+
+/* Bit field of UFSHCI_UICCMDR register */
+#define UICCMDR_DME_GET 0x01
+#define UICCMDR_DME_SET 0x02
+#define UICCMDR_DME_PEER_GET 0x03
+#define UICCMDR_DME_PEER_SET 0x04
+#define UICCMDR_DME_POWERON 0x10
+#define UICCMDR_DME_POWEROFF 0x11
+#define UICCMDR_DME_ENABLE 0x12
+#define UICCMDR_DME_RESET 0x14
+#define UICCMDR_DME_ENDPOINTRESET 0x15
+#define UICCMDR_DME_LINKSTARTUP 0x16
+#define UICCMDR_DME_HIBERNATE_ENTER 0x17
+#define UICCMDR_DME_HIBERNATE_EXIT 0x18
+#define UICCMDR_DME_TEST_MODE 0x1a
+
+/* Retry value for commands. */
+#define DME_NOP_NUM_RETRIES 20
+#define DME_FDEVICEINIT_RETRIES 20
+
+/* Timeout value for commands. */
+#define DME_NOP_QUERY_TIMEOUT 10
+#define DME_LINK_START_TIMEOUT 1
+
+/* UFS descriptor type ident value */
+enum utp_ufs_desc_type
+{
+ UFS_DESC_IDN_DEVICE = 0x00,
+ UFS_DESC_IDN_CONFIGURATION = 0x01,
+ UFS_DESC_IDN_UNIT = 0x02,
+ UFS_DESC_IDN_INTERCONNECT = 0x04,
+ UFS_DESC_IDN_STRING = 0x05,
+ UFS_DESC_IDN_GEOMETRY = 0x07,
+ UFS_DESC_IDN_POWER = 0x08,
+};
+
+// Attributes definitions
+#define UFS_IDX_bBootLunEn 0x00
+#define UFS_IDX_bCurrentPowerMode 0x01
+#define UFS_IDX_bActiveICCLevel 0x03
+#define UFS_IDX_bRefClkFreq 0x0a
+#define UFS_IDX_bConfigDescrLock 0x0b
+
+enum utp_query_req_upiu_func_type
+{
+ UPIU_QUERY_FUNC_STD_READ_REQ = 0x01,
+ UPIU_QUERY_FUNC_STD_WRITE_REQ = 0x81,
+};
+
+/* Flags definitions */
+#define UFS_IDX_fDeviceInit 0x01
+#define UFS_IDX_fPowerOnWPEn 0x03
+
+enum utp_query_response_upiu_type
+{
+ UPIU_QUERY_RESP_SUCCESS = 0x00,
+ UPIU_QUERY_RESP_PARAM_NOT_READABLE = 0xF6,
+ UPIU_QUERY_RESP_PARAM_NOT_WRITABLE = 0xF7,
+ UPIU_QUERY_RESP_PARAM_ALREADY_WRITTEN = 0xF8,
+ UPIU_QUERY_RESP_INVALID_LEN = 0xF9,
+ UPIU_QUERY_RESP_INVALID_VALUE = 0xFA,
+ UPIU_QUERY_RESP_INVALID_SELECTOR = 0xFB,
+ UPIU_QUERY_RESP_INVALID_IDN = 0xFC,
+ UPIU_QUERY_RESP_INVALID_OPCODE = 0xFD,
+ UPIU_QUERY_RESP_GEN_FAILURE = 0xFE,
+};
+
+struct dme_get_req_type
+{
+ uint16_t attribute;
+ uint16_t index;
+ uint32_t *mibval;
+};
+
+#define DEV_DESC_LEN 0x1F
+
+struct utp_query_req_upiu_type
+{
+ enum upiu_query_opcode_type opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ addr_t buf;
+ size_t buf_len;
+};
+
+struct ufs_dev_desc
+{
+ uint8_t desc_len;
+ uint8_t desc_type;
+ uint8_t dev_type;
+ uint8_t dev_class;
+ uint8_t dev_sub_class;
+ uint8_t protocol;
+ uint8_t num_lu;
+ uint8_t num_wlun;
+ uint8_t boot_en;
+ uint8_t desc_access_en;
+ uint8_t init_pwr_mode;
+ uint8_t high_pior_lun;
+ uint8_t sec_removal_type;
+ uint8_t sec_lun;
+ uint8_t resv_0;
+ uint8_t active_icc_level;
+ uint16_t spec_ver;
+ uint16_t manufacture_date;
+ uint8_t manufacture_name;
+ uint8_t product_name;
+ uint8_t serial_num;
+ uint8_t oem_id;
+ uint16_t manufacture_id;
+ uint8_t ud0_base_offset;
+ uint8_t ud_config_p_len;
+ uint8_t dev_rtt_cap;
+}__PACKED;
+
+struct ufs_unit_desc
+{
+ uint8_t desc_len;
+ uint8_t desc_type;
+ uint8_t unit_index;
+ uint8_t lu_enable;
+ uint8_t boot_lun_id;
+ uint8_t lu_wp;
+ uint8_t lu_queue_depth;
+ uint8_t resv;
+ uint8_t mem_type;
+ uint8_t data_reliability;
+ uint8_t logical_blk_size;
+ uint64_t logical_blk_cnt;
+ uint32_t erase_blk_size;
+ uint8_t provisioning_type;
+ uint8_t phy_mem_resource_cnt[8];
+ uint16_t ctx_capabilities;
+ uint8_t large_unit_size_m1;
+}__PACKED;
+
+struct ufs_geometry_desc
+{
+ uint8_t desc_len;
+ uint8_t desc_type;
+ uint8_t media_tech;
+ uint8_t resv_0;
+ uint8_t raw_dev_capacity[8];
+ uint8_t resv_1;
+ uint32_t segment_size;
+ uint8_t alloc_unit_size;
+ uint8_t min_addr_blk_size;
+ uint8_t optimal_read_blk_size;
+ uint8_t optimal_write_blk_size;
+ uint8_t max_inbuf_size;
+ uint8_t maxoutbuf_size;
+ uint8_t rpmb_rdwr_size;
+ uint8_t resv_2;
+ uint8_t data_ordering;
+ uint8_t resv_3[5];
+ uint8_t max_ctx_id_num;
+ uint8_t sys_data_tag_unit_size;
+ uint8_t sys_data_tag_res_size;
+ uint8_t supp_sec_rt_types;
+ uint16_t supp_mem_types;
+}__PACKED;
+
+struct ufs_dev_desc_config_params
+{
+ uint8_t num_lu;
+ uint8_t boot_enable;
+ uint8_t desc_access_en;
+ uint8_t init_pwr_mode;
+ uint8_t high_pior_lun;
+ uint8_t sec_removal_type;
+ uint8_t active_icc_level;
+ uint16_t dev_rtt_cap;
+ uint8_t resv[5];
+}__PACKED;
+
+struct ufs_unit_desc_config_params
+{
+ uint8_t lu_enable;
+ uint8_t boot_lun_id;
+ uint8_t lu_wp;
+ uint8_t mem_type;
+ uint32_t num_alloc_units;
+ uint8_t data_reliability;
+ uint8_t logical_blk_size;
+ uint8_t provisioning_type;
+ uint16_t ctx_capabilities;
+ uint8_t resv[3];
+}__PACKED;
+
+struct ufs_config_desc
+{
+ uint8_t desc_len;
+ uint8_t desc_type;
+ struct ufs_dev_desc_config_params config_params;
+ struct ufs_unit_desc_config_params unit_params[8];
+}__PACKED;
+
+struct ufs_string_desc
+{
+ uint8_t desc_len;
+ uint8_t desc_type;
+ uint8_t serial_num[128];
+}__PACKED;
+
+int dme_send_linkstartup_req(struct ufs_dev *dev);
+int dme_get_req(struct ufs_dev *dev, struct dme_get_req_type *req);
+int utp_build_query_req_upiu(struct upiu_trans_mgmt_query_hdr *req_upiu,
+ struct upiu_req_build_type *upiu_data);
+int dme_send_nop_query(struct ufs_dev *dev);
+int dme_set_fdeviceinit(struct ufs_dev *dev);
+int dme_read_unit_desc(struct ufs_dev *dev, uint8_t index, uint64_t *capacity);
+
+#endif
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 12181b3..597992a 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -37,6 +37,8 @@
#define MMC_SLOT 0
#endif
+#define BOARD_KERNEL_PAGESIZE 2048
+
extern unsigned int mmc_boot_mci_base;
#define MMC_BOOT_MCI_REG(offset) ((mmc_boot_mci_base) + offset)
@@ -512,6 +514,7 @@
unsigned int status;
#define MMC_BOOT_STATUS_INACTIVE 0
#define MMC_BOOT_STATUS_ACTIVE 1
+ uint32_t block_size;
unsigned int rd_timeout_ns;
unsigned int wr_timeout_ns;
unsigned int rd_block_len;
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index feae9f3..b6a2ca6 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -266,6 +266,7 @@
struct mmc_card {
uint32_t rca; /* Relative addres of the card*/
uint32_t ocr; /* Operating range of the card*/
+ uint32_t block_size; /* Block size for the card */
uint64_t capacity; /* card capacity */
uint32_t type; /* Type of the card */
uint32_t status; /* Card status */
diff --git a/platform/msm_shared/include/mmc_wrapper.h b/platform/msm_shared/include/mmc_wrapper.h
index 5b12990..a05b42b 100644
--- a/platform/msm_shared/include/mmc_wrapper.h
+++ b/platform/msm_shared/include/mmc_wrapper.h
@@ -31,6 +31,7 @@
#include <mmc_sdhci.h>
+#define BOARD_KERNEL_PAGESIZE 2048
/* Wrapper APIs */
struct mmc_device *get_mmc_device();
@@ -41,4 +42,7 @@
uint32_t mmc_erase_card(uint64_t, uint64_t);
uint64_t mmc_get_device_capacity(void);
uint32_t mmc_erase_card(uint64_t addr, uint64_t len);
+uint32_t mmc_get_device_blocksize();
+uint32_t mmc_page_size();
+void mmc_device_sleep();
#endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 1cf0e64..b7b57ad 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -160,6 +160,7 @@
char lane_swap;
uint8_t dual_dsi;
uint8_t broadcast;
+ uint8_t mode_gpio_state;
};
struct edp_panel_info {
diff --git a/platform/msm_shared/include/ucs.h b/platform/msm_shared/include/ucs.h
new file mode 100644
index 0000000..9f02a03
--- /dev/null
+++ b/platform/msm_shared/include/ucs.h
@@ -0,0 +1,129 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UCS_H
+#define _UCS_H
+
+#define SCSI_MAX_DATA_TRANS_BLK_LEN 0x01
+#define UFS_DEFAULT_SECTORE_SIZE 4096
+
+#define SCSI_STATUS_GOOD 0x00
+#define SCSI_STATUS_CHK_COND 0x02
+#define SCSI_STATUS_BUSY 0x08
+#define SCSI_STATUS_TASK_SET_FULL 0x08
+
+#define SCSI_SENSE_BUF_LEN 0x20
+#define SCSI_INQUIRY_LEN 36
+#define SCSI_CDB_PARAM_LEN 16
+
+/* FLAGS for indication of read or write */
+enum scsi_upiu_flags
+{
+ UPIU_FLAGS_READ = 0x40,
+ UPIU_FLAGS_WRITE = 0x20,
+ UPIU_FLAGS_ATTR_SIMPLE = 0x00,
+ UPIU_FLAGS_ATTR_ORDERED = 0x01,
+ UPIU_FLAGS_ATTR_HOQ = 0x02,
+};
+
+#define SCSI_READ_WRITE_10_CDB1(rd_protect, dpo, fua, fua_nv) ((rd_protect) << 5 | (dpo) << 4 | (fua) << 3 | (fua_nv) << 1)
+
+/* SCSI commands */
+enum utp_scsi_cmd_type
+{
+ SCSI_CMD_TEST_UNIT_RDY = 0x00,
+ SCSI_CMD_SENSE_REQ = 0x03,
+ SCSI_CMD_INQUIRY = 0x12,
+ SCSI_CMD_READ10 = 0x28,
+ SCSI_CMD_READ_CAP10 = 0x25, // Read Capacity
+ SCSI_CMD_SYNC_CACHE10 = 0x35,
+ SCSI_CMD_UNMAP = 0x42,
+ SCSI_CMD_WRITE10 = 0x2A,
+ SCSI_CMD_SECPROT_IN = 0xA2, // Security Protocal in
+ SCSI_CMD_SECPROT_OUT = 0xB5, // Security Protocal out
+ SCSI_CMD_REPORT_LUNS = 0xA0,
+};
+
+struct scsi_req_build_type
+{
+ addr_t cdb;
+ uint8_t lun;
+ addr_t data_buffer_addr;
+ uint32_t data_len;
+ enum scsi_upiu_flags flags;
+ enum upiu_dd_type dd;
+};
+
+struct scsi_rdwr_req
+{
+ uint8_t lun;
+ uint32_t start_lba;
+ uint32_t num_blocks;
+ uint32_t data_buffer_base;
+};
+
+struct scsi_rdwr_cdb
+{
+ uint8_t opcode;
+ uint8_t cdb1;
+ uint32_t lba;
+ uint8_t grp_num;
+ uint16_t trans_len;
+ uint8_t control;
+ uint8_t resv[6];
+}__PACKED;
+
+struct scsi_sense_cdb
+{
+ uint8_t opcode;
+ uint8_t desc;
+ uint16_t resv_0;
+ uint8_t alloc_len;
+ uint8_t control;
+ uint8_t resv_1[10];
+}__PACKED;
+
+struct scsi_failure_sense_data
+{
+ uint8_t valid_resp_code;
+ uint8_t obsolete;
+ uint16_t file_mark_eom_ili_resv_sense_key;
+ uint8_t sense_info[4];
+ uint8_t additional_sense_len;
+ uint32_t csi;
+ uint8_t asc;
+ uint8_t ascq;
+ uint8_t fruc;
+ uint8_t sense_key_specific;
+}__PACKED;
+
+int ucs_scsi_send_inquiry(struct ufs_dev *dev);
+int ucs_do_scsi_read(struct ufs_dev *dev, struct scsi_rdwr_req *req);
+int ucs_do_scsi_write(struct ufs_dev *dev, struct scsi_rdwr_req *req);
+
+#endif
diff --git a/platform/msm_shared/include/ufs.h b/platform/msm_shared/include/ufs.h
new file mode 100644
index 0000000..e5578bd
--- /dev/null
+++ b/platform/msm_shared/include/ufs.h
@@ -0,0 +1,96 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UFS_H_
+#define _UFS_H_
+
+#include <sys/types.h>
+#include <kernel/mutex.h>
+#include <kernel/event.h>
+#include <list.h>
+
+enum ufs_err
+{
+ UFS_SUCCESS,
+ UFS_FAILURE,
+ UFS_RETRY,
+};
+
+struct ufs_req_node
+{
+ uint32_t task_id;
+ uint32_t door_bell_bit;
+ event_t *event;
+ struct list_node list_node;
+};
+
+
+struct ufs_utp_req_meta_data
+{
+ mutex_t bitmap_mutex;
+ struct ufs_req_node list_head;
+ uint32_t bitmap;
+ uint32_t task_id;
+ uint64_t list_base_addr;
+};
+
+struct ufs_uic_meta_data
+{
+ mutex_t uic_mutex;
+ event_t uic_event;
+};
+
+struct ufs_dev
+{
+ uint8_t instance;
+ uint32_t base;
+ uint8_t num_lus;
+ uint32_t serial_num;
+ uint32_t block_size;
+
+ /* UTRD maintainance data structures.*/
+ struct ufs_utp_req_meta_data utrd_data;
+ struct ufs_utp_req_meta_data utmrd_data;
+
+ /* UIC maintainance data structures.*/
+ struct ufs_uic_meta_data uic_data;
+};
+
+/* Define all the basic WLUN type */
+#define UFS_WLUN_REPORT 0x81
+#define UFS_UFS_DEVICE 0xD0
+#define UFS_WLUN_BOOT 0xB0
+#define UFS_WLUN_RPMB 0xC4
+
+int ufs_init(struct ufs_dev *dev);
+int ufs_read(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks);
+int ufs_write(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks);
+uint64_t ufs_get_dev_capacity(struct ufs_dev* dev);
+uint32_t ufs_get_serial_num(struct ufs_dev* dev);
+
+#endif
diff --git a/platform/msm_shared/include/ufs_hci.h b/platform/msm_shared/include/ufs_hci.h
new file mode 100644
index 0000000..b1b76f6
--- /dev/null
+++ b/platform/msm_shared/include/ufs_hci.h
@@ -0,0 +1,53 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UFS_HCI_H
+#define _UFS_HCI_H_
+
+#include <kernel/mutex.h>
+#include <kernel/event.h>
+#include <list.h>
+#include <ufs.h>
+
+#define UFS_HCE_TIMEOUT 100000
+
+struct ufs_req_irq_type
+{
+ struct list_node *list;
+ uint32_t irq_handled;
+ uint32_t door_bell_reg;
+};
+
+int ufs_reg_target_val_timeout_loop(uint32_t reg_addr, uint32_t target_val, uint32_t timeout);
+enum handler_return ufs_irq_handler(void* data);
+void ufs_irq_enable(struct ufs_dev *dev, uint32_t irq);
+int ufs_enable_hci(struct ufs_dev *dev);
+uint64_t ufs_alloc_trans_req_list();
+uint64_t ufs_alloc_task_mgmt_req_list();
+
+#endif
diff --git a/platform/msm_shared/include/ufs_hw.h b/platform/msm_shared/include/ufs_hw.h
new file mode 100644
index 0000000..cf4da12
--- /dev/null
+++ b/platform/msm_shared/include/ufs_hw.h
@@ -0,0 +1,107 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UFS_HW_H_
+#define _UFS_HW_H_
+
+#include <bits.h>
+
+#define UFS_CAP(_base) (_base + 0x00000000)
+#define UFS_VER(_base) (_base + 0x00000008)
+#define UFS_HCDDID(_base) (_base + 0x00000010)
+#define UFS_HCPMID(_base) (_base + 0x00000014)
+#define UFS_IS(_base) (_base + 0x00000020)
+#define UFS_IE(_base) (_base + 0x00000024)
+#define UFS_HCS(_base) (_base + 0x00000030)
+#define UFS_HCE(_base) (_base + 0x00000034)
+#define UFS_UECPA(_base) (_base + 0x00000038)
+#define UFS_UECDL(_base) (_base + 0x0000003C)
+#define UFS_UTRIACR(_base) (_base + 0x0000004C)
+#define UFS_UTRLBA(_base) (_base + 0x00000050)
+#define UFS_UTRLBAU(_base) (_base + 0x00000054)
+#define UFS_UTRLDBR(_base) (_base + 0x00000058)
+#define UFS_UTRLCLR(_base) (_base + 0x0000005C)
+#define UFS_UTRLRSR(_base) (_base + 0x00000060)
+#define UFS_UTMRLBA(_base) (_base + 0x00000070)
+#define UFS_UTMRLBAU(_base) (_base + 0x00000074)
+#define UFS_UTMRLRSR(_base) (_base + 0x00000080)
+#define UFS_UICCMD(_base) (_base + 0x00000090)
+#define UFS_UICCMDARG1(_base) (_base + 0x00000094)
+#define UFS_UICCMDARG2(_base) (_base + 0x00000098)
+#define UFS_UICCMDARG3(_base) (_base + 0x0000009C)
+#define UFS_SYS1CLK_1US(_base) (_base + 0x000000C0)
+#define UFS_TX_SYMBOL_CLK_NS_US(_base) (_base + 0x000000C4)
+#define UFS_REG_PA_LINK_STARTUP_TIMER(_base) (_base + 0x000000D8)
+#define UFS_CFG1(_base) (_base + 0x000000DC)
+
+#define UFS_CFG1_PHY_SOFT_RESET BIT(0)
+
+/* Bit field of UFSHCI_HCS register */
+#define UFS_HCS_DP BIT(0)
+#define UFS_HCS_UTRLRDY BIT(1)
+#define UFS_HCS_UTMRLRDY BIT(2)
+#define UFS_HCS_UCRDY BIT(3)
+
+/* Bit field of UFSHCI_IE register */
+#define UFS_IE_UTRCE BIT(0)
+#define UFS_IE_UDEPRIU BIT(1)
+#define UFS_IE_UEE BIT(2)
+#define UFS_IE_UTMSE BIT(3)
+#define UFS_IE_UPMSE BIT(4)
+#define UFS_IE_UHXSE BIT(5)
+#define UFS_IE_UHESE BIT(6)
+#define UFS_IE_ULLSE BIT(7)
+#define UFS_IE_ULSSE BIT(8)
+#define UFS_IE_UTMRCE BIT(9)
+#define UFS_IE_UCCE BIT(10)
+#define UFS_IE_DFEE BIT(11)
+#define UFS_IE_UTPEE BIT(12)
+#define UFS_IE_HCFEE BIT(16)
+#define UFS_IE_SBFEE BIT(17)
+
+/* Bit field of UFSHCI_IS register */
+#define UFS_IS_UTRCS BIT(0)
+#define UFS_IS_UDEPRI BIT(1)
+#define UFS_IS_UE BIT(2)
+#define UFS_IS_UTMS BIT(3)
+#define UFS_IS_UPMS BIT(4)
+#define UFS_IS_UHXS BIT(5)
+#define UFS_IS_UHES BIT(6)
+#define UFS_IS_ULLS BIT(7)
+#define UFS_IS_ULSS BIT(8)
+#define UFS_IS_UTMRCS BIT(9)
+#define UFS_IS_UCCS BIT(10)
+#define UFS_IS_DFES BIT(11)
+#define UFS_IS_UTPES BIT(12)
+#define UFS_IS_HCFES BIT(16)
+#define UFS_IS_SBFES BIT(17)
+
+/* Bit field for UFS_HCE register. */
+#define UFS_HCE_ENABLE BIT(0)
+
+#endif
diff --git a/platform/msm_shared/include/uic.h b/platform/msm_shared/include/uic.h
new file mode 100644
index 0000000..bc85241
--- /dev/null
+++ b/platform/msm_shared/include/uic.h
@@ -0,0 +1,81 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _UIC_H_
+#define _UIC_H_
+
+#include <sys/types.h>
+
+#define HCI_UIC_TIMEOUT 100000
+#define HCI_ENABLE_TIMEOUT 100000
+
+enum uic_error_codes
+{
+ UIC_ERR_UNKNOWN,
+ UIC_ERR_TIMEOUT,
+};
+
+enum uic_gen_err_code
+{
+ UICCMD_SUCCESS,
+ UICCMD_FAILURE,
+};
+
+enum uic_num_cmd_args
+{
+ UICCMD_NO_ARGS = 0,
+ UICCMD_ONE_ARGS = 1,
+ UICCMD_TWO_ARGS = 2,
+ UICCMD_THREE_ARGS = 4,
+};
+
+struct uic_cmd
+{
+ uint32_t uiccmd;
+ uint32_t num_args;
+ uint32_t uiccmdarg1;
+ uint32_t uiccmdarg2;
+ uint32_t uiccmdarg3;
+ uint32_t gen_err_code;
+ uint32_t timeout_msecs;
+};
+
+/* UFS init settings. */
+#define UFS_SYS1CLK_1US_VAL 100
+#define UFS_TX_SYMBOL_CLK_1US_VAL 1
+#define UFS_CLK_NS_REG_VAL 10
+#define UFS_PA_LINK_STARTUP_TIMER_VAL 20000000
+#define UFS_LINK_STARTUP_RETRY 10
+
+#define SHFT_CLK_NS_REG (10)
+
+int uic_init(struct ufs_dev *dev);
+int uic_send_cmd(struct ufs_dev *dev, struct uic_cmd *cmd);
+int uic_reset(struct ufs_dev *dev);
+
+
+#endif
diff --git a/platform/msm_shared/include/upiu.h b/platform/msm_shared/include/upiu.h
new file mode 100644
index 0000000..1c9968d
--- /dev/null
+++ b/platform/msm_shared/include/upiu.h
@@ -0,0 +1,164 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UPIU_H
+#define _UPIU_H
+
+struct upiu_basic_hdr
+{
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ uint8_t task_tag;
+ uint8_t cmd_set_type;
+ uint8_t query_task_mgmt_func;
+ uint8_t response;
+ uint8_t status;
+ uint8_t total_ehs_len;
+ uint8_t device_info;
+ uint16_t data_seg_len;
+} __PACKED;
+
+struct upiu_trans_mgmt_query_hdr
+{
+ struct upiu_basic_hdr basic_hdr;
+ uint8_t opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ uint8_t resv_0[2];
+ uint16_t resp_len;
+ uint8_t resv_1[3];
+ uint8_t flag_value;
+ uint8_t resv_2[4];
+}__PACKED;
+
+struct upiu_cmd_hdr
+{
+ struct upiu_basic_hdr basic_hdr;
+ uint32_t data_expected_len; // Requested length
+ uint8_t param[16]; // Payload, operation specefic field
+}__PACKED;
+
+struct upiu_cmd_resp_hdr
+{
+ struct upiu_basic_hdr basic_hdr;
+ uint32_t residual_trans_count;
+ uint8_t resv_0[16];
+}__PACKED;
+
+struct upiu_gen_hdr
+{
+ struct upiu_basic_hdr basic_hdr;
+ uint8_t trans_specific_fields[20];
+}__PACKED;
+
+/* UPIU transaction codes. */
+enum upiu_trans_type
+{
+ UPIU_TYPE_NOP_OUT = 0x00,
+ UPIU_TYPE_COMMAND = 0x01,
+ UPIU_TYPE_TASK_MGMT = 0x04,
+ UPIU_TYPE_QUERY_REQ = 0x16,
+ UPIU_TYPE_NOP_IN = 0x20,
+ UPIU_TYPE_RESPONSE = 0x21,
+ UPIU_TYPE_TASK_MAN_RESP = 0x24,
+ UPIU_TYPE_QUERY_RESP = 0x36,
+ UPIU_TYPE_REJECT = 0x3f,
+};
+
+/* UPIU respones */
+enum upiu_response
+{
+ UPIU_RESPONSE_TARGET_SUCCESS = 0x00,
+ UPIU_RESPONSE_TARGET_FAILURE = 0x01,
+};
+
+enum upiu_cmd_set_type
+{
+ UPIU_SCSI_CMD_SET = 0,
+ UPIU_UFS_SPECIFIC_CMD_SET = 1,
+};
+
+enum upiu_query_opcode_type
+{
+ UPIU_QUERY_OP_NOP = 0x0,
+ UPIU_QUERY_OP_READ_DESCRIPTOR = 0x1,
+ UPIU_QUERY_OP_WRITE_DESCRIPTOR = 0x2,
+ UPIU_QUERY_OP_READ_ATTRIBUTE = 0x3,
+ UPIU_QUERY_OP_WRITE_ATTRIBUTE = 0x4,
+ UPIU_QUERY_OP_READ_FLAG = 0x5,
+ UPIU_QUERY_OP_SET_FLAG = 0x6,
+ UPIU_QUERY_OP_CLEAR_FLAG = 0x7,
+ UPIU_QUERY_OP_TOGGLE_FLAG = 0x8,
+};
+
+enum upiu_cmd_type
+{
+ UTRD_SCSCI_CMD = 0,
+ UTRD_NATIVE_UFS_CMD = 1,
+ UTRD_DEV_MGMT_FUNC = 2,
+};
+
+enum upiu_dd_type
+{
+ UTRD_NO_DATA_TRANSFER = 0,
+ UTRD_SYSTEM_TO_TARGET = 1,
+ UTRD_TARGET_TO_SYSTEM = 2,
+};
+
+struct upiu_req_build_type
+{
+ enum upiu_trans_type trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ enum upiu_cmd_set_type cmd_set_type;
+ uint8_t query_mgmt_func;
+ uint8_t ehs_len;
+ uint16_t data_seg_len;
+ addr_t data_buffer_addr;
+ uint32_t data_buffer_len;
+ addr_t cdb;
+ uint64_t expected_data_len;
+ enum upiu_query_opcode_type opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ struct upiu_basic_hdr *resp_ptr;
+ uint64_t resp_len;
+ uint16_t resp_data_len;
+ addr_t resp_data_ptr;
+
+ /* UTRD properties. */
+ enum upiu_cmd_type cmd_type;
+ enum upiu_dd_type dd;
+ uint64_t timeout_msecs;
+};
+
+
+#endif
diff --git a/platform/msm_shared/include/utp.h b/platform/msm_shared/include/utp.h
new file mode 100644
index 0000000..4d70f16
--- /dev/null
+++ b/platform/msm_shared/include/utp.h
@@ -0,0 +1,149 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UTP_H_
+#define _UTP_H_
+
+#include <ufs_hci.h>
+#include <upiu.h>
+#include <ucs.h>
+#include <dme.h>
+
+/* UPIU general header length without the extra segments. */
+#define UPIU_HDR_LEN 0x20
+
+#define UTP_MAX_PRD_DATA_BYTE_CNT 0x40000
+#define UTP_MAX_PRD_DATA_BYTE_CNT_BYTE_SHIFT 18
+#define UTP_MAX_PRD_TABLE_ENTRIES 1024
+
+#define UTP_CMD_DESC_BASE_ALIGNMENT_SIZE 128
+#define UTP_REQ_BUILD_CMD_DD_IRQ_FIELD(cmd, dd, irq) ((cmd << 4) | (dd << 1) | irq)
+
+#define UTP_MUTEX_ACQUIRE_TIMEOUT 0x100000
+
+#define UTP_GENERIC_CMD_TIMEOUT 10000
+
+struct utp_prdt_entry
+{
+ uint32_t data_base_addr;
+ uint32_t data_upper_addr;
+ uint8_t resv_0[4];
+ uint32_t data_byte_cnt;
+}__PACKED;
+
+struct utp_trans_req_desc
+{
+ uint8_t resv_0[3];
+ uint8_t cmd_type_dd_irq;
+ uint8_t resv_1[4];
+ uint8_t overall_cmd_status;
+ uint8_t resv_2[7];
+ uint8_t cmd_desc_base_addr[4];
+ uint8_t cmd_desc_base_addr_upper[4];
+ uint16_t resp_upiu_len;
+ uint16_t resp_upiu_offset;
+ uint16_t prdt_len;
+ uint16_t prdt_offset;
+}__PACKED;
+
+enum utp_utrd_irq_type
+{
+ UTRD_REGULAR_CMD = 0,
+ UTRD_IRQ_CMD = 1,
+};
+
+enum utp_utrd_overall_status_type
+{
+ UTRD_OCS_SUCCESS = 0x0,
+ UTRD_OCS_INVALID_COM_TABLE_ATTR = 0x1,
+ UTRD_OCS_INVALID_PRDT_ATTR = 0x2,
+ UTRD_OCS_MISMATCH_DATA_BUFFER_SIZE = 0x3,
+ UTRD_OCS_MISMATCH_RESPONSE_UPIU_SIZE = 0x4,
+ UTRD_OCS_COMMUNICATION_FAILURE = 0x5,
+ UTRD_OCS_ABORTED = 0x6,
+ UTRD_OCS_INVALID_OCS_VALUE = 0xf,
+};
+
+struct utp_utrd_req_build_type
+{
+ struct upiu_basic_hdr *req_upiu;
+ uint32_t req_upiu_len;
+ uint32_t resp_upiu_len;
+ enum upiu_cmd_type cmd_type;
+ enum upiu_dd_type dd;
+ enum utp_utrd_irq_type irq;
+ enum utp_utrd_overall_status_type ocs;
+ uint32_t prdt_offset;
+ uint32_t prdt_len;
+ uint32_t timeout;
+};
+
+struct utp_task_mgmt_req_desc
+{
+ uint8_t resv_0[3];
+ uint8_t irq;
+ uint8_t resv_1[4];
+ uint8_t overall_cmd_status;
+ uint8_t resv_2[7];
+}__PACKED;
+
+enum utp_utmrd_irq_type
+{
+ NO_IRQ = 0,
+ ENABLE_IRQ = 1,
+};
+
+enum utp_utmrd_overall_status_type
+{
+ UTMRD_OCS_SUCCESS = 0x0,
+ UTMRD_OCS_TASK_MGMT_FUNC_ATTR = 0x1,
+ UTMRD_OCS_MISMATCH_TASK_MGMT_REQ_SIZE = 0x2,
+ UTMRD_OCS_MISMATCH_TASK_MGMT_RES_SIZE = 0x3,
+ UTMRD_OCS_PEER_COMM_FAILURE = 0x4,
+ UTMRD_OCS_ABORTED = 0x5,
+ UTMRD_OCS_FATAL_ERR = 0x6,
+};
+
+struct utrd_cmd_desc
+{
+ struct upiu_gen_hdr *req_upiu;
+ uint32_t resp_upiu_len;
+ uint32_t num_prdt;
+};
+
+struct utp_bitmap_access_type
+{
+ uint32_t *bitmap;
+ uint32_t door_bell_bit;
+ mutex_t *mutx;
+};
+
+int utp_enqueue_upiu(struct ufs_dev *dev, struct upiu_req_build_type *upiu_data);
+void utp_process_req_completion(struct ufs_req_irq_type *irq);
+
+#endif
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 5616956..72f2f94 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -64,220 +64,8 @@
return dividend / divisor;
}
-static uint32_t dsi_pll_enable_seq_m(void)
-{
- uint32_t i = 0;
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- if (i != 0)
- writel(0x34, MIPI_DSI_BASE + 0x00270); /* CAL CFG1*/
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- }
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_d(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_f1(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_c(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_e(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-
-
-static uint32_t dsi_pll_enable_seq_8974(void)
-{
- uint32_t rc = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
-
- while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- }
- return rc;
-}
-
-static uint32_t dsi_pll_enable_seq(void)
-{
- uint32_t platformid = board_platform_id();
-
- /* Only one enable seq for 8974 target */
- if (platformid == MSM8974) {
- dsi_pll_enable_seq_8974();
- }
-
- /* 6 enable seq for 8226 target */
- else if (platformid == MSM8826 ||
- platformid == MSM8626 ||
- platformid == MSM8226 ||
- platformid == MSM8926 ||
- platformid == MSM8126 ||
- platformid == MSM8326 ||
- platformid == APQ8026) {
- if (dsi_pll_enable_seq_m()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_f1()) {
- } else if (dsi_pll_enable_seq_c()) {
- } else if (dsi_pll_enable_seq_e()) {
- } else {
- dprintf(CRITICAL, "Not able to enable the pll\n");
- }
- } else {
- dprintf(CRITICAL, "Target not supported in auto PLL\n");
- }
-
-}
-
-int32_t mdss_dsi_auto_pll_config(struct mdss_dsi_pll_config *pd)
+int32_t mdss_dsi_auto_pll_config(uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
{
uint32_t rem, divider;
uint32_t refclk_cfg = 0, frac_n_mode = 0, ref_doubler_en_b = 0;
@@ -299,25 +87,25 @@
return rc;
}
- mdss_dsi_phy_sw_reset(MIPI_DSI_BASE);
+ mdss_dsi_phy_sw_reset(ctl_base);
/* Loop filter resistance value */
- writel(lpfr_lut[i].resistance, MIPI_DSI_BASE + 0x022c);
+ writel(lpfr_lut[i].resistance, ctl_base + 0x022c);
/* Loop filter capacitance values : c1 and c2 */
- writel(0x70, MIPI_DSI_BASE + 0x0230);
- writel(0x15, MIPI_DSI_BASE + 0x0234);
+ writel(0x70, ctl_base + 0x0230);
+ writel(0x15, ctl_base + 0x0234);
- writel(0x02, MIPI_DSI_BASE + 0x0208); /* ChgPump */
+ writel(0x02, ctl_base + 0x0208); /* ChgPump */
/* postDiv1 - calculated in pll config*/
- writel(pd->posdiv1, MIPI_DSI_BASE + 0x0204);
+ writel(pd->posdiv1, ctl_base + 0x0204);
/* postDiv2 - fixed devision 4 */
- writel(0x03, MIPI_DSI_BASE + 0x0224);
+ writel(0x03, ctl_base + 0x0224);
/* postDiv3 - calculated in pll config */
- writel(pd->posdiv3, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
+ writel(pd->posdiv3, ctl_base + 0x0228); /* postDiv3 */
- writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
- writel(0x66, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
- writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+ writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
+ writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
+ writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
if (rem) {
@@ -361,27 +149,25 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(sdm_cfg1 , MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
- writel(sdm_cfg2 , MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
- writel(sdm_cfg3 , MIPI_DSI_BASE + 0x0244); /* SDM CFG3 */
- writel(0x00, MIPI_DSI_BASE + 0x0248); /* SDM CFG4 */
+ writel(sdm_cfg1 , ctl_base + 0x023c); /* SDM CFG1 */
+ writel(sdm_cfg2 , ctl_base + 0x0240); /* SDM CFG2 */
+ writel(sdm_cfg3 , ctl_base + 0x0244); /* SDM CFG3 */
+ writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
udelay(10);
- writel(refclk_cfg, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
- writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
- writel(0x71, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
- writel(pd->directpath, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
- writel(sdm_cfg0, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
+ writel(refclk_cfg, ctl_base + 0x0200); /* REFCLK CFG */
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
+ writel(pd->directpath, ctl_base + 0x0210); /* VREG CFG */
+ writel(sdm_cfg0, ctl_base + 0x0238); /* SDM CFG0 */
- writel(0x0a, MIPI_DSI_BASE + 0x026c); /* CAL CFG0 */
- writel(0x30, MIPI_DSI_BASE + 0x0284); /* CAL CFG6 */
- writel(0x00, MIPI_DSI_BASE + 0x0288); /* CAL CFG7 */
- writel(0x60, MIPI_DSI_BASE + 0x028c); /* CAL CFG8 */
- writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
- writel(cal_cfg10, MIPI_DSI_BASE + 0x0294); /* CAL CFG10 */
- writel(cal_cfg11, MIPI_DSI_BASE + 0x0298); /* CAL CFG11 */
- writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
-
- dsi_pll_enable_seq();
+ writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
+ writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
+ writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
+ writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
+ writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
+ writel(cal_cfg10, ctl_base + 0x0294); /* CAL CFG10 */
+ writel(cal_cfg11, ctl_base + 0x0298); /* CAL CFG11 */
+ writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index e3a4527..90e541a 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -213,154 +213,6 @@
udelay(1);
}
-int mdss_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 424 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x05, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0a, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0xab, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x0a, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x5f, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xa8, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
-int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 500 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x0b, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0c, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0x55, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x05, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x01, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xf4, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd)
{
/* DSI0 and DSI1 have a common regulator */
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 7783f10..75f937f 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -85,7 +85,7 @@
static unsigned int
mmc_boot_bam_setup_desc(unsigned int *data_ptr,
unsigned int data_len, unsigned char direction);
-
+uint32_t mmc_page_size();
#endif
@@ -159,6 +159,11 @@
24);
}
+uint32_t mmc_page_size()
+{
+ return BOARD_KERNEL_PAGESIZE;
+}
+
void mmc_mclk_reg_wr_delay()
{
if (mmc_host.mmc_cont_version)
@@ -2163,6 +2168,9 @@
Initialization not completed\n", mmc_return);
return MMC_BOOT_E_CARD_BUSY;
}
+
+ card->block_size = BLOCK_SIZE;
+
return MMC_BOOT_E_SUCCESS;
}
@@ -3408,6 +3416,12 @@
return mmc_card.capacity;
}
+/* Return the block size of the mmc device */
+uint32_t mmc_get_device_blocksize()
+{
+ return mmc_card.block_size;
+}
+
void mmc_put_card_to_sleep(void)
{
uint32_t mmc_ret;
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 5487d94..de3db2b 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -1454,6 +1454,8 @@
if (MMC_CARD_STATUS(status) != MMC_TRAN_STATE)
mmc_return = 1;
+ card->block_size = MMC_BLK_SZ;
+
return mmc_return;
}
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 01ef7e4..46515d3 100644
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -28,12 +28,44 @@
#include <stdlib.h>
#include <stdint.h>
-#include <mmc_sdhci.h>
#include <mmc_wrapper.h>
+#include <mmc_sdhci.h>
#include <sdhci.h>
+#include <ufs.h>
#include <target.h>
/*
+ * Weak function for UFS.
+ * These are needed to avoid link errors for platforms which
+ * do not support UFS. Its better to keep this inside the
+ * mmc wrapper.
+ */
+__WEAK int ufs_write(struct ufs_dev *dev, uint64_t data_addr, addr_t in, uint32_t len)
+{
+ return 0;
+}
+
+__WEAK int ufs_read(struct ufs_dev *dev, uint64_t data_addr, addr_t in, uint32_t len)
+{
+ return 0;
+}
+
+__WEAK uint32_t ufs_get_page_size(struct ufs_dev *dev)
+{
+ return 0;
+}
+
+__WEAK uint32_t ufs_get_serial_num(struct ufs_dev *dev)
+{
+ return 0;
+}
+
+__WEAK uint64_t ufs_get_dev_capacity(struct ufs_dev *dev)
+{
+ return 0;
+}
+
+/*
* Function: get mmc card
* Arg : None
* Return : Pointer to mmc card structure
@@ -41,11 +73,11 @@
*/
static struct mmc_card *get_mmc_card()
{
- struct mmc_device *dev;
+ void *dev;
struct mmc_card *card;
dev = target_mmc_device();
- card = &dev->card;
+ card = &((struct mmc_device*)dev)->card;
return card;
}
@@ -59,39 +91,58 @@
uint32_t mmc_write(uint64_t data_addr, uint32_t data_len, void *in)
{
uint32_t val = 0;
+ int ret = 0;
+ uint32_t block_size = 0;
uint32_t write_size = SDHCI_ADMA_MAX_TRANS_SZ;
uint8_t *sptr = (uint8_t *)in;
- struct mmc_device *dev;
+ void *dev;
dev = target_mmc_device();
- ASSERT(!(data_addr % MMC_BLK_SZ));
+ block_size = mmc_get_device_blocksize();
- if (data_len % MMC_BLK_SZ)
- data_len = ROUNDUP(data_len, MMC_BLK_SZ);
+ ASSERT(!(data_addr % block_size));
- /* TODO: This function is aware of max data that can be
- * tranferred using sdhci adma mode, need to have a cleaner
- * implementation to keep this function independent of sdhci
- * limitations
- */
- while (data_len > write_size) {
- val = mmc_sdhci_write(dev, (void *)sptr, (data_addr / MMC_BLK_SZ), (write_size / MMC_BLK_SZ));
- if (val)
- {
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / MMC_BLK_SZ));
- return val;
+ if (data_len % block_size)
+ data_len = ROUNDUP(data_len, block_size);
+
+ if (target_boot_device_emmc())
+ {
+ /* TODO: This function is aware of max data that can be
+ * tranferred using sdhci adma mode, need to have a cleaner
+ * implementation to keep this function independent of sdhci
+ * limitations
+ */
+ while (data_len > write_size) {
+ val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (write_size / block_size));
+ if (val)
+ {
+ dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
+ return val;
+ }
+ sptr += write_size;
+ data_addr += write_size;
+ data_len -= write_size;
}
- sptr += write_size;
- data_addr += write_size;
- data_len -= write_size;
+
+ if (data_len)
+ val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
+
+ if (val)
+ dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
}
+ else
+ {
+ arch_clean_invalidate_cache_range((addr_t)in, data_len);
- if (data_len)
- val = mmc_sdhci_write(dev, (void *)sptr, (data_addr / MMC_BLK_SZ), (data_len / MMC_BLK_SZ));
+ ret = ufs_write((struct ufs_dev *)dev, data_addr, (addr_t)in, (data_len / block_size));
- if (val)
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / MMC_BLK_SZ));
+ if (ret)
+ {
+ dprintf(CRITICAL, "Error: UFS write failed writing to block: %llu\n", data_addr);
+ val = 1;
+ }
+ }
return val;
}
@@ -105,38 +156,54 @@
uint32_t mmc_read(uint64_t data_addr, uint32_t *out, uint32_t data_len)
{
uint32_t ret = 0;
+ uint32_t block_size;
uint32_t read_size = SDHCI_ADMA_MAX_TRANS_SZ;
- struct mmc_device *dev;
+ void *dev;
uint8_t *sptr = (uint8_t *)out;
- ASSERT(!(data_addr % MMC_BLK_SZ));
- ASSERT(!(data_len % MMC_BLK_SZ));
-
dev = target_mmc_device();
+ block_size = mmc_get_device_blocksize();
- /* TODO: This function is aware of max data that can be
- * tranferred using sdhci adma mode, need to have a cleaner
- * implementation to keep this function independent of sdhci
- * limitations
- */
- while (data_len > read_size) {
- ret = mmc_sdhci_read(dev, (void *)sptr, (data_addr / MMC_BLK_SZ), (read_size / MMC_BLK_SZ));
+ ASSERT(!(data_addr % block_size));
+ ASSERT(!(data_len % block_size));
+
+
+ if (target_boot_device_emmc())
+ {
+ /* TODO: This function is aware of max data that can be
+ * tranferred using sdhci adma mode, need to have a cleaner
+ * implementation to keep this function independent of sdhci
+ * limitations
+ */
+ while (data_len > read_size) {
+ ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (read_size / block_size));
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ return ret;
+ }
+ sptr += read_size;
+ data_addr += read_size;
+ data_len -= read_size;
+ }
+
+ if (data_len)
+ ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
+
+ if (ret)
+ dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ }
+ else
+ {
+ ret = ufs_read((struct ufs_dev *) dev, data_addr, (addr_t)out, (data_len / block_size));
if (ret)
{
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / MMC_BLK_SZ));
- return ret;
+ dprintf(CRITICAL, "Error: UFS read failed writing to block: %llu\n", data_addr);
}
- sptr += read_size;
- data_addr += read_size;
- data_len -= read_size;
+
+ arch_invalidate_cache_range((addr_t)out, data_len);
}
- if (data_len)
- ret = mmc_sdhci_read(dev, (void *)sptr, (data_addr / MMC_BLK_SZ), (data_len / MMC_BLK_SZ));
-
- if (ret)
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / MMC_BLK_SZ));
-
return ret;
}
@@ -148,18 +215,25 @@
*/
uint32_t mmc_erase_card(uint64_t addr, uint64_t len)
{
- struct mmc_device *dev;
+ void *dev;
+ uint32_t block_size;
- dev = target_mmc_device();
-
- ASSERT(!(addr % MMC_BLK_SZ));
- ASSERT(!(len % MMC_BLK_SZ));
-
- if (mmc_sdhci_erase(dev, (addr / MMC_BLK_SZ), len))
+ if (target_boot_device_emmc())
{
- dprintf(CRITICAL, "MMC erase failed\n");
- return 1;
+ block_size = mmc_get_device_blocksize();
+
+ dev = target_mmc_device();
+
+ ASSERT(!(addr % block_size));
+ ASSERT(!(len % block_size));
+
+ if (mmc_sdhci_erase((struct mmc_device *)dev, (addr / block_size), len))
+ {
+ dprintf(CRITICAL, "MMC erase failed\n");
+ return 1;
+ }
}
+
return 0;
}
@@ -171,11 +245,22 @@
*/
uint32_t mmc_get_psn(void)
{
- struct mmc_card *card;
+ if (target_boot_device_emmc())
+ {
+ struct mmc_card *card;
- card = get_mmc_card();
+ card = get_mmc_card();
- return card->cid.psn;
+ return card->cid.psn;
+ }
+ else
+ {
+ void *dev;
+
+ dev = target_mmc_device();
+
+ return ufs_get_serial_num((struct ufs_dev *)dev);
+ }
}
/*
@@ -186,10 +271,85 @@
*/
uint64_t mmc_get_device_capacity()
{
- struct mmc_card *card;
+ if (target_boot_device_emmc())
+ {
+ struct mmc_card *card;
- card = get_mmc_card();
+ card = get_mmc_card();
- return card->capacity;
+ return card->capacity;
+ }
+ else
+ {
+ void *dev;
+
+ dev = target_mmc_device();
+
+ return ufs_get_dev_capacity((struct ufs_dev *)dev);
+ }
}
+/*
+ * Function: mmc get blocksize
+ * Arg : None
+ * Return : Returns the block size of the storage
+ * Flow : Get the block size form the card
+ */
+uint32_t mmc_get_device_blocksize()
+{
+ if (target_boot_device_emmc())
+ {
+ struct mmc_card *card;
+
+ card = get_mmc_card();
+
+ return card->block_size;
+ }
+ else
+ {
+ void *dev;
+
+ dev = target_mmc_device();
+
+ return ufs_get_page_size((struct ufs_dev *)dev);
+ }
+}
+
+/*
+ * Function: storage page size
+ * Arg : None
+ * Return : Returns the page size for the card
+ * Flow : Get the page size for storage
+ */
+uint32_t mmc_page_size()
+{
+ if (target_boot_device_emmc())
+ {
+ return BOARD_KERNEL_PAGESIZE;
+ }
+ else
+ {
+ void *dev;
+
+ dev = target_mmc_device();
+
+ return ufs_get_page_size((struct ufs_dev *)dev);
+ }
+}
+
+/*
+ * Function: mmc device sleep
+ * Arg : None
+ * Return : Clean up function for storage
+ * Flow : Put the mmc card to sleep
+ */
+void mmc_device_sleep()
+{
+ void *dev;
+ dev = target_mmc_device();
+
+ if (target_boot_device_emmc())
+ {
+ mmc_put_card_to_sleep((struct mmc_device *)dev);
+ }
+}
diff --git a/platform/msm_shared/nand.c b/platform/msm_shared/nand.c
index 4030c34..d8df0eb 100644
--- a/platform/msm_shared/nand.c
+++ b/platform/msm_shared/nand.c
@@ -3460,17 +3460,22 @@
}
int
-flash_write(struct ptentry *ptn, unsigned extra_per_page, const void *data,
+flash_write(struct ptentry *ptn, unsigned write_extra_bytes, const void *data,
unsigned bytes)
{
unsigned page = ptn->start * num_pages_per_blk;
unsigned lastpage = (ptn->start + ptn->length) * num_pages_per_blk;
unsigned *spare = (unsigned *)flash_spare;
const unsigned char *image = data;
- unsigned wsize = flash_pagesize + extra_per_page;
+ unsigned wsize;
unsigned n;
int r;
+ if(write_extra_bytes)
+ wsize = flash_pagesize + flash_info.spare_size;
+ else
+ wsize = flash_pagesize;
+
if ((flash_info.type == FLASH_ONENAND_DEVICE)
&& (ptn->type == TYPE_MODEM_PARTITION)) {
dprintf(CRITICAL, "flash_write_image: feature not supported\n");
@@ -3504,7 +3509,7 @@
}
}
- if (extra_per_page) {
+ if (write_extra_bytes) {
r = _flash_write_page(flash_cmdlist, flash_ptrlist,
page, image,
image + flash_pagesize);
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 6c0ae6c..e2d548e 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -31,8 +31,8 @@
#include "mmc.h"
#include "partition_parser.h"
-static uint32_t mmc_boot_read_gpt();
-static uint32_t mmc_boot_read_mbr();
+static uint32_t mmc_boot_read_gpt(uint32_t block_size);
+static uint32_t mmc_boot_read_mbr(uint32_t block_size);
static void mbr_fill_name(struct partition_entry *partition_ent,
uint32_t type);
static uint32_t partition_verify_mbr_signature(uint32_t size,
@@ -48,8 +48,8 @@
uint32_t *header_size,
uint32_t *max_partition_count);
-static uint32_t write_mbr(uint32_t, uint8_t *mbrImage);
-static uint32_t write_gpt(uint32_t size, uint8_t *gptImage);
+static uint32_t write_mbr(uint32_t, uint8_t *mbrImage, uint32_t block_size);
+static uint32_t write_gpt(uint32_t size, uint8_t *gptImage, uint32_t block_size);
char *ext3_partitions[] =
{ "system", "userdata", "persist", "cache", "tombstones" };
@@ -65,9 +65,12 @@
unsigned int partition_read_table()
{
unsigned int ret;
+ uint32_t block_size;
+
+ block_size = mmc_get_device_blocksize();
/* Read MBR of the card */
- ret = mmc_boot_read_mbr();
+ ret = mmc_boot_read_mbr(block_size);
if (ret) {
dprintf(CRITICAL, "MMC Boot: MBR read failed!\n");
return 1;
@@ -75,7 +78,7 @@
/* Read GPT of the card if exist */
if (gpt_partitions_exist) {
- ret = mmc_boot_read_gpt();
+ ret = mmc_boot_read_gpt(block_size);
if (ret) {
dprintf(CRITICAL, "MMC Boot: GPT read failed!\n");
return 1;
@@ -87,9 +90,9 @@
/*
* Read MBR from MMC card and fill partition table.
*/
-static unsigned int mmc_boot_read_mbr()
+static unsigned int mmc_boot_read_mbr(uint32_t block_size)
{
- BUF_DMA_ALIGN(buffer, BLOCK_SIZE);
+ uint8_t *buffer = NULL;
unsigned int dtype;
unsigned int dfirstsec;
unsigned int EBR_first_sec;
@@ -97,17 +100,26 @@
int ret = 0;
int idx, i;
+ buffer = (uint8_t *)memalign(CACHE_LINE, ROUNDUP(block_size, CACHE_LINE));
+
+ if (!buffer)
+ {
+ dprintf(CRITICAL, "Error allocating memory while reading partition table\n");
+ ret = -1;
+ goto end;
+ }
+
/* Print out the MBR first */
- ret = mmc_read(0, (unsigned int *)buffer, BLOCK_SIZE);
+ ret = mmc_read(0, (unsigned int *)buffer, block_size);
if (ret) {
dprintf(CRITICAL, "Could not read partition from mmc\n");
- return ret;
+ goto end;
}
/* Check to see if signature exists */
- ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
+ ret = partition_verify_mbr_signature(block_size, buffer);
if (ret) {
- return ret;
+ goto end;
}
/*
@@ -121,7 +133,7 @@
dtype = buffer[idx + i * TABLE_ENTRY_SIZE + OFFSET_TYPE];
if (dtype == MBR_PROTECTED_TYPE) {
gpt_partitions_exist = 1;
- return ret;
+ goto end;
}
partition_entries[partition_count].dtype = dtype;
partition_entries[partition_count].attribute_flag =
@@ -139,24 +151,24 @@
partition_entries[partition_count].dtype);
partition_count++;
if (partition_count == NUM_PARTITIONS)
- return ret;
+ goto end;
}
/* See if the last partition is EBR, if not, parsing is done */
if (dtype != MBR_EBR_TYPE) {
- return ret;
+ goto end;
}
EBR_first_sec = dfirstsec;
EBR_current_sec = dfirstsec;
- ret = mmc_read((EBR_first_sec * 512), (unsigned int *)buffer, BLOCK_SIZE);
+ ret = mmc_read((EBR_first_sec * block_size), (unsigned int *)buffer, block_size);
if (ret)
- return ret;
+ goto end;
/* Loop to parse the EBR */
for (i = 0;; i++) {
- ret = partition_verify_mbr_signature(BLOCK_SIZE, buffer);
+ ret = partition_verify_mbr_signature(block_size, buffer);
if (ret) {
ret = 0;
break;
@@ -175,7 +187,7 @@
partition_entries[partition_count].dtype);
partition_count++;
if (partition_count == NUM_PARTITIONS)
- return ret;
+ goto end;
dfirstsec =
GET_LWORD_FROM_BYTE(&buffer
@@ -187,22 +199,25 @@
/* More EBR to follow - read in the next EBR sector */
dprintf(SPEW, "Reading EBR block from 0x%X\n", EBR_first_sec
+ dfirstsec);
- ret = mmc_read(((EBR_first_sec + dfirstsec) * 512),(unsigned int *)buffer,
- BLOCK_SIZE);
+ ret = mmc_read(((EBR_first_sec + dfirstsec) * block_size),(unsigned int *)buffer,
+ block_size);
if (ret)
- return ret;
+ goto end;
EBR_current_sec = EBR_first_sec + dfirstsec;
}
+end:
+ if (buffer)
+ free(buffer);
+
return ret;
}
/*
* Read GPT from MMC and fill partition table
*/
-static unsigned int mmc_boot_read_gpt()
+static unsigned int mmc_boot_read_gpt(uint32_t block_size)
{
- BUF_DMA_ALIGN(data, BLOCK_SIZE);
int ret = 0;
unsigned int header_size;
unsigned long long first_usable_lba;
@@ -210,13 +225,15 @@
unsigned long long card_size_sec;
unsigned int max_partition_count = 0;
unsigned int partition_entry_size;
- unsigned int i = 0; /* Counter for each 512 block */
- unsigned int j = 0; /* Counter for each 128 entry in the 512 block */
+ unsigned int i = 0; /* Counter for each block */
+ unsigned int j = 0; /* Counter for each entry in a block */
unsigned int n = 0; /* Counter for UTF-16 -> 8 conversion */
unsigned char UTF16_name[MAX_GPT_NAME_SIZE];
/* LBA of first partition -- 1 Block after Protected MBR + 1 for PT */
unsigned long long partition_0;
uint64_t device_density;
+ uint8_t *data = NULL;
+ uint32_t part_entry_cnt = block_size / ENTRY_SIZE;
partition_count = 0;
@@ -224,12 +241,20 @@
device_density = mmc_get_device_capacity();
+ data = (uint8_t *)memalign(CACHE_LINE, ROUNDUP(block_size, CACHE_LINE));
+ if (!data)
+ {
+ dprintf(CRITICAL, "Failed to Allocate memory to read partition table\n");
+ ret = -1;
+ goto end;
+ }
+
/* Print out the GPT first */
- ret = mmc_read(PROTECTIVE_MBR_SIZE, (unsigned int *)data, BLOCK_SIZE);
+ ret = mmc_read(block_size, (unsigned int *)data, block_size);
if (ret)
{
dprintf(CRITICAL, "GPT: Could not read primary gpt from mmc\n");
- return ret;
+ goto end;
}
ret = partition_parse_gpt_header(data, &first_usable_lba,
@@ -241,17 +266,17 @@
/* Check the backup gpt */
/* Get size of MMC */
- card_size_sec = (device_density) / BLOCK_SIZE;
+ card_size_sec = (device_density) / block_size;
ASSERT (card_size_sec > 0);
backup_header_lba = card_size_sec - 1;
- ret = mmc_read((backup_header_lba * BLOCK_SIZE), (unsigned int *)data,
- BLOCK_SIZE);
+ ret = mmc_read((backup_header_lba * block_size), (unsigned int *)data,
+ block_size);
if (ret) {
dprintf(CRITICAL,
"GPT: Could not read backup gpt from mmc\n");
- return ret;
+ goto end;
}
ret = partition_parse_gpt_header(data, &first_usable_lba,
@@ -261,23 +286,23 @@
if (ret) {
dprintf(CRITICAL,
"GPT: Primary and backup signatures invalid\n");
- return ret;
+ goto end;
}
}
partition_0 = GET_LLWORD_FROM_BYTE(&data[PARTITION_ENTRIES_OFFSET]);
/* Read GPT Entries */
- for (i = 0; i < (ROUNDUP(max_partition_count, 4)) / 4; i++) {
+ for (i = 0; i < (ROUNDUP(max_partition_count, part_entry_cnt)) / part_entry_cnt; i++) {
ASSERT(partition_count < NUM_PARTITIONS);
- ret = mmc_read((partition_0 * BLOCK_SIZE) + (i * BLOCK_SIZE),
- (uint32_t *) data, BLOCK_SIZE);
+ ret = mmc_read((partition_0 * block_size) + (i * block_size),
+ (uint32_t *) data, block_size);
if (ret) {
dprintf(CRITICAL,
"GPT: mmc read card failed reading partition entries.\n");
- return ret;
+ goto end;
}
- for (j = 0; j < 4; j++) {
+ for (j = 0; j < part_entry_cnt; j++) {
memcpy(&(partition_entries[partition_count].type_guid),
&data[(j * partition_entry_size)],
PARTITION_TYPE_GUID_SIZE);
@@ -285,7 +310,7 @@
0x00
&& partition_entries[partition_count].
type_guid[1] == 0x00) {
- i = ROUNDUP(max_partition_count, 4);
+ i = ROUNDUP(max_partition_count, part_entry_cnt);
break;
}
memcpy(&
@@ -325,10 +350,14 @@
partition_count++;
}
}
+end:
+ if (data)
+ free(data);
+
return ret;
}
-static unsigned int write_mbr_in_blocks(unsigned size, unsigned char *mbrImage)
+static unsigned int write_mbr_in_blocks(uint32_t size, uint8_t *mbrImage, uint32_t block_size)
{
unsigned int dtype;
unsigned int dfirstsec;
@@ -339,7 +368,7 @@
unsigned int ret;
/* Write the first block */
- ret = mmc_write(0, BLOCK_SIZE, (unsigned int *)mbrImage);
+ ret = mmc_write(0, block_size, (unsigned int *)mbrImage);
if (ret) {
dprintf(CRITICAL, "Failed to write mbr partition\n");
goto end;
@@ -362,7 +391,7 @@
goto end;
}
/* EBR exists. Write each EBR block to mmc */
- ebrImage = mbrImage + BLOCK_SIZE;
+ ebrImage = mbrImage + block_size;
ebrSectorOffset =
GET_LWORD_FROM_BYTE(&mbrImage
[idx + i * TABLE_ENTRY_SIZE +
@@ -372,10 +401,10 @@
lastAddress = mbrImage + size;
while (ebrImage < lastAddress) {
dprintf(SPEW, "writing to 0x%X\n",
- (ebrSectorOffset + dfirstsec) * BLOCK_SIZE);
+ (ebrSectorOffset + dfirstsec) * block_size);
ret =
- mmc_write((ebrSectorOffset + dfirstsec) * BLOCK_SIZE,
- BLOCK_SIZE, (unsigned int *)ebrImage);
+ mmc_write((ebrSectorOffset + dfirstsec) * block_size,
+ block_size, (unsigned int *)ebrImage);
if (ret) {
dprintf(CRITICAL,
"Failed to write EBR block to sector 0x%X\n",
@@ -385,7 +414,7 @@
dfirstsec =
GET_LWORD_FROM_BYTE(&ebrImage
[TABLE_ENTRY_1 + OFFSET_FIRST_SEC]);
- ebrImage += BLOCK_SIZE;
+ ebrImage += block_size;
}
dprintf(INFO, "MBR written to mmc successfully\n");
end:
@@ -393,7 +422,7 @@
}
/* Write the MBR/EBR to the MMC. */
-static unsigned int write_mbr(unsigned size, unsigned char *mbrImage)
+static unsigned int write_mbr(uint32_t size, uint8_t *mbrImage, uint32_t block_size)
{
unsigned int ret;
@@ -404,13 +433,13 @@
}
/* Write the MBR/EBR to mmc */
- ret = write_mbr_in_blocks(size, mbrImage);
+ ret = write_mbr_in_blocks(size, mbrImage, block_size);
if (ret) {
dprintf(CRITICAL, "Failed to write MBR block to mmc.\n");
goto end;
}
/* Re-read the MBR partition into mbr table */
- ret = mmc_boot_read_mbr();
+ ret = mmc_boot_read_mbr(block_size);
if (ret) {
dprintf(CRITICAL, "Failed to re-read mbr partition.\n");
goto end;
@@ -475,9 +504,10 @@
* Write the GPT Partition Entry Array to the MMC.
*/
static unsigned int
-write_gpt_partition_array(unsigned char *header,
- unsigned int partition_array_start,
- unsigned int array_size)
+write_gpt_partition_array(uint8_t *header,
+ uint32_t partition_array_start,
+ uint32_t array_size,
+ uint32_t block_size)
{
unsigned int ret = 1;
unsigned long long partition_entry_lba;
@@ -485,7 +515,7 @@
partition_entry_lba =
GET_LLWORD_FROM_BYTE(&header[PARTITION_ENTRIES_OFFSET]);
- partition_entry_array_start_location = partition_entry_lba * BLOCK_SIZE;
+ partition_entry_array_start_location = partition_entry_lba * block_size;
ret = mmc_write(partition_entry_array_start_location, array_size,
(unsigned int *)partition_array_start);
@@ -500,8 +530,8 @@
}
static void
-patch_gpt(unsigned char *gptImage, uint64_t density, unsigned int array_size,
- unsigned int max_part_count, unsigned int part_entry_size)
+patch_gpt(uint8_t *gptImage, uint64_t density, uint32_t array_size,
+ uint32_t max_part_count, uint32_t part_entry_size, uint32_t block_size)
{
unsigned int partition_entry_array_start;
unsigned char *primary_gpt_header;
@@ -513,14 +543,14 @@
unsigned int crc_value;
/* Get size of MMC */
- card_size_sec = (density) / 512;
+ card_size_sec = (density) / block_size;
/* Working around cap at 4GB */
if (card_size_sec == 0) {
card_size_sec = 4 * 1024 * 1024 * 2 - 1;
}
/* Patching primary header */
- primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
+ primary_gpt_header = (gptImage + block_size);
PUT_LONG_LONG(primary_gpt_header + BACKUP_HEADER_OFFSET,
((long long)(card_size_sec - 1)));
PUT_LONG_LONG(primary_gpt_header + LAST_USABLE_LBA_OFFSET,
@@ -528,7 +558,7 @@
/* Patching backup GPT */
offset = (2 * array_size);
- secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
+ secondary_gpt_header = offset + block_size + primary_gpt_header;
PUT_LONG_LONG(secondary_gpt_header + PRIMARY_HEADER_OFFSET,
((long long)(card_size_sec - 1)));
PUT_LONG_LONG(secondary_gpt_header + LAST_USABLE_LBA_OFFSET,
@@ -537,7 +567,7 @@
((long long)(card_size_sec - 33)));
/* Find last partition */
- while (*(primary_gpt_header + BLOCK_SIZE + total_part * ENTRY_SIZE) !=
+ while (*(primary_gpt_header + block_size + total_part * ENTRY_SIZE) !=
0) {
total_part++;
}
@@ -545,13 +575,13 @@
/* Patching last partition */
last_part_offset =
(total_part - 1) * ENTRY_SIZE + PARTITION_ENTRY_LAST_LBA;
- PUT_LONG_LONG(primary_gpt_header + BLOCK_SIZE + last_part_offset,
+ PUT_LONG_LONG(primary_gpt_header + block_size + last_part_offset,
(long long)(card_size_sec - 34));
- PUT_LONG_LONG(primary_gpt_header + BLOCK_SIZE + last_part_offset +
+ PUT_LONG_LONG(primary_gpt_header + block_size + last_part_offset +
array_size, (long long)(card_size_sec - 34));
/* Updating CRC of the Partition entry array in both headers */
- partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
+ partition_entry_array_start = primary_gpt_header + block_size;
crc_value = calculate_crc32(partition_entry_array_start,
max_part_count * part_entry_size);
PUT_LONG(primary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
@@ -574,7 +604,7 @@
/*
* Write the GPT to the MMC.
*/
-static unsigned int write_gpt(unsigned size, unsigned char *gptImage)
+static unsigned int write_gpt(uint32_t size, uint8_t *gptImage, uint32_t block_size)
{
unsigned int ret = 1;
unsigned int header_size;
@@ -592,7 +622,7 @@
uint64_t device_density;
/* Verify that passed block has a valid GPT primary header */
- primary_gpt_header = (gptImage + PROTECTIVE_MBR_SIZE);
+ primary_gpt_header = (gptImage + block_size);
ret = partition_parse_gpt_header(primary_gpt_header, &first_usable_lba,
&partition_entry_size, &header_size,
&max_partition_count);
@@ -612,7 +642,7 @@
partition_entry_array_size = MIN_PARTITION_ARRAY_SIZE;
}
offset = (2 * partition_entry_array_size);
- secondary_gpt_header = offset + BLOCK_SIZE + primary_gpt_header;
+ secondary_gpt_header = offset + block_size + primary_gpt_header;
ret =
partition_parse_gpt_header(secondary_gpt_header, &first_usable_lba,
&partition_entry_size, &header_size,
@@ -625,7 +655,7 @@
/* Patching the primary and the backup header of the GPT table */
patch_gpt(gptImage, device_density, partition_entry_array_size,
- max_partition_count, partition_entry_size);
+ max_partition_count, partition_entry_size, block_size);
/* Erasing the eMMC card before writing */
ret = mmc_erase_card(0x00000000, device_density);
@@ -635,14 +665,14 @@
}
/* Writing protective MBR */
- ret = mmc_write(0, PROTECTIVE_MBR_SIZE, (unsigned int *)gptImage);
+ ret = mmc_write(0, block_size, (unsigned int *)gptImage);
if (ret) {
dprintf(CRITICAL, "Failed to write Protective MBR\n");
goto end;
}
/* Writing the primary GPT header */
- primary_header_location = PROTECTIVE_MBR_SIZE;
- ret = mmc_write(primary_header_location, BLOCK_SIZE,
+ primary_header_location = block_size;
+ ret = mmc_write(primary_header_location, block_size,
(unsigned int *)primary_gpt_header);
if (ret) {
dprintf(CRITICAL, "Failed to write GPT header\n");
@@ -652,8 +682,8 @@
/* Writing the backup GPT header */
backup_header_lba = GET_LLWORD_FROM_BYTE
(&primary_gpt_header[BACKUP_HEADER_OFFSET]);
- secondary_header_location = backup_header_lba * BLOCK_SIZE;
- ret = mmc_write(secondary_header_location, BLOCK_SIZE,
+ secondary_header_location = backup_header_lba * block_size;
+ ret = mmc_write(secondary_header_location, block_size,
(unsigned int *)secondary_gpt_header);
if (ret) {
dprintf(CRITICAL, "Failed to write GPT backup header\n");
@@ -661,10 +691,10 @@
}
/* Writing the partition entries array for the primary header */
- partition_entry_array_start = primary_gpt_header + BLOCK_SIZE;
+ partition_entry_array_start = primary_gpt_header + block_size;
ret = write_gpt_partition_array(primary_gpt_header,
partition_entry_array_start,
- partition_entry_array_size);
+ partition_entry_array_size, block_size);
if (ret) {
dprintf(CRITICAL,
"GPT: Could not write GPT Partition entries array\n");
@@ -672,11 +702,11 @@
}
/*Writing the partition entries array for the backup header */
- partition_entry_array_start = primary_gpt_header + BLOCK_SIZE +
+ partition_entry_array_start = primary_gpt_header + block_size +
partition_entry_array_size;
ret = write_gpt_partition_array(secondary_gpt_header,
partition_entry_array_start,
- partition_entry_array_size);
+ partition_entry_array_size, block_size);
if (ret) {
dprintf(CRITICAL,
"GPT: Could not write GPT Partition entries array\n");
@@ -685,7 +715,7 @@
/* Re-read the GPT partition table */
dprintf(INFO, "Re-reading the GPT Partition Table\n");
- ret = mmc_boot_read_gpt();
+ ret = mmc_boot_read_gpt(block_size);
if (ret) {
dprintf(CRITICAL,
"GPT: Failure to re- read the GPT Partition table\n");
@@ -703,12 +733,14 @@
{
unsigned int ret = 1;
unsigned int partition_type;
+ uint32_t block_size;
if (partition == 0) {
dprintf(CRITICAL, "NULL partition\n");
goto end;
}
+ block_size = mmc_get_device_blocksize();
ret = partition_get_type(size, partition, &partition_type);
if (ret)
goto end;
@@ -716,12 +748,12 @@
switch (partition_type) {
case PARTITION_TYPE_MBR:
dprintf(INFO, "Writing MBR partition\n");
- ret = write_mbr(size, partition);
+ ret = write_mbr(size, partition, block_size);
break;
case PARTITION_TYPE_GPT:
dprintf(INFO, "Writing GPT partition\n");
- ret = write_gpt(size, partition);
+ ret = write_gpt(size, partition, block_size);
dprintf(CRITICAL, "Re-Flash all the partitions\n");
break;
@@ -833,20 +865,28 @@
/* Get size of the partition */
unsigned long long partition_get_size(int index)
{
+ uint32_t block_size;
+
+ block_size = mmc_get_device_blocksize();
+
if (index == INVALID_PTN)
return 0;
else {
- return partition_entries[index].size * BLOCK_SIZE;
+ return partition_entries[index].size * block_size;
}
}
/* Get offset of the partition */
unsigned long long partition_get_offset(int index)
{
+ uint32_t block_size;
+
+ block_size = mmc_get_device_blocksize();
+
if (index == INVALID_PTN)
return 0;
else {
- return partition_entries[index].first_lba * BLOCK_SIZE;
+ return partition_entries[index].first_lba * block_size;
}
}
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index df8480d..ca3b123 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -63,6 +63,7 @@
static struct flash_id supported_flash[] = {
/* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
{0x1590AC2C, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
+ {0x1590AA2C, 0xFFFFFFFF, 0x10000000, 0, 2048, 0x00020000, 0xE0, 1},
{0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
{0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
@@ -1611,7 +1612,7 @@
int
flash_write(struct ptentry *ptn,
- unsigned extra_per_page,
+ unsigned write_extra_bytes,
const void *data,
unsigned bytes)
{
@@ -1619,9 +1620,14 @@
uint32_t lastpage = (ptn->start + ptn->length) * flash.num_pages_per_blk;
uint32_t *spare = (unsigned *)flash_spare_bytes;
const unsigned char *image = data;
- uint32_t wsize = flash.page_size + extra_per_page;
+ uint32_t wsize;
int r;
+ if(write_extra_bytes)
+ wsize = flash.page_size + flash.spare_size;
+ else
+ wsize = flash.page_size;
+
memset(spare, 0xff, (flash.spare_size / flash.cws_per_page));
while (bytes > 0)
@@ -1656,9 +1662,9 @@
memcpy(rdwr_buf, image, flash.page_size);
- if (extra_per_page)
+ if (write_extra_bytes)
{
- memcpy(rdwr_buf + flash.page_size, image + flash.page_size, extra_per_page);
+ memcpy(rdwr_buf + flash.page_size, image + flash.page_size, flash.spare_size);
r = qpic_nand_write_page(page,
NAND_CFG,
rdwr_buf,
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index ccf164c..e20a32d 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -86,6 +86,7 @@
$(LOCAL_DIR)/display.o \
$(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
@@ -188,7 +189,13 @@
$(LOCAL_DIR)/qpic_nand.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
- $(LOCAL_DIR)/scm.o
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/ufs.o \
+ $(LOCAL_DIR)/utp.o \
+ $(LOCAL_DIR)/uic.o \
+ $(LOCAL_DIR)/ucs.o \
+ $(LOCAL_DIR)/ufs_hci.o \
+ $(LOCAL_DIR)/dme.o
endif
ifeq ($(PLATFORM),msm7x27a)
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 03996f9..4399c60 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -383,8 +383,11 @@
static uint8_t sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd)
{
uint8_t i;
+ uint8_t ret = 0;
+ uint8_t need_reset = 0;
uint32_t retry = 0;
uint32_t int_status;
+ uint32_t trans_complete = 0;
do {
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
@@ -397,6 +400,7 @@
udelay(500);
if (retry == SDHCI_MAX_CMD_RETRY) {
dprintf(CRITICAL, "Error: Command never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -435,12 +439,16 @@
int_status &= SDHCI_INT_STS_TRANS_COMPLETE;
if (int_status & SDHCI_INT_STS_TRANS_COMPLETE)
+ {
+ trans_complete = 1;
break;
+ }
retry++;
udelay(1000);
if (retry == SDHCI_MAX_TRANS_RETRY) {
dprintf(CRITICAL, "Error: Transfer never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -452,20 +460,41 @@
err:
/* Look for errors */
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
- if (int_status & SDHCI_ERR_INT_STAT_MASK) {
- if (sdhci_cmd_err_status(host)) {
- dprintf(CRITICAL, "Error: Command completed with errors\n");
- /* Reset the command & Data line */
- sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 1;
+
+ if (int_status & SDHCI_ERR_INT_STAT_MASK)
+ {
+ /*
+ * As per SDHC spec transfer complete has higher priority than data timeout
+ * If both transfer complete & data timeout are set then we should ignore
+ * data timeout error.
+ * ---------------------------------------------------------------------------
+ * | Transfer complete | Data timeout error | Meaning of the Status |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 0 | Interrupted by another factor |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 1 | Time out occured during transfer|
+ * |--------------------------------------------------------------------------|
+ * | 1 | Don't Care | Command execution complete |
+ * --------------------------------------------------------------------------
+ */
+ if ((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK) && trans_complete)
+ {
+ ret = 0;
}
+ else if (sdhci_cmd_err_status(host))
+ {
+ dprintf(CRITICAL, "Error: Command completed with errors\n");
+ ret = 1;
+ }
+ /* Reset Command & Dat lines on error */
+ need_reset = 1;
}
/* Reset data & command line */
- if (cmd->data_present)
+ if (cmd->data_present || need_reset)
sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 0;
+ return ret;
}
/*
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
old mode 100755
new mode 100644
index e287c8e..8e18903
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -37,6 +37,20 @@
#define SMEM_V8_SMEM_MAX_PMIC_DEVICES 3
#define SMEM_MAX_PMIC_DEVICES SMEM_V8_SMEM_MAX_PMIC_DEVICES
+#define SMEM_RAM_PTABLE_VERSION_OFFSET 8
+
+#define RAM_PART_NAME_LENGTH 16
+#define RAM_NUM_PART_ENTRIES 32
+
+#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
+#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
+
+enum smem_ram_ptable_version
+{
+ SMEM_RAM_PTABLE_VERSION_0,
+ SMEM_RAM_PTABLE_VERSION_1,
+};
+
struct smem_proc_comm {
unsigned command;
unsigned status;
@@ -348,7 +362,9 @@
HW_PLATFORM_RUMI = 15,
HW_PLATFORM_VIRTIO = 16,
HW_PLATFORM_BTS = 19,
+ HW_PLATFORM_RCM = 21,
HW_PLATFORM_DMA = 22,
+ HW_PLATFORM_STP = 23,
HW_PLATFORM_32BITS = 0x7FFFFFFF,
};
@@ -437,28 +453,33 @@
struct smem_ram_ptn {
char name[16];
- unsigned start;
- unsigned size;
+ uint32_t start;
+ uint32_t size;
+ uint32_t attr; /* RAM Partition attribute: READ_ONLY, READWRITE etc.*/
+ uint32_t category; /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
+ uint32_t domain; /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
+ uint32_t type; /* RAM Partition type: system, bootloader, appsboot, apps etc. */
+ uint32_t num_partitions;/* Number of memory partitions */
+ uint32_t reserved3;
+ uint32_t reserved4;
+ uint32_t reserved5;
+} __attribute__ ((__packed__));
- /* RAM Partition attribute: READ_ONLY, READWRITE etc. */
- unsigned attr;
-
- /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
- unsigned category;
-
- /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
- unsigned domain;
-
- /* RAM Partition type: system, bootloader, appsboot, apps etc. */
- unsigned type;
-
- /* reserved for future expansion without changing version number */
- unsigned reserved2, reserved3, reserved4, reserved5;
+struct smem_ram_ptn_v1 {
+ char name[RAM_PART_NAME_LENGTH];
+ uint64_t start;
+ uint64_t size;
+ uint32_t attr; /* RAM Partition attribute: READ_ONLY, READWRITE etc.*/
+ uint32_t category; /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
+ uint32_t domain; /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
+ uint32_t type; /* RAM Partition type: system, bootloader, appsboot, apps etc. */
+ uint32_t num_partitions;/* Number of memory partitions */
+ uint32_t reserved3;
+ uint32_t reserved4; /* Reserved for future use */
+ uint32_t reserved5; /* Reserved for future use */
} __attribute__ ((__packed__));
struct smem_ram_ptable {
-#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
-#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
unsigned magic[2];
unsigned version;
unsigned reserved1;
@@ -467,6 +488,20 @@
unsigned buf;
} __attribute__ ((__packed__));
+struct smem_ram_ptable_hdr
+{
+ uint32_t magic[2];
+ uint32_t version;
+ uint32_t reserved1;
+ uint32_t len;
+} __attribute__ ((__packed__));
+
+struct smem_ram_ptable_v1 {
+ struct smem_ram_ptable_hdr hdr;
+ uint32_t reserved2; /* Added for 8 bytes alignment of header */
+ struct smem_ram_ptn_v1 parts[RAM_NUM_PART_ENTRIES];
+} __attribute__ ((__packed__));
+
/* Power on reason/status info */
#define PWR_ON_EVENT_RTC_ALARM 0x2
#define PWR_ON_EVENT_USB_CHG 0x20
@@ -495,7 +530,13 @@
struct smem_ptn parts[SMEM_PTABLE_MAX_PARTS];
} __attribute__ ((__packed__));
+typedef struct smem_ram_ptable_v1 ram_partition_table;
+typedef struct smem_ram_ptn_v1 ram_partition;
+
unsigned smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len, int offset);
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
-
+int smem_ram_ptable_init_v1(); /* Used on platforms that use ram ptable v1 */
+void smem_get_ram_ptable_entry(ram_partition*, uint32_t entry);
+uint32_t smem_get_ram_ptable_version(void);
+uint32_t smem_get_ram_ptable_len(void);
#endif /* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 291b242..6ec563a 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -42,6 +42,8 @@
static struct smem_ptable smem_ptable;
static unsigned smem_apps_flash_start = 0xFFFFFFFF;
+static ram_partition_table ptable;
+
static void dump_smem_ptable(void)
{
unsigned i;
@@ -150,6 +152,44 @@
}
}
+static void smem_copy_ram_ptable(void *buf)
+{
+ struct smem_ram_ptable *table_v0;
+ struct smem_ram_ptable_v1 *table_v1;
+ uint32_t pentry = 0;
+
+ ptable.hdr = *(struct smem_ram_ptable_hdr*)buf;
+
+ /* Perform member to member copy from smem_ram_ptable to wrapper struct ram_ptable */
+ if(ptable.hdr.version == SMEM_RAM_PTABLE_VERSION_1)
+ {
+ table_v1 = (struct smem_ram_ptable_v1*)buf;
+
+ memcpy(&ptable, table_v1, sizeof(ram_partition_table));
+ }
+ else if(ptable.hdr.version == SMEM_RAM_PTABLE_VERSION_0)
+ {
+ table_v0 = (struct smem_ram_ptable*)buf;
+
+ for(pentry = 0; pentry < ((struct smem_ram_ptable_hdr*)buf)->len; pentry++)
+ {
+ ptable.parts[pentry].start = table_v0->parts[pentry].start;
+ ptable.parts[pentry].size = table_v0->parts[pentry].size;
+ ptable.parts[pentry].attr = table_v0->parts[pentry].attr;
+ ptable.parts[pentry].category = table_v0->parts[pentry].category;
+ ptable.parts[pentry].domain = table_v0->parts[pentry].domain;
+ ptable.parts[pentry].type = table_v0->parts[pentry].type;
+ ptable.parts[pentry].num_partitions = table_v0->parts[pentry].num_partitions;
+ }
+
+ }
+ else
+ {
+ dprintf(CRITICAL,"ERROR: Unknown smem ram ptable version: %u", ptable.hdr.version);
+ ASSERT(0);
+ }
+}
+
/* RAM Partition table from SMEM */
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable)
{
@@ -168,5 +208,71 @@
dprintf(SPEW, "smem ram ptable found: ver: %d len: %d\n",
smem_ram_ptable->version, smem_ram_ptable->len);
+ smem_copy_ram_ptable((void*)smem_ram_ptable);
+
return 1;
}
+
+/* RAM Partition table from SMEM */
+static uint32_t buffer[sizeof(struct smem_ram_ptable_v1)];
+int smem_ram_ptable_init_v1()
+{
+ uint32_t i;
+ uint32_t ret;
+ uint32_t version;
+ uint32_t smem_ram_ptable_size;
+ struct smem_ram_ptable_hdr *ram_ptable_hdr;
+
+ /* Check smem ram partition table version and decide on length of ram_ptable */
+ ret = smem_read_alloc_entry_offset(SMEM_USABLE_RAM_PARTITION_TABLE,
+ &version,
+ sizeof(version),
+ SMEM_RAM_PTABLE_VERSION_OFFSET);
+
+ if(ret)
+ return 0;
+
+ if(version == SMEM_RAM_PTABLE_VERSION_1)
+ smem_ram_ptable_size = sizeof(struct smem_ram_ptable_v1);
+ else if(version == SMEM_RAM_PTABLE_VERSION_0)
+ smem_ram_ptable_size = sizeof(struct smem_ram_ptable);
+ else
+ {
+ dprintf(CRITICAL,"ERROR: Wrong smem_ram_ptable version: %u", version);
+ ASSERT(0);
+ }
+
+ i = smem_read_alloc_entry(SMEM_USABLE_RAM_PARTITION_TABLE,
+ (void*)buffer,
+ smem_ram_ptable_size);
+ if (i != 0)
+ return 0;
+
+ ram_ptable_hdr = (struct smem_ram_ptable_hdr *)buffer;
+
+ if (ram_ptable_hdr->magic[0] != _SMEM_RAM_PTABLE_MAGIC_1 ||
+ ram_ptable_hdr->magic[1] != _SMEM_RAM_PTABLE_MAGIC_2)
+ return 0;
+
+ smem_copy_ram_ptable((void*)buffer);
+
+ dprintf(SPEW, "smem ram ptable found: ver: %u len: %u\n",
+ ram_ptable_hdr->version, ram_ptable_hdr->len);
+
+ return 1;
+}
+
+void smem_get_ram_ptable_entry(ram_partition *ptn, uint32_t entry)
+{
+ memcpy(ptn, &(ptable.parts[entry]), sizeof(ram_partition));
+}
+
+uint32_t smem_get_ram_ptable_len(void)
+{
+ return ptable.hdr.len;
+}
+
+uint32_t smem_get_ram_ptable_version(void)
+{
+ return ptable.hdr.version;
+}
diff --git a/platform/msm_shared/ucs.c b/platform/msm_shared/ucs.c
new file mode 100644
index 0000000..783737f
--- /dev/null
+++ b/platform/msm_shared/ucs.c
@@ -0,0 +1,282 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <endian.h>
+#include <string.h>
+#include <utp.h>
+
+static int ucs_do_request_sense(struct ufs_dev *dev);
+
+int ucs_do_scsi_cmd(struct ufs_dev *dev, struct scsi_req_build_type *req)
+{
+ struct upiu_req_build_type req_upiu;
+ struct upiu_basic_hdr resp_upiu;
+ int ret;
+
+ memset(&req_upiu, 0 , sizeof(struct upiu_req_build_type));
+
+ req_upiu.cmd_set_type = UPIU_SCSI_CMD_SET;
+ req_upiu.trans_type = UPIU_TYPE_COMMAND;
+ req_upiu.data_buffer_addr = req->data_buffer_addr;
+ req_upiu.expected_data_len = req->data_len;
+ req_upiu.data_seg_len = 0;
+ req_upiu.ehs_len = 0;
+ req_upiu.flags = req->flags;
+ req_upiu.lun = req->lun;
+ req_upiu.query_mgmt_func = 0;
+ req_upiu.cdb = req->cdb;
+ req_upiu.cmd_type = UTRD_SCSCI_CMD;
+ req_upiu.dd = req->dd;
+ req_upiu.resp_ptr = &resp_upiu;
+ req_upiu.resp_len = sizeof(resp_upiu);
+ req_upiu.timeout_msecs = UTP_GENERIC_CMD_TIMEOUT;
+
+ if (utp_enqueue_upiu(dev, &req_upiu))
+ {
+ dprintf(CRITICAL, "Data read failed\n");
+ return -UFS_FAILURE;
+ }
+
+ if (resp_upiu.status != SCSI_STATUS_GOOD)
+ {
+ if (resp_upiu.status == SCSI_STATUS_CHK_COND && (*((uint8_t *)(req->cdb)) != SCSI_CMD_SENSE_REQ))
+ {
+ ret = ucs_do_request_sense(dev);
+ if (ret)
+ dprintf(CRITICAL, "SCSI request sense failed.\n");
+ }
+
+ dprintf(CRITICAL, "SCSI read failed. status = %x\n", resp_upiu.status);
+ return -UFS_FAILURE;
+ }
+
+ return UFS_SUCCESS;
+}
+
+int ucs_do_scsi_read(struct ufs_dev *dev, struct scsi_rdwr_req *req)
+{
+ STACKBUF_DMA_ALIGN(cdb, sizeof(struct scsi_rdwr_cdb));
+ struct scsi_req_build_type req_upiu;
+ struct scsi_rdwr_cdb *cdb_param;
+ uint32_t blks_remaining;
+ uint16_t blks_to_transfer;
+ uint64_t bytes_to_transfer;
+ uint32_t start_blk;
+ uint32_t buf;
+
+ blks_remaining = req->num_blocks;
+ buf = req->data_buffer_base;
+ start_blk = req->start_lba;
+
+ cdb_param = (struct scsi_rdwr_cdb*) cdb;
+ while (blks_remaining)
+ {
+ if (blks_remaining <= SCSI_MAX_DATA_TRANS_BLK_LEN)
+ {
+ blks_to_transfer = blks_remaining;
+ blks_remaining = 0;
+ }
+ else
+ {
+ blks_to_transfer = SCSI_MAX_DATA_TRANS_BLK_LEN;
+ blks_remaining -= SCSI_MAX_DATA_TRANS_BLK_LEN;
+ }
+
+ bytes_to_transfer = blks_to_transfer * UFS_DEFAULT_SECTORE_SIZE;
+
+ memset(cdb_param, 0, sizeof(struct scsi_rdwr_cdb));
+ cdb_param->opcode = SCSI_CMD_READ10;
+ cdb_param->cdb1 = SCSI_READ_WRITE_10_CDB1(0, 0, 1, 0);
+ cdb_param->lba = BE32(start_blk);
+ cdb_param->trans_len = BE16(blks_to_transfer);
+
+
+ dsb();
+ arch_clean_invalidate_cache_range((addr_t) cdb_param, sizeof(struct scsi_rdwr_cdb));
+
+ memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
+
+ req_upiu.cdb = (addr_t) cdb_param;
+ req_upiu.data_buffer_addr = buf;
+ req_upiu.data_len = bytes_to_transfer;
+ req_upiu.flags = UPIU_FLAGS_READ;
+ req_upiu.lun = req->lun;
+ req_upiu.dd = UTRD_TARGET_TO_SYSTEM;
+
+ if (ucs_do_scsi_cmd(dev, &req_upiu))
+ {
+ dprintf(CRITICAL, "Data read failed\n");
+ return -UFS_FAILURE;
+ }
+
+ buf += bytes_to_transfer;
+ start_blk += SCSI_MAX_DATA_TRANS_BLK_LEN;
+ }
+
+ return UFS_SUCCESS;
+}
+
+int ucs_do_scsi_write(struct ufs_dev *dev, struct scsi_rdwr_req *req)
+{
+ struct scsi_req_build_type req_upiu;
+ STACKBUF_DMA_ALIGN(cdb, sizeof(struct scsi_rdwr_cdb));
+ struct scsi_rdwr_cdb *cdb_param;
+ uint32_t blks_remaining;
+ uint16_t blks_to_transfer;
+ uint64_t bytes_to_transfer;
+ uint32_t start_blk;
+ uint32_t buf;
+
+ blks_remaining = req->num_blocks;
+ buf = req->data_buffer_base;
+ start_blk = req->start_lba;
+
+ cdb_param = (struct scsi_rdwr_cdb*) cdb;
+ while (blks_remaining)
+ {
+ if (blks_remaining <= SCSI_MAX_DATA_TRANS_BLK_LEN)
+ {
+ blks_to_transfer = blks_remaining;
+ blks_remaining = 0;
+ }
+ else
+ {
+ blks_to_transfer = SCSI_MAX_DATA_TRANS_BLK_LEN;
+ blks_remaining -= SCSI_MAX_DATA_TRANS_BLK_LEN;
+ }
+
+ bytes_to_transfer = blks_to_transfer * UFS_DEFAULT_SECTORE_SIZE;
+
+ memset(cdb_param, 0, sizeof(struct scsi_rdwr_cdb));
+ cdb_param->opcode = SCSI_CMD_WRITE10;
+ cdb_param->cdb1 = SCSI_READ_WRITE_10_CDB1(0, 0, 1, 0);
+ cdb_param->lba = BE32(start_blk);
+ cdb_param->trans_len = BE16(blks_to_transfer);
+
+ /* Flush cdb to memory. */
+ dsb();
+ arch_clean_invalidate_cache_range((addr_t) cdb_param, sizeof(struct scsi_rdwr_cdb));
+
+ memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
+
+ req_upiu.cdb = (addr_t) cdb_param;
+ req_upiu.data_buffer_addr = buf;
+ req_upiu.data_len = bytes_to_transfer;
+ req_upiu.flags = UPIU_FLAGS_WRITE;
+ req_upiu.lun = req->lun;
+ req_upiu.dd = UTRD_SYSTEM_TO_TARGET;
+
+ if (ucs_do_scsi_cmd(dev, &req_upiu))
+ {
+ dprintf(CRITICAL, "Data read failed\n");
+ return -UFS_FAILURE;
+ }
+
+ buf += bytes_to_transfer;
+ start_blk += SCSI_MAX_DATA_TRANS_BLK_LEN;
+ }
+
+ return UFS_SUCCESS;
+}
+
+int ucs_scsi_send_inquiry(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(cdb_param, SCSI_CDB_PARAM_LEN);
+ STACKBUF_DMA_ALIGN(param, SCSI_INQUIRY_LEN);
+ struct scsi_req_build_type req_upiu;
+
+ memset(cdb_param, 0, SCSI_CDB_PARAM_LEN);
+ cdb_param[0] = SCSI_CMD_INQUIRY;
+ cdb_param[3] = sizeof(param)>> 8;
+ cdb_param[4] = sizeof(param);
+
+ /* Flush cdb to memory. */
+ dsb();
+ arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+
+ memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
+
+ req_upiu.cdb = (addr_t) cdb_param;
+ req_upiu.data_buffer_addr = (addr_t) param;
+ req_upiu.data_len = SCSI_INQUIRY_LEN;
+ req_upiu.flags = UPIU_FLAGS_READ;
+ req_upiu.lun = 0;
+ req_upiu.dd = UTRD_TARGET_TO_SYSTEM;
+
+ if (ucs_do_scsi_cmd(dev, &req_upiu))
+ {
+ dprintf(CRITICAL, "Failed to send SCSI inquiry\n");
+ return -UFS_FAILURE;
+ }
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) param, SCSI_INQUIRY_LEN);
+
+ return UFS_SUCCESS;
+}
+
+static int ucs_do_request_sense(struct ufs_dev *dev)
+{
+ STACKBUF_DMA_ALIGN(cdb, sizeof(struct scsi_sense_cdb));
+ struct scsi_req_build_type req_upiu;
+ struct scsi_sense_cdb *cdb_param;
+ uint8_t buf[SCSI_SENSE_BUF_LEN];
+
+ cdb_param = cdb;
+
+ memset(cdb, 0, sizeof(struct scsi_sense_cdb));
+
+ cdb_param->opcode = SCSI_CMD_SENSE_REQ;
+ cdb_param->alloc_len = SCSI_SENSE_BUF_LEN;
+
+ /* Flush cdb to memory. */
+ dsb();
+ arch_invalidate_cache_range((addr_t) cdb_param, SCSI_CDB_PARAM_LEN);
+
+ memset(&req_upiu, 0 , sizeof(struct scsi_req_build_type));
+
+ req_upiu.cdb = (addr_t) cdb_param;
+ req_upiu.data_buffer_addr = (addr_t) buf;
+ req_upiu.data_len = SCSI_SENSE_BUF_LEN;
+ req_upiu.flags = UPIU_FLAGS_READ;
+ req_upiu.lun = 0;
+ req_upiu.dd = UTRD_TARGET_TO_SYSTEM;
+
+ if (ucs_do_scsi_cmd(dev, &req_upiu))
+ {
+ dprintf(CRITICAL, "Data read failed\n");
+ return -UFS_FAILURE;
+ }
+
+ /* Flush buffer. */
+ arch_invalidate_cache_range((addr_t) buf, SCSI_INQUIRY_LEN);
+
+ return UFS_SUCCESS;
+}
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
new file mode 100644
index 0000000..b0470cd
--- /dev/null
+++ b/platform/msm_shared/ufs.c
@@ -0,0 +1,207 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <ufs_hw.h>
+#include <utp.h>
+#include <upiu.h>
+#include <uic.h>
+#include <ucs.h>
+#include <dme.h>
+#include <string.h>
+#include <platform/iomap.h>
+#include <kernel/mutex.h>
+
+static int ufs_dev_init(struct ufs_dev *dev)
+{
+ /* Init the mutexes. */
+ mutex_init(&(dev->uic_data.uic_mutex));
+ mutex_init(&(dev->utrd_data.bitmap_mutex));
+ mutex_init(&(dev->utmrd_data.bitmap_mutex));
+
+ /* Initialize wait lists. */
+ list_initialize(&(dev->utrd_data.list_head.list_node));
+ list_initialize(&(dev->utmrd_data.list_head.list_node));
+
+ /* Initialize the bitmaps. */
+ dev->utrd_data.bitmap = 0;
+ dev->utmrd_data.bitmap = 0;
+
+ /* Initialize task ids. */
+ dev->utrd_data.task_id = 0;
+ dev->utmrd_data.task_id = 0;
+
+ /* Allocate memory for lists. */
+ dev->utrd_data.list_base_addr = ufs_alloc_trans_req_list();
+ dev->utmrd_data.list_base_addr = ufs_alloc_task_mgmt_req_list();
+
+ if (!dev->utrd_data.list_base_addr || !dev->utmrd_data.list_base_addr)
+ return -UFS_FAILURE;
+
+ return UFS_SUCCESS;
+}
+
+static void ufs_setup_req_lists(struct ufs_dev *dev)
+{
+ uint32_t val;
+
+ writel(dev->utmrd_data.list_base_addr, UFS_UTMRLBA(dev->base));
+ writel(dev->utmrd_data.list_base_addr << 32, UFS_UTMRLBAU(dev->base));
+
+ writel(dev->utrd_data.list_base_addr, UFS_UTRLBA(dev->base));
+ writel(dev->utrd_data.list_base_addr << 32, UFS_UTRLBAU(dev->base));
+
+ writel(1, UFS_UTMRLRSR(dev->base));
+ writel(1, UFS_UTRLRSR(dev->base));
+
+ /* Enable the required irqs. */
+ val = UFS_IE_UTRCE | UFS_IE_UEE | UFS_IE_UTMRCE | UFS_IE_UCCE ;
+ ufs_irq_enable(dev, val);
+}
+
+int ufs_read(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks)
+{
+ struct scsi_rdwr_req req;
+ int ret;
+
+ req.data_buffer_base = buffer;
+ req.lun = 0;
+ req.num_blocks = num_blocks;
+ req.start_lba = start_lba / dev->block_size;
+
+ ret = ucs_do_scsi_read(dev, &req);
+ if (ret)
+ {
+ dprintf(CRITICAL, "UFS read failed.\n");
+ }
+
+ return ret;
+}
+
+int ufs_write(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks)
+{
+ struct scsi_rdwr_req req;
+ int ret;
+
+ req.data_buffer_base = buffer;
+ req.lun = 0;
+ req.num_blocks = num_blocks;
+ req.start_lba = start_lba / dev->block_size;
+
+ ret = ucs_do_scsi_write(dev, &req);
+ if (ret)
+ {
+ dprintf(CRITICAL, "UFS write failed.\n");
+ }
+
+ return ret;
+}
+uint64_t ufs_get_dev_capacity(struct ufs_dev* dev)
+{
+ uint64_t capacity;
+ int ret = 0;
+
+ ret = dme_read_unit_desc(dev, 0, &capacity);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to read unit descriptor\n");
+ }
+
+ return capacity;
+}
+
+uint32_t ufs_get_serial_num(struct ufs_dev* dev)
+{
+ int ret;
+
+ ret = dme_read_device_desc(dev);
+ if (ret)
+ {
+ dprintf(CRITICAL, "UFS get serial number failed.\n");
+ }
+
+ return dev->serial_num;
+}
+
+uint32_t ufs_get_page_size(struct ufs_dev* dev)
+{
+ return dev->block_size;
+}
+
+int ufs_init(struct ufs_dev *dev)
+{
+ uint32_t ret = UFS_SUCCESS;
+ uint64_t cap;
+
+ dev->block_size = 4096;
+
+ /* Init dev struct. */
+ ret = ufs_dev_init(dev);
+ if (ret != UFS_SUCCESS)
+ {
+ dprintf(CRITICAL, "UFS init failed\n");
+ goto ufs_init_err;
+ }
+
+ /* Perform Data link init. */
+ ret = uic_init(dev);
+ if (ret != UFS_SUCCESS)
+ {
+ dprintf(CRITICAL, "UFS init failed\n");
+ goto ufs_init_err;
+ }
+
+ /* Setup request lists. */
+ ufs_setup_req_lists(dev);
+
+ /* Send NOP to check if device UTP layer is ready. */
+ ret = dme_send_nop_query(dev);
+ if (ret != UFS_SUCCESS)
+ {
+ dprintf(CRITICAL, "UFS init failed\n");
+ goto ufs_init_err;
+ }
+
+ ret = dme_set_fdeviceinit(dev);
+ if (ret != UFS_SUCCESS)
+ {
+ dprintf(CRITICAL, "UFS init failed\n");
+ goto ufs_init_err;
+ }
+
+ ret = ucs_scsi_send_inquiry(dev);
+ if (ret != UFS_SUCCESS)
+ {
+ dprintf(CRITICAL, "UFS init failed\n");
+ goto ufs_init_err;
+ }
+
+ufs_init_err:
+ return ret;
+}
diff --git a/platform/msm_shared/ufs_hci.c b/platform/msm_shared/ufs_hci.c
new file mode 100644
index 0000000..479c0ff
--- /dev/null
+++ b/platform/msm_shared/ufs_hci.c
@@ -0,0 +1,174 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <arch/ops.h>
+#include <sys/types.h>
+#include <reg.h>
+#include <platform/interrupts.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <ufs_hw.h>
+#include <utp.h>
+
+uint64_t ufs_alloc_trans_req_list()
+{
+ void *ptr;
+
+ ptr = memalign(lcm(CACHE_LINE, 1024), 32 * sizeof(struct utp_trans_req_desc));
+
+ if (!ptr)
+ {
+ dprintf(CRITICAL, "Failed to allocate utrd list.\n");
+ }
+
+ return (addr_t) ptr;
+}
+
+uint64_t ufs_alloc_task_mgmt_req_list()
+{
+ addr_t ptr = (addr_t) memalign(1024, 1024);
+
+ if (!ptr)
+ {
+ dprintf(CRITICAL, "Failed to allocate memory for Task mamagement request list.\n");
+ }
+
+ return ptr;
+}
+
+int ufs_enable_hci(struct ufs_dev *dev)
+{
+ int ret;
+
+ /* Enable host controller */
+ writel(UFS_HCE_ENABLE, UFS_HCE(dev->base));
+
+ /* Wait until host controller is enabled. */
+ ret = ufs_reg_target_val_timeout_loop(UFS_HCE(dev->base), 1, UFS_HCE_TIMEOUT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable UFS host controller.\n");
+ }
+
+ return ret;
+}
+
+void ufs_irq_enable(struct ufs_dev *dev, uint32_t irq)
+{
+ /* Clear all irqs. */
+ writel(0xFFFFFFFF, UFS_IS(dev->base));
+
+ writel(irq, UFS_IE(dev->base));
+ register_int_handler(UFS_IRQ, ufs_irq_handler, dev);
+ unmask_interrupt(UFS_IRQ);
+}
+
+enum handler_return ufs_irq_handler(void* data)
+{
+ uint32_t val;
+ struct ufs_dev *dev = (struct ufs_dev *) data;
+ struct ufs_req_irq_type irq;
+
+ val = readl(UFS_IS(dev->base));
+
+ if (val & UFS_IS_SBFES || val & UFS_IS_HCFES || val & UFS_IS_UTPES || val & UFS_IS_DFES || val & UFS_IS_UE)
+ {
+ /* Controller might be in a bad state, unrecoverable error. */
+ dprintf(CRITICAL, "UFS error\n");
+ ASSERT(0);
+ }
+
+ while (val)
+ {
+ irq.irq_handled = 0;
+
+ if (val & UFS_IS_UCCS)
+ {
+ /* UIC command */
+ event_signal(&(dev->uic_data.uic_event), false);
+ /* Clear irq. */
+ writel(UFS_IS_UCCS, UFS_IS(dev->base));
+ val &= ~UFS_IS_UCCS;
+ irq.irq_handled = UFS_IS_UCCS;
+ continue;
+ }
+ else if (val & UFS_IS_UTRCS)
+ {
+ /* UTRD completion. */
+ irq.list = &(dev->utrd_data.list_head.list_node);
+ irq.irq_handled = UFS_IS_UTRCS;
+ irq.door_bell_reg = UFS_UTRLDBR(dev->base);
+
+ /* Clear irq. */
+ writel(irq.irq_handled, UFS_IS(dev->base));
+ val &= ~irq.irq_handled;
+
+ utp_process_req_completion(&irq);
+ }
+ else if (val & UFS_IS_UTMRCS)
+ {
+ /* UTMRD completion. */
+ irq.list = &(dev->utmrd_data.list_head.list_node);
+ irq.irq_handled = UFS_IS_UTMRCS;
+ /* TODO: Fill in door bell reg for management requests. */
+
+ /* Clear irq. */
+ writel(irq.irq_handled, UFS_IS(dev->base));
+ val &= ~irq.irq_handled;
+
+ utp_process_req_completion(&irq);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Unknown irq.\n");
+ ASSERT(0);
+ }
+ }
+
+ return INT_NO_RESCHEDULE;
+}
+
+int ufs_reg_target_val_timeout_loop(uint32_t reg_addr, uint32_t target_val, uint32_t timeout)
+{
+ uint32_t try_again;
+ uint32_t val;
+
+ try_again = timeout;
+
+ do
+ {
+ try_again--;
+ val = readl(reg_addr);
+ } while (!(val & target_val) && try_again);
+
+ if (!(val & target_val))
+ return -UFS_FAILURE;
+ else
+ return UFS_SUCCESS;
+}
diff --git a/platform/msm_shared/uic.c b/platform/msm_shared/uic.c
new file mode 100644
index 0000000..3ba35b5
--- /dev/null
+++ b/platform/msm_shared/uic.c
Binary files differ
diff --git a/platform/msm_shared/utp.c b/platform/msm_shared/utp.c
new file mode 100644
index 0000000..c7d30ff
--- /dev/null
+++ b/platform/msm_shared/utp.c
Binary files differ
diff --git a/project/apq8084.mk b/project/apq8084.mk
index 8b1075b..4e67a84 100644
--- a/project/apq8084.mk
+++ b/project/apq8084.mk
@@ -9,6 +9,7 @@
DEBUG := 1
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
+ENABLE_UFS_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -25,3 +26,7 @@
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
+
+ifeq ($(ENABLE_UFS_SUPPORT),1)
+DEFINES += UFS_SUPPORT=1
+endif
diff --git a/project/fsm9900.mk b/project/fsm9900.mk
index ae8706f..2745b63 100644
--- a/project/fsm9900.mk
+++ b/project/fsm9900.mk
@@ -17,7 +17,6 @@
#DEFINES += MMC_BOOT_BAM=1
DEFINES += CRYPTO_BAM=1
DEFINES += CRYPTO_REG_ACCESS=1
-DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
#Disable thumb mode
ENABLE_THUMB := false
diff --git a/project/msm8610.mk b/project/msm8610.mk
index b53a77f..72eaf81 100644
--- a/project/msm8610.mk
+++ b/project/msm8610.mk
@@ -16,6 +16,11 @@
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
#DEFINES += CRYPTO_BAM=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
#Disable thumb mode
#TODO: The gold linker has issues generating correct
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 3aaa70f..dc552f1 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -51,14 +51,42 @@
#include <platform/gpio.h>
#include <platform/timer.h>
#include <stdlib.h>
+#include <ufs.h>
#define PMIC_ARB_CHANNEL_NUM 0
#define PMIC_ARB_OWNER_ID 0
#define FASTBOOT_MODE 0x77665500
-static void set_sdc_power_ctrl(void);
+#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1)
+enum cdp_subtype
+{
+ CDP_SUBTYPE_SMB349 = 0,
+ CDP_SUBTYPE_9x25_SMB349,
+ CDP_SUBTYPE_9x25_SMB1357,
+ CDP_SUBTYPE_9x35,
+ CDP_SUBTYPE_SMB1357
+};
+
+enum mtp_subtype
+{
+ MTP_SUBTYPE_SMB349 = 0,
+ MTP_SUBTYPE_9x25_SMB349,
+ MTP_SUBTYPE_9x25_SMB1357,
+ MTP_SUBTYPE_9x35,
+};
+
+enum rcm_subtype
+{
+ RCM_SUBTYPE_SMB349 = 0,
+ RCM_SUBTYPE_9x25_SMB349,
+ RCM_SUBTYPE_9x25_SMB1357,
+ RCM_SUBTYPE_9x35,
+ RCM_SUBTYPE_SMB1357,
+};
+
+static void set_sdc_power_ctrl(void);
static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
@@ -69,13 +97,14 @@
{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
struct mmc_device *dev;
+struct ufs_dev ufs_device;
extern void ulpi_write(unsigned val, unsigned reg);
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(7, 0, BLSP2_UART1_BASE);
#endif
}
@@ -116,6 +145,11 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
+void target_uninit(void)
+{
+ mmc_put_card_to_sleep(dev);
+}
+
/* Do target specific usb initialization */
void target_usb_init(void)
{
@@ -193,18 +227,48 @@
ASSERT(0);
}
}
-
- /* MMC initialization is complete, read the partition table info */
- if (partition_read_table())
- {
- dprintf(CRITICAL, "Error reading the partition table info\n");
- ASSERT(0);
- }
}
-struct mmc_device *target_mmc_device()
+static uint32_t boot_device;
+static uint32_t target_read_boot_config()
{
- return dev;
+ uint32_t val;
+
+ val = readl(BOOT_CONFIG_REG);
+
+ val = BOOT_DEVICE_MASK(val);
+
+ return val;
+}
+
+uint32_t target_get_boot_device()
+{
+ return boot_device;
+}
+
+/*
+ * Return 1 if boot from emmc else 0
+ */
+uint32_t target_boot_device_emmc()
+{
+ uint32_t boot_dev_type;
+
+ boot_dev_type = target_get_boot_device();
+
+ if (boot_dev_type == BOOT_EMMC || boot_dev_type == BOOT_DEFAULT)
+ boot_dev_type = 1;
+ else
+ boot_dev_type = 0;
+
+ return boot_dev_type;
+}
+
+void *target_mmc_device()
+{
+ if (target_boot_device_emmc())
+ return (void *) dev;
+ else
+ return (void *) &ufs_device;
}
void target_init(void)
@@ -215,7 +279,23 @@
target_keystatus();
- target_sdc_init();
+ boot_device = target_read_boot_config();
+
+ if (target_boot_device_emmc())
+ target_sdc_init();
+ else
+ {
+ ufs_device.base = UFS_BASE;
+ ufs_init(&ufs_device);
+ }
+
+ /* Storage initialization is complete, read the partition table info */
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+
}
unsigned board_machtype(void)
@@ -229,37 +309,105 @@
board->target = LINUX_MACHTYPE_UNKNOWN;
}
+void set_cdp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case CDP_SUBTYPE_9x25_SMB349:
+ case CDP_SUBTYPE_9x25_SMB1357:
+ case CDP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case CDP_SUBTYPE_SMB349:
+ case CDP_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "CDP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+
+}
+
+void set_mtp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case MTP_SUBTYPE_9x25_SMB349:
+ case MTP_SUBTYPE_9x25_SMB1357:
+ case MTP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case MTP_SUBTYPE_SMB349:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "MTP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+void set_rcm_baseband(struct board_data *board)
+{
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case RCM_SUBTYPE_9x25_SMB349:
+ case RCM_SUBTYPE_9x25_SMB1357:
+ case RCM_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case RCM_SUBTYPE_SMB349:
+ case RCM_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "RCM platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
uint32_t platform;
uint32_t platform_subtype;
+ uint32_t platform_hardware;
platform = board->platform;
- platform_subtype = board->platform_subtype;
- /*
- * Look for platform subtype if present, else
- * check for platform type to decide on the
- * baseband type
- */
- switch(platform_subtype) {
- case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ platform_hardware = board->platform_hw;
+
+ switch(platform_hardware) {
+ case HW_PLATFORM_SURF:
+ set_cdp_baseband(board);
break;
-
- default:
- dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
- ASSERT(0);
- };
-
- switch(platform) {
- case APQ8084:
+ case HW_PLATFORM_MTP:
+ set_mtp_baseband(board);
+ break;
+ case HW_PLATFORM_RCM:
+ set_rcm_baseband(board);
+ break;
+ case HW_PLATFORM_LIQUID:
board->baseband = BASEBAND_APQ;
break;
default:
- dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ dprintf(CRITICAL, "Platform :%u is not supported\n",
+ platform_hardware);
ASSERT(0);
- }
+ };
}
unsigned target_baseband()
diff --git a/target/apq8084/meminfo.c b/target/apq8084/meminfo.c
index 745657b..7358027 100644
--- a/target/apq8084/meminfo.c
+++ b/target/apq8084/meminfo.c
@@ -35,31 +35,32 @@
#include <platform/iomap.h>
#include <dev_tree.h>
-/* Funtion to add the ram partition entries into device tree.
- * The function assumes that all the entire fixed memory regions should
- * be listed in the first bank of the passed in ddr regions.
- */
uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
{
- struct smem_ram_ptable ram_ptable;
- unsigned int i;
+ ram_partition ptn_entry;
+ unsigned int index;
int ret = 0;
+ uint32_t len = 0;
/* Make sure RAM partition table is initialized */
- ASSERT(smem_ram_ptable_init(&ram_ptable));
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
/* Calculating the size of the mem_info_ptr */
- for (i = 0 ; i < ram_ptable.len; i++)
+ for (index = 0 ; index < len; index++)
{
- if((ram_ptable.parts[i].category == SDRAM) &&
- (ram_ptable.parts[i].type == SYS_MEMORY))
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
{
/* Pass along all other usable memory regions to Linux */
ret = dev_tree_add_mem_info(fdt,
memory_node_offset,
- ram_ptable.parts[i].start,
- ram_ptable.parts[i].size);
+ ptn_entry.start,
+ ptn_entry.size);
if (ret)
{
diff --git a/target/apq8084/rules.mk b/target/apq8084/rules.mk
index aa2abf1..ef4c377 100644
--- a/target/apq8084/rules.mk
+++ b/target/apq8084/rules.mk
@@ -9,7 +9,7 @@
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0xFF00000
+SCRATCH_ADDR := 0x10000000
DEFINES += DISPLAY_SPLASH_SCREEN=0
DEFINES += DISPLAY_TYPE_MIPI=1
diff --git a/target/init.c b/target/init.c
index 57181d4..a4188a8 100644
--- a/target/init.c
+++ b/target/init.c
@@ -145,3 +145,13 @@
{
return false;
}
+
+__WEAK uint32_t target_boot_device_emmc()
+{
+ return 1;
+}
+
+__WEAK uint32_t target_get_boot_device()
+{
+ return 0;
+}
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index 48b145b..62f0eac 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -98,7 +98,7 @@
#define msm8226_DSI_FEATURE_ENABLE 0
-#define MIPI_FB_ADDR 0x0F100000
+#define MIPI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
@@ -109,6 +109,4 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-int mdss_dsi_auto_pll_config(struct mipi_dsi_panel_config *);
#endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index d33aa95..a206c98 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -462,6 +462,8 @@
dload_util_write_cookie(mode == NORMAL_DLOAD ?
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ pm8x41_clear_pmic_watchdog();
+
return 0;
}
@@ -488,7 +490,7 @@
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
-struct mmc_device *target_mmc_device()
+void *target_mmc_device()
{
- return dev;
+ return (void *) dev;
}
diff --git a/dev/gcdb/display/oem_panel.c b/target/msm8226/oem_panel.c
similarity index 84%
rename from dev/gcdb/display/oem_panel.c
rename to target/msm8226/oem_panel.c
index 228dc6b..17955a7 100755
--- a/dev/gcdb/display/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -46,6 +46,7 @@
#include "include/panel_hx8394a_720p_video.h"
#include "include/panel_nt35596_1080p_video.h"
#include "include/panel_nt35521_720p_video.h"
+#include "include/panel_ssd2080m_720p_video.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -56,7 +57,8 @@
NT35590_720P_VIDEO_PANEL,
NT35596_1080P_VIDEO_PANEL,
HX8394A_720P_VIDEO_PANEL,
-NT35521_720P_VIDEO_PANEL
+NT35521_720P_VIDEO_PANEL,
+SSD2080M_720P_VIDEO_PANEL
};
static uint32_t panel_id;
@@ -162,6 +164,26 @@
memcpy(phy_db->timing,
nt35521_720p_video_timings, TIMING_SIZE);
break;
+ case SSD2080M_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &ssd2080m_720p_video_panel_data;
+ panelstruct->panelres = &ssd2080m_720p_video_panel_res;
+ panelstruct->color = &ssd2080m_720p_video_color;
+ panelstruct->videopanel = &ssd2080m_720p_video_video_panel;
+ panelstruct->commandpanel = &ssd2080m_720p_video_command_panel;
+ panelstruct->state = &ssd2080m_720p_video_state;
+ panelstruct->laneconfig = &ssd2080m_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &ssd2080m_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &ssd2080m_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &ssd2080m_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = ssd2080m_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SSD2080M_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ ssd2080m_720p_video_timings, TIMING_SIZE);
+ break;
case HX8394A_720P_VIDEO_PANEL:
panelstruct->paneldata = &hx8394a_720p_video_panel_data;
panelstruct->panelres = &hx8394a_720p_video_panel_res;
@@ -231,7 +253,6 @@
struct mdss_dsi_phy_ctrl *phy_db)
{
uint32_t hw_id = board_hardware_id();
- uint32_t platformid = board_platform_id();
uint32_t target_id = board_target_id();
uint32_t nt35590_panel_id = NT35590_720P_VIDEO_PANEL;
@@ -239,56 +260,31 @@
nt35590_panel_id = NT35590_720P_CMD_PANEL;
#endif
- switch (platformid) {
- case MSM8974:
- switch (hw_id) {
- case HW_PLATFORM_FLUID:
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_SURF:
- panel_id = TOSHIBA_720P_VIDEO_PANEL;
- break;
- default:
- dprintf(CRITICAL, "Display not enabled for %d HW type\n"
- , hw_id);
- return false;
+ switch (hw_id) {
+ case HW_PLATFORM_QRD:
+ if (board_hardware_subtype() == 2) { //HW_PLATFORM_SUBTYPE_SKUF
+ panel_id = NT35521_720P_VIDEO_PANEL;
+ } else if (board_hardware_subtype() == 5) { //HW_PLATFORM_SUBTYPE_SKUG
+ panel_id = SSD2080M_720P_VIDEO_PANEL;
+ } else {
+ if (((target_id >> 16) & 0xFF) == 0x1) //EVT
+ panel_id = nt35590_panel_id;
+ else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
+ panel_id = HX8394A_720P_VIDEO_PANEL;
+ else {
+ dprintf(CRITICAL, "Not supported device, target_id=%x\n"
+ , target_id);
+ return false;
+ }
}
break;
- case MSM8826:
- case MSM8626:
- case MSM8226:
- case MSM8926:
- case MSM8126:
- case MSM8326:
- case APQ8026:
- switch (hw_id) {
- case HW_PLATFORM_QRD:
- if (board_hardware_subtype() == 2) {
- panel_id = NT35521_720P_VIDEO_PANEL;
- } else {
- if (((target_id >> 16) & 0xFF) == 0x1) //EVT
- panel_id = nt35590_panel_id;
- else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
- panel_id = HX8394A_720P_VIDEO_PANEL;
- else {
- dprintf(CRITICAL, "Not supported device, target_id=%x\n"
- , target_id);
- return false;
- }
- }
- break;
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_SURF:
- panel_id = nt35590_panel_id;
- break;
- default:
- dprintf(CRITICAL, "Display not enabled for %d HW type\n"
- , hw_id);
- return false;
- }
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_SURF:
+ panel_id = nt35590_panel_id;
break;
default:
- dprintf(CRITICAL, "GCDB:Display: Platform id:%d not supported\n"
- , platformid);
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
return false;
}
diff --git a/target/msm8226/rules.mk b/target/msm8226/rules.mk
index 0d338c8..f5c9596 100755
--- a/target/msm8226/rules.mk
+++ b/target/msm8226/rules.mk
@@ -41,4 +41,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 3cdc936..04e0615 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -54,6 +54,149 @@
.fdbck = 0x1
};
+static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
+{
+ uint32_t i = 0;
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ for (i = 0; (i < 4) && !pll_locked; i++) {
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ if (i != 0)
+ writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ }
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
int target_backlight_ctrl(uint8_t enable)
{
dprintf(SPEW, "target_backlight_ctrl\n");
@@ -66,6 +209,19 @@
return 0;
}
+static void dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ if (dsi_pll_enable_seq_m(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_f1(ctl_base)) {
+ } else if (dsi_pll_enable_seq_c(ctl_base)) {
+ } else if (dsi_pll_enable_seq_e(ctl_base)) {
+ } else {
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ }
+}
+
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
@@ -76,7 +232,8 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(pll_data);
+ mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
mmss_clock_auto_pll_init(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
@@ -91,40 +248,37 @@
return 0;
}
-int target_panel_reset(uint8_t enable,
- struct gpio_pin *resetgpio,
- struct gpio_pin *enablegpio,
- struct panel_reset_sequence *resetseq)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- gpio_tlmm_config(resetgpio->pin_id, 0,
- resetgpio->pin_direction, resetgpio->pin_pull,
- resetgpio->pin_strength, resetgpio->pin_state);
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
- gpio_set_dir(resetgpio->pin_id, 2);
+ gpio_set_dir(reset_gpio.pin_id, 2);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[0]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]);
mdelay(resetseq->sleep[0]);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[1]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]);
mdelay(resetseq->sleep[1]);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[2]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]);
mdelay(resetseq->sleep[2]);
} else if(!target_cont_splash_screen()) {
- gpio_set_value(resetgpio->pin_id, 0);
+ gpio_set_value(reset_gpio.pin_id, 0);
}
return ret;
}
-int target_ldo_ctrl(uint8_t enable, struct ldo_entry ldo_entry_array[],
- uint8_t ldo_array_size)
+int target_ldo_ctrl(uint8_t enable)
{
uint32_t ret = NO_ERROR;
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
- while (ldocounter < ldo_array_size) {
+ while (ldocounter < TOTAL_LDO_DEFINED) {
struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
0x100 * ldo_entry_array[ldocounter].ldo_id),
ldo_entry_array[ldocounter].ldo_type);
diff --git a/target/msm8610/include/target/display.h b/target/msm8610/include/target/display.h
index 4c8bd15..c6e93c4 100644
--- a/target/msm8610/include/target/display.h
+++ b/target/msm8610/include/target/display.h
@@ -29,8 +29,80 @@
#ifndef _TARGET_MSM8610_DISPLAY_H
#define _TARGET_MSM8610_DISPLAY_H
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
-#define MIPI_FB_ADDR 0x0D200000
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 41, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin te_gpio = {
+ "msmgpio", 12, 0, 2, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin mode_gpio = {
+ "msmgpio", 7, 3, 1, 0, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Supply configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+{ "vddio", 14, 0, 1800000, 100000, 100, 0, 0, 0, 0},
+{ "vdda", 19, 0, 2850000, 100000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 2
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x03, 0x03, 0x00, 0x00, 0x0f, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x02, 0x08, 0x05, 0x00, 0x20, 0x03, 0x00
+};
+
+static const char panel_lane_config[] = {
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x7f, 0x00, 0x00, 0x00
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+
+#define msm8610_DSI_FEATURE_ENABLE 0
+
+#define MIPI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 8
#define MIPI_HSYNC_BACK_PORCH_DCLK 40
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index a116dbe..fb7dd4d 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -122,12 +122,6 @@
/* Set drive strength & pull ctrl values */
set_sdc_power_ctrl();
- /* Display splash screen if enabled */
- dprintf(SPEW, "Display Init: Start\n");
- display_init();
- dprintf(SPEW, "Display Init: Done\n");
-
-
config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_200MHZ;
@@ -169,6 +163,11 @@
target_keystatus();
target_sdc_init();
+
+ /* Display splash screen if enabled */
+ dprintf(SPEW, "Display Init: Start\n");
+ display_init();
+ dprintf(SPEW, "Display Init: Done\n");
}
void target_uninit(void)
@@ -419,7 +418,7 @@
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
-struct mmc_device *target_mmc_device()
+void *target_mmc_device()
{
- return dev;
+ return (void *) dev;
}
diff --git a/target/msm8610/oem_panel.c b/target/msm8610/oem_panel.c
new file mode 100755
index 0000000..e532b56
--- /dev/null
+++ b/target/msm8610/oem_panel.c
@@ -0,0 +1,226 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_truly_wvga_cmd.h"
+#include "include/panel_truly_wvga_video.h"
+#include "include/panel_hx8379a_wvga_video.h"
+#include "include/panel_otm8018b_fwvga_video.h"
+#include "include/panel_nt35590_720p_video.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+TRULY_WVGA_CMD_PANEL,
+TRULY_WVGA_VIDEO_PANEL,
+HX8379A_WVGA_VIDEO_PANEL,
+OTM8018B_FWVGA_VIDEO_PANEL,
+NT35590_720P_VIDEO_PANEL,
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel spefic off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ switch (panel_id) {
+ case TRULY_WVGA_CMD_PANEL:
+ panelstruct->paneldata = &truly_wvga_cmd_panel_data;
+ panelstruct->panelres = &truly_wvga_cmd_panel_res;
+ panelstruct->color = &truly_wvga_cmd_color;
+ panelstruct->videopanel = &truly_wvga_cmd_video_panel;
+ panelstruct->commandpanel = &truly_wvga_cmd_command_panel;
+ panelstruct->state = &truly_wvga_cmd_state;
+ panelstruct->laneconfig = &truly_wvga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_cmd_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_cmd_backlight;
+ pinfo->mipi.panel_cmds
+ = truly_wvga_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TRULY_WVGA_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_cmd_timings, TIMING_SIZE);
+ break;
+ case TRULY_WVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &truly_wvga_video_panel_data;
+ panelstruct->panelres = &truly_wvga_video_panel_res;
+ panelstruct->color = &truly_wvga_video_color;
+ panelstruct->videopanel = &truly_wvga_video_video_panel;
+ panelstruct->commandpanel = &truly_wvga_video_command_panel;
+ panelstruct->state = &truly_wvga_video_state;
+ panelstruct->laneconfig = &truly_wvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_video_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = truly_wvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TRULY_WVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_video_timings, TIMING_SIZE);
+ break;
+ case HX8379A_WVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8379a_wvga_video_panel_data;
+ panelstruct->panelres = &hx8379a_wvga_video_panel_res;
+ panelstruct->color = &hx8379a_wvga_video_color;
+ panelstruct->videopanel = &hx8379a_wvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379a_wvga_video_command_panel;
+ panelstruct->state = &hx8379a_wvga_video_state;
+ panelstruct->laneconfig = &hx8379a_wvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379a_wvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379a_wvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379a_wvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8379a_wvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8379A_WVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8379a_wvga_video_timings, TIMING_SIZE);
+ break;
+ case OTM8018B_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &otm8018b_fwvga_video_panel_data;
+ panelstruct->panelres = &otm8018b_fwvga_video_panel_res;
+ panelstruct->color = &otm8018b_fwvga_video_color;
+ panelstruct->videopanel = &otm8018b_fwvga_video_video_panel;
+ panelstruct->commandpanel = &otm8018b_fwvga_video_command_panel;
+ panelstruct->state = &otm8018b_fwvga_video_state;
+ panelstruct->laneconfig = &otm8018b_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &otm8018b_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &otm8018b_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &otm8018b_fwvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = otm8018b_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = OTM8018B_FWVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ otm8018b_fwvga_video_timings, TIMING_SIZE);
+ break;
+ case NT35590_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35590_720p_video_panel_data;
+ panelstruct->panelres = &nt35590_720p_video_panel_res;
+ panelstruct->color = &nt35590_720p_video_color;
+ panelstruct->videopanel = &nt35590_720p_video_video_panel;
+ panelstruct->commandpanel = &nt35590_720p_video_command_panel;
+ panelstruct->state = &nt35590_720p_video_state;
+ panelstruct->laneconfig = &nt35590_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35590_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &nt35590_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35590_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35590_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35590_720p_video_timings, TIMING_SIZE);
+ break;
+ default:
+ dprintf(CRITICAL, "Panel ID not detected %d\n", panel_id);
+ return false;
+ }
+ return true;
+}
+
+bool oem_panel_select(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t platform_subtype = board_hardware_subtype();
+
+ switch (hw_id) {
+ case HW_PLATFORM_QRD:
+ if ((0 == platform_subtype) || (1 == platform_subtype))
+ panel_id = HX8379A_WVGA_VIDEO_PANEL;
+ else if (3 == platform_subtype)
+ panel_id = OTM8018B_FWVGA_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_MTP:
+ if (0 == platform_subtype)
+ panel_id = TRULY_WVGA_VIDEO_PANEL;
+ else
+ panel_id = NT35590_720P_VIDEO_PANEL;
+ break;
+
+ case HW_PLATFORM_SURF:
+ panel_id = TRULY_WVGA_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n", hw_id);
+ return false;
+ }
+
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8610/rules.mk b/target/msm8610/rules.mk
index 92c669f..909e673 100644
--- a/target/msm8610/rules.mk
+++ b/target/msm8610/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8610
@@ -23,6 +24,7 @@
lib/ptable \
dev/pmic/pm8x41 \
dev/panel/msm \
+ dev/gcdb/display \
lib/libfdt
DEFINES += \
@@ -38,4 +40,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 6e6f412..3610413 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -29,7 +29,9 @@
#include <debug.h>
#include <smem.h>
+#include <err.h>
#include <msm_panel.h>
+#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
@@ -37,21 +39,20 @@
#include <platform/iomap.h>
#include <target/display.h>
-static struct msm_fb_panel_data panel;
-static uint8_t display_enable;
+#include "include/panel.h"
+#include "include/display_resource.h"
-extern int msm_display_init(struct msm_fb_panel_data *pdata);
-extern int msm_display_off();
-extern void dsi_phy_init(struct msm_panel_info *pinfo);
+#define MODE_GPIO_STATE_ENABLE 1
-static int msm8610_backlight(uint8_t enable)
+#define MODE_GPIO_STATE_DISABLE 2
+
+int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_mpp mpp;
mpp.base = PM8x41_MMP3_BASE;
mpp.mode = MPP_HIGH;
mpp.vin = MPP_VIN3;
- if (enable)
- {
+ if (enable) {
pm8x41_config_output_mpp(&mpp);
pm8x41_enable_mpp(&mpp, MPP_ENABLE);
} else {
@@ -62,41 +63,18 @@
return 0;
}
-void dsi_calc_clk_rate(uint32_t *dsiclk_rate, uint32_t *byteclk_rate)
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t hbp, hfp, vbp, vfp, hspw, vspw, width, height;
- uint32_t bitclk_rate;
- int frame_rate, lanes;
+ struct mdss_dsi_pll_config *pll_data;
+ dprintf(SPEW, "target_panel_clock\n");
- width = panel.panel_info.xres;
- height = panel.panel_info.yres;
- hbp = panel.panel_info.lcdc.h_back_porch;
- hfp = panel.panel_info.lcdc.h_front_porch;
- hspw = panel.panel_info.lcdc.h_pulse_width;
- vbp = panel.panel_info.lcdc.v_back_porch;
- vfp = panel.panel_info.lcdc.v_front_porch;
- vspw = panel.panel_info.lcdc.v_pulse_width;
- lanes = panel.panel_info.mipi.num_of_lanes;
- frame_rate = panel.panel_info.mipi.frame_rate;
+ pll_data = pinfo->mipi.dsi_pll_config;
- bitclk_rate = (width + hbp + hfp + hspw) * (height + vbp + vfp + vspw);
- bitclk_rate *= frame_rate;
- bitclk_rate *= panel.panel_info.bpp;
- bitclk_rate /= lanes;
-
- *byteclk_rate = bitclk_rate / 8;
- *dsiclk_rate = *byteclk_rate * lanes;
-}
-
-static int msm8610_mdss_dsi_panel_clock(uint8_t enable)
-{
- uint32_t dsiclk_rate, byteclk_rate;
-
- if (enable)
- {
+ if (enable) {
mdp_clock_enable();
- dsi_calc_clk_rate(&dsiclk_rate, &byteclk_rate);
- dsi_clock_enable(dsiclk_rate, byteclk_rate);
+ dsi_clock_enable(
+ pll_data->byte_clock * pinfo->mipi.num_of_lanes,
+ pll_data->byte_clock);
} else if(!target_cont_splash_screen()) {
dsi_clock_disable();
mdp_clock_disable();
@@ -105,115 +83,72 @@
return 0;
}
-static void msm8610_mdss_mipi_panel_reset(int enable)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
dprintf(SPEW, "msm8610_mdss_mipi_panel_reset, enable = %d\n", enable);
- if (enable)
- {
- gpio_tlmm_config(41, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
- gpio_tlmm_config(7, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ if (enable) {
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+
+ gpio_tlmm_config(mode_gpio.pin_id, 0,
+ mode_gpio.pin_direction, mode_gpio.pin_pull,
+ mode_gpio.pin_strength, mode_gpio.pin_state);
/* reset */
- gpio_set(41, 2);
- mdelay(20);
- gpio_set(41, 0);
- udelay(20);
- gpio_set(41, 2);
- mdelay(20);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[0]);
+ mdelay(resetseq->sleep[0]);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[1]);
+ mdelay(resetseq->sleep[1]);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[2]);
+ mdelay(resetseq->sleep[2]);
- if (panel.panel_info.type == MIPI_VIDEO_PANEL)
- gpio_set(7, 2);
- else if (panel.panel_info.type == MIPI_CMD_PANEL)
- gpio_set(7, 0);
+ if (pinfo->mipi.mode_gpio_state == MODE_GPIO_STATE_ENABLE)
+ gpio_set(mode_gpio.pin_id, 2);
+ else if (pinfo->mipi.mode_gpio_state == MODE_GPIO_STATE_DISABLE)
+ gpio_set(mode_gpio.pin_id, 0);
} else if(!target_cont_splash_screen()) {
- gpio_set(7, 0);
- gpio_set(41, 0);
+ gpio_set(reset_gpio.pin_id, 0);
+ gpio_set(mode_gpio.pin_id, 0);
}
- return;
+ return 0;
}
-static int msm8610_mipi_panel_power(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable)
{
- int ret;
- struct pm8x41_ldo ldo14 = LDO(PM8x41_LDO14, PLDO_TYPE);
- struct pm8x41_ldo ldo19 = LDO(PM8x41_LDO19, PLDO_TYPE);
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
- dprintf(SPEW, "msm8610_mipi_panel_power, enable = %d\n", enable);
- if (enable)
- {
- /* backlight */
- msm8610_backlight(enable);
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
- /* regulators */
- pm8x41_ldo_set_voltage(&ldo14, 1800000);
- pm8x41_ldo_control(&ldo14, enable);
- pm8x41_ldo_set_voltage(&ldo19, 2850000);
- pm8x41_ldo_control(&ldo19, enable);
+ dprintf(SPEW, "Setting %s\n",
+ ldo_entry_array[ldocounter].ldo_id);
- /* reset */
- msm8610_mdss_mipi_panel_reset(enable);
- } else if(!target_cont_splash_screen()) {
- msm8610_backlight(0);
- msm8610_mdss_mipi_panel_reset(enable);
-
- pm8x41_ldo_control(&ldo19, enable);
- pm8x41_ldo_control(&ldo14, enable);
+ /* Set voltage during power on */
+ if (enable) {
+ pm8x41_ldo_set_voltage(&ldo_entry,
+ ldo_entry_array[ldocounter].ldo_voltage);
+ pm8x41_ldo_control(&ldo_entry, enable);
+ } else if(!target_cont_splash_screen()) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
}
+
return 0;
}
void display_init(void)
{
- uint32_t hw_id = board_hardware_id();
- uint32_t platform_subtype = board_hardware_subtype();
-
- dprintf(SPEW, "display_init(),target_id=%d.\n", hw_id);
- dprintf(SPEW, "display_init(),platform_subtype=%d.\n",
- platform_subtype);
-
- switch (hw_id) {
- case HW_PLATFORM_QRD:
- if ((0 == platform_subtype) || (1 == platform_subtype))
- mipi_hx8379a_video_wvga_init(&(panel.panel_info));
- else if (3 == platform_subtype)
- mipi_otm8018b_video_wvga_init(&(panel.panel_info));
-
- break;
- case HW_PLATFORM_MTP:
- if (0 == platform_subtype)
- mipi_truly_video_wvga_init(&(panel.panel_info));
- else
- mipi_nt35590_video_720p_init(&(panel.panel_info));
- break;
- case HW_PLATFORM_SURF:
- mipi_truly_video_wvga_init(&(panel.panel_info));
- break;
- default:
- return;
- };
-
- panel.clk_func = msm8610_mdss_dsi_panel_clock;
- panel.power_func = msm8610_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_304;
-
- if (msm_display_init(&panel))
- {
- dprintf(CRITICAL, "Display init failed!\n");
- return;
- }
-
- display_enable = 1;
+ gcdb_display_init(MDP_REV_304, MIPI_FB_ADDR);
}
void display_shutdown(void)
{
- if (display_enable)
- msm_display_off();
+ gcdb_display_shutdown();
}
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 468b6d5..8897239 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -29,8 +29,68 @@
#ifndef _TARGET_COPPER_DISPLAY_H
#define _TARGET_COPPER_DISPLAY_H
-#define MIPI_FB_ADDR 0x0D200000
-#define EDP_FB_ADDR 0x7EF00000
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "pm8941_gpios", 19, 2, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 58, 3, 1, 0, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 22, 0, 3000000, 100000, 100, 0, 20, 0, 0},
+{ "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+{ "vdda", 2, 1, 1200000, 100000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+
+#define MIPI_FB_ADDR 0x03200000
+#define EDP_FB_ADDR MIPI_FB_ADDR
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
@@ -41,6 +101,5 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
#endif
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 64e9f9e..d544424 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -107,27 +107,6 @@
#endif
}
-/* Check for 8974 chip */
-static int target_is_8974()
-{
- uint32_t platform = board_platform_id();
- int ret = 0;
-
- switch(platform)
- {
- case APQ8074:
- case MSM8274:
- case MSM8674:
- case MSM8974:
- ret = 1;
- break;
- default:
- ret = 0;
- };
-
- return ret;
-}
-
/* Return 1 if vol_up pressed */
static int target_volume_up()
{
@@ -162,7 +141,7 @@
uint32_t target_volume_down()
{
/* Volume down button is tied in with RESIN on MSM8974. */
- if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
+ if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
return pm8x41_v2_resin_status();
else
return pm8x41_resin_status();
@@ -230,7 +209,7 @@
switch(board_hardware_id())
{
case HW_PLATFORM_FLUID:
- if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver))
+ if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
config.bus_width = DATA_BUS_WIDTH_4BIT;
else
config.bus_width = DATA_BUS_WIDTH_8BIT;
@@ -269,9 +248,9 @@
}
}
-struct mmc_device *target_mmc_device()
+void *target_mmc_device()
{
- return dev;
+ return (void *) dev;
}
#else
@@ -312,7 +291,7 @@
switch(board_hardware_id())
{
case HW_PLATFORM_FLUID:
- if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver))
+ if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_4_BIT;
else
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
@@ -484,7 +463,7 @@
soc_ver = board_soc_version();
- if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver))
+ if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
restart_reason_addr = RESTART_REASON_ADDR;
else
restart_reason_addr = RESTART_REASON_ADDR_V2;
@@ -504,7 +483,7 @@
soc_ver = board_soc_version();
/* Write the reboot reason */
- if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver))
+ if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
writel(reboot_reason, RESTART_REASON_ADDR);
else
writel(reboot_reason, RESTART_REASON_ADDR_V2);
@@ -515,7 +494,7 @@
reset_type = PON_PSHOLD_HARD_RESET;
/* Configure PMIC for warm reset */
- if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
+ if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
pm8x41_v2_reset_configure(reset_type);
else
pm8x41_reset_configure(reset_type);
@@ -550,7 +529,7 @@
/* Check if MSM needs VBUS mimic for USB */
static int target_needs_vbus_mimic()
{
- if (target_is_8974())
+ if (platform_is_8974())
return 0;
return 1;
@@ -652,7 +631,7 @@
dprintf(CRITICAL, "Going down for shutdown.\n");
/* Configure PMIC for shutdown. */
- if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
+ if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
pm8x41_v2_reset_configure(PON_PSHOLD_SHUTDOWN);
else
pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
diff --git a/target/msm8974/oem_panel.c b/target/msm8974/oem_panel.c
new file mode 100755
index 0000000..3ea115e
--- /dev/null
+++ b/target/msm8974/oem_panel.c
@@ -0,0 +1,151 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_toshiba_720p_video.h"
+#include "include/panel_sharp_qhd_video.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+TOSHIBA_720P_VIDEO_PANEL,
+SHARP_QHD_VIDEO_PANEL
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel spefic off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static void init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ switch (panel_id) {
+ case TOSHIBA_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &toshiba_720p_video_panel_data;
+ panelstruct->panelres = &toshiba_720p_video_panel_res;
+ panelstruct->color = &toshiba_720p_video_color;
+ panelstruct->videopanel = &toshiba_720p_video_video_panel;
+ panelstruct->commandpanel = &toshiba_720p_video_command_panel;
+ panelstruct->state = &toshiba_720p_video_state;
+ panelstruct->laneconfig = &toshiba_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &toshiba_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &toshiba_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &toshiba_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = toshiba_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TOSHIBA_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ toshiba_720p_video_timings, TIMING_SIZE);
+ break;
+ case SHARP_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &sharp_qhd_video_panel_data;
+ panelstruct->panelres = &sharp_qhd_video_panel_res;
+ panelstruct->color = &sharp_qhd_video_color;
+ panelstruct->videopanel = &sharp_qhd_video_video_panel;
+ panelstruct->commandpanel = &sharp_qhd_video_command_panel;
+ panelstruct->state = &sharp_qhd_video_state;
+ panelstruct->laneconfig = &sharp_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &sharp_qhd_video_backlight;
+ pinfo->mipi.panel_cmds
+ = sharp_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SHARP_QHD_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_qhd_video_timings, TIMING_SIZE);
+ break;
+ }
+}
+
+bool oem_panel_select(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t target_id = board_target_id();
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_SURF:
+ panel_id = TOSHIBA_720P_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_DRAGON:
+ panel_id = SHARP_QHD_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
+ return false;
+ }
+
+ init_panel_data(panelstruct, pinfo, phy_db);
+
+ return true;
+}
diff --git a/target/msm8974/rules.mk b/target/msm8974/rules.mk
index e2acd10..ab9a431 100644
--- a/target/msm8974/rules.mk
+++ b/target/msm8974/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8974
@@ -22,6 +23,7 @@
dev/keys \
dev/pmic/pm8x41 \
dev/panel/msm \
+ dev/gcdb/display \
lib/ptable \
lib/libfdt
@@ -38,4 +40,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 3c0cadd..e02ea22 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -29,7 +29,9 @@
#include <debug.h>
#include <smem.h>
+#include <err.h>
#include <msm_panel.h>
+#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
@@ -38,15 +40,13 @@
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
static struct msm_fb_panel_data panel;
-static uint8_t display_enable;
+static uint8_t edp_enable;
-extern int msm_display_init(struct msm_fb_panel_data *pdata);
-extern int msm_display_off();
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern void edp_auo_1080p_init(struct edp_panel_data *edp_panel);
+#define HFPLL_LDO_ID 12
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0x00,
@@ -58,38 +58,85 @@
.full_current_scale = 0x19
};
-static int msm8974_backlight_on()
+static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ uint32_t rc = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+
+ while (!(readl(ctl_base + 0x02c0) & 0x01)) {
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(2);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ }
+ return rc;
+}
+
+int target_backlight_ctrl(uint8_t enable)
{
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- uint8_t slave_id = 1, i;
- struct board_pmic_data *pmic_info;
+ uint8_t slave_id = 1;
- if (platform_id == MSM8974AC)
- if ((hardware_id == HW_PLATFORM_MTP)
- || (hardware_id == HW_PLATFORM_LIQUID))
- slave_id = 3;
+ if (enable) {
+ if (platform_id == MSM8974AC)
+ if ((hardware_id == HW_PLATFORM_MTP)
+ || (hardware_id == HW_PLATFORM_LIQUID))
+ slave_id = 3;
- pm8x41_wled_config_slave_id(slave_id);
- pm8x41_wled_config(&wled_ctrl);
- pm8x41_wled_sink_control(1);
- pm8x41_wled_iled_sync_control(1);
- pm8x41_wled_enable(1);
+ pm8x41_wled_config_slave_id(slave_id);
+ pm8x41_wled_config(&wled_ctrl);
+ pm8x41_wled_sink_control(enable);
+ pm8x41_wled_iled_sync_control(enable);
+ }
+ pm8x41_wled_enable(enable);
- return 0;
+ return NO_ERROR;
}
-static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t dual_dsi = panel.panel_info.mipi.dual_dsi;
+ struct mdss_dsi_pll_config *pll_data;
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (panel.panel_info.mipi.dual_dsi &&
- !(panel.panel_info.mipi.broadcast))
- mdss_dsi_uniphy_pll_config(MIPI_DSI1_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT, dual_dsi);
+ !(panel.panel_info.mipi.broadcast)) {
+ mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI1_BASE);
+ }
+ mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
@@ -97,34 +144,18 @@
mdp_gdsc_ctrl(enable);
}
- return 0;
-}
-
-static int msm8974_mdss_sharp_dsi_panel_clock(uint8_t enable)
-{
- if (enable) {
- mdp_gdsc_ctrl(enable);
- mdp_clock_init();
- mdss_sharp_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT);
- } else if (!target_cont_splash_screen()) {
- /* Add here for continuous splash */
- mmss_clock_disable();
- mdp_clock_disable();
- mdp_gdsc_ctrl(enable);
- }
-
- return 0;
+ return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
-static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
- uint32_t rst_gpio = 19;
+ uint32_t rst_gpio = reset_gpio.pin_id;
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- struct pm8x41_gpio gpio_param = {
+ struct pm8x41_gpio resetgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
@@ -138,65 +169,53 @@
dprintf(SPEW, "platform_id: %u, rst_gpio: %u\n",
platform_id, rst_gpio);
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
if (enable) {
- gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength, enable_gpio.pin_state);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- mdelay(5);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[0]);
+ mdelay(resetseq->sleep[0]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[1]);
+ mdelay(resetseq->sleep[1]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[2]);
+ mdelay(resetseq->sleep[2]);
} else {
- gpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ resetgpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
}
+ return NO_ERROR;
}
-static int msm8974_mipi_panel_power(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable)
{
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
- struct pm8x41_ldo ldo2 = LDO(PM8x41_LDO2, NLDO_TYPE);
- struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
- struct pm8x41_ldo ldo22 = LDO(PM8x41_LDO22, PLDO_TYPE);
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
- if (enable) {
+ dprintf(SPEW, "Setting %s\n",
+ ldo_entry_array[ldocounter].ldo_id);
- /* Enable backlight */
- msm8974_backlight_on();
-
- /* Turn on LDO8 for lcd1 mipi vdd */
- dprintf(SPEW, " Setting LDO22\n");
- pm8x41_ldo_set_voltage(&ldo22, 3000000);
- pm8x41_ldo_control(&ldo22, enable);
-
- dprintf(SPEW, " Setting LDO12\n");
- /* Turn on LDO23 for lcd1 mipi vddio */
- pm8x41_ldo_set_voltage(&ldo12, 1800000);
- pm8x41_ldo_control(&ldo12, enable);
-
- dprintf(SPEW, " Setting LDO2\n");
- /* Turn on LDO2 for vdda_mipi_dsi */
- pm8x41_ldo_set_voltage(&ldo2, 1200000);
- pm8x41_ldo_control(&ldo2, enable);
-
- dprintf(SPEW, " Panel Reset \n");
- /* Panel Reset */
- msm8974_mdss_mipi_panel_reset(enable);
- dprintf(SPEW, " Panel Reset Done\n");
- } else {
- msm8974_mdss_mipi_panel_reset(enable);
- pm8x41_wled_enable(enable);
- pm8x41_ldo_control(&ldo2, enable);
- pm8x41_ldo_control(&ldo22, enable);
-
+ /* Set voltage during power on */
+ if (enable) {
+ pm8x41_ldo_set_voltage(&ldo_entry,
+ ldo_entry_array[ldocounter].ldo_voltage);
+ pm8x41_ldo_control(&ldo_entry, enable);
+ } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
}
- return 0;
+ return NO_ERROR;
}
static int msm8974_mdss_edp_panel_clock(int enable)
@@ -256,40 +275,7 @@
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
- uint32_t soc_ver = board_soc_version();
-
- dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
-
switch (hw_id) {
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_FLUID:
- case HW_PLATFORM_SURF:
- mipi_toshiba_video_720p_init(&(panel.panel_info));
- panel.clk_func = msm8974_mdss_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
- case HW_PLATFORM_DRAGON:
- mipi_sharp_video_qhd_init(&(panel.panel_info));
- wled_ctrl.ovp = 0x0; /* 35V */
- wled_ctrl.full_current_scale = 0x14; /* 20mA */
- wled_ctrl.max_duty_cycle = 0; /* 26ns */
- panel.clk_func = msm8974_mdss_sharp_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
panel.clk_func = msm8974_mdss_edp_panel_clock;
@@ -297,21 +283,30 @@
panel.fb.base = (void *)EDP_FB_ADDR;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
+
+ if (msm_display_init(&panel)) {
+ dprintf(CRITICAL, "edp init failed!\n");
+ return;
+ }
+
+ edp_enable = 1;
break;
default:
- return;
- };
-
- if (msm_display_init(&panel)) {
- dprintf(CRITICAL, "Display init failed!\n");
- return;
+ gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ break;
}
-
- display_enable = 1;
}
void display_shutdown(void)
{
- if (display_enable)
- msm_display_off();
+ uint32_t hw_id = board_hardware_id();
+ switch (hw_id) {
+ case HW_PLATFORM_LIQUID:
+ if (edp_enable)
+ msm_display_off();
+ break;
+ default:
+ gcdb_display_shutdown();
+ break;
+ }
}