target,platform: msm_shared: correct sdcc ddr register
sdcc ddr config register has changed for new targets.
ensure that correct register is read.
Change-Id: I8893f05c4775073921a1cef480284d18ff0d70bc
diff --git a/include/target.h b/include/target.h
index d0d830d..62369ed 100644
--- a/include/target.h
+++ b/include/target.h
@@ -93,6 +93,7 @@
struct qmp_reg *target_get_qmp_settings();
int target_get_qmp_regsize();
+uint32_t target_ddr_cfg_reg();
#if PON_VIB_SUPPORT
void get_vibration_type();
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 1d4229a..f295533 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -556,7 +556,7 @@
DBG("\n CM_DLL_SDC4 Calibration Start\n");
/*1.Write the DDR config value to SDCC_HC_REG_DDR_CONFIG register*/
- REG_WRITE32(host, target_ddr_cfg_val(), SDCC_HC_REG_DDR_CONFIG);
+ REG_WRITE32(host, target_ddr_cfg_val(), target_ddr_cfg_reg());
/*2. Write DDR_CAL_EN to '1' */
REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | DDR_CAL_EN), SDCC_HC_REG_DLL_CONFIG_2);
diff --git a/target/init.c b/target/init.c
index d5cfa92..a0e0e10 100644
--- a/target/init.c
+++ b/target/init.c
@@ -248,6 +248,33 @@
return DDR_CONFIG_VAL;
}
+/* Default CFG register value */
+uint32_t target_ddr_cfg_reg()
+{
+ uint32_t platform = board_platform_id();
+ uint32_t ret = SDCC_HC_REG_DDR_CONFIG;
+
+ switch(platform)
+ {
+ case MSM8937:
+ case MSM8940:
+ case APQ8037:
+ case MSM8917:
+ case MSM8920:
+ case MSM8217:
+ case MSM8617:
+ case APQ8017:
+ case MSM8953:
+ case APQ8053:
+ /* SDCC HC DDR CONFIG has shifted by 4 bytes for these platform */
+ ret += 4;
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
#if PON_VIB_SUPPORT
void get_vibration_type(struct qpnp_hap *config)
{