Deepa Dinamani | 0bb64ff | 2011-12-06 10:45:44 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifndef __PMIC_PWM_H |
| 31 | #define __PMIC_PWM_H |
| 32 | |
| 33 | /* PMIC 8921 LPG defines */ |
| 34 | |
| 35 | #define PM8921_LPG_CTL_BASE (0x13C) |
| 36 | |
| 37 | #define PM8921_LPG_CTL(n) (PM8921_LPG_CTL_BASE + (n)) |
| 38 | #define PM8921_LPG_BANK_SEL (0x143) |
| 39 | #define PM8921_LPG_BANK_ENABLE (0x144) |
| 40 | |
| 41 | #define USEC_PER_SEC 1000000L |
| 42 | #define NSEC_PER_SEC 1000000000L |
| 43 | #define NSEC_PER_USEC 1000 |
| 44 | |
| 45 | #define PWM_FREQ_HZ 300 |
| 46 | #define PWM_LEVEL 15 |
| 47 | |
| 48 | #define NUM_CLOCKS 3 |
| 49 | #define NUM_PRE_DIVIDE 4 |
| 50 | |
| 51 | #define NUM_LPG_CTL_REGS 7 |
| 52 | |
| 53 | #define PRE_DIVIDE_0 2 |
| 54 | #define PRE_DIVIDE_1 3 |
| 55 | #define PRE_DIVIDE_2 5 |
| 56 | #define PRE_DIVIDE_3 6 |
| 57 | |
| 58 | #define PRE_DIVIDE_MIN PRE_DIVIDE_0 |
| 59 | #define PRE_DIVIDE_MAX PRE_DIVIDE_3 |
| 60 | |
| 61 | #define PM_PWM_M_MIN 0 |
| 62 | #define PM_PWM_M_MAX 7 |
| 63 | |
| 64 | #define NSEC_1000HZ (NSEC_PER_SEC / 1000) |
| 65 | #define NSEC_32768HZ (NSEC_PER_SEC / 32768) |
| 66 | #define NSEC_19P2MHZ (NSEC_PER_SEC / 19200000) |
| 67 | |
| 68 | #define CLK_PERIOD_MIN NSEC_19P2MHZ |
| 69 | #define CLK_PERIOD_MAX NSEC_1000HZ |
| 70 | |
| 71 | #define MIN_MPT ((PRE_DIVIDE_MIN * CLK_PERIOD_MIN) << PM_PWM_M_MIN) |
| 72 | #define MAX_MPT ((PRE_DIVIDE_MAX * CLK_PERIOD_MAX) << PM_PWM_M_MAX) |
| 73 | |
| 74 | /* The MAX value is computation limit. Hardware limit is 393 seconds. */ |
| 75 | #define PM_PWM_PERIOD_MAX (274 * USEC_PER_SEC) |
| 76 | /* The MIN value is hardware limit. */ |
| 77 | #define PM_PWM_PERIOD_MIN 7 /* micro seconds */ |
| 78 | |
| 79 | #define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ) |
| 80 | #define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL) |
| 81 | |
| 82 | /* Control 0 */ |
| 83 | #define PM_PWM_1KHZ_COUNT_MASK 0xF0 |
| 84 | #define PM_PWM_1KHZ_COUNT_SHIFT 4 |
| 85 | |
| 86 | #define PM_PWM_1KHZ_COUNT_MAX 15 |
| 87 | |
| 88 | #define PM_PWM_OUTPUT_EN 0x08 |
| 89 | #define PM_PWM_PWM_EN 0x04 |
| 90 | #define PM_PWM_RAMP_GEN_EN 0x02 |
| 91 | #define PM_PWM_RAMP_START 0x01 |
| 92 | |
| 93 | #define PM_PWM_PWM_START (PM_PWM_OUTPUT_EN | PM_PWM_PWM_EN) |
| 94 | #define PM_PWM_RAMP_GEN_START (PM_PWM_RAMP_GEN_EN | PM_PWM_RAMP_START) |
| 95 | |
| 96 | /* Control 1 */ |
| 97 | #define PM_PWM_REVERSE_EN 0x80 |
| 98 | #define PM_PWM_BYPASS_LUT 0x40 |
| 99 | #define PM_PWM_HIGH_INDEX_MASK 0x3F |
| 100 | |
| 101 | /* Control 2 */ |
| 102 | #define PM_PWM_LOOP_EN 0x80 |
| 103 | #define PM_PWM_RAMP_UP 0x40 |
| 104 | #define PM_PWM_LOW_INDEX_MASK 0x3F |
| 105 | |
| 106 | /* Control 3 */ |
| 107 | #define PM_PWM_VALUE_BIT7_0 0xFF |
| 108 | #define PM_PWM_VALUE_BIT5_0 0x3F |
| 109 | |
| 110 | /* Control 4 */ |
| 111 | #define PM_PWM_VALUE_BIT8 0x80 |
| 112 | |
| 113 | #define PM_PWM_CLK_SEL_MASK 0x60 |
| 114 | #define PM_PWM_CLK_SEL_SHIFT 5 |
| 115 | |
| 116 | #define PM_PWM_CLK_SEL_NO 0 |
| 117 | #define PM_PWM_CLK_SEL_1KHZ 1 |
| 118 | #define PM_PWM_CLK_SEL_32KHZ 2 |
| 119 | #define PM_PWM_CLK_SEL_19P2MHZ 3 |
| 120 | |
| 121 | #define PM_PWM_PREDIVIDE_MASK 0x18 |
| 122 | #define PM_PWM_PREDIVIDE_SHIFT 3 |
| 123 | |
| 124 | #define PM_PWM_PREDIVIDE_2 0 |
| 125 | #define PM_PWM_PREDIVIDE_3 1 |
| 126 | #define PM_PWM_PREDIVIDE_5 2 |
| 127 | #define PM_PWM_PREDIVIDE_6 3 |
| 128 | |
| 129 | #define PM_PWM_M_MASK 0x07 |
| 130 | #define PM_PWM_M_MIN 0 |
| 131 | #define PM_PWM_M_MAX 7 |
| 132 | |
| 133 | /* Control 5 */ |
| 134 | #define PM_PWM_PAUSE_COUNT_HI_MASK 0xFC |
| 135 | #define PM_PWM_PAUSE_COUNT_HI_SHIFT 2 |
| 136 | |
| 137 | #define PM_PWM_PAUSE_ENABLE_HIGH 0x02 |
| 138 | #define PM_PWM_SIZE_9_BIT 0x01 |
| 139 | |
| 140 | /* Control 6 */ |
| 141 | #define PM_PWM_PAUSE_COUNT_LO_MASK 0xFC |
| 142 | #define PM_PWM_PAUSE_COUNT_LO_SHIFT 2 |
| 143 | |
| 144 | #define PM_PWM_PAUSE_ENABLE_LOW 0x02 |
| 145 | #define PM_PWM_RESERVED 0x01 |
| 146 | |
| 147 | #define PM_PWM_PAUSE_COUNT_MAX 56 /* < 2^6 = 64*/ |
| 148 | |
| 149 | struct pm_pwm_config { |
| 150 | uint8_t pwm_size; /* round up to 6 or 9 for 6/9-bit PWM SIZE */ |
| 151 | uint8_t clk; |
| 152 | uint8_t pre_div; |
| 153 | uint8_t pre_div_exp; |
| 154 | uint8_t pwm_value; |
| 155 | uint8_t bypass_lut; |
| 156 | uint8_t pwm_ctl[NUM_LPG_CTL_REGS]; |
| 157 | }; |
| 158 | |
| 159 | /* External PWM functions */ |
| 160 | int pm8921_pwm_enable(uint8_t pwm_id, pm8921_dev_t *dev); |
| 161 | int pm8921_pwm_config(uint8_t pwm_id, |
| 162 | uint32_t duty_us, |
| 163 | uint32_t period_us, |
| 164 | pm8921_dev_t *dev); |
| 165 | |
| 166 | #endif |