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Amol Jadicd43ea02011-02-15 20:56:04 -08001/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in
11 * the documentation and/or other materials provided with the
12 * distribution.
13 * * Neither the name of Google, Inc. nor the names of its contributors
14 * may be used to endorse or promote products derived from this
15 * software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
21 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
27 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <debug.h>
32#include <reg.h>
33#include <platform/iomap.h>
Amol Jadidb1edb32011-07-18 14:24:46 -070034#include <qgic.h>
Amol Jadic52c8a32011-07-12 11:27:04 -070035#include <uart_dm.h>
Kinson Chike5c93432011-06-17 09:10:29 -070036#include <dev/fbcon.h>
Amol Jadida055742011-06-14 16:15:12 -070037#include <mmu.h>
38#include <arch/arm/mmu.h>
Amol Jadicd43ea02011-02-15 20:56:04 -080039
Amol Jadicd43ea02011-02-15 20:56:04 -080040extern void platform_init_timer(void);
Greg Grisco1073a5e2011-07-28 18:59:18 -070041extern void platform_panel_backlight_on(void);
42extern void platform_uninit_timer(void);
Kinson Chike5c93432011-06-17 09:10:29 -070043extern void mipi_panel_reset(void);
44extern void mipi_dsi_panel_power_on(void);
45extern void mdp_clock_init(void);
46extern void mmss_clock_init(void);
47extern struct fbcon_config *mipi_init(void);
48extern void mipi_dsi_shutdown(void);
Greg Grisco1073a5e2011-07-28 18:59:18 -070049extern uint8_t target_uart_gsbi(void);
Amol Jadicd43ea02011-02-15 20:56:04 -080050
Amol Jadiaeda4e62011-07-19 18:07:29 -070051static uint32_t ticks_per_sec = 0;
52
Amol Jadida055742011-06-14 16:15:12 -070053#define MB (1024*1024)
54
55#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
56
57/* LK memory - cacheable, write through */
58#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
59 MMU_MEMORY_AP_READ_WRITE)
60
61/* Kernel region - cacheable, write through */
62#define KERNEL_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
63 MMU_MEMORY_AP_READ_WRITE)
64
65/* Scratch region - cacheable, write through */
66#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
67 MMU_MEMORY_AP_READ_WRITE)
68
69/* Peripherals - non-shared device */
70#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_NON_SHARED | \
71 MMU_MEMORY_AP_READ_WRITE)
72
73
74mmu_section_t mmu_section_table[] = {
75/* Physical addr, Virtual addr, Size (in MB), Flags */
76 {MEMBASE, MEMBASE, (MEMSIZE/MB), LK_MEMORY},
77 {BASE_ADDR, BASE_ADDR, 44, KERNEL_MEMORY},
78 {SCRATCH_ADDR, SCRATCH_ADDR, 128, SCRATCH_MEMORY},
79 {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
80};
81
Amol Jadicd43ea02011-02-15 20:56:04 -080082void platform_early_init(void)
83{
Amol Jadic52c8a32011-07-12 11:27:04 -070084 uart_init(target_uart_gsbi());
Amol Jadidb1edb32011-07-18 14:24:46 -070085 qgic_init();
Amol Jadicd43ea02011-02-15 20:56:04 -080086 platform_init_timer();
87}
88
89void platform_init(void)
90{
91 dprintf(INFO, "platform_init()\n");
92}
Kinson Chike5c93432011-06-17 09:10:29 -070093
94void display_init(void){
95 struct fbcon_config *fb_cfg;
96
Kinson Chikc1ad9462011-07-20 17:40:06 -070097 panel_backlight_on();
98
Kinson Chike5c93432011-06-17 09:10:29 -070099 mipi_dsi_panel_power_on();
100 mipi_panel_reset();
101
102 mdp_clock_init();
103 mmss_clock_init();
104
105 fb_cfg = mipi_init();
106 fbcon_setup(fb_cfg);
107}
108
109void display_shutdown(void)
110{
111 mipi_dsi_shutdown();
112}
Amol Jadi4421e652011-06-16 15:00:48 -0700113
114void platform_uninit(void)
115{
116 platform_uninit_timer();
117#if DISPLAY_SPLASH_SCREEN
118 display_shutdown();
119#endif
120}
121
Amol Jadida055742011-06-14 16:15:12 -0700122/* Setup memory for this platform */
123void platform_init_mmu_mappings(void)
124{
125 uint32_t i;
126 uint32_t sections;
127 uint32_t table_size = ARRAY_SIZE(mmu_section_table);
128
129 for (i = 0; i < table_size; i++)
130 {
131 sections = mmu_section_table[i].num_of_sections;
132
133 while (sections--)
134 {
135 arm_mmu_map_section(mmu_section_table[i].paddress + sections*MB,
136 mmu_section_table[i].vaddress + sections*MB,
137 mmu_section_table[i].flags);
138 }
139 }
140}
Amol Jadiaeda4e62011-07-19 18:07:29 -0700141
142/* Initialize DGT timer */
143void platform_init_timer(void)
144{
145 /* disable timer */
146 writel(0, DGT_ENABLE);
147
148 /* DGT uses LPXO source which is 27MHz.
149 * Set clock divider to 4.
150 */
151 writel(3, DGT_CLK_CTL);
152
153 ticks_per_sec = 6750000; /* (27 MHz / 4) */
154}
155
156/* Returns timer ticks per sec */
157uint32_t platform_tick_rate(void)
158{
159 return ticks_per_sec;
160}