blob: d179c8f7c13fd6377f0c552e06f6dcd0dbe26459 [file] [log] [blame]
Amol Jadif3d5a892013-07-23 16:09:44 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* This file implements the UDC (usb device controller) layer to be used with
30 * the new dwc controller.
31 * It exposes APIs to initialize UDC (and thus usb) and perform data transfer
32 * over usb.
33 */
34
35#include <reg.h>
36#include <debug.h>
37#include <string.h>
38#include <malloc.h>
39#include <stdlib.h>
40#include <arch/defines.h>
41#include <dev/udc.h>
42#include <platform/iomap.h>
43#include <usb30_dwc.h>
44#include <usb30_wrapper.h>
45#include <usb30_udc.h>
Amol Jadi5418da32013-10-11 14:14:47 -070046#include <smem.h>
47#include <board.h>
48#include <platform/timer.h>
Amol Jadif3d5a892013-07-23 16:09:44 -070049
50//#define DEBUG_USB
51
52#ifdef DEBUG_USB
53#define DBG(...) dprintf(ALWAYS, __VA_ARGS__)
54#else
55#define DBG(...)
56#endif
57
58#define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
59
60/* control data transfer is max 512 bytes */
61#define UDC_CONTROL_RX_BUF_SIZE 512
62#define UDC_CONTROL_TX_BUF_SIZE 512
63
64/* Buffer used by dwc driver to process events.
65 * Must be multiple of 4: snps 6.2.7.2.
66 */
67#define UDC_DWC_EVENT_BUF_SIZE 4096
68
69/* macro to parse setup request */
70#define SETUP(type,request) (((type) << 8) | (request))
71
72/* macro to generate bit representation of an EP */
73#define EPT_TX(n) (1 << ((n) + 16))
74#define EPT_RX(n) (1 << (n))
75
76/* Local functions */
77static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
78 uint32_t num,
79 uint32_t len,
80 udc_desc_spec_t spec);
81static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str);
82
83static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc);
84static void udc_register_language_desc(udc_t *udc);
85static void udc_register_bos_desc(udc_t *udc);
86static void udc_register_device_desc_usb_20(udc_t *udc, struct udc_device *dev_info);
87static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info);
88static void udc_register_config_desc_usb20(udc_t *udc, struct udc_gadget *gadget);
89static void udc_register_config_desc_usb30(udc_t *udc, struct udc_gadget *gadget);
90
91static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data);
92static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data);
93
94static void udc_dwc_notify(void *context, dwc_notify_event_t event);
95static int udc_handle_setup(void *context, uint8_t *data);
96
97/* TODO: This must be the only global var in this file, for now.
98 * Ideally, all APIs should be sending
99 * this to us and this ptr should be kept outside of this code.
100 * This needs change in the common udc APIs and thus keeping it here until that
101 * is done.
102 */
103static udc_t *udc_dev = NULL;
104
105
Amol Jadi5418da32013-10-11 14:14:47 -0700106__WEAK int platform_is_8974()
Amol Jadif3d5a892013-07-23 16:09:44 -0700107{
Amol Jadi5418da32013-10-11 14:14:47 -0700108 return 0;
Amol Jadif3d5a892013-07-23 16:09:44 -0700109}
110
Amol Jadi5418da32013-10-11 14:14:47 -0700111__WEAK int platform_is_8974Pro()
Amol Jadif3d5a892013-07-23 16:09:44 -0700112{
Amol Jadi5418da32013-10-11 14:14:47 -0700113 return 0;
114}
115
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700116__WEAK int platform_is_8x62()
117{
118 return 0;
119}
120
Amol Jadi5418da32013-10-11 14:14:47 -0700121static void phy_mux_configure(void)
122{
123 /* configuring of hs phy mux is different for some platforms. */
124 target_usb_phy_mux_configure();
125}
126
127static void phy_reset(usb_wrapper_dev_t *wrapper)
128{
129 /* phy reset is different for some platforms. */
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700130 if (platform_is_8974() || platform_is_8974Pro() || platform_is_8x62())
Amol Jadi5418da32013-10-11 14:14:47 -0700131 {
132 /* SS PHY */
133 usb_wrapper_ss_phy_reset(wrapper);
134
135 /* For 8974: hs phy is reset as part of soft reset.
136 * No need for explicit reset.
137 */
138 }
139 else if (board_platform_id() == APQ8084)
140 {
141 target_usb_phy_reset();
142 }
143}
144
145/* Initialize HS phy */
146void hs_phy_init(udc_t *dev)
147{
148 /* only for 8974 */
Channagoud Kadabi16b23bc2013-10-17 19:00:10 -0700149 if (platform_is_8974() || platform_is_8974Pro() || platform_is_8x62())
Amol Jadi5418da32013-10-11 14:14:47 -0700150 {
151 /* 5.a, 5.b */
152 usb_wrapper_hs_phy_init(dev->wrapper_dev);
153
154 /* 5.d */
155 dwc_usb2_phy_soft_reset(dev->dwc);
156 }
157}
158
159/* vbus override */
160void vbus_override(udc_t *dev)
161{
162 /* when vbus signal is not available directly to the controller,
163 * simulate vbus presense.
164 */
165 if (board_platform_id() == APQ8084)
166 {
167 usb_wrapper_vbus_override(dev->wrapper_dev);
168 }
Amol Jadif3d5a892013-07-23 16:09:44 -0700169}
170
171
172/* Initialize usb wrapper and dwc h/w blocks. */
173static void usb30_init(void)
174{
175 usb_wrapper_dev_t* wrapper;
176 usb_wrapper_config_t wrapper_config;
177
178 dwc_dev_t *dwc;
179 dwc_config_t dwc_config;
180
181 /* initialize the usb wrapper h/w block */
182 wrapper_config.qscratch_base = (void*) MSM_USB30_QSCRATCH_BASE;
183
184 wrapper = usb_wrapper_init(&wrapper_config);
185 ASSERT(wrapper);
186
187 /* save the wrapper ptr */
188 udc_dev->wrapper_dev = wrapper;
189
190 /* initialize the dwc device block */
191 dwc_config.base = (void*) MSM_USB30_BASE;
192
193 /* buffer must be aligned to buf size. snps 8.2.2 */
194 dwc_config.event_buf = memalign(lcm(CACHE_LINE, UDC_DWC_EVENT_BUF_SIZE),
195 ROUNDUP(UDC_DWC_EVENT_BUF_SIZE, CACHE_LINE));
196 ASSERT(dwc_config.event_buf);
197
198 dwc_config.event_buf_size = UDC_DWC_EVENT_BUF_SIZE;
199
200 /* notify handler */
201 dwc_config.notify_context = udc_dev;
202 dwc_config.notify = udc_dwc_notify;
203
204 /* setup handler */
205 dwc_config.setup_context = udc_dev;
206 dwc_config.setup_handler = udc_handle_setup;
207
208 dwc = dwc_init(&dwc_config);
209 ASSERT(dwc);
210
211 /* save the dwc dev ptr */
212 udc_dev->dwc = dwc;
213
214
215 /* USB3.0 core and phy initialization as described in HPG */
216
217 /* section 4.4.1 Control sequence */
218 usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS);
219
220 /* section 4.4.1: use config 0 - all of RAM1 */
221 usb_wrapper_ram_configure(wrapper);
222
223 /* section 4.4.2: Initialization and configuration sequences */
224
225 /* 1. UTMI Mux configuration */
Amol Jadi5418da32013-10-11 14:14:47 -0700226 phy_mux_configure();
Amol Jadif3d5a892013-07-23 16:09:44 -0700227
228 /* 2. Put controller in reset */
229 dwc_reset(dwc, 1);
230
Amol Jadi5418da32013-10-11 14:14:47 -0700231 /* Steps 3 - 7 must be done while dwc is in reset condition */
Amol Jadif3d5a892013-07-23 16:09:44 -0700232
Amol Jadi5418da32013-10-11 14:14:47 -0700233 /* 3. Reset PHY */
234 phy_reset(wrapper);
Amol Jadif3d5a892013-07-23 16:09:44 -0700235
236 /* 4. SS phy config */
237 usb_wrapper_ss_phy_configure(wrapper);
238
239 /* 5. HS phy init */
240 usb_wrapper_hs_phy_init(wrapper);
241
Amol Jadif3d5a892013-07-23 16:09:44 -0700242 /* 6. hs phy config */
243 usb_wrapper_hs_phy_configure(wrapper);
244
245 /* 7. Reset PHY digital interface */
246 dwc_phy_digital_reset(dwc);
247
248 /* 8. Bring dwc controller out of reset */
249 dwc_reset(dwc, 0);
250
251 /* 9. */
252 usb_wrapper_ss_phy_electrical_config(wrapper);
253
254 /* 10. */
255 usb_wrapper_workaround_10(wrapper);
256
257 /* 11. */
258 usb_wrapper_workaround_11(wrapper);
259
260 /* 12. */
261 dwc_ss_phy_workaround_12(dwc);
262
263 /* 13. */
264 usb_wrapper_workaround_13(wrapper);
265
266 /* 14. needed only for host mode. ignored. */
267
Amol Jadi5418da32013-10-11 14:14:47 -0700268 /* If the target does not support vbus detection in controller,
269 * simulate vbus presence.
270 */
271 vbus_override(udc_dev);
272
Amol Jadif3d5a892013-07-23 16:09:44 -0700273 /* 15 - 20 */
274 dwc_device_init(dwc);
275}
276
277/* udc_init: creates and registers various usb descriptor */
Amol Jadi151f2a52013-10-07 12:39:11 -0700278int usb30_udc_init(struct udc_device *dev_info)
Amol Jadif3d5a892013-07-23 16:09:44 -0700279{
280 /* create and initialize udc instance */
281 udc_dev = (udc_t*) malloc(sizeof(udc_t));
282 ASSERT(udc_dev);
283
284 /* initialize everything to 0 */
285 memset(udc_dev, 0 , sizeof(udc_t));
286
287 /* malloc control data buffers */
288 udc_dev->ctrl_rx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_RX_BUF_SIZE, CACHE_LINE));
289 ASSERT(udc_dev->ctrl_rx_buf);
290
291 udc_dev->ctrl_tx_buf = memalign(CACHE_LINE, ROUNDUP(UDC_CONTROL_TX_BUF_SIZE, CACHE_LINE));
292 ASSERT(udc_dev->ctrl_tx_buf);
293
294 /* initialize string id */
295 udc_dev->next_string_id = 1;
296
297 /* Initialize ept data */
298 /* alloc table to assume EP0 In/OUT are already allocated.*/
299 udc_dev->ept_alloc_table = EPT_TX(0) | EPT_RX(0);
300 udc_dev->ept_list = NULL;
301
302 usb30_init();
303
304 /* register descriptors */
305 udc_register_language_desc(udc_dev);
306 udc_register_device_desc_usb_20(udc_dev, dev_info);
307 udc_register_device_desc_usb_30(udc_dev, dev_info);
308 udc_register_bos_desc(udc_dev);
309
310 return 0;
311}
312
313/* application registers its gadget by calling this func.
314 * gadget == interface descriptor
315 */
Amol Jadi151f2a52013-10-07 12:39:11 -0700316int usb30_udc_register_gadget(struct udc_gadget *gadget)
Amol Jadif3d5a892013-07-23 16:09:44 -0700317{
318 ASSERT(gadget);
319
320 /* check if already registered */
321 if (udc_dev->gadget)
322 {
323 ERR("\nonly one gadget supported\n");
324 return -1;
325 }
326
327 /* create our configuration descriptors based on this gadget data */
328 udc_register_config_desc_usb20(udc_dev, gadget);
329 udc_register_config_desc_usb30(udc_dev, gadget);
330
331 /* save the gadget */
332 udc_dev->gadget = gadget;
333
334 return 0;
335}
336
337/* udc_start: */
Amol Jadi151f2a52013-10-07 12:39:11 -0700338int usb30_udc_start(void)
Amol Jadif3d5a892013-07-23 16:09:44 -0700339{
340 /* 19. run
341 * enable device to receive SOF packets and
342 * respond to control transfers on EP0 and generate events.
343 */
344 dwc_device_run(udc_dev->dwc, 1);
345
346 return 0;
347}
348
349/* Control data rx callback. Called by DWC layer when it receives control
350 * data from host.
351 */
352void udc_control_rx_callback(void *context, unsigned actual, int status)
353{
354 udc_t *udc = (udc_t *) context;
355
356 /* Force reload of buffer update by controller from memory */
357 arch_invalidate_cache_range((addr_t) udc->ctrl_rx_buf, actual);
358
359 /* TODO: for now, there is only one 3-stage write during 3.0 enumeration
360 * (SET_SEL), which causes this callback. Ideally, set_periodic() must
361 * be based on which control rx just happened.
362 * Also, the value of 0x65 should depend on the data received for SET_SEL.
363 * For now, this value works just fine.
364 */
365 dwc_device_set_periodic_param(udc->dwc, 0x65);
366}
367
368/* lookup request name for debug purposes */
369static const char *reqname(uint32_t r)
370{
371 switch (r) {
372 case GET_STATUS:
373 return "GET_STATUS";
374 case CLEAR_FEATURE:
375 return "CLEAR_FEATURE";
376 case SET_FEATURE:
377 return "SET_FEATURE";
378 case SET_ADDRESS:
379 return "SET_ADDRESS";
380 case GET_DESCRIPTOR:
381 return "GET_DESCRIPTOR";
382 case SET_DESCRIPTOR:
383 return "SET_DESCRIPTOR";
384 case GET_CONFIGURATION:
385 return "GET_CONFIGURATION";
386 case SET_CONFIGURATION:
387 return "SET_CONFIGURATION";
388 case GET_INTERFACE:
389 return "GET_INTERFACE";
390 case SET_INTERFACE:
391 return "SET_INTERFACE";
392 case SET_SEL:
393 return "SET_SEL";
394 default:
395 return "*UNKNOWN*";
396 }
397}
398
399/* callback function called by DWC layer when a setup packed is received.
400 * the return value tells dwc layer whether this setup pkt results in
401 * a 2-stage or a 3-stage control transfer or stall.
402 */
403static int udc_handle_setup(void *context, uint8_t *data)
404{
405 udc_t *udc = (udc_t *) context;
406 uint32_t len;
407
408 ASSERT(udc);
409
410 dwc_dev_t *dwc = udc->dwc;
411 ASSERT(dwc);
412
413 struct setup_packet s = *((struct setup_packet*) data);
414
415 DBG("\n SETUP request: \n type = 0x%x \n request = 0x%x \n value = 0x%x"
416 " \n index = 0x%x \n length = 0x%x\n",
417 s.type, s.request, s.value, s.index, s.length);
418
419 switch (SETUP(s.type, s.request))
420 {
421 case SETUP(DEVICE_READ, GET_STATUS):
422 {
423 DBG("\n DEVICE_READ : GET_STATUS: value = %d index = %d"
424 " length = %d", s.value, s.index, s.length);
425
426 if (s.length == 2) {
427
428 uint16_t zero = 0;
429 len = 2;
430
431 /* copy to tx buffer */
432 memcpy(udc->ctrl_tx_buf, &zero, len);
433
434 /* flush buffer to main memory before queueing the request */
435 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
436
437 dwc_transfer_request(udc->dwc,
438 0,
439 DWC_EP_DIRECTION_IN,
440 udc->ctrl_tx_buf,
441 len,
442 NULL,
443 NULL);
444
445 return DWC_SETUP_3_STAGE;
446 }
447 }
448 break;
449 case SETUP(DEVICE_READ, GET_DESCRIPTOR):
450 {
451 DBG("\n DEVICE_READ : GET_DESCRIPTOR: value = %d", s.value);
452
453 /* setup usb ep0-IN to send our device descriptor */
454 struct udc_descriptor *desc;
455
456 for (desc = udc->desc_list; desc; desc = desc->next)
457 {
458 /* tag must match the value AND
459 * if speed is SS, desc must comply with 30 spec OR
460 * if speed is not SS, desc must comply with 20 spec.
461 */
462 if ((desc->tag == s.value) &&
463 (((udc->speed == UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_30)) ||
464 ((udc->speed != UDC_SPEED_SS) && (desc->spec & UDC_DESC_SPEC_20)))
465 )
466 {
467 if (desc->len > s.length)
468 len = s.length;
469 else
470 len = desc->len;
471
472 /* copy to tx buffer */
473 memcpy(udc->ctrl_tx_buf, desc->data, len);
474
475 /* flush buffer to main memory before queueing the request */
476 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
477
478 dwc_transfer_request(udc->dwc,
479 0,
480 DWC_EP_DIRECTION_IN,
481 udc->ctrl_tx_buf,
482 len,
483 NULL,
484 NULL);
485
486 return DWC_SETUP_3_STAGE;
487 }
488 }
489 DBG("\n Did not find matching descriptor: = 0x%x", s.value);
490 }
491 break;
492 case SETUP(DEVICE_READ, GET_CONFIGURATION):
493 {
494 DBG("\n DEVICE_READ : GET_CONFIGURATION");
495
496 if ((s.value == 0) && (s.index == 0) && (s.length == 1)) {
497
498 len = 1;
499
500 /* copy to tx buffer */
501 memcpy(udc->ctrl_tx_buf, &udc->config_selected, len);
502
503 /* flush buffer to main memory before queueing the request */
504 arch_clean_invalidate_cache_range((addr_t) udc->ctrl_tx_buf, len);
505
506 dwc_transfer_request(udc->dwc,
507 0,
508 DWC_EP_DIRECTION_IN,
509 udc->ctrl_tx_buf,
510 len,
511 NULL,
512 NULL);
513
514 return DWC_SETUP_3_STAGE;
515 }
516 else
517 {
518 ASSERT(0);
519 }
520 }
521 break;
522 case SETUP(DEVICE_WRITE, SET_CONFIGURATION):
523 {
524 DBG("\n DEVICE_WRITE : SET_CONFIGURATION");
525
526 /* select configuration 1 */
527 if (s.value == 1) {
528 struct udc_endpoint *ept;
529 /* enable endpoints */
530 for (ept = udc->ept_list; ept; ept = ept->next) {
531 if (ept->num == 0)
532 continue;
533 else
534 {
535 /* add this ep to dwc ep list */
536 dwc_ep_t ep;
537
538 ep.number = ept->num;
539 ep.dir = ept->in;
540 ep.type = EP_TYPE_BULK; /* the only one supported */
541 ep.max_pkt_size = ept->maxpkt;
542 ep.burst_size = ept->maxburst;
543 ep.zlp = 0; /* TODO: zlp could be made part of ept */
544 ep.trb_count = ept->trb_count;
545 ep.trb = ept->trb;
546
547 dwc_device_add_ep(dwc, ep);
548 }
549 }
550
551 /* now that we have saved the non-control EP details, set config */
552 dwc_device_set_configuration(dwc);
553
554 /* inform client that we are configured. */
555 udc->gadget->notify(udc_dev->gadget, UDC_EVENT_ONLINE);
556
557 udc->config_selected = 1;
558
559 return DWC_SETUP_2_STAGE;
560 }
561 else if (s.value == 0)
562 {
563 /* 0 == de-configure. */
564 udc->config_selected = 0;
565 DBG("\n\n CONFIG = 0 !!!!!!!!!\n\n");
566 return DWC_SETUP_2_STAGE;
567 /* TODO: do proper handling for de-config */
568 }
569 else
570 {
571 ERR("\n CONFIG = %d not supported\n", s.value);
572 ASSERT(0);
573 }
574 }
575 break;
576 case SETUP(DEVICE_WRITE, SET_ADDRESS):
577 {
578 DBG("\n DEVICE_WRITE : SET_ADDRESS");
579
580 dwc_device_set_addr(dwc, s.value);
581 return DWC_SETUP_2_STAGE;
582 }
583 break;
584 case SETUP(INTERFACE_WRITE, SET_INTERFACE):
585 {
586 DBG("\n DEVICE_WRITE : SET_INTERFACE");
587 /* if we ack this everything hangs */
588 /* per spec, STALL is valid if there is not alt func */
589 goto stall;
590 }
591 break;
592 case SETUP(DEVICE_WRITE, SET_FEATURE):
593 {
594 DBG("\n DEVICE_WRITE : SET_FEATURE");
595 goto stall;
596 }
597 break;
598 case SETUP(DEVICE_WRITE, CLEAR_FEATURE):
599 {
600 DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
601 goto stall;
602 }
603 break;
604 case SETUP(ENDPOINT_WRITE, CLEAR_FEATURE):
605 {
606 DBG("\n DEVICE_WRITE : CLEAR_FEATURE");
607 goto stall;
608 }
609 break;
610 case SETUP(DEVICE_WRITE, SET_SEL):
611 {
612 DBG("\n DEVICE_WRITE : SET_SEL");
613
614 /* this is 3-stage write. need to receive data of s.length size. */
615 if (s.length > 0) {
616 dwc_transfer_request(udc->dwc,
617 0,
618 DWC_EP_DIRECTION_OUT,
619 udc->ctrl_rx_buf,
620 UDC_CONTROL_RX_BUF_SIZE,
621 udc_control_rx_callback,
622 (void *) udc);
623 return DWC_SETUP_3_STAGE;
624 }
625 else
626 {
627 /* length must be non-zero */
628 ASSERT(0);
629 }
630 }
631 break;
632
633 default:
634 ERR("\n Unknown setup req.\n type = 0x%x value = %d index = %d"
635 " length = %d\n", s.type, s.value, s.index, s.length);
636 ASSERT(0);
637 }
638
639stall:
640 ERR("\nSTALL. Unsupported setup req: %s %d %d %d %d %d\n",
641 reqname(s.request), s.type, s.request, s.value, s.index, s.length);
642
643 return DWC_SETUP_ERROR;
644}
645
646/* Callback function called by DWC layer when a request to transfer data
647 * on non-control EP is completed.
648 */
649void udc_request_complete(void *context, uint32_t actual, int status)
650{
651 struct udc_request *req = ((udc_t *) context)->queued_req;
652
653 DBG("\n UDC: udc_request_callback: xferred %d bytes status = %d\n",
654 actual, status);
655
656 /* clear the queued request. */
657 ((udc_t *) context)->queued_req = NULL;
658
659 if (req->complete)
660 {
661 req->complete(req, actual, status);
662 }
663
664 DBG("\n UDC: udc_request_callback: done fastboot callback\n");
665}
666
667/* App interface to queue in data transfer requests for control and data ep */
Amol Jadi151f2a52013-10-07 12:39:11 -0700668int usb30_udc_request_queue(struct udc_endpoint *ept, struct udc_request *req)
Amol Jadif3d5a892013-07-23 16:09:44 -0700669{
670 int ret;
671 dwc_dev_t *dwc_dev = udc_dev->dwc;
672
673 /* ensure device is initialized before queuing request */
674 ASSERT(dwc_dev);
675
676 /* if device is not configured, return error */
677 if(udc_dev->config_selected == 0)
678 {
679 return -1;
680 }
681
682 /* only one request at a time is supported.
683 * check if a request is already queued.
684 */
685 if(udc_dev->queued_req)
686 {
687 return -1;
688 }
689
690 DBG("\n udc_request_queue: entry: ep_usb_num = %d", ept->num);
691
692 /* save the queued request. */
693 udc_dev->queued_req = req;
694
695 ret = dwc_transfer_request(dwc_dev,
696 ept->num,
697 ept->in ? DWC_EP_DIRECTION_IN : DWC_EP_DIRECTION_OUT,
698 req->buf,
699 req->length,
700 udc_request_complete,
701 (void *) udc_dev);
702
703 DBG("\n udc_request_queue: exit: ep_usb_num = %d", ept->num);
704
705 return ret;
706}
707
708/* callback function called by dwc layer if any dwc event occurs */
709void udc_dwc_notify(void *context, dwc_notify_event_t event)
710{
711 udc_t *udc = (udc_t *) context;
712
713 switch (event)
714 {
715 case DWC_NOTIFY_EVENT_CONNECTED_LS:
716 udc->speed = UDC_SPEED_LS;
717 break;
718 case DWC_NOTIFY_EVENT_CONNECTED_FS:
719 udc->speed = UDC_SPEED_FS;
720 break;
721 case DWC_NOTIFY_EVENT_CONNECTED_HS:
722 udc->speed = UDC_SPEED_HS;
723 break;
724 case DWC_NOTIFY_EVENT_CONNECTED_SS:
725 udc->speed = UDC_SPEED_SS;
726 break;
727 case DWC_NOTIFY_EVENT_DISCONNECTED:
728 case DWC_NOTIFY_EVENT_OFFLINE:
729 udc->config_selected = 0;
730 if (udc->gadget && udc->gadget->notify)
731 udc->gadget->notify(udc->gadget, UDC_EVENT_OFFLINE);
732 break;
733 default:
734 ASSERT(0);
735 }
736}
737
738
739/******************* Function related to descriptor allocation etc.************/
740
741static struct udc_endpoint *_udc_endpoint_alloc(uint8_t num,
742 uint8_t in,
743 uint16_t max_pkt)
744{
745 struct udc_endpoint *ept;
746 udc_t *udc = udc_dev;
747
748 ept = malloc(sizeof(*ept));
749 ASSERT(ept);
750
751 ept->maxpkt = max_pkt;
752 ept->num = num;
753 ept->in = !!in;
754 ept->maxburst = 4; /* no performance improvement is seen beyond burst size of 4 */
755 ept->trb_count = 66; /* each trb can transfer (16MB - 1). 65 for 1GB transfer + 1 for roundup/zero length pkt. */
756 ept->trb = memalign(lcm(CACHE_LINE, 16), ROUNDUP(ept->trb_count*sizeof(dwc_trb_t), CACHE_LINE)); /* TRB must be aligned to 16 */
757 ASSERT(ept->trb);
758
759 /* push it on top of ept_list */
760 ept->next = udc->ept_list;
761 udc->ept_list = ept;
762
763 return ept;
764}
765
766/* Called to create non-control in/out End Point structures by the APP */
Amol Jadi151f2a52013-10-07 12:39:11 -0700767struct udc_endpoint *usb30_udc_endpoint_alloc(unsigned type, unsigned maxpkt)
Amol Jadif3d5a892013-07-23 16:09:44 -0700768{
769 struct udc_endpoint *ept;
770 uint8_t in;
771 uint8_t n;
772 udc_t *udc = udc_dev;
773
774 if (type == UDC_TYPE_BULK_IN) {
775 in = 1;
776 } else if (type == UDC_TYPE_BULK_OUT) {
777 in = 0;
778 } else {
779 return 0;
780 }
781
782 for (n = 1; n < 16; n++) {
783 uint32_t bit = in ? EPT_TX(n) : EPT_RX(n);
784 if (udc->ept_alloc_table & bit)
785 continue;
786 ept = _udc_endpoint_alloc(n, in, maxpkt);
787 if (ept)
788 udc->ept_alloc_table |= bit;
789 return ept;
790 }
791 return 0;
792}
793
794
795/* create config + interface + ep desc for 2.0 */
796static void udc_register_config_desc_usb20(udc_t *udc,
797 struct udc_gadget *gadget)
798{
799 uint8_t *data;
800 uint16_t size;
801 struct udc_descriptor *desc;
802
803 ASSERT(udc);
804 ASSERT(gadget);
805
806 /* create our configuration descriptor */
807
808 /* size is the total size of (config + interface + all EPs) descriptor */
809 size = UDC_DESC_SIZE_CONFIGURATION +
810 UDC_DESC_SIZE_INTERFACE +
811 (gadget->ifc_endpoints*UDC_DESC_SIZE_ENDPOINT);
812
813 desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_20);
814
815 data = desc->data;
816
817 /* Config desc */
818 data[0] = 0x09;
819 data[1] = TYPE_CONFIGURATION;
820 data[2] = size;
821 data[3] = size >> 8;
822 data[4] = 0x01; /* number of interfaces */
823 data[5] = 0x01; /* configuration value */
824 data[6] = 0x00; /* configuration string */
825 data[7] = 0xC0; /* attributes: reserved and self-powered set */
826 data[8] = 0x00; /* max power: 0ma since we are self powered */
827 data += 9;
828
829 /* Interface desc */
830 data[0] = 0x09;
831 data[1] = TYPE_INTERFACE;
832 data[2] = 0x00; /* ifc number */
833 data[3] = 0x00; /* alt number */
834 data[4] = gadget->ifc_endpoints;
835 data[5] = gadget->ifc_class;
836 data[6] = gadget->ifc_subclass;
837 data[7] = gadget->ifc_protocol;
838 data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
839 data += 9;
840
841 for (uint8_t n = 0; n < gadget->ifc_endpoints; n++) {
842 udc_ept_desc_fill(gadget->ept[n], data);
843 data += UDC_DESC_SIZE_ENDPOINT;
844 }
845
846 udc_descriptor_register(udc, desc);
847}
848
849/* create config + interface + ep desc for 3.0 */
850static void udc_register_config_desc_usb30(udc_t *udc,
851 struct udc_gadget *gadget)
852{
853 uint8_t *data;
854 uint16_t size;
855 struct udc_descriptor *desc;
856
857 ASSERT(udc);
858 ASSERT(gadget);
859
860 /* create our configuration descriptor */
861
862 /* size is the total size of (config + interface + all EPs) descriptor */
863 size = UDC_DESC_SIZE_CONFIGURATION +
864 UDC_DESC_SIZE_INTERFACE +
865 (gadget->ifc_endpoints*(UDC_DESC_SIZE_ENDPOINT + UDC_DESC_SIZE_ENDPOINT_COMP));
866
867 desc = udc_descriptor_alloc(TYPE_CONFIGURATION, 0, size, UDC_DESC_SPEC_30);
868
869 data = desc->data;
870
871 /* Config desc */
872 data[0] = 0x09;
873 data[1] = TYPE_CONFIGURATION;
874 data[2] = size;
875 data[3] = size >> 8;
876 data[4] = 0x01; /* number of interfaces */
877 data[5] = 0x01; /* configuration value */
878 data[6] = 0x00; /* configuration string */
879 data[7] = 0xC0; /* attributes: reserved and self-powered set */
880 data[8] = 0x00; /* max power: 0ma since we are self powered */
881 data += 9;
882
883 /* Interface desc */
884 data[0] = 0x09;
885 data[1] = TYPE_INTERFACE;
886 data[2] = 0x00; /* ifc number */
887 data[3] = 0x00; /* alt number */
888 data[4] = gadget->ifc_endpoints;
889 data[5] = gadget->ifc_class;
890 data[6] = gadget->ifc_subclass;
891 data[7] = gadget->ifc_protocol;
892 data[8] = udc_string_desc_alloc(udc, gadget->ifc_string);
893 data += 9;
894
895 for (uint8_t n = 0; n < gadget->ifc_endpoints; n++)
896 {
897 /* fill EP desc */
898 udc_ept_desc_fill(gadget->ept[n], data);
899 data += UDC_DESC_SIZE_ENDPOINT;
900
901 /* fill EP companion desc */
902 udc_ept_comp_desc_fill(gadget->ept[n], data);
903 data += UDC_DESC_SIZE_ENDPOINT_COMP;
904 }
905
906 udc_descriptor_register(udc, desc);
907}
908
909
910static void udc_register_device_desc_usb_20(udc_t *udc,
911 struct udc_device *dev_info)
912{
913 uint8_t *data;
914 struct udc_descriptor *desc;
915
916 /* create our device descriptor */
917 desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_20);
918 data = desc->data;
919
920 /* data 0 and 1 is filled by descriptor alloc routine.
921 * fill in the remaining entries.
922 */
923 data[2] = 0x00; /* usb spec minor rev */
924 data[3] = 0x02; /* usb spec major rev */
925 data[4] = 0x00; /* class */
926 data[5] = 0x00; /* subclass */
927 data[6] = 0x00; /* protocol */
928 data[7] = 0x40; /* max packet size on ept 0 */
929
930 memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
931 memcpy(data + 10, &dev_info->product_id, sizeof(short));
932 memcpy(data + 12, &dev_info->version_id, sizeof(short));
933
934 data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
935 data[15] = udc_string_desc_alloc(udc, dev_info->product);
936 data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
937 data[17] = 1; /* number of configurations */
938
939 udc_descriptor_register(udc, desc);
940}
941
942static void udc_register_device_desc_usb_30(udc_t *udc, struct udc_device *dev_info)
943{
944 uint8_t *data;
945 struct udc_descriptor *desc;
946
947 /* create our device descriptor */
948 desc = udc_descriptor_alloc(TYPE_DEVICE, 0, 18, UDC_DESC_SPEC_30);
949 data = desc->data;
950
951 /* data 0 and 1 is filled by descriptor alloc routine.
952 * fill in the remaining entries.
953 */
954 data[2] = 0x00; /* usb spec minor rev */
955 data[3] = 0x03; /* usb spec major rev */
956 data[4] = 0x00; /* class */
957 data[5] = 0x00; /* subclass */
958 data[6] = 0x00; /* protocol */
959 data[7] = 0x09; /* max packet size on ept 0 */
960 memcpy(data + 8, &dev_info->vendor_id, sizeof(short));
961 memcpy(data + 10, &dev_info->product_id, sizeof(short));
962 memcpy(data + 12, &dev_info->version_id, sizeof(short));
963 data[14] = udc_string_desc_alloc(udc, dev_info->manufacturer);
964 data[15] = udc_string_desc_alloc(udc, dev_info->product);
965 data[16] = udc_string_desc_alloc(udc, dev_info->serialno);
966 data[17] = 1; /* number of configurations */
967
968 udc_descriptor_register(udc, desc);
969}
970
971static void udc_register_bos_desc(udc_t *udc)
972{
973 uint8_t *data;
974 struct udc_descriptor *desc;
975
976 /* create our device descriptor */
977 desc = udc_descriptor_alloc(TYPE_BOS, 0, 15, UDC_DESC_SPEC_30); /* 15 is total length of bos + other descriptors inside it */
978 data = desc->data;
979
980 /* data 0 and 1 is filled by descriptor alloc routine.
981 * fill in the remaining entries.
982 */
983 data[0] = 0x05; /* BOS desc len */
984 data[1] = TYPE_BOS; /* BOS desc type */
985 data[2] = 0x0F; /* total len of bos desc and its sub desc */
986 data[3] = 0x00; /* total len of bos desc and its sub desc */
987 data[4] = 0x01; /* num of sub desc inside bos */
988
989 data[5] = 0x0A; /* desc len */
990 data[6] = 0x10; /* Device Capability desc */
991 data[7] = 0x03; /* 3 == SuperSpeed capable */
992 data[8] = 0x00; /* Attribute: latency tolerance msg: No */
993 data[9] = 0x0F; /* Supported Speeds (bit mask): LS, FS, HS, SS */
994 data[10] = 0x00; /* Reserved part of supported wSupportedSpeeds */
995 data[11] = 0x01; /* lowest supported speed with full functionality: FS */
996 data[12] = 0x00; /* U1 device exit latency */
997 data[13] = 0x00; /* U2 device exit latency (lsb) */
998 data[14] = 0x00; /* U2 device exit latency (msb) */
999
1000 udc_descriptor_register(udc, desc);
1001}
1002
1003static void udc_register_language_desc(udc_t *udc)
1004{
1005 /* create and register a language table descriptor */
1006 /* language 0x0409 is US English */
1007 struct udc_descriptor *desc = udc_descriptor_alloc(TYPE_STRING,
1008 0,
1009 4,
1010 UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
1011 desc->data[2] = 0x09;
1012 desc->data[3] = 0x04;
1013 udc_descriptor_register(udc, desc);
1014}
1015
1016static void udc_ept_desc_fill(struct udc_endpoint *ept, uint8_t *data)
1017{
1018 data[0] = 7;
1019 data[1] = TYPE_ENDPOINT;
1020 data[2] = ept->num | (ept->in ? 0x80 : 0x00);
1021 data[3] = 0x02; /* bulk -- the only kind we support */
1022 data[4] = ept->maxpkt;
1023 data[5] = ept->maxpkt >> 8;
1024 data[6] = 0; /* bInterval: must be 0 for bulk. */
1025}
1026
1027static void udc_ept_comp_desc_fill(struct udc_endpoint *ept, uint8_t *data)
1028{
1029 data[0] = 6; /* bLength */
1030 data[1] = TYPE_SS_EP_COMP; /* ep type */
1031 data[2] = ept->maxburst; /* maxBurst */
1032 data[3] = 0x0; /* maxStreams */
1033 data[4] = 0x0; /* wBytesPerInterval */
1034 data[5] = 0x0; /* wBytesPerInterval */
1035}
1036
1037static uint8_t udc_string_desc_alloc(udc_t *udc, const char *str)
1038{
1039 uint32_t len;
1040 struct udc_descriptor *desc;
1041 uint8_t *data;
1042
1043 if (udc->next_string_id > 255)
1044 return 0;
1045
1046 if (!str)
1047 return 0;
1048
1049 len = strlen(str);
1050 desc = udc_descriptor_alloc(TYPE_STRING,
1051 udc->next_string_id,
1052 len * 2 + 2,
1053 UDC_DESC_SPEC_20 | UDC_DESC_SPEC_30);
1054 if (!desc)
1055 return 0;
1056 udc->next_string_id++;
1057
1058 /* expand ascii string to utf16 */
1059 data = desc->data + 2;
1060 while (len-- > 0) {
1061 *data++ = *str++;
1062 *data++ = 0;
1063 }
1064
1065 udc_descriptor_register(udc, desc);
1066 return desc->tag & 0xff;
1067}
1068
1069
1070static struct udc_descriptor *udc_descriptor_alloc(uint32_t type,
1071 uint32_t num,
1072 uint32_t len,
1073 udc_desc_spec_t spec)
1074{
1075 struct udc_descriptor *desc;
1076 if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
1077 return 0;
1078
1079 if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
1080 return 0;
1081
1082 desc->next = 0;
1083 desc->tag = (type << 8) | num;
1084 desc->len = len;
1085 desc->spec = spec;
1086
1087 /* descriptor data */
1088 desc->data[0] = len;
1089 desc->data[1] = type;
1090
1091 return desc;
1092}
1093
1094static void udc_descriptor_register(udc_t *udc, struct udc_descriptor *desc)
1095{
1096 desc->next = udc->desc_list;
1097 udc->desc_list = desc;
1098}
1099
1100
Amol Jadi151f2a52013-10-07 12:39:11 -07001101struct udc_request *usb30_udc_request_alloc(void)
Amol Jadif3d5a892013-07-23 16:09:44 -07001102{
1103 struct udc_request *req;
1104
1105 req = malloc(sizeof(*req));
1106 ASSERT(req);
1107
1108 req->buf = 0;
1109 req->length = 0;
1110 req->complete = NULL;
1111 req->context = 0;
1112
1113 return req;
1114}
1115
Amol Jadi151f2a52013-10-07 12:39:11 -07001116void usb30_udc_request_free(struct udc_request *req)
Amol Jadif3d5a892013-07-23 16:09:44 -07001117{
1118 free(req);
1119}
1120
Amol Jadi151f2a52013-10-07 12:39:11 -07001121void usb30_udc_endpoint_free(struct udc_endpoint *ept)
Amol Jadif3d5a892013-07-23 16:09:44 -07001122{
1123 /* TODO */
1124}
1125
Amol Jadi151f2a52013-10-07 12:39:11 -07001126int usb30_udc_stop(void)
Amol Jadif3d5a892013-07-23 16:09:44 -07001127{
1128 dwc_device_run(udc_dev->dwc, 0);
1129
1130 return 0;
1131}