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Travis Geiselbrecht1d0df692008-09-01 02:26:09 -07001/*
2 * Copyright (c) 2008 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <debug.h>
24#include <arch.h>
25#include <arch/ops.h>
26#include <arch/arm.h>
27#include <arch/arm/mmu.h>
28#include <platform.h>
29
30#if ARM_CPU_CORTEX_A8
31static void set_vector_base(addr_t addr)
32{
33 __asm__ volatile("mcr p15, 0, %0, c12, c0, 0" :: "r" (addr));
34}
35#endif
36
37void arch_early_init(void)
38{
39 /* turn off the cache */
40 arch_disable_cache(UCACHE);
41
42 /* set the vector base to our exception vectors so we dont need to double map at 0 */
43#if ARM_CPU_CORTEX_A8
44 set_vector_base(MEMBASE);
45#endif
46
47#if ARM_WITH_MMU
48 arm_mmu_init();
49
50 platform_init_mmu_mappings();
51#endif
52
53 /* turn the cache back on */
54 arch_enable_cache(UCACHE);
55
56#if ARM_WITH_NEON
57 /* enable cp10 and cp11 */
58 uint32_t val;
59 __asm__ volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (val));
60 val |= (3<<22)|(3<<20);
61 __asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
62
63 /* set enable bit in fpexc */
64 val = (1<<30);
65 __asm__ volatile("mcr p10, 7, %0, c8, c0, 0" :: "r" (val));
66#endif
67}
68
69void arch_init(void)
70{
71}
72