| Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | .text |
| 24 | .globl _start |
| 25 | _start: |
| 26 | b reset |
| 27 | b arm_undefined |
| 28 | b arm_syscall |
| 29 | b arm_prefetch_abort |
| 30 | b arm_data_abort |
| 31 | b arm_reserved |
| 32 | b arm_irq |
| 33 | b arm_fiq |
| 34 | |
| 35 | reset: |
| 36 | /* do some cpu setup */ |
| 37 | #if ARM_WITH_CP15 |
| 38 | mrc p15, 0, r0, c1, c0, 0 |
| 39 | /* XXX this is currently for arm926, revist with armv6 cores */ |
| 40 | /* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */ |
| 41 | bic r0, r0, #(1<<15| 1<<13 | 1<<12) |
| 42 | bic r0, r0, #(1<<2 | 1<<0) |
| 43 | /* enable alignment faults */ |
| 44 | orr r0, r0, #(1<<1) |
| 45 | mcr p15, 0, r0, c1, c0, 0 |
| 46 | #endif |
| 47 | |
| 48 | /* set up the stack for irq, fiq, abort, undefined, system/user, and lastly supervisor mode */ |
| 49 | mrs r0, cpsr |
| 50 | bic r0, r0, #0x1f |
| 51 | |
| 52 | ldr r2, =abort_stack_top |
| 53 | orr r1, r0, #0x12 // irq |
| 54 | msr cpsr_c, r1 |
| 55 | ldr r13, =irq_save_spot /* save a pointer to a temporary dumping spot used during irq delivery */ |
| 56 | |
| 57 | orr r1, r0, #0x11 // fiq |
| 58 | msr cpsr_c, r1 |
| 59 | mov sp, r2 |
| 60 | |
| 61 | orr r1, r0, #0x17 // abort |
| 62 | msr cpsr_c, r1 |
| 63 | mov sp, r2 |
| 64 | |
| 65 | orr r1, r0, #0x1b // undefined |
| 66 | msr cpsr_c, r1 |
| 67 | mov sp, r2 |
| 68 | |
| 69 | orr r1, r0, #0x1f // system |
| 70 | msr cpsr_c, r1 |
| 71 | mov sp, r2 |
| 72 | |
| 73 | orr r1, r0, #0x13 // supervisor |
| 74 | msr cpsr_c, r1 |
| 75 | mov sp, r2 |
| 76 | |
| 77 | /* copy the initialized data segment out of rom if necessary */ |
| 78 | ldr r0, =__data_start_rom |
| 79 | ldr r1, =__data_start |
| 80 | ldr r2, =__data_end |
| 81 | |
| 82 | cmp r0, r1 |
| 83 | beq __do_bss |
| 84 | |
| 85 | __copy_loop: |
| 86 | cmp r1, r2 |
| 87 | ldrlt r3, [r0], #4 |
| 88 | strlt r3, [r1], #4 |
| 89 | blt __copy_loop |
| 90 | |
| 91 | __do_bss: |
| 92 | /* clear out the bss */ |
| 93 | ldr r0, =__bss_start |
| 94 | ldr r1, =_end |
| 95 | mov r2, #0 |
| 96 | __bss_loop: |
| 97 | cmp r0, r1 |
| 98 | strlt r2, [r0], #4 |
| 99 | blt __bss_loop |
| 100 | |
| 101 | bl kmain |
| 102 | b . |
| 103 | |
| 104 | .ltorg |
| 105 | |
| 106 | .bss |
| 107 | .align 2 |
| 108 | /* the abort stack is for unrecoverable errors. |
| 109 | * also note the initial working stack is set to here. |
| 110 | * when the threading system starts up it'll switch to a new |
| 111 | * dynamically allocated stack, so we don't need it for very long |
| 112 | */ |
| 113 | abort_stack: |
| 114 | .skip 1024 |
| 115 | abort_stack_top: |